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KVM: VMX: Fix host MSR_KERNEL_GS_BASE corruption
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
e495606d 19
1d737c8a 20#include "mmu.h"
836a1b3c 21#include "x86.h"
6de4f3ad 22#include "kvm_cache_regs.h"
e495606d 23
edf88417 24#include <linux/kvm_host.h>
6aa8b732
AK		 25#include <linux/types.h>
26#include <linux/string.h>
6aa8b732
AK		 27#include <linux/mm.h>
28#include <linux/highmem.h>
29#include <linux/module.h>
448353ca 30#include <linux/swap.h>
05da4558 31#include <linux/hugetlb.h>
2f333bcb 32#include <linux/compiler.h>
bc6678a3 33#include <linux/srcu.h>
5a0e3ad6 34#include <linux/slab.h>
6aa8b732 35
e495606d
AK		 36#include <asm/page.h>
37#include <asm/cmpxchg.h>
4e542370 38#include <asm/io.h>
13673a90 39#include <asm/vmx.h>
6aa8b732 40
18552672
JR		 41/*
42 * When setting this variable to true it enables Two-Dimensional-Paging
43 * where the hardware walks 2 page tables:
44 * 1. the guest-virtual to guest-physical
45 * 2. while doing 1. it walks guest-physical to host-physical
46 * If the hardware supports that we don't need to do shadow paging.
47 */
2f333bcb 48bool tdp_enabled = false;
18552672 49
37a7d8b0
AK		 50#undef MMU_DEBUG
51
52#undef AUDIT
53
54#ifdef AUDIT
55static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
56#else
57static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
58#endif
59
60#ifdef MMU_DEBUG
61
62#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
63#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
64
65#else
66
67#define pgprintk(x...) do { } while (0)
68#define rmap_printk(x...) do { } while (0)
69
70#endif
71
72#if defined(MMU_DEBUG) || defined(AUDIT)
6ada8cca
AK		 73static int dbg = 0;
74module_param(dbg, bool, 0644);
37a7d8b0 75#endif
6aa8b732 76
582801a9
MT		 77static int oos_shadow = 1;
78module_param(oos_shadow, bool, 0644);
79
d6c69ee9
YD		 80#ifndef MMU_DEBUG
81#define ASSERT(x) do { } while (0)
82#else
6aa8b732
AK		 83#define ASSERT(x) \
84 if (!(x)) { \
85 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
86 __FILE__, __LINE__, #x); \
87 }
d6c69ee9 88#endif
6aa8b732 89
6aa8b732
AK		 90#define PT_FIRST_AVAIL_BITS_SHIFT 9
91#define PT64_SECOND_AVAIL_BITS_SHIFT 52
92
6aa8b732
AK		 93#define VALID_PAGE(x) ((x) != INVALID_PAGE)
94
95#define PT64_LEVEL_BITS 9
96
97#define PT64_LEVEL_SHIFT(level) \
d77c26fc 98 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732
AK		 99
100#define PT64_LEVEL_MASK(level) \
101 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
102
103#define PT64_INDEX(address, level)\
104 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105
106
107#define PT32_LEVEL_BITS 10
108
109#define PT32_LEVEL_SHIFT(level) \
d77c26fc 110 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732
AK		 111
112#define PT32_LEVEL_MASK(level) \
113 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
e04da980
JR		 114#define PT32_LVL_OFFSET_MASK(level) \
115 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
116 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK		 117
118#define PT32_INDEX(address, level)\
119 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
120
121
27aba766 122#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 123#define PT64_DIR_BASE_ADDR_MASK \
124 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
e04da980
JR		 125#define PT64_LVL_ADDR_MASK(level) \
126 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
127 * PT64_LEVEL_BITS))) - 1))
128#define PT64_LVL_OFFSET_MASK(level) \
129 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
130 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK		 131
132#define PT32_BASE_ADDR_MASK PAGE_MASK
133#define PT32_DIR_BASE_ADDR_MASK \
134 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR		 135#define PT32_LVL_ADDR_MASK(level) \
136 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
137 * PT32_LEVEL_BITS))) - 1))
6aa8b732 138
79539cec
AK		 139#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
140 | PT64_NX_MASK)
6aa8b732 141
cd4a4e53
AK		 142#define RMAP_EXT 4
143
fe135d2c
AK		 144#define ACC_EXEC_MASK 1
145#define ACC_WRITE_MASK PT_WRITABLE_MASK
146#define ACC_USER_MASK PT_USER_MASK
147#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
148
90bb6fc5
AK		 149#include <trace/events/kvm.h>
150
07420171
AK		 151#define CREATE_TRACE_POINTS
152#include "mmutrace.h"
153
1403283a
IE		 154#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
155
135f8c2b
AK		 156#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
157
cd4a4e53 158struct kvm_rmap_desc {
d555c333 159 u64 *sptes[RMAP_EXT];
cd4a4e53
AK		 160 struct kvm_rmap_desc *more;
161};
162
2d11123a
AK		 163struct kvm_shadow_walk_iterator {
164 u64 addr;
165 hpa_t shadow_addr;
166 int level;
167 u64 *sptep;
168 unsigned index;
169};
170
171#define for_each_shadow_entry(_vcpu, _addr, _walker) \
172 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
173 shadow_walk_okay(&(_walker)); \
174 shadow_walk_next(&(_walker)))
175
6b18493d 176typedef int (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp);
ad8cfbe3 177
b5a33a75
AK		 178static struct kmem_cache *pte_chain_cache;
179static struct kmem_cache *rmap_desc_cache;
d3d25b04 180static struct kmem_cache *mmu_page_header_cache;
b5a33a75 181
c7addb90
AK		 182static u64 __read_mostly shadow_trap_nonpresent_pte;
183static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 184static u64 __read_mostly shadow_base_present_pte;
185static u64 __read_mostly shadow_nx_mask;
186static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
187static u64 __read_mostly shadow_user_mask;
188static u64 __read_mostly shadow_accessed_mask;
189static u64 __read_mostly shadow_dirty_mask;
c7addb90 190
82725b20
DE		 191static inline u64 rsvd_bits(int s, int e)
192{
193 return ((1ULL << (e - s + 1)) - 1) << s;
194}
195
c7addb90
AK		 196void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
197{
198 shadow_trap_nonpresent_pte = trap_pte;
199 shadow_notrap_nonpresent_pte = notrap_pte;
200}
201EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
202
7b52345e
SY		 203void kvm_mmu_set_base_ptes(u64 base_pte)
204{
205 shadow_base_present_pte = base_pte;
206}
207EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
208
209void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 210 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 211{
212 shadow_user_mask = user_mask;
213 shadow_accessed_mask = accessed_mask;
214 shadow_dirty_mask = dirty_mask;
215 shadow_nx_mask = nx_mask;
216 shadow_x_mask = x_mask;
217}
218EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
219
3dbe1415 220static bool is_write_protection(struct kvm_vcpu *vcpu)
6aa8b732 221{
4d4ec087 222 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
6aa8b732
AK		 223}
224
225static int is_cpuid_PSE36(void)
226{
227 return 1;
228}
229
73b1087e
AK		 230static int is_nx(struct kvm_vcpu *vcpu)
231{
f6801dff 232 return vcpu->arch.efer & EFER_NX;
73b1087e
AK		 233}
234
c7addb90
AK		 235static int is_shadow_present_pte(u64 pte)
236{
c7addb90
AK		 237 return pte != shadow_trap_nonpresent_pte
238 && pte != shadow_notrap_nonpresent_pte;
239}
240
05da4558
MT		 241static int is_large_pte(u64 pte)
242{
243 return pte & PT_PAGE_SIZE_MASK;
244}
245
8dae4445 246static int is_writable_pte(unsigned long pte)
6aa8b732
AK		 247{
248 return pte & PT_WRITABLE_MASK;
249}
250
43a3795a 251static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 252{
439e218a 253 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 254}
255
43a3795a 256static int is_rmap_spte(u64 pte)
cd4a4e53 257{
4b1a80fa 258 return is_shadow_present_pte(pte);
cd4a4e53
AK		 259}
260
776e6633
MT		 261static int is_last_spte(u64 pte, int level)
262{
263 if (level == PT_PAGE_TABLE_LEVEL)
264 return 1;
852e3c19 265 if (is_large_pte(pte))
776e6633
MT		 266 return 1;
267 return 0;
268}
269
35149e21 270static pfn_t spte_to_pfn(u64 pte)
0b49ea86 271{
35149e21 272 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 273}
274
da928521
AK		 275static gfn_t pse36_gfn_delta(u32 gpte)
276{
277 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
278
279 return (gpte & PT32_DIR_PSE36_MASK) << shift;
280}
281
d555c333 282static void __set_spte(u64 *sptep, u64 spte)
e663ee64
AK		 283{
284#ifdef CONFIG_X86_64
285 set_64bit((unsigned long *)sptep, spte);
286#else
287 set_64bit((unsigned long long *)sptep, spte);
288#endif
289}
290
e2dec939 291static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 292 struct kmem_cache *base_cache, int min)
714b93da
AK		 293{
294 void *obj;
295
296 if (cache->nobjs >= min)
e2dec939 297 return 0;
714b93da 298 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 299 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 300 if (!obj)
e2dec939 301 return -ENOMEM;
714b93da
AK		 302 cache->objects[cache->nobjs++] = obj;
303 }
e2dec939 304 return 0;
714b93da
AK		 305}
306
307static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
308{
309 while (mc->nobjs)
310 kfree(mc->objects[--mc->nobjs]);
311}
312
c1158e63 313static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 314 int min)
c1158e63
AK		 315{
316 struct page *page;
317
318 if (cache->nobjs >= min)
319 return 0;
320 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 321 page = alloc_page(GFP_KERNEL);
c1158e63
AK		 322 if (!page)
323 return -ENOMEM;
c1158e63
AK		 324 cache->objects[cache->nobjs++] = page_address(page);
325 }
326 return 0;
327}
328
329static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
330{
331 while (mc->nobjs)
c4d198d5 332 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 333}
334
2e3e5882 335static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 336{
e2dec939
AK		 337 int r;
338
ad312c7c 339 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 340 pte_chain_cache, 4);
e2dec939
AK		 341 if (r)
342 goto out;
ad312c7c 343 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 344 rmap_desc_cache, 4);
d3d25b04
AK		 345 if (r)
346 goto out;
ad312c7c 347 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 348 if (r)
349 goto out;
ad312c7c 350 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 351 mmu_page_header_cache, 4);
e2dec939
AK		 352out:
353 return r;
714b93da
AK		 354}
355
356static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
357{
ad312c7c
ZX		 358 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
359 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
360 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
361 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
714b93da
AK		 362}
363
364static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
365 size_t size)
366{
367 void *p;
368
369 BUG_ON(!mc->nobjs);
370 p = mc->objects[--mc->nobjs];
714b93da
AK		 371 return p;
372}
373
714b93da
AK		 374static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
375{
ad312c7c 376 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
714b93da
AK		 377 sizeof(struct kvm_pte_chain));
378}
379
90cb0529 380static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 381{
90cb0529 382 kfree(pc);
714b93da
AK		 383}
384
385static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
386{
ad312c7c 387 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
714b93da
AK		 388 sizeof(struct kvm_rmap_desc));
389}
390
90cb0529 391static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 392{
90cb0529 393 kfree(rd);
714b93da
AK		 394}
395
05da4558
MT		 396/*
397 * Return the pointer to the largepage write count for a given
398 * gfn, handling slots that are not large page aligned.
399 */
d25797b2
JR		 400static int *slot_largepage_idx(gfn_t gfn,
401 struct kvm_memory_slot *slot,
402 int level)
05da4558
MT		 403{
404 unsigned long idx;
405
d25797b2
JR		 406 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
407 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
408 return &slot->lpage_info[level - 2][idx].write_count;
05da4558
MT		 409}
410
411static void account_shadowed(struct kvm *kvm, gfn_t gfn)
412{
d25797b2 413 struct kvm_memory_slot *slot;
05da4558 414 int *write_count;
d25797b2 415 int i;
05da4558 416
2843099f 417 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 418
419 slot = gfn_to_memslot_unaliased(kvm, gfn);
420 for (i = PT_DIRECTORY_LEVEL;
421 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
422 write_count = slot_largepage_idx(gfn, slot, i);
423 *write_count += 1;
424 }
05da4558
MT		 425}
426
427static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
428{
d25797b2 429 struct kvm_memory_slot *slot;
05da4558 430 int *write_count;
d25797b2 431 int i;
05da4558 432
2843099f 433 gfn = unalias_gfn(kvm, gfn);
77a1a715 434 slot = gfn_to_memslot_unaliased(kvm, gfn);
d25797b2
JR		 435 for (i = PT_DIRECTORY_LEVEL;
436 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
d25797b2
JR		 437 write_count = slot_largepage_idx(gfn, slot, i);
438 *write_count -= 1;
439 WARN_ON(*write_count < 0);
440 }
05da4558
MT		 441}
442
d25797b2
JR		 443static int has_wrprotected_page(struct kvm *kvm,
444 gfn_t gfn,
445 int level)
05da4558 446{
2843099f 447 struct kvm_memory_slot *slot;
05da4558
MT		 448 int *largepage_idx;
449
2843099f
IE		 450 gfn = unalias_gfn(kvm, gfn);
451 slot = gfn_to_memslot_unaliased(kvm, gfn);
05da4558 452 if (slot) {
d25797b2 453 largepage_idx = slot_largepage_idx(gfn, slot, level);
05da4558
MT		 454 return *largepage_idx;
455 }
456
457 return 1;
458}
459
d25797b2 460static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 461{
8f0b1ab6 462 unsigned long page_size;
d25797b2 463 int i, ret = 0;
05da4558 464
8f0b1ab6 465 page_size = kvm_host_page_size(kvm, gfn);
05da4558 466
d25797b2
JR		 467 for (i = PT_PAGE_TABLE_LEVEL;
468 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
469 if (page_size >= KVM_HPAGE_SIZE(i))
470 ret = i;
471 else
472 break;
473 }
474
4c2155ce 475 return ret;
05da4558
MT		 476}
477
d25797b2 478static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
05da4558
MT		 479{
480 struct kvm_memory_slot *slot;
878403b7 481 int host_level, level, max_level;
05da4558
MT		 482
483 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
484 if (slot && slot->dirty_bitmap)
d25797b2 485 return PT_PAGE_TABLE_LEVEL;
05da4558 486
d25797b2
JR		 487 host_level = host_mapping_level(vcpu->kvm, large_gfn);
488
489 if (host_level == PT_PAGE_TABLE_LEVEL)
490 return host_level;
491
878403b7
SY		 492 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
493 kvm_x86_ops->get_lpage_level() : host_level;
494
495 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
d25797b2
JR		 496 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
497 break;
d25797b2
JR		 498
499 return level - 1;
05da4558
MT		 500}
501
290fc38d
IE		 502/*
503 * Take gfn and return the reverse mapping to it.
504 * Note: gfn must be unaliased before this function get called
505 */
506
44ad9944 507static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
290fc38d
IE		 508{
509 struct kvm_memory_slot *slot;
05da4558 510 unsigned long idx;
290fc38d
IE		 511
512 slot = gfn_to_memslot(kvm, gfn);
44ad9944 513 if (likely(level == PT_PAGE_TABLE_LEVEL))
05da4558
MT		 514 return &slot->rmap[gfn - slot->base_gfn];
515
44ad9944
JR		 516 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
517 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
05da4558 518
44ad9944 519 return &slot->lpage_info[level - 2][idx].rmap_pde;
290fc38d
IE		 520}
521
cd4a4e53
AK		 522/*
523 * Reverse mapping data structures:
524 *
290fc38d
IE		 525 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
526 * that points to page_address(page).
cd4a4e53 527 *
290fc38d
IE		 528 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
529 * containing more mappings.
53a27b39
MT		 530 *
531 * Returns the number of rmap entries before the spte was added or zero if
532 * the spte was not added.
533 *
cd4a4e53 534 */
44ad9944 535static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 536{
4db35314 537 struct kvm_mmu_page *sp;
cd4a4e53 538 struct kvm_rmap_desc *desc;
290fc38d 539 unsigned long *rmapp;
53a27b39 540 int i, count = 0;
cd4a4e53 541
43a3795a 542 if (!is_rmap_spte(*spte))
53a27b39 543 return count;
290fc38d 544 gfn = unalias_gfn(vcpu->kvm, gfn);
4db35314
AK		 545 sp = page_header(__pa(spte));
546 sp->gfns[spte - sp->spt] = gfn;
44ad9944 547 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
290fc38d 548 if (!*rmapp) {
cd4a4e53 549 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE		 550 *rmapp = (unsigned long)spte;
551 } else if (!(*rmapp & 1)) {
cd4a4e53 552 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 553 desc = mmu_alloc_rmap_desc(vcpu);
d555c333
AK		 554 desc->sptes[0] = (u64 *)*rmapp;
555 desc->sptes[1] = spte;
290fc38d 556 *rmapp = (unsigned long)desc | 1;
cd4a4e53
AK		 557 } else {
558 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 559 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
d555c333 560 while (desc->sptes[RMAP_EXT-1] && desc->more) {
cd4a4e53 561 desc = desc->more;
53a27b39
MT		 562 count += RMAP_EXT;
563 }
d555c333 564 if (desc->sptes[RMAP_EXT-1]) {
714b93da 565 desc->more = mmu_alloc_rmap_desc(vcpu);
cd4a4e53
AK		 566 desc = desc->more;
567 }
d555c333 568 for (i = 0; desc->sptes[i]; ++i)
cd4a4e53 569 ;
d555c333 570 desc->sptes[i] = spte;
cd4a4e53 571 }
53a27b39 572 return count;
cd4a4e53
AK		 573}
574
290fc38d 575static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
AK		 576 struct kvm_rmap_desc *desc,
577 int i,
578 struct kvm_rmap_desc *prev_desc)
579{
580 int j;
581
d555c333 582 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 583 ;
d555c333
AK		 584 desc->sptes[i] = desc->sptes[j];
585 desc->sptes[j] = NULL;
cd4a4e53
AK		 586 if (j != 0)
587 return;
588 if (!prev_desc && !desc->more)
d555c333 589 *rmapp = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 590 else
591 if (prev_desc)
592 prev_desc->more = desc->more;
593 else
290fc38d 594 *rmapp = (unsigned long)desc->more | 1;
90cb0529 595 mmu_free_rmap_desc(desc);
cd4a4e53
AK		 596}
597
290fc38d 598static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 599{
cd4a4e53
AK		 600 struct kvm_rmap_desc *desc;
601 struct kvm_rmap_desc *prev_desc;
4db35314 602 struct kvm_mmu_page *sp;
35149e21 603 pfn_t pfn;
290fc38d 604 unsigned long *rmapp;
cd4a4e53
AK		 605 int i;
606
43a3795a 607 if (!is_rmap_spte(*spte))
cd4a4e53 608 return;
4db35314 609 sp = page_header(__pa(spte));
35149e21 610 pfn = spte_to_pfn(*spte);
7b52345e 611 if (*spte & shadow_accessed_mask)
35149e21 612 kvm_set_pfn_accessed(pfn);
8dae4445 613 if (is_writable_pte(*spte))
acb66dd0 614 kvm_set_pfn_dirty(pfn);
44ad9944 615 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
290fc38d 616 if (!*rmapp) {
cd4a4e53
AK		 617 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
618 BUG();
290fc38d 619 } else if (!(*rmapp & 1)) {
cd4a4e53 620 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 621 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK		 622 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
623 spte, *spte);
624 BUG();
625 }
290fc38d 626 *rmapp = 0;
cd4a4e53
AK		 627 } else {
628 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 629 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK		 630 prev_desc = NULL;
631 while (desc) {
d555c333
AK		 632 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
633 if (desc->sptes[i] == spte) {
290fc38d 634 rmap_desc_remove_entry(rmapp,
714b93da 635 desc, i,
cd4a4e53
AK		 636 prev_desc);
637 return;
638 }
639 prev_desc = desc;
640 desc = desc->more;
641 }
186a3e52 642 pr_err("rmap_remove: %p %llx many->many\n", spte, *spte);
cd4a4e53
AK		 643 BUG();
644 }
645}
646
98348e95 647static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 648{
374cbac0 649 struct kvm_rmap_desc *desc;
98348e95
IE		 650 u64 *prev_spte;
651 int i;
652
653 if (!*rmapp)
654 return NULL;
655 else if (!(*rmapp & 1)) {
656 if (!spte)
657 return (u64 *)*rmapp;
658 return NULL;
659 }
660 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
98348e95
IE		 661 prev_spte = NULL;
662 while (desc) {
d555c333 663 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
98348e95 664 if (prev_spte == spte)
d555c333
AK		 665 return desc->sptes[i];
666 prev_spte = desc->sptes[i];
98348e95
IE		 667 }
668 desc = desc->more;
669 }
670 return NULL;
671}
672
b1a36821 673static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 674{
290fc38d 675 unsigned long *rmapp;
374cbac0 676 u64 *spte;
44ad9944 677 int i, write_protected = 0;
374cbac0 678
4a4c9924 679 gfn = unalias_gfn(kvm, gfn);
44ad9944 680 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 681
98348e95
IE		 682 spte = rmap_next(kvm, rmapp, NULL);
683 while (spte) {
374cbac0 684 BUG_ON(!spte);
374cbac0 685 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 686 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
8dae4445 687 if (is_writable_pte(*spte)) {
d555c333 688 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 689 write_protected = 1;
690 }
9647c14c 691 spte = rmap_next(kvm, rmapp, spte);
374cbac0 692 }
855149aa 693 if (write_protected) {
35149e21 694 pfn_t pfn;
855149aa
IE		 695
696 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL		 697 pfn = spte_to_pfn(*spte);
698 kvm_set_pfn_dirty(pfn);
855149aa
IE		 699 }
700
05da4558 701 /* check for huge page mappings */
44ad9944
JR		 702 for (i = PT_DIRECTORY_LEVEL;
703 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
704 rmapp = gfn_to_rmap(kvm, gfn, i);
705 spte = rmap_next(kvm, rmapp, NULL);
706 while (spte) {
707 BUG_ON(!spte);
708 BUG_ON(!(*spte & PT_PRESENT_MASK));
709 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
710 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
8dae4445 711 if (is_writable_pte(*spte)) {
44ad9944
JR		 712 rmap_remove(kvm, spte);
713 --kvm->stat.lpages;
714 __set_spte(spte, shadow_trap_nonpresent_pte);
715 spte = NULL;
716 write_protected = 1;
717 }
718 spte = rmap_next(kvm, rmapp, spte);
05da4558 719 }
05da4558
MT		 720 }
721
b1a36821 722 return write_protected;
374cbac0
AK		 723}
724
8a8365c5
FD		 725static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
726 unsigned long data)
e930bffe
AA		 727{
728 u64 *spte;
729 int need_tlb_flush = 0;
730
731 while ((spte = rmap_next(kvm, rmapp, NULL))) {
732 BUG_ON(!(*spte & PT_PRESENT_MASK));
733 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
734 rmap_remove(kvm, spte);
d555c333 735 __set_spte(spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 736 need_tlb_flush = 1;
737 }
738 return need_tlb_flush;
739}
740
8a8365c5
FD		 741static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
742 unsigned long data)
3da0dd43
IE		 743{
744 int need_flush = 0;
745 u64 *spte, new_spte;
746 pte_t *ptep = (pte_t *)data;
747 pfn_t new_pfn;
748
749 WARN_ON(pte_huge(*ptep));
750 new_pfn = pte_pfn(*ptep);
751 spte = rmap_next(kvm, rmapp, NULL);
752 while (spte) {
753 BUG_ON(!is_shadow_present_pte(*spte));
754 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
755 need_flush = 1;
756 if (pte_write(*ptep)) {
757 rmap_remove(kvm, spte);
758 __set_spte(spte, shadow_trap_nonpresent_pte);
759 spte = rmap_next(kvm, rmapp, NULL);
760 } else {
761 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
762 new_spte |= (u64)new_pfn << PAGE_SHIFT;
763
764 new_spte &= ~PT_WRITABLE_MASK;
765 new_spte &= ~SPTE_HOST_WRITEABLE;
8dae4445 766 if (is_writable_pte(*spte))
3da0dd43
IE		 767 kvm_set_pfn_dirty(spte_to_pfn(*spte));
768 __set_spte(spte, new_spte);
769 spte = rmap_next(kvm, rmapp, spte);
770 }
771 }
772 if (need_flush)
773 kvm_flush_remote_tlbs(kvm);
774
775 return 0;
776}
777
8a8365c5
FD		 778static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
779 unsigned long data,
3da0dd43 780 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
8a8365c5 781 unsigned long data))
e930bffe 782{
852e3c19 783 int i, j;
90bb6fc5 784 int ret;
e930bffe 785 int retval = 0;
bc6678a3
MT		 786 struct kvm_memslots *slots;
787
90d83dc3 788 slots = kvm_memslots(kvm);
e930bffe 789
46a26bf5
MT		 790 for (i = 0; i < slots->nmemslots; i++) {
791 struct kvm_memory_slot *memslot = &slots->memslots[i];
e930bffe
AA		 792 unsigned long start = memslot->userspace_addr;
793 unsigned long end;
794
e930bffe
AA		 795 end = start + (memslot->npages << PAGE_SHIFT);
796 if (hva >= start && hva < end) {
797 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
852e3c19 798
90bb6fc5 799 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
852e3c19
JR		 800
801 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
802 int idx = gfn_offset;
803 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
90bb6fc5 804 ret |= handler(kvm,
3da0dd43
IE		 805 &memslot->lpage_info[j][idx].rmap_pde,
806 data);
852e3c19 807 }
90bb6fc5
AK		 808 trace_kvm_age_page(hva, memslot, ret);
809 retval |= ret;
e930bffe
AA		 810 }
811 }
812
813 return retval;
814}
815
816int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
817{
3da0dd43
IE		 818 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
819}
820
821void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
822{
8a8365c5 823 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA		 824}
825
8a8365c5
FD		 826static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
827 unsigned long data)
e930bffe
AA		 828{
829 u64 *spte;
830 int young = 0;
831
6316e1c8
RR		 832 /*
833 * Emulate the accessed bit for EPT, by checking if this page has
834 * an EPT mapping, and clearing it if it does. On the next access,
835 * a new EPT mapping will be established.
836 * This has some overhead, but not as much as the cost of swapping
837 * out actively used pages or breaking up actively used hugepages.
838 */
534e38b4 839 if (!shadow_accessed_mask)
6316e1c8 840 return kvm_unmap_rmapp(kvm, rmapp, data);
534e38b4 841
e930bffe
AA		 842 spte = rmap_next(kvm, rmapp, NULL);
843 while (spte) {
844 int _young;
845 u64 _spte = *spte;
846 BUG_ON(!(_spte & PT_PRESENT_MASK));
847 _young = _spte & PT_ACCESSED_MASK;
848 if (_young) {
849 young = 1;
850 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
851 }
852 spte = rmap_next(kvm, rmapp, spte);
853 }
854 return young;
855}
856
53a27b39
MT		 857#define RMAP_RECYCLE_THRESHOLD 1000
858
852e3c19 859static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 860{
861 unsigned long *rmapp;
852e3c19
JR		 862 struct kvm_mmu_page *sp;
863
864 sp = page_header(__pa(spte));
53a27b39
MT		 865
866 gfn = unalias_gfn(vcpu->kvm, gfn);
852e3c19 867 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 868
3da0dd43 869 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT		 870 kvm_flush_remote_tlbs(vcpu->kvm);
871}
872
e930bffe
AA		 873int kvm_age_hva(struct kvm *kvm, unsigned long hva)
874{
3da0dd43 875 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA		 876}
877
d6c69ee9 878#ifdef MMU_DEBUG
47ad8e68 879static int is_empty_shadow_page(u64 *spt)
6aa8b732 880{
139bdb2d
AK		 881 u64 *pos;
882 u64 *end;
883
47ad8e68 884 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 885 if (is_shadow_present_pte(*pos)) {
b8688d51 886 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 887 pos, *pos);
6aa8b732 888 return 0;
139bdb2d 889 }
6aa8b732
AK		 890 return 1;
891}
d6c69ee9 892#endif
6aa8b732 893
4db35314 894static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 895{
4db35314
AK		 896 ASSERT(is_empty_shadow_page(sp->spt));
897 list_del(&sp->link);
898 __free_page(virt_to_page(sp->spt));
899 __free_page(virt_to_page(sp->gfns));
900 kfree(sp);
f05e70ac 901 ++kvm->arch.n_free_mmu_pages;
260746c0
AK		 902}
903
cea0f0e7
AK		 904static unsigned kvm_page_table_hashfn(gfn_t gfn)
905{
1ae0a13d 906 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 907}
908
25c0de2c
AK		 909static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
910 u64 *parent_pte)
6aa8b732 911{
4db35314 912 struct kvm_mmu_page *sp;
6aa8b732 913
ad312c7c
ZX		 914 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
915 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
916 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 917 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 918 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
291f26bc 919 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK		 920 sp->multimapped = 0;
921 sp->parent_pte = parent_pte;
f05e70ac 922 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 923 return sp;
6aa8b732
AK		 924}
925
714b93da 926static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 927 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK		 928{
929 struct kvm_pte_chain *pte_chain;
930 struct hlist_node *node;
931 int i;
932
933 if (!parent_pte)
934 return;
4db35314
AK		 935 if (!sp->multimapped) {
936 u64 *old = sp->parent_pte;
cea0f0e7
AK		 937
938 if (!old) {
4db35314 939 sp->parent_pte = parent_pte;
cea0f0e7
AK		 940 return;
941 }
4db35314 942 sp->multimapped = 1;
714b93da 943 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK		 944 INIT_HLIST_HEAD(&sp->parent_ptes);
945 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 946 pte_chain->parent_ptes[0] = old;
947 }
4db35314 948 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK		 949 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
950 continue;
951 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
952 if (!pte_chain->parent_ptes[i]) {
953 pte_chain->parent_ptes[i] = parent_pte;
954 return;
955 }
956 }
714b93da 957 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 958 BUG_ON(!pte_chain);
4db35314 959 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 960 pte_chain->parent_ptes[0] = parent_pte;
961}
962
4db35314 963static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 964 u64 *parent_pte)
965{
966 struct kvm_pte_chain *pte_chain;
967 struct hlist_node *node;
968 int i;
969
4db35314
AK		 970 if (!sp->multimapped) {
971 BUG_ON(sp->parent_pte != parent_pte);
972 sp->parent_pte = NULL;
cea0f0e7
AK		 973 return;
974 }
4db35314 975 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK		 976 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
977 if (!pte_chain->parent_ptes[i])
978 break;
979 if (pte_chain->parent_ptes[i] != parent_pte)
980 continue;
697fe2e2
AK		 981 while (i + 1 < NR_PTE_CHAIN_ENTRIES
982 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK		 983 pte_chain->parent_ptes[i]
984 = pte_chain->parent_ptes[i + 1];
985 ++i;
986 }
987 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK		 988 if (i == 0) {
989 hlist_del(&pte_chain->link);
90cb0529 990 mmu_free_pte_chain(pte_chain);
4db35314
AK		 991 if (hlist_empty(&sp->parent_ptes)) {
992 sp->multimapped = 0;
993 sp->parent_pte = NULL;
697fe2e2
AK		 994 }
995 }
cea0f0e7
AK		 996 return;
997 }
998 BUG();
999}
1000
ad8cfbe3 1001
6b18493d 1002static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn)
ad8cfbe3
MT		 1003{
1004 struct kvm_pte_chain *pte_chain;
1005 struct hlist_node *node;
1006 struct kvm_mmu_page *parent_sp;
1007 int i;
1008
1009 if (!sp->multimapped && sp->parent_pte) {
1010 parent_sp = page_header(__pa(sp->parent_pte));
6b18493d
XG		 1011 fn(parent_sp);
1012 mmu_parent_walk(parent_sp, fn);
ad8cfbe3
MT		 1013 return;
1014 }
1015 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1016 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1017 if (!pte_chain->parent_ptes[i])
1018 break;
1019 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
6b18493d
XG		 1020 fn(parent_sp);
1021 mmu_parent_walk(parent_sp, fn);
ad8cfbe3
MT		 1022 }
1023}
1024
0074ff63
MT		 1025static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1026{
1027 unsigned int index;
1028 struct kvm_mmu_page *sp = page_header(__pa(spte));
1029
1030 index = spte - sp->spt;
60c8aec6
MT		 1031 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1032 sp->unsync_children++;
1033 WARN_ON(!sp->unsync_children);
0074ff63
MT		 1034}
1035
1036static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1037{
1038 struct kvm_pte_chain *pte_chain;
1039 struct hlist_node *node;
1040 int i;
1041
1042 if (!sp->parent_pte)
1043 return;
1044
1045 if (!sp->multimapped) {
1046 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1047 return;
1048 }
1049
1050 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1051 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1052 if (!pte_chain->parent_ptes[i])
1053 break;
1054 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1055 }
1056}
1057
6b18493d 1058static int unsync_walk_fn(struct kvm_mmu_page *sp)
0074ff63 1059{
0074ff63
MT		 1060 kvm_mmu_update_parents_unsync(sp);
1061 return 1;
1062}
1063
6b18493d 1064static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
0074ff63 1065{
6b18493d 1066 mmu_parent_walk(sp, unsync_walk_fn);
0074ff63
MT		 1067 kvm_mmu_update_parents_unsync(sp);
1068}
1069
d761a501
AK		 1070static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1071 struct kvm_mmu_page *sp)
1072{
1073 int i;
1074
1075 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1076 sp->spt[i] = shadow_trap_nonpresent_pte;
1077}
1078
e8bc217a
MT		 1079static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1080 struct kvm_mmu_page *sp)
1081{
1082 return 1;
1083}
1084
a7052897
MT		 1085static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1086{
1087}
1088
60c8aec6
MT		 1089#define KVM_PAGE_ARRAY_NR 16
1090
1091struct kvm_mmu_pages {
1092 struct mmu_page_and_offset {
1093 struct kvm_mmu_page *sp;
1094 unsigned int idx;
1095 } page[KVM_PAGE_ARRAY_NR];
1096 unsigned int nr;
1097};
1098
0074ff63
MT		 1099#define for_each_unsync_children(bitmap, idx) \
1100 for (idx = find_first_bit(bitmap, 512); \
1101 idx < 512; \
1102 idx = find_next_bit(bitmap, 512, idx+1))
1103
cded19f3
HE		 1104static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1105 int idx)
4731d4c7 1106{
60c8aec6 1107 int i;
4731d4c7 1108
60c8aec6
MT		 1109 if (sp->unsync)
1110 for (i=0; i < pvec->nr; i++)
1111 if (pvec->page[i].sp == sp)
1112 return 0;
1113
1114 pvec->page[pvec->nr].sp = sp;
1115 pvec->page[pvec->nr].idx = idx;
1116 pvec->nr++;
1117 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1118}
1119
1120static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1121 struct kvm_mmu_pages *pvec)
1122{
1123 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1124
0074ff63 1125 for_each_unsync_children(sp->unsync_child_bitmap, i) {
4731d4c7
MT		 1126 u64 ent = sp->spt[i];
1127
87917239 1128 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
4731d4c7
MT		 1129 struct kvm_mmu_page *child;
1130 child = page_header(ent & PT64_BASE_ADDR_MASK);
1131
1132 if (child->unsync_children) {
60c8aec6
MT		 1133 if (mmu_pages_add(pvec, child, i))
1134 return -ENOSPC;
1135
1136 ret = __mmu_unsync_walk(child, pvec);
1137 if (!ret)
1138 __clear_bit(i, sp->unsync_child_bitmap);
1139 else if (ret > 0)
1140 nr_unsync_leaf += ret;
1141 else
4731d4c7
MT		 1142 return ret;
1143 }
1144
1145 if (child->unsync) {
60c8aec6
MT		 1146 nr_unsync_leaf++;
1147 if (mmu_pages_add(pvec, child, i))
1148 return -ENOSPC;
4731d4c7
MT		 1149 }
1150 }
1151 }
1152
0074ff63 1153 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
4731d4c7
MT		 1154 sp->unsync_children = 0;
1155
60c8aec6
MT		 1156 return nr_unsync_leaf;
1157}
1158
1159static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1160 struct kvm_mmu_pages *pvec)
1161{
1162 if (!sp->unsync_children)
1163 return 0;
1164
1165 mmu_pages_add(pvec, sp, 0);
1166 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1167}
1168
4db35314 1169static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
cea0f0e7
AK		 1170{
1171 unsigned index;
1172 struct hlist_head *bucket;
4db35314 1173 struct kvm_mmu_page *sp;
cea0f0e7
AK		 1174 struct hlist_node *node;
1175
b8688d51 1176 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1ae0a13d 1177 index = kvm_page_table_hashfn(gfn);
f05e70ac 1178 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1179 hlist_for_each_entry(sp, node, bucket, hash_link)
f6e2c02b 1180 if (sp->gfn == gfn && !sp->role.direct
2e53d63a 1181 && !sp->role.invalid) {
cea0f0e7 1182 pgprintk("%s: found role %x\n",
b8688d51 1183 __func__, sp->role.word);
4db35314 1184 return sp;
cea0f0e7
AK		 1185 }
1186 return NULL;
1187}
1188
4731d4c7
MT		 1189static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1190{
1191 WARN_ON(!sp->unsync);
5e1b3ddb 1192 trace_kvm_mmu_sync_page(sp);
4731d4c7
MT		 1193 sp->unsync = 0;
1194 --kvm->stat.mmu_unsync;
1195}
1196
1197static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1198
1199static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1200{
5b7e0102 1201 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
4731d4c7
MT		 1202 kvm_mmu_zap_page(vcpu->kvm, sp);
1203 return 1;
1204 }
1205
b1a36821
MT		 1206 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1207 kvm_flush_remote_tlbs(vcpu->kvm);
0c0f40bd 1208 kvm_unlink_unsync_page(vcpu->kvm, sp);
4731d4c7
MT		 1209 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1210 kvm_mmu_zap_page(vcpu->kvm, sp);
1211 return 1;
1212 }
1213
1214 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1215 return 0;
1216}
1217
60c8aec6
MT		 1218struct mmu_page_path {
1219 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1220 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1221};
1222
60c8aec6
MT		 1223#define for_each_sp(pvec, sp, parents, i) \
1224 for (i = mmu_pages_next(&pvec, &parents, -1), \
1225 sp = pvec.page[i].sp; \
1226 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1227 i = mmu_pages_next(&pvec, &parents, i))
1228
cded19f3
HE		 1229static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1230 struct mmu_page_path *parents,
1231 int i)
60c8aec6
MT		 1232{
1233 int n;
1234
1235 for (n = i+1; n < pvec->nr; n++) {
1236 struct kvm_mmu_page *sp = pvec->page[n].sp;
1237
1238 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1239 parents->idx[0] = pvec->page[n].idx;
1240 return n;
1241 }
1242
1243 parents->parent[sp->role.level-2] = sp;
1244 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1245 }
1246
1247 return n;
1248}
1249
cded19f3 1250static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1251{
60c8aec6
MT		 1252 struct kvm_mmu_page *sp;
1253 unsigned int level = 0;
1254
1255 do {
1256 unsigned int idx = parents->idx[level];
4731d4c7 1257
60c8aec6
MT		 1258 sp = parents->parent[level];
1259 if (!sp)
1260 return;
1261
1262 --sp->unsync_children;
1263 WARN_ON((int)sp->unsync_children < 0);
1264 __clear_bit(idx, sp->unsync_child_bitmap);
1265 level++;
1266 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1267}
1268
60c8aec6
MT		 1269static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1270 struct mmu_page_path *parents,
1271 struct kvm_mmu_pages *pvec)
4731d4c7 1272{
60c8aec6
MT		 1273 parents->parent[parent->role.level-1] = NULL;
1274 pvec->nr = 0;
1275}
4731d4c7 1276
60c8aec6
MT		 1277static void mmu_sync_children(struct kvm_vcpu *vcpu,
1278 struct kvm_mmu_page *parent)
1279{
1280 int i;
1281 struct kvm_mmu_page *sp;
1282 struct mmu_page_path parents;
1283 struct kvm_mmu_pages pages;
1284
1285 kvm_mmu_pages_init(parent, &parents, &pages);
1286 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1287 int protected = 0;
1288
1289 for_each_sp(pages, sp, parents, i)
1290 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1291
1292 if (protected)
1293 kvm_flush_remote_tlbs(vcpu->kvm);
1294
60c8aec6
MT		 1295 for_each_sp(pages, sp, parents, i) {
1296 kvm_sync_page(vcpu, sp);
1297 mmu_pages_clear_parents(&parents);
1298 }
4731d4c7 1299 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1300 kvm_mmu_pages_init(parent, &parents, &pages);
1301 }
4731d4c7
MT		 1302}
1303
cea0f0e7
AK		 1304static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1305 gfn_t gfn,
1306 gva_t gaddr,
1307 unsigned level,
f6e2c02b 1308 int direct,
41074d07 1309 unsigned access,
f7d9c7b7 1310 u64 *parent_pte)
cea0f0e7
AK		 1311{
1312 union kvm_mmu_page_role role;
1313 unsigned index;
1314 unsigned quadrant;
1315 struct hlist_head *bucket;
4db35314 1316 struct kvm_mmu_page *sp;
4731d4c7 1317 struct hlist_node *node, *tmp;
cea0f0e7 1318
a770f6f2 1319 role = vcpu->arch.mmu.base_role;
cea0f0e7 1320 role.level = level;
f6e2c02b 1321 role.direct = direct;
84b0c8c6 1322 if (role.direct)
5b7e0102 1323 role.cr4_pae = 0;
41074d07 1324 role.access = access;
ad312c7c 1325 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1326 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1327 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1328 role.quadrant = quadrant;
1329 }
1ae0a13d 1330 index = kvm_page_table_hashfn(gfn);
f05e70ac 1331 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4731d4c7
MT		 1332 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1333 if (sp->gfn == gfn) {
1334 if (sp->unsync)
1335 if (kvm_sync_page(vcpu, sp))
1336 continue;
1337
1338 if (sp->role.word != role.word)
1339 continue;
1340
4db35314 1341 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
0074ff63
MT		 1342 if (sp->unsync_children) {
1343 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
6b18493d 1344 kvm_mmu_mark_parents_unsync(sp);
0074ff63 1345 }
f691fe1d 1346 trace_kvm_mmu_get_page(sp, false);
4db35314 1347 return sp;
cea0f0e7 1348 }
dfc5aa00 1349 ++vcpu->kvm->stat.mmu_cache_miss;
4db35314
AK		 1350 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1351 if (!sp)
1352 return sp;
4db35314
AK		 1353 sp->gfn = gfn;
1354 sp->role = role;
1355 hlist_add_head(&sp->hash_link, bucket);
f6e2c02b 1356 if (!direct) {
b1a36821
MT		 1357 if (rmap_write_protect(vcpu->kvm, gfn))
1358 kvm_flush_remote_tlbs(vcpu->kvm);
4731d4c7
MT		 1359 account_shadowed(vcpu->kvm, gfn);
1360 }
131d8279
AK		 1361 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1362 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1363 else
1364 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1365 trace_kvm_mmu_get_page(sp, true);
4db35314 1366 return sp;
cea0f0e7
AK		 1367}
1368
2d11123a
AK		 1369static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1370 struct kvm_vcpu *vcpu, u64 addr)
1371{
1372 iterator->addr = addr;
1373 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1374 iterator->level = vcpu->arch.mmu.shadow_root_level;
1375 if (iterator->level == PT32E_ROOT_LEVEL) {
1376 iterator->shadow_addr
1377 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1378 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1379 --iterator->level;
1380 if (!iterator->shadow_addr)
1381 iterator->level = 0;
1382 }
1383}
1384
1385static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1386{
1387 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1388 return false;
4d88954d
MT		 1389
1390 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1391 if (is_large_pte(*iterator->sptep))
1392 return false;
1393
2d11123a
AK		 1394 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1395 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1396 return true;
1397}
1398
1399static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1400{
1401 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1402 --iterator->level;
1403}
1404
90cb0529 1405static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1406 struct kvm_mmu_page *sp)
a436036b 1407{
697fe2e2
AK		 1408 unsigned i;
1409 u64 *pt;
1410 u64 ent;
1411
4db35314 1412 pt = sp->spt;
697fe2e2 1413
697fe2e2
AK		 1414 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1415 ent = pt[i];
1416
05da4558 1417 if (is_shadow_present_pte(ent)) {
776e6633 1418 if (!is_last_spte(ent, sp->role.level)) {
05da4558
MT		 1419 ent &= PT64_BASE_ADDR_MASK;
1420 mmu_page_remove_parent_pte(page_header(ent),
1421 &pt[i]);
1422 } else {
776e6633
MT		 1423 if (is_large_pte(ent))
1424 --kvm->stat.lpages;
05da4558
MT		 1425 rmap_remove(kvm, &pt[i]);
1426 }
1427 }
c7addb90 1428 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1429 }
a436036b
AK		 1430}
1431
4db35314 1432static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1433{
4db35314 1434 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1435}
1436
12b7d28f
AK		 1437static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1438{
1439 int i;
988a2cae 1440 struct kvm_vcpu *vcpu;
12b7d28f 1441
988a2cae
GN		 1442 kvm_for_each_vcpu(i, vcpu, kvm)
1443 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1444}
1445
31aa2b44 1446static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1447{
1448 u64 *parent_pte;
1449
4db35314
AK		 1450 while (sp->multimapped || sp->parent_pte) {
1451 if (!sp->multimapped)
1452 parent_pte = sp->parent_pte;
a436036b
AK		 1453 else {
1454 struct kvm_pte_chain *chain;
1455
4db35314 1456 chain = container_of(sp->parent_ptes.first,
a436036b
AK		 1457 struct kvm_pte_chain, link);
1458 parent_pte = chain->parent_ptes[0];
1459 }
697fe2e2 1460 BUG_ON(!parent_pte);
4db35314 1461 kvm_mmu_put_page(sp, parent_pte);
d555c333 1462 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1463 }
31aa2b44
AK		 1464}
1465
60c8aec6
MT		 1466static int mmu_zap_unsync_children(struct kvm *kvm,
1467 struct kvm_mmu_page *parent)
4731d4c7 1468{
60c8aec6
MT		 1469 int i, zapped = 0;
1470 struct mmu_page_path parents;
1471 struct kvm_mmu_pages pages;
4731d4c7 1472
60c8aec6 1473 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1474 return 0;
60c8aec6
MT		 1475
1476 kvm_mmu_pages_init(parent, &parents, &pages);
1477 while (mmu_unsync_walk(parent, &pages)) {
1478 struct kvm_mmu_page *sp;
1479
1480 for_each_sp(pages, sp, parents, i) {
1481 kvm_mmu_zap_page(kvm, sp);
1482 mmu_pages_clear_parents(&parents);
77662e00 1483 zapped++;
60c8aec6 1484 }
60c8aec6
MT		 1485 kvm_mmu_pages_init(parent, &parents, &pages);
1486 }
1487
1488 return zapped;
4731d4c7
MT		 1489}
1490
07385413 1491static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
31aa2b44 1492{
4731d4c7 1493 int ret;
f691fe1d
AK		 1494
1495 trace_kvm_mmu_zap_page(sp);
31aa2b44 1496 ++kvm->stat.mmu_shadow_zapped;
4731d4c7 1497 ret = mmu_zap_unsync_children(kvm, sp);
4db35314 1498 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1499 kvm_mmu_unlink_parents(kvm, sp);
5b5c6a5a 1500 kvm_flush_remote_tlbs(kvm);
f6e2c02b 1501 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1502 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1503 if (sp->unsync)
1504 kvm_unlink_unsync_page(kvm, sp);
4db35314
AK		 1505 if (!sp->root_count) {
1506 hlist_del(&sp->hash_link);
1507 kvm_mmu_free_page(kvm, sp);
2e53d63a 1508 } else {
2e53d63a 1509 sp->role.invalid = 1;
5b5c6a5a 1510 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1511 kvm_reload_remote_mmus(kvm);
1512 }
12b7d28f 1513 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1514 return ret;
a436036b
AK		 1515}
1516
82ce2c96
IE		 1517/*
1518 * Changing the number of mmu pages allocated to the vm
1519 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1520 */
1521void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1522{
025dbbf3
MT		 1523 int used_pages;
1524
1525 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1526 used_pages = max(0, used_pages);
1527
82ce2c96
IE		 1528 /*
1529 * If we set the number of mmu pages to be smaller be than the
1530 * number of actived pages , we must to free some mmu pages before we
1531 * change the value
1532 */
1533
025dbbf3 1534 if (used_pages > kvm_nr_mmu_pages) {
77662e00
XG		 1535 while (used_pages > kvm_nr_mmu_pages &&
1536 !list_empty(&kvm->arch.active_mmu_pages)) {
82ce2c96
IE		 1537 struct kvm_mmu_page *page;
1538
f05e70ac 1539 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96 1540 struct kvm_mmu_page, link);
77662e00 1541 used_pages -= kvm_mmu_zap_page(kvm, page);
025dbbf3 1542 used_pages--;
82ce2c96 1543 }
77662e00 1544 kvm_nr_mmu_pages = used_pages;
f05e70ac 1545 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE		 1546 }
1547 else
f05e70ac
ZX		 1548 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1549 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1550
f05e70ac 1551 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE		 1552}
1553
f67a46f4 1554static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK		 1555{
1556 unsigned index;
1557 struct hlist_head *bucket;
4db35314 1558 struct kvm_mmu_page *sp;
a436036b
AK		 1559 struct hlist_node *node, *n;
1560 int r;
1561
b8688d51 1562 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1563 r = 0;
1ae0a13d 1564 index = kvm_page_table_hashfn(gfn);
f05e70ac 1565 bucket = &kvm->arch.mmu_page_hash[index];
3246af0e 1566restart:
4db35314 1567 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
f6e2c02b 1568 if (sp->gfn == gfn && !sp->role.direct) {
b8688d51 1569 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
4db35314 1570 sp->role.word);
a436036b 1571 r = 1;
07385413 1572 if (kvm_mmu_zap_page(kvm, sp))
3246af0e 1573 goto restart;
a436036b
AK		 1574 }
1575 return r;
cea0f0e7
AK		 1576}
1577
f67a46f4 1578static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1579{
4677a3b6
AK		 1580 unsigned index;
1581 struct hlist_head *bucket;
4db35314 1582 struct kvm_mmu_page *sp;
4677a3b6 1583 struct hlist_node *node, *nn;
97a0a01e 1584
4677a3b6
AK		 1585 index = kvm_page_table_hashfn(gfn);
1586 bucket = &kvm->arch.mmu_page_hash[index];
3246af0e 1587restart:
4677a3b6 1588 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
f6e2c02b 1589 if (sp->gfn == gfn && !sp->role.direct
4677a3b6
AK		 1590 && !sp->role.invalid) {
1591 pgprintk("%s: zap %lx %x\n",
1592 __func__, gfn, sp->role.word);
77662e00 1593 if (kvm_mmu_zap_page(kvm, sp))
3246af0e 1594 goto restart;
4677a3b6 1595 }
97a0a01e
AK		 1596 }
1597}
1598
38c335f1 1599static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1600{
bc6678a3 1601 int slot = memslot_id(kvm, gfn);
4db35314 1602 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1603
291f26bc 1604 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1605}
1606
6844dec6
MT		 1607static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1608{
1609 int i;
1610 u64 *pt = sp->spt;
1611
1612 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1613 return;
1614
1615 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1616 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1617 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1618 }
1619}
1620
74be52e3
SY		 1621/*
1622 * The function is based on mtrr_type_lookup() in
1623 * arch/x86/kernel/cpu/mtrr/generic.c
1624 */
1625static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1626 u64 start, u64 end)
1627{
1628 int i;
1629 u64 base, mask;
1630 u8 prev_match, curr_match;
1631 int num_var_ranges = KVM_NR_VAR_MTRR;
1632
1633 if (!mtrr_state->enabled)
1634 return 0xFF;
1635
1636 /* Make end inclusive end, instead of exclusive */
1637 end--;
1638
1639 /* Look in fixed ranges. Just return the type as per start */
1640 if (mtrr_state->have_fixed && (start < 0x100000)) {
1641 int idx;
1642
1643 if (start < 0x80000) {
1644 idx = 0;
1645 idx += (start >> 16);
1646 return mtrr_state->fixed_ranges[idx];
1647 } else if (start < 0xC0000) {
1648 idx = 1 * 8;
1649 idx += ((start - 0x80000) >> 14);
1650 return mtrr_state->fixed_ranges[idx];
1651 } else if (start < 0x1000000) {
1652 idx = 3 * 8;
1653 idx += ((start - 0xC0000) >> 12);
1654 return mtrr_state->fixed_ranges[idx];
1655 }
1656 }
1657
1658 /*
1659 * Look in variable ranges
1660 * Look of multiple ranges matching this address and pick type
1661 * as per MTRR precedence
1662 */
1663 if (!(mtrr_state->enabled & 2))
1664 return mtrr_state->def_type;
1665
1666 prev_match = 0xFF;
1667 for (i = 0; i < num_var_ranges; ++i) {
1668 unsigned short start_state, end_state;
1669
1670 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1671 continue;
1672
1673 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1674 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1675 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1676 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1677
1678 start_state = ((start & mask) == (base & mask));
1679 end_state = ((end & mask) == (base & mask));
1680 if (start_state != end_state)
1681 return 0xFE;
1682
1683 if ((start & mask) != (base & mask))
1684 continue;
1685
1686 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1687 if (prev_match == 0xFF) {
1688 prev_match = curr_match;
1689 continue;
1690 }
1691
1692 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1693 curr_match == MTRR_TYPE_UNCACHABLE)
1694 return MTRR_TYPE_UNCACHABLE;
1695
1696 if ((prev_match == MTRR_TYPE_WRBACK &&
1697 curr_match == MTRR_TYPE_WRTHROUGH) ||
1698 (prev_match == MTRR_TYPE_WRTHROUGH &&
1699 curr_match == MTRR_TYPE_WRBACK)) {
1700 prev_match = MTRR_TYPE_WRTHROUGH;
1701 curr_match = MTRR_TYPE_WRTHROUGH;
1702 }
1703
1704 if (prev_match != curr_match)
1705 return MTRR_TYPE_UNCACHABLE;
1706 }
1707
1708 if (prev_match != 0xFF)
1709 return prev_match;
1710
1711 return mtrr_state->def_type;
1712}
1713
4b12f0de 1714u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1715{
1716 u8 mtrr;
1717
1718 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1719 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1720 if (mtrr == 0xfe || mtrr == 0xff)
1721 mtrr = MTRR_TYPE_WRBACK;
1722 return mtrr;
1723}
4b12f0de 1724EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1725
4731d4c7
MT		 1726static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1727{
1728 unsigned index;
1729 struct hlist_head *bucket;
1730 struct kvm_mmu_page *s;
1731 struct hlist_node *node, *n;
1732
1733 index = kvm_page_table_hashfn(sp->gfn);
1734 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1735 /* don't unsync if pagetable is shadowed with multiple roles */
1736 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
f6e2c02b 1737 if (s->gfn != sp->gfn || s->role.direct)
4731d4c7
MT		 1738 continue;
1739 if (s->role.word != sp->role.word)
1740 return 1;
1741 }
5e1b3ddb 1742 trace_kvm_mmu_unsync_page(sp);
4731d4c7
MT		 1743 ++vcpu->kvm->stat.mmu_unsync;
1744 sp->unsync = 1;
6cffe8ca 1745
6b18493d 1746 kvm_mmu_mark_parents_unsync(sp);
6cffe8ca 1747
4731d4c7
MT		 1748 mmu_convert_notrap(sp);
1749 return 0;
1750}
1751
1752static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1753 bool can_unsync)
1754{
1755 struct kvm_mmu_page *shadow;
1756
1757 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1758 if (shadow) {
1759 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1760 return 1;
1761 if (shadow->unsync)
1762 return 0;
582801a9 1763 if (can_unsync && oos_shadow)
4731d4c7
MT		 1764 return kvm_unsync_page(vcpu, shadow);
1765 return 1;
1766 }
1767 return 0;
1768}
1769
d555c333 1770static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1771 unsigned pte_access, int user_fault,
852e3c19 1772 int write_fault, int dirty, int level,
c2d0ee46 1773 gfn_t gfn, pfn_t pfn, bool speculative,
1403283a 1774 bool can_unsync, bool reset_host_protection)
1c4f1fd6
AK		 1775{
1776 u64 spte;
1e73f9dd 1777 int ret = 0;
64d4d521 1778
1c4f1fd6
AK		 1779 /*
1780 * We don't set the accessed bit, since we sometimes want to see
1781 * whether the guest actually used the pte (in order to detect
1782 * demand paging).
1783 */
7b52345e 1784 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1785 if (!speculative)
3201b5d9 1786 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1787 if (!dirty)
1788 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1789 if (pte_access & ACC_EXEC_MASK)
1790 spte |= shadow_x_mask;
1791 else
1792 spte |= shadow_nx_mask;
1c4f1fd6 1793 if (pte_access & ACC_USER_MASK)
7b52345e 1794 spte |= shadow_user_mask;
852e3c19 1795 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1796 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY		 1797 if (tdp_enabled)
1798 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1799 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1800
1403283a
IE		 1801 if (reset_host_protection)
1802 spte |= SPTE_HOST_WRITEABLE;
1803
35149e21 1804 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1805
1806 if ((pte_access & ACC_WRITE_MASK)
1807 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1808
852e3c19
JR		 1809 if (level > PT_PAGE_TABLE_LEVEL &&
1810 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83
MT		 1811 ret = 1;
1812 spte = shadow_trap_nonpresent_pte;
1813 goto set_pte;
1814 }
1815
1c4f1fd6 1816 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1817
69325a12
AK		 1818 if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK))
1819 spte &= ~PT_USER_MASK;
1820
ecc5589f
MT		 1821 /*
1822 * Optimization: for pte sync, if spte was writable the hash
1823 * lookup is unnecessary (and expensive). Write protection
1824 * is responsibility of mmu_get_page / kvm_sync_page.
1825 * Same reasoning can be applied to dirty page accounting.
1826 */
8dae4445 1827 if (!can_unsync && is_writable_pte(*sptep))
ecc5589f
MT		 1828 goto set_pte;
1829
4731d4c7 1830 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1831 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1832 __func__, gfn);
1e73f9dd 1833 ret = 1;
1c4f1fd6 1834 pte_access &= ~ACC_WRITE_MASK;
8dae4445 1835 if (is_writable_pte(spte))
1c4f1fd6 1836 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 1837 }
1838 }
1839
1c4f1fd6
AK		 1840 if (pte_access & ACC_WRITE_MASK)
1841 mark_page_dirty(vcpu->kvm, gfn);
1842
38187c83 1843set_pte:
d555c333 1844 __set_spte(sptep, spte);
1e73f9dd
MT		 1845 return ret;
1846}
1847
d555c333 1848static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 1849 unsigned pt_access, unsigned pte_access,
1850 int user_fault, int write_fault, int dirty,
852e3c19 1851 int *ptwrite, int level, gfn_t gfn,
1403283a
IE		 1852 pfn_t pfn, bool speculative,
1853 bool reset_host_protection)
1e73f9dd
MT		 1854{
1855 int was_rmapped = 0;
8dae4445 1856 int was_writable = is_writable_pte(*sptep);
53a27b39 1857 int rmap_count;
1e73f9dd
MT		 1858
1859 pgprintk("%s: spte %llx access %x write_fault %d"
1860 " user_fault %d gfn %lx\n",
d555c333 1861 __func__, *sptep, pt_access,
1e73f9dd
MT		 1862 write_fault, user_fault, gfn);
1863
d555c333 1864 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 1865 /*
1866 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1867 * the parent of the now unreachable PTE.
1868 */
852e3c19
JR		 1869 if (level > PT_PAGE_TABLE_LEVEL &&
1870 !is_large_pte(*sptep)) {
1e73f9dd 1871 struct kvm_mmu_page *child;
d555c333 1872 u64 pte = *sptep;
1e73f9dd
MT		 1873
1874 child = page_header(pte & PT64_BASE_ADDR_MASK);
d555c333 1875 mmu_page_remove_parent_pte(child, sptep);
3be2264b
MT		 1876 __set_spte(sptep, shadow_trap_nonpresent_pte);
1877 kvm_flush_remote_tlbs(vcpu->kvm);
d555c333 1878 } else if (pfn != spte_to_pfn(*sptep)) {
1e73f9dd 1879 pgprintk("hfn old %lx new %lx\n",
d555c333
AK		 1880 spte_to_pfn(*sptep), pfn);
1881 rmap_remove(vcpu->kvm, sptep);
6bed6b9e
JR		 1882 } else
1883 was_rmapped = 1;
1e73f9dd 1884 }
852e3c19 1885
d555c333 1886 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a
IE		 1887 dirty, level, gfn, pfn, speculative, true,
1888 reset_host_protection)) {
1e73f9dd
MT		 1889 if (write_fault)
1890 *ptwrite = 1;
a378b4e6
MT		 1891 kvm_x86_ops->tlb_flush(vcpu);
1892 }
1e73f9dd 1893
d555c333 1894 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1e73f9dd 1895 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
d555c333 1896 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 1897 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1898 *sptep, sptep);
d555c333 1899 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 1900 ++vcpu->kvm->stat.lpages;
1901
d555c333 1902 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 1903 if (!was_rmapped) {
44ad9944 1904 rmap_count = rmap_add(vcpu, sptep, gfn);
acb66dd0 1905 kvm_release_pfn_clean(pfn);
53a27b39 1906 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 1907 rmap_recycle(vcpu, sptep, gfn);
75e68e60 1908 } else {
8dae4445 1909 if (was_writable)
35149e21 1910 kvm_release_pfn_dirty(pfn);
75e68e60 1911 else
35149e21 1912 kvm_release_pfn_clean(pfn);
1c4f1fd6 1913 }
1b7fcd32 1914 if (speculative) {
d555c333 1915 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 1916 vcpu->arch.last_pte_gfn = gfn;
1917 }
1c4f1fd6
AK		 1918}
1919
6aa8b732
AK		 1920static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1921{
1922}
1923
9f652d21 1924static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
852e3c19 1925 int level, gfn_t gfn, pfn_t pfn)
140754bc 1926{
9f652d21 1927 struct kvm_shadow_walk_iterator iterator;
140754bc 1928 struct kvm_mmu_page *sp;
9f652d21 1929 int pt_write = 0;
140754bc 1930 gfn_t pseudo_gfn;
6aa8b732 1931
9f652d21 1932 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 1933 if (iterator.level == level) {
9f652d21
AK		 1934 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1935 0, write, 1, &pt_write,
1403283a 1936 level, gfn, pfn, false, true);
9f652d21
AK		 1937 ++vcpu->stat.pf_fixed;
1938 break;
6aa8b732
AK		 1939 }
1940
9f652d21
AK		 1941 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1942 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1943 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1944 iterator.level - 1,
1945 1, ACC_ALL, iterator.sptep);
1946 if (!sp) {
1947 pgprintk("nonpaging_map: ENOMEM\n");
1948 kvm_release_pfn_clean(pfn);
1949 return -ENOMEM;
1950 }
140754bc 1951
d555c333
AK		 1952 __set_spte(iterator.sptep,
1953 __pa(sp->spt)
1954 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1955 | shadow_user_mask | shadow_x_mask);
9f652d21
AK		 1956 }
1957 }
1958 return pt_write;
6aa8b732
AK		 1959}
1960
10589a46
MT		 1961static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1962{
1963 int r;
852e3c19 1964 int level;
35149e21 1965 pfn_t pfn;
e930bffe 1966 unsigned long mmu_seq;
aaee2c94 1967
852e3c19
JR		 1968 level = mapping_level(vcpu, gfn);
1969
1970 /*
1971 * This path builds a PAE pagetable - so we can map 2mb pages at
1972 * maximum. Therefore check if the level is larger than that.
1973 */
1974 if (level > PT_DIRECTORY_LEVEL)
1975 level = PT_DIRECTORY_LEVEL;
1976
1977 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 1978
e930bffe 1979 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 1980 smp_rmb();
35149e21 1981 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 1982
d196e343 1983 /* mmio */
35149e21
AL		 1984 if (is_error_pfn(pfn)) {
1985 kvm_release_pfn_clean(pfn);
d196e343
AK		 1986 return 1;
1987 }
1988
aaee2c94 1989 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 1990 if (mmu_notifier_retry(vcpu, mmu_seq))
1991 goto out_unlock;
eb787d10 1992 kvm_mmu_free_some_pages(vcpu);
852e3c19 1993 r = __direct_map(vcpu, v, write, level, gfn, pfn);
aaee2c94
MT		 1994 spin_unlock(&vcpu->kvm->mmu_lock);
1995
aaee2c94 1996
10589a46 1997 return r;
e930bffe
AA		 1998
1999out_unlock:
2000 spin_unlock(&vcpu->kvm->mmu_lock);
2001 kvm_release_pfn_clean(pfn);
2002 return 0;
10589a46
MT		 2003}
2004
2005
17ac10ad
AK		 2006static void mmu_free_roots(struct kvm_vcpu *vcpu)
2007{
2008 int i;
4db35314 2009 struct kvm_mmu_page *sp;
17ac10ad 2010
ad312c7c 2011 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2012 return;
aaee2c94 2013 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX		 2014 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2015 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2016
4db35314
AK		 2017 sp = page_header(root);
2018 --sp->root_count;
2e53d63a
MT		 2019 if (!sp->root_count && sp->role.invalid)
2020 kvm_mmu_zap_page(vcpu->kvm, sp);
ad312c7c 2021 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2022 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2023 return;
2024 }
17ac10ad 2025 for (i = 0; i < 4; ++i) {
ad312c7c 2026 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2027
417726a3 2028 if (root) {
417726a3 2029 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 2030 sp = page_header(root);
2031 --sp->root_count;
2e53d63a
MT		 2032 if (!sp->root_count && sp->role.invalid)
2033 kvm_mmu_zap_page(vcpu->kvm, sp);
417726a3 2034 }
ad312c7c 2035 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2036 }
aaee2c94 2037 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2038 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2039}
2040
8986ecc0
MT		 2041static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2042{
2043 int ret = 0;
2044
2045 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2046 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2047 ret = 1;
2048 }
2049
2050 return ret;
2051}
2052
2053static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK		 2054{
2055 int i;
cea0f0e7 2056 gfn_t root_gfn;
4db35314 2057 struct kvm_mmu_page *sp;
f6e2c02b 2058 int direct = 0;
6de4f3ad 2059 u64 pdptr;
3bb65a22 2060
ad312c7c 2061 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 2062
ad312c7c
ZX		 2063 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2064 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2065
2066 ASSERT(!VALID_PAGE(root));
8986ecc0
MT		 2067 if (mmu_check_root(vcpu, root_gfn))
2068 return 1;
5a7388c2
EN		 2069 if (tdp_enabled) {
2070 direct = 1;
2071 root_gfn = 0;
2072 }
8facbbff 2073 spin_lock(&vcpu->kvm->mmu_lock);
4db35314 2074 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 2075 PT64_ROOT_LEVEL, direct,
fb72d167 2076 ACC_ALL, NULL);
4db35314
AK		 2077 root = __pa(sp->spt);
2078 ++sp->root_count;
8facbbff 2079 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2080 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2081 return 0;
17ac10ad 2082 }
f6e2c02b 2083 direct = !is_paging(vcpu);
17ac10ad 2084 for (i = 0; i < 4; ++i) {
ad312c7c 2085 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2086
2087 ASSERT(!VALID_PAGE(root));
ad312c7c 2088 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
6de4f3ad 2089 pdptr = kvm_pdptr_read(vcpu, i);
43a3795a 2090 if (!is_present_gpte(pdptr)) {
ad312c7c 2091 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2092 continue;
2093 }
6de4f3ad 2094 root_gfn = pdptr >> PAGE_SHIFT;
ad312c7c 2095 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 2096 root_gfn = 0;
8986ecc0
MT		 2097 if (mmu_check_root(vcpu, root_gfn))
2098 return 1;
5a7388c2
EN		 2099 if (tdp_enabled) {
2100 direct = 1;
2101 root_gfn = i << 30;
2102 }
8facbbff 2103 spin_lock(&vcpu->kvm->mmu_lock);
4db35314 2104 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 2105 PT32_ROOT_LEVEL, direct,
f7d9c7b7 2106 ACC_ALL, NULL);
4db35314
AK		 2107 root = __pa(sp->spt);
2108 ++sp->root_count;
8facbbff
AK		 2109 spin_unlock(&vcpu->kvm->mmu_lock);
2110
ad312c7c 2111 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 2112 }
ad312c7c 2113 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 2114 return 0;
17ac10ad
AK		 2115}
2116
0ba73cda
MT		 2117static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2118{
2119 int i;
2120 struct kvm_mmu_page *sp;
2121
2122 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2123 return;
2124 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2125 hpa_t root = vcpu->arch.mmu.root_hpa;
2126 sp = page_header(root);
2127 mmu_sync_children(vcpu, sp);
2128 return;
2129 }
2130 for (i = 0; i < 4; ++i) {
2131 hpa_t root = vcpu->arch.mmu.pae_root[i];
2132
8986ecc0 2133 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2134 root &= PT64_BASE_ADDR_MASK;
2135 sp = page_header(root);
2136 mmu_sync_children(vcpu, sp);
2137 }
2138 }
2139}
2140
2141void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2142{
2143 spin_lock(&vcpu->kvm->mmu_lock);
2144 mmu_sync_roots(vcpu);
6cffe8ca 2145 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2146}
2147
1871c602
GN		 2148static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2149 u32 access, u32 *error)
6aa8b732 2150{
1871c602
GN		 2151 if (error)
2152 *error = 0;
6aa8b732
AK		 2153 return vaddr;
2154}
2155
2156static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2157 u32 error_code)
6aa8b732 2158{
e833240f 2159 gfn_t gfn;
e2dec939 2160 int r;
6aa8b732 2161
b8688d51 2162 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2163 r = mmu_topup_memory_caches(vcpu);
2164 if (r)
2165 return r;
714b93da 2166
6aa8b732 2167 ASSERT(vcpu);
ad312c7c 2168 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2169
e833240f 2170 gfn = gva >> PAGE_SHIFT;
6aa8b732 2171
e833240f
AK		 2172 return nonpaging_map(vcpu, gva & PAGE_MASK,
2173 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK		 2174}
2175
fb72d167
JR		 2176static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2177 u32 error_code)
2178{
35149e21 2179 pfn_t pfn;
fb72d167 2180 int r;
852e3c19 2181 int level;
05da4558 2182 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2183 unsigned long mmu_seq;
fb72d167
JR		 2184
2185 ASSERT(vcpu);
2186 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2187
2188 r = mmu_topup_memory_caches(vcpu);
2189 if (r)
2190 return r;
2191
852e3c19
JR		 2192 level = mapping_level(vcpu, gfn);
2193
2194 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2195
e930bffe 2196 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2197 smp_rmb();
35149e21 2198 pfn = gfn_to_pfn(vcpu->kvm, gfn);
35149e21
AL		 2199 if (is_error_pfn(pfn)) {
2200 kvm_release_pfn_clean(pfn);
fb72d167
JR		 2201 return 1;
2202 }
2203 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2204 if (mmu_notifier_retry(vcpu, mmu_seq))
2205 goto out_unlock;
fb72d167
JR		 2206 kvm_mmu_free_some_pages(vcpu);
2207 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
852e3c19 2208 level, gfn, pfn);
fb72d167 2209 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2210
2211 return r;
e930bffe
AA		 2212
2213out_unlock:
2214 spin_unlock(&vcpu->kvm->mmu_lock);
2215 kvm_release_pfn_clean(pfn);
2216 return 0;
fb72d167
JR		 2217}
2218
6aa8b732
AK		 2219static void nonpaging_free(struct kvm_vcpu *vcpu)
2220{
17ac10ad 2221 mmu_free_roots(vcpu);
6aa8b732
AK		 2222}
2223
2224static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2225{
ad312c7c 2226 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2227
2228 context->new_cr3 = nonpaging_new_cr3;
2229 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2230 context->gva_to_gpa = nonpaging_gva_to_gpa;
2231 context->free = nonpaging_free;
c7addb90 2232 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2233 context->sync_page = nonpaging_sync_page;
a7052897 2234 context->invlpg = nonpaging_invlpg;
cea0f0e7 2235 context->root_level = 0;
6aa8b732 2236 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2237 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2238 return 0;
2239}
2240
d835dfec 2241void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2242{
1165f5fe 2243 ++vcpu->stat.tlb_flush;
cbdd1bea 2244 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK		 2245}
2246
2247static void paging_new_cr3(struct kvm_vcpu *vcpu)
2248{
b8688d51 2249 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2250 mmu_free_roots(vcpu);
6aa8b732
AK		 2251}
2252
6aa8b732
AK		 2253static void inject_page_fault(struct kvm_vcpu *vcpu,
2254 u64 addr,
2255 u32 err_code)
2256{
c3c91fee 2257 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK		 2258}
2259
6aa8b732
AK		 2260static void paging_free(struct kvm_vcpu *vcpu)
2261{
2262 nonpaging_free(vcpu);
2263}
2264
82725b20
DE		 2265static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2266{
2267 int bit7;
2268
2269 bit7 = (gpte >> 7) & 1;
2270 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2271}
2272
6aa8b732
AK		 2273#define PTTYPE 64
2274#include "paging_tmpl.h"
2275#undef PTTYPE
2276
2277#define PTTYPE 32
2278#include "paging_tmpl.h"
2279#undef PTTYPE
2280
82725b20
DE		 2281static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2282{
2283 struct kvm_mmu *context = &vcpu->arch.mmu;
2284 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2285 u64 exb_bit_rsvd = 0;
2286
2287 if (!is_nx(vcpu))
2288 exb_bit_rsvd = rsvd_bits(63, 63);
2289 switch (level) {
2290 case PT32_ROOT_LEVEL:
2291 /* no rsvd bits for 2 level 4K page table entries */
2292 context->rsvd_bits_mask[0][1] = 0;
2293 context->rsvd_bits_mask[0][0] = 0;
f815bce8
XG		 2294 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2295
2296 if (!is_pse(vcpu)) {
2297 context->rsvd_bits_mask[1][1] = 0;
2298 break;
2299 }
2300
82725b20
DE		 2301 if (is_cpuid_PSE36())
2302 /* 36bits PSE 4MB page */
2303 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2304 else
2305 /* 32 bits PSE 4MB page */
2306 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
82725b20
DE		 2307 break;
2308 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2309 context->rsvd_bits_mask[0][2] =
2310 rsvd_bits(maxphyaddr, 63) |
2311 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2312 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2313 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2314 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2315 rsvd_bits(maxphyaddr, 62); /* PTE */
2316 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2317 rsvd_bits(maxphyaddr, 62) |
2318 rsvd_bits(13, 20); /* large page */
f815bce8 2319 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2320 break;
2321 case PT64_ROOT_LEVEL:
2322 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2323 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2324 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2325 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2326 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2327 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2328 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2329 rsvd_bits(maxphyaddr, 51);
2330 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR		 2331 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2332 rsvd_bits(maxphyaddr, 51) |
2333 rsvd_bits(13, 29);
82725b20 2334 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2335 rsvd_bits(maxphyaddr, 51) |
2336 rsvd_bits(13, 20); /* large page */
f815bce8 2337 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2338 break;
2339 }
2340}
2341
17ac10ad 2342static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2343{
ad312c7c 2344 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2345
2346 ASSERT(is_pae(vcpu));
2347 context->new_cr3 = paging_new_cr3;
2348 context->page_fault = paging64_page_fault;
6aa8b732 2349 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2350 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2351 context->sync_page = paging64_sync_page;
a7052897 2352 context->invlpg = paging64_invlpg;
6aa8b732 2353 context->free = paging_free;
17ac10ad
AK		 2354 context->root_level = level;
2355 context->shadow_root_level = level;
17c3ba9d 2356 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2357 return 0;
2358}
2359
17ac10ad
AK		 2360static int paging64_init_context(struct kvm_vcpu *vcpu)
2361{
82725b20 2362 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK		 2363 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2364}
2365
6aa8b732
AK		 2366static int paging32_init_context(struct kvm_vcpu *vcpu)
2367{
ad312c7c 2368 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2369
82725b20 2370 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK		 2371 context->new_cr3 = paging_new_cr3;
2372 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2373 context->gva_to_gpa = paging32_gva_to_gpa;
2374 context->free = paging_free;
c7addb90 2375 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2376 context->sync_page = paging32_sync_page;
a7052897 2377 context->invlpg = paging32_invlpg;
6aa8b732
AK		 2378 context->root_level = PT32_ROOT_LEVEL;
2379 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2380 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2381 return 0;
2382}
2383
2384static int paging32E_init_context(struct kvm_vcpu *vcpu)
2385{
82725b20 2386 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2387 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2388}
2389
fb72d167
JR		 2390static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2391{
2392 struct kvm_mmu *context = &vcpu->arch.mmu;
2393
2394 context->new_cr3 = nonpaging_new_cr3;
2395 context->page_fault = tdp_page_fault;
2396 context->free = nonpaging_free;
2397 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2398 context->sync_page = nonpaging_sync_page;
a7052897 2399 context->invlpg = nonpaging_invlpg;
67253af5 2400 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR		 2401 context->root_hpa = INVALID_PAGE;
2402
2403 if (!is_paging(vcpu)) {
2404 context->gva_to_gpa = nonpaging_gva_to_gpa;
2405 context->root_level = 0;
2406 } else if (is_long_mode(vcpu)) {
82725b20 2407 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR		 2408 context->gva_to_gpa = paging64_gva_to_gpa;
2409 context->root_level = PT64_ROOT_LEVEL;
2410 } else if (is_pae(vcpu)) {
82725b20 2411 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR		 2412 context->gva_to_gpa = paging64_gva_to_gpa;
2413 context->root_level = PT32E_ROOT_LEVEL;
2414 } else {
82725b20 2415 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR		 2416 context->gva_to_gpa = paging32_gva_to_gpa;
2417 context->root_level = PT32_ROOT_LEVEL;
2418 }
2419
2420 return 0;
2421}
2422
2423static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2424{
a770f6f2
AK		 2425 int r;
2426
6aa8b732 2427 ASSERT(vcpu);
ad312c7c 2428 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2429
2430 if (!is_paging(vcpu))
a770f6f2 2431 r = nonpaging_init_context(vcpu);
a9058ecd 2432 else if (is_long_mode(vcpu))
a770f6f2 2433 r = paging64_init_context(vcpu);
6aa8b732 2434 else if (is_pae(vcpu))
a770f6f2 2435 r = paging32E_init_context(vcpu);
6aa8b732 2436 else
a770f6f2
AK		 2437 r = paging32_init_context(vcpu);
2438
5b7e0102 2439 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3dbe1415 2440 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
a770f6f2
AK		 2441
2442 return r;
6aa8b732
AK		 2443}
2444
fb72d167
JR		 2445static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2446{
35149e21
AL		 2447 vcpu->arch.update_pte.pfn = bad_pfn;
2448
fb72d167
JR		 2449 if (tdp_enabled)
2450 return init_kvm_tdp_mmu(vcpu);
2451 else
2452 return init_kvm_softmmu(vcpu);
2453}
2454
6aa8b732
AK		 2455static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2456{
2457 ASSERT(vcpu);
ad312c7c
ZX		 2458 if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
2459 vcpu->arch.mmu.free(vcpu);
2460 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6aa8b732
AK		 2461 }
2462}
2463
2464int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 2465{
2466 destroy_kvm_mmu(vcpu);
2467 return init_kvm_mmu(vcpu);
2468}
8668a3c4 2469EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 2470
2471int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2472{
714b93da
AK		 2473 int r;
2474
e2dec939 2475 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 2476 if (r)
2477 goto out;
aaee2c94 2478 spin_lock(&vcpu->kvm->mmu_lock);
eb787d10 2479 kvm_mmu_free_some_pages(vcpu);
8facbbff 2480 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0 2481 r = mmu_alloc_roots(vcpu);
8facbbff 2482 spin_lock(&vcpu->kvm->mmu_lock);
0ba73cda 2483 mmu_sync_roots(vcpu);
aaee2c94 2484 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 2485 if (r)
2486 goto out;
3662cb1c 2487 /* set_cr3() should ensure TLB has been flushed */
ad312c7c 2488 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 2489out:
2490 return r;
6aa8b732 2491}
17c3ba9d
AK		 2492EXPORT_SYMBOL_GPL(kvm_mmu_load);
2493
2494void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2495{
2496 mmu_free_roots(vcpu);
2497}
6aa8b732 2498
09072daf 2499static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2500 struct kvm_mmu_page *sp,
ac1b714e
AK		 2501 u64 *spte)
2502{
2503 u64 pte;
2504 struct kvm_mmu_page *child;
2505
2506 pte = *spte;
c7addb90 2507 if (is_shadow_present_pte(pte)) {
776e6633 2508 if (is_last_spte(pte, sp->role.level))
290fc38d 2509 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK		 2510 else {
2511 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2512 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK		 2513 }
2514 }
d555c333 2515 __set_spte(spte, shadow_trap_nonpresent_pte);
05da4558
MT		 2516 if (is_large_pte(pte))
2517 --vcpu->kvm->stat.lpages;
ac1b714e
AK		 2518}
2519
0028425f 2520static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2521 struct kvm_mmu_page *sp,
0028425f 2522 u64 *spte,
489f1d65 2523 const void *new)
0028425f 2524{
30945387 2525 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR		 2526 ++vcpu->kvm->stat.mmu_pde_zapped;
2527 return;
30945387 2528 }
0028425f 2529
4cee5764 2530 ++vcpu->kvm->stat.mmu_pte_updated;
5b7e0102 2531 if (!sp->role.cr4_pae)
489f1d65 2532 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2533 else
489f1d65 2534 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK		 2535}
2536
79539cec
AK		 2537static bool need_remote_flush(u64 old, u64 new)
2538{
2539 if (!is_shadow_present_pte(old))
2540 return false;
2541 if (!is_shadow_present_pte(new))
2542 return true;
2543 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2544 return true;
2545 old ^= PT64_NX_MASK;
2546 new ^= PT64_NX_MASK;
2547 return (old & ~new & PT64_PERM_MASK) != 0;
2548}
2549
2550static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2551{
2552 if (need_remote_flush(old, new))
2553 kvm_flush_remote_tlbs(vcpu->kvm);
2554 else
2555 kvm_mmu_flush_tlb(vcpu);
2556}
2557
12b7d28f
AK		 2558static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2559{
ad312c7c 2560 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2561
7b52345e 2562 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 2563}
2564
d7824fff 2565static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
72016f3a 2566 u64 gpte)
d7824fff
AK		 2567{
2568 gfn_t gfn;
35149e21 2569 pfn_t pfn;
d7824fff 2570
43a3795a 2571 if (!is_present_gpte(gpte))
d7824fff
AK		 2572 return;
2573 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2574
e930bffe 2575 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2576 smp_rmb();
35149e21 2577 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2578
35149e21
AL		 2579 if (is_error_pfn(pfn)) {
2580 kvm_release_pfn_clean(pfn);
d196e343
AK		 2581 return;
2582 }
d7824fff 2583 vcpu->arch.update_pte.gfn = gfn;
35149e21 2584 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK		 2585}
2586
1b7fcd32
AK		 2587static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2588{
2589 u64 *spte = vcpu->arch.last_pte_updated;
2590
2591 if (spte
2592 && vcpu->arch.last_pte_gfn == gfn
2593 && shadow_accessed_mask
2594 && !(*spte & shadow_accessed_mask)
2595 && is_shadow_present_pte(*spte))
2596 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2597}
2598
09072daf 2599void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 2600 const u8 *new, int bytes,
2601 bool guest_initiated)
da4a00f0 2602{
9b7a0325 2603 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2604 struct kvm_mmu_page *sp;
0e7bc4b9 2605 struct hlist_node *node, *n;
9b7a0325
AK		 2606 struct hlist_head *bucket;
2607 unsigned index;
489f1d65 2608 u64 entry, gentry;
9b7a0325 2609 u64 *spte;
9b7a0325 2610 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2611 unsigned pte_size;
9b7a0325 2612 unsigned page_offset;
0e7bc4b9 2613 unsigned misaligned;
fce0657f 2614 unsigned quadrant;
9b7a0325 2615 int level;
86a5ba02 2616 int flooded = 0;
ac1b714e 2617 int npte;
489f1d65 2618 int r;
08e850c6 2619 int invlpg_counter;
9b7a0325 2620
b8688d51 2621 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
72016f3a 2622
08e850c6 2623 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
72016f3a
AK		 2624
2625 /*
2626 * Assume that the pte write on a page table of the same type
2627 * as the current vcpu paging mode. This is nearly always true
2628 * (might be false while changing modes). Note it is verified later
2629 * by update_pte().
2630 */
08e850c6 2631 if ((is_pae(vcpu) && bytes == 4) || !new) {
72016f3a 2632 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
08e850c6
AK		 2633 if (is_pae(vcpu)) {
2634 gpa &= ~(gpa_t)7;
2635 bytes = 8;
2636 }
2637 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
72016f3a
AK		 2638 if (r)
2639 gentry = 0;
08e850c6
AK		 2640 new = (const u8 *)&gentry;
2641 }
2642
2643 switch (bytes) {
2644 case 4:
2645 gentry = *(const u32 *)new;
2646 break;
2647 case 8:
2648 gentry = *(const u64 *)new;
2649 break;
2650 default:
2651 gentry = 0;
2652 break;
72016f3a
AK		 2653 }
2654
2655 mmu_guess_page_from_pte_write(vcpu, gpa, gentry);
aaee2c94 2656 spin_lock(&vcpu->kvm->mmu_lock);
08e850c6
AK		 2657 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
2658 gentry = 0;
1b7fcd32 2659 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2660 kvm_mmu_free_some_pages(vcpu);
4cee5764 2661 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2662 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT		 2663 if (guest_initiated) {
2664 if (gfn == vcpu->arch.last_pt_write_gfn
2665 && !last_updated_pte_accessed(vcpu)) {
2666 ++vcpu->arch.last_pt_write_count;
2667 if (vcpu->arch.last_pt_write_count >= 3)
2668 flooded = 1;
2669 } else {
2670 vcpu->arch.last_pt_write_gfn = gfn;
2671 vcpu->arch.last_pt_write_count = 1;
2672 vcpu->arch.last_pte_updated = NULL;
2673 }
86a5ba02 2674 }
1ae0a13d 2675 index = kvm_page_table_hashfn(gfn);
f05e70ac 2676 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
3246af0e
XG		 2677
2678restart:
4db35314 2679 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
f6e2c02b 2680 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
9b7a0325 2681 continue;
5b7e0102 2682 pte_size = sp->role.cr4_pae ? 8 : 4;
0e7bc4b9 2683 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2684 misaligned |= bytes < 4;
86a5ba02 2685 if (misaligned || flooded) {
0e7bc4b9
AK		 2686 /*
2687 * Misaligned accesses are too much trouble to fix
2688 * up; also, they usually indicate a page is not used
2689 * as a page table.
86a5ba02
AK		 2690 *
2691 * If we're seeing too many writes to a page,
2692 * it may no longer be a page table, or we may be
2693 * forking, in which case it is better to unmap the
2694 * page.
0e7bc4b9
AK		 2695 */
2696 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2697 gpa, bytes, sp->role.word);
07385413 2698 if (kvm_mmu_zap_page(vcpu->kvm, sp))
3246af0e 2699 goto restart;
4cee5764 2700 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 2701 continue;
2702 }
9b7a0325 2703 page_offset = offset;
4db35314 2704 level = sp->role.level;
ac1b714e 2705 npte = 1;
5b7e0102 2706 if (!sp->role.cr4_pae) {
ac1b714e
AK		 2707 page_offset <<= 1; /* 32->64 */
2708 /*
2709 * A 32-bit pde maps 4MB while the shadow pdes map
2710 * only 2MB. So we need to double the offset again
2711 * and zap two pdes instead of one.
2712 */
2713 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2714 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 2715 page_offset <<= 1;
2716 npte = 2;
2717 }
fce0657f 2718 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2719 page_offset &= ~PAGE_MASK;
4db35314 2720 if (quadrant != sp->role.quadrant)
fce0657f 2721 continue;
9b7a0325 2722 }
4db35314 2723 spte = &sp->spt[page_offset / sizeof(*spte)];
ac1b714e 2724 while (npte--) {
79539cec 2725 entry = *spte;
4db35314 2726 mmu_pte_write_zap_pte(vcpu, sp, spte);
72016f3a
AK		 2727 if (gentry)
2728 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
79539cec 2729 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 2730 ++spte;
9b7a0325 2731 }
9b7a0325 2732 }
c7addb90 2733 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2734 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL		 2735 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2736 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2737 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2738 }
da4a00f0
AK		 2739}
2740
a436036b
AK		 2741int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2742{
10589a46
MT		 2743 gpa_t gpa;
2744 int r;
a436036b 2745
60f24784
AK		 2746 if (tdp_enabled)
2747 return 0;
2748
1871c602 2749 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
10589a46 2750
aaee2c94 2751 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2752 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2753 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2754 return r;
a436036b 2755}
577bdc49 2756EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2757
22d95b12 2758void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2759{
3b80fffe
IE		 2760 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
2761 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 2762 struct kvm_mmu_page *sp;
ebeace86 2763
f05e70ac 2764 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK		 2765 struct kvm_mmu_page, link);
2766 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 2767 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK		 2768 }
2769}
ebeace86 2770
3067714c
AK		 2771int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2772{
2773 int r;
2774 enum emulation_result er;
2775
ad312c7c 2776 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK		 2777 if (r < 0)
2778 goto out;
2779
2780 if (!r) {
2781 r = 1;
2782 goto out;
2783 }
2784
b733bfb5
AK		 2785 r = mmu_topup_memory_caches(vcpu);
2786 if (r)
2787 goto out;
2788
851ba692 2789 er = emulate_instruction(vcpu, cr2, error_code, 0);
3067714c
AK		 2790
2791 switch (er) {
2792 case EMULATE_DONE:
2793 return 1;
2794 case EMULATE_DO_MMIO:
2795 ++vcpu->stat.mmio_exits;
2796 return 0;
2797 case EMULATE_FAIL:
3f5d18a9
AK		 2798 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2799 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 2800 vcpu->run->internal.ndata = 0;
3f5d18a9 2801 return 0;
3067714c
AK		 2802 default:
2803 BUG();
2804 }
2805out:
3067714c
AK		 2806 return r;
2807}
2808EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2809
a7052897
MT		 2810void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2811{
a7052897 2812 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 2813 kvm_mmu_flush_tlb(vcpu);
2814 ++vcpu->stat.invlpg;
2815}
2816EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2817
18552672
JR		 2818void kvm_enable_tdp(void)
2819{
2820 tdp_enabled = true;
2821}
2822EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2823
5f4cb662
JR		 2824void kvm_disable_tdp(void)
2825{
2826 tdp_enabled = false;
2827}
2828EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2829
6aa8b732
AK		 2830static void free_mmu_pages(struct kvm_vcpu *vcpu)
2831{
ad312c7c 2832 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK		 2833}
2834
2835static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2836{
17ac10ad 2837 struct page *page;
6aa8b732
AK		 2838 int i;
2839
2840 ASSERT(vcpu);
2841
17ac10ad
AK		 2842 /*
2843 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2844 * Therefore we need to allocate shadow page tables in the first
2845 * 4GB of memory, which happens to fit the DMA32 zone.
2846 */
2847 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2848 if (!page)
d7fa6ab2
WY		 2849 return -ENOMEM;
2850
ad312c7c 2851 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2852 for (i = 0; i < 4; ++i)
ad312c7c 2853 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2854
6aa8b732 2855 return 0;
6aa8b732
AK		 2856}
2857
8018c27b 2858int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 2859{
6aa8b732 2860 ASSERT(vcpu);
ad312c7c 2861 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2862
8018c27b
IM		 2863 return alloc_mmu_pages(vcpu);
2864}
6aa8b732 2865
8018c27b
IM		 2866int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2867{
2868 ASSERT(vcpu);
ad312c7c 2869 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 2870
8018c27b 2871 return init_kvm_mmu(vcpu);
6aa8b732
AK		 2872}
2873
2874void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2875{
2876 ASSERT(vcpu);
2877
2878 destroy_kvm_mmu(vcpu);
2879 free_mmu_pages(vcpu);
714b93da 2880 mmu_free_memory_caches(vcpu);
6aa8b732
AK		 2881}
2882
90cb0529 2883void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 2884{
4db35314 2885 struct kvm_mmu_page *sp;
6aa8b732 2886
f05e70ac 2887 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 2888 int i;
2889 u64 *pt;
2890
291f26bc 2891 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 2892 continue;
2893
4db35314 2894 pt = sp->spt;
6aa8b732
AK		 2895 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2896 /* avoid RMW */
9647c14c 2897 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 2898 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 2899 }
171d595d 2900 kvm_flush_remote_tlbs(kvm);
6aa8b732 2901}
37a7d8b0 2902
90cb0529 2903void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 2904{
4db35314 2905 struct kvm_mmu_page *sp, *node;
e0fa826f 2906
aaee2c94 2907 spin_lock(&kvm->mmu_lock);
3246af0e 2908restart:
f05e70ac 2909 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
07385413 2910 if (kvm_mmu_zap_page(kvm, sp))
3246af0e
XG		 2911 goto restart;
2912
aaee2c94 2913 spin_unlock(&kvm->mmu_lock);
e0fa826f 2914
90cb0529 2915 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL		 2916}
2917
d35b8dd9 2918static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm)
3ee16c81
IE		 2919{
2920 struct kvm_mmu_page *page;
2921
2922 page = container_of(kvm->arch.active_mmu_pages.prev,
2923 struct kvm_mmu_page, link);
d35b8dd9 2924 return kvm_mmu_zap_page(kvm, page) + 1;
3ee16c81
IE		 2925}
2926
2927static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask)
2928{
2929 struct kvm *kvm;
2930 struct kvm *kvm_freed = NULL;
2931 int cache_count = 0;
2932
2933 spin_lock(&kvm_lock);
2934
2935 list_for_each_entry(kvm, &vm_list, vm_list) {
d35b8dd9 2936 int npages, idx, freed_pages;
3ee16c81 2937
f656ce01 2938 idx = srcu_read_lock(&kvm->srcu);
3ee16c81
IE		 2939 spin_lock(&kvm->mmu_lock);
2940 npages = kvm->arch.n_alloc_mmu_pages -
2941 kvm->arch.n_free_mmu_pages;
2942 cache_count += npages;
2943 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
d35b8dd9
GJ		 2944 freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm);
2945 cache_count -= freed_pages;
3ee16c81
IE		 2946 kvm_freed = kvm;
2947 }
2948 nr_to_scan--;
2949
2950 spin_unlock(&kvm->mmu_lock);
f656ce01 2951 srcu_read_unlock(&kvm->srcu, idx);
3ee16c81
IE		 2952 }
2953 if (kvm_freed)
2954 list_move_tail(&kvm_freed->vm_list, &vm_list);
2955
2956 spin_unlock(&kvm_lock);
2957
2958 return cache_count;
2959}
2960
2961static struct shrinker mmu_shrinker = {
2962 .shrink = mmu_shrink,
2963 .seeks = DEFAULT_SEEKS * 10,
2964};
2965
2ddfd20e 2966static void mmu_destroy_caches(void)
b5a33a75
AK		 2967{
2968 if (pte_chain_cache)
2969 kmem_cache_destroy(pte_chain_cache);
2970 if (rmap_desc_cache)
2971 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK		 2972 if (mmu_page_header_cache)
2973 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 2974}
2975
3ee16c81
IE		 2976void kvm_mmu_module_exit(void)
2977{
2978 mmu_destroy_caches();
2979 unregister_shrinker(&mmu_shrinker);
2980}
2981
b5a33a75
AK		 2982int kvm_mmu_module_init(void)
2983{
2984 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
2985 sizeof(struct kvm_pte_chain),
20c2df83 2986 0, 0, NULL);
b5a33a75
AK		 2987 if (!pte_chain_cache)
2988 goto nomem;
2989 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
2990 sizeof(struct kvm_rmap_desc),
20c2df83 2991 0, 0, NULL);
b5a33a75
AK		 2992 if (!rmap_desc_cache)
2993 goto nomem;
2994
d3d25b04
AK		 2995 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
2996 sizeof(struct kvm_mmu_page),
20c2df83 2997 0, 0, NULL);
d3d25b04
AK		 2998 if (!mmu_page_header_cache)
2999 goto nomem;
3000
3ee16c81
IE		 3001 register_shrinker(&mmu_shrinker);
3002
b5a33a75
AK		 3003 return 0;
3004
3005nomem:
3ee16c81 3006 mmu_destroy_caches();
b5a33a75
AK		 3007 return -ENOMEM;
3008}
3009
3ad82a7e
ZX		 3010/*
3011 * Caculate mmu pages needed for kvm.
3012 */
3013unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3014{
3015 int i;
3016 unsigned int nr_mmu_pages;
3017 unsigned int nr_pages = 0;
bc6678a3 3018 struct kvm_memslots *slots;
3ad82a7e 3019
90d83dc3
LJ		 3020 slots = kvm_memslots(kvm);
3021
bc6678a3
MT		 3022 for (i = 0; i < slots->nmemslots; i++)
3023 nr_pages += slots->memslots[i].npages;
3ad82a7e
ZX		 3024
3025 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3026 nr_mmu_pages = max(nr_mmu_pages,
3027 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3028
3029 return nr_mmu_pages;
3030}
3031
2f333bcb
MT		 3032static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3033 unsigned len)
3034{
3035 if (len > buffer->len)
3036 return NULL;
3037 return buffer->ptr;
3038}
3039
3040static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3041 unsigned len)
3042{
3043 void *ret;
3044
3045 ret = pv_mmu_peek_buffer(buffer, len);
3046 if (!ret)
3047 return ret;
3048 buffer->ptr += len;
3049 buffer->len -= len;
3050 buffer->processed += len;
3051 return ret;
3052}
3053
3054static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3055 gpa_t addr, gpa_t value)
3056{
3057 int bytes = 8;
3058 int r;
3059
3060 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3061 bytes = 4;
3062
3063 r = mmu_topup_memory_caches(vcpu);
3064 if (r)
3065 return r;
3066
3200f405 3067 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3068 return -EFAULT;
3069
3070 return 1;
3071}
3072
3073static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3074{
a8cd0244 3075 kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT		 3076 return 1;
3077}
3078
3079static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3080{
3081 spin_lock(&vcpu->kvm->mmu_lock);
3082 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3083 spin_unlock(&vcpu->kvm->mmu_lock);
3084 return 1;
3085}
3086
3087static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3088 struct kvm_pv_mmu_op_buffer *buffer)
3089{
3090 struct kvm_mmu_op_header *header;
3091
3092 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3093 if (!header)
3094 return 0;
3095 switch (header->op) {
3096 case KVM_MMU_OP_WRITE_PTE: {
3097 struct kvm_mmu_op_write_pte *wpte;
3098
3099 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3100 if (!wpte)
3101 return 0;
3102 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3103 wpte->pte_val);
3104 }
3105 case KVM_MMU_OP_FLUSH_TLB: {
3106 struct kvm_mmu_op_flush_tlb *ftlb;
3107
3108 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3109 if (!ftlb)
3110 return 0;
3111 return kvm_pv_mmu_flush_tlb(vcpu);
3112 }
3113 case KVM_MMU_OP_RELEASE_PT: {
3114 struct kvm_mmu_op_release_pt *rpt;
3115
3116 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3117 if (!rpt)
3118 return 0;
3119 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3120 }
3121 default: return 0;
3122 }
3123}
3124
3125int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3126 gpa_t addr, unsigned long *ret)
3127{
3128 int r;
6ad18fba 3129 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3130
6ad18fba
DH		 3131 buffer->ptr = buffer->buf;
3132 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3133 buffer->processed = 0;
2f333bcb 3134
6ad18fba 3135 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3136 if (r)
3137 goto out;
3138
6ad18fba
DH		 3139 while (buffer->len) {
3140 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3141 if (r < 0)
3142 goto out;
3143 if (r == 0)
3144 break;
3145 }
3146
3147 r = 1;
3148out:
6ad18fba 3149 *ret = buffer->processed;
2f333bcb
MT		 3150 return r;
3151}
3152
94d8b056
MT		 3153int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3154{
3155 struct kvm_shadow_walk_iterator iterator;
3156 int nr_sptes = 0;
3157
3158 spin_lock(&vcpu->kvm->mmu_lock);
3159 for_each_shadow_entry(vcpu, addr, iterator) {
3160 sptes[iterator.level-1] = *iterator.sptep;
3161 nr_sptes++;
3162 if (!is_shadow_present_pte(*iterator.sptep))
3163 break;
3164 }
3165 spin_unlock(&vcpu->kvm->mmu_lock);
3166
3167 return nr_sptes;
3168}
3169EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3170
37a7d8b0
AK		 3171#ifdef AUDIT
3172
3173static const char *audit_msg;
3174
3175static gva_t canonicalize(gva_t gva)
3176{
3177#ifdef CONFIG_X86_64
3178 gva = (long long)(gva << 16) >> 16;
3179#endif
3180 return gva;
3181}
3182
08a3732b 3183
805d32de 3184typedef void (*inspect_spte_fn) (struct kvm *kvm, u64 *sptep);
08a3732b
MT		 3185
3186static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3187 inspect_spte_fn fn)
3188{
3189 int i;
3190
3191 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3192 u64 ent = sp->spt[i];
3193
3194 if (is_shadow_present_pte(ent)) {
2920d728 3195 if (!is_last_spte(ent, sp->role.level)) {
08a3732b
MT		 3196 struct kvm_mmu_page *child;
3197 child = page_header(ent & PT64_BASE_ADDR_MASK);
3198 __mmu_spte_walk(kvm, child, fn);
2920d728 3199 } else
805d32de 3200 fn(kvm, &sp->spt[i]);
08a3732b
MT		 3201 }
3202 }
3203}
3204
3205static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3206{
3207 int i;
3208 struct kvm_mmu_page *sp;
3209
3210 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3211 return;
3212 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3213 hpa_t root = vcpu->arch.mmu.root_hpa;
3214 sp = page_header(root);
3215 __mmu_spte_walk(vcpu->kvm, sp, fn);
3216 return;
3217 }
3218 for (i = 0; i < 4; ++i) {
3219 hpa_t root = vcpu->arch.mmu.pae_root[i];
3220
3221 if (root && VALID_PAGE(root)) {
3222 root &= PT64_BASE_ADDR_MASK;
3223 sp = page_header(root);
3224 __mmu_spte_walk(vcpu->kvm, sp, fn);
3225 }
3226 }
3227 return;
3228}
3229
37a7d8b0
AK		 3230static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3231 gva_t va, int level)
3232{
3233 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3234 int i;
3235 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3236
3237 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3238 u64 ent = pt[i];
3239
c7addb90 3240 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK		 3241 continue;
3242
3243 va = canonicalize(va);
2920d728
MT		 3244 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3245 audit_mappings_page(vcpu, ent, va, level - 1);
3246 else {
1871c602 3247 gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL);
34382539
JK		 3248 gfn_t gfn = gpa >> PAGE_SHIFT;
3249 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3250 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3251
2aaf65e8
MT		 3252 if (is_error_pfn(pfn)) {
3253 kvm_release_pfn_clean(pfn);
3254 continue;
3255 }
3256
c7addb90 3257 if (is_shadow_present_pte(ent)
37a7d8b0 3258 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK		 3259 printk(KERN_ERR "xx audit error: (%s) levels %d"
3260 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3261 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD		 3262 va, gpa, hpa, ent,
3263 is_shadow_present_pte(ent));
c7addb90
AK		 3264 else if (ent == shadow_notrap_nonpresent_pte
3265 && !is_error_hpa(hpa))
3266 printk(KERN_ERR "audit: (%s) notrap shadow,"
3267 " valid guest gva %lx\n", audit_msg, va);
35149e21 3268 kvm_release_pfn_clean(pfn);
c7addb90 3269
37a7d8b0
AK		 3270 }
3271 }
3272}
3273
3274static void audit_mappings(struct kvm_vcpu *vcpu)
3275{
1ea252af 3276 unsigned i;
37a7d8b0 3277
ad312c7c
ZX		 3278 if (vcpu->arch.mmu.root_level == 4)
3279 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK		 3280 else
3281 for (i = 0; i < 4; ++i)
ad312c7c 3282 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3283 audit_mappings_page(vcpu,
ad312c7c 3284 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK		 3285 i << 30,
3286 2);
3287}
3288
3289static int count_rmaps(struct kvm_vcpu *vcpu)
3290{
805d32de
XG		 3291 struct kvm *kvm = vcpu->kvm;
3292 struct kvm_memslots *slots;
37a7d8b0 3293 int nmaps = 0;
bc6678a3 3294 int i, j, k, idx;
37a7d8b0 3295
bc6678a3 3296 idx = srcu_read_lock(&kvm->srcu);
90d83dc3 3297 slots = kvm_memslots(kvm);
37a7d8b0 3298 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
bc6678a3 3299 struct kvm_memory_slot *m = &slots->memslots[i];
37a7d8b0
AK		 3300 struct kvm_rmap_desc *d;
3301
3302 for (j = 0; j < m->npages; ++j) {
290fc38d 3303 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3304
290fc38d 3305 if (!*rmapp)
37a7d8b0 3306 continue;
290fc38d 3307 if (!(*rmapp & 1)) {
37a7d8b0
AK		 3308 ++nmaps;
3309 continue;
3310 }
290fc38d 3311 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK		 3312 while (d) {
3313 for (k = 0; k < RMAP_EXT; ++k)
d555c333 3314 if (d->sptes[k])
37a7d8b0
AK		 3315 ++nmaps;
3316 else
3317 break;
3318 d = d->more;
3319 }
3320 }
3321 }
bc6678a3 3322 srcu_read_unlock(&kvm->srcu, idx);
37a7d8b0
AK		 3323 return nmaps;
3324}
3325
805d32de 3326void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep)
08a3732b
MT		 3327{
3328 unsigned long *rmapp;
3329 struct kvm_mmu_page *rev_sp;
3330 gfn_t gfn;
3331
3332 if (*sptep & PT_WRITABLE_MASK) {
3333 rev_sp = page_header(__pa(sptep));
3334 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3335
3336 if (!gfn_to_memslot(kvm, gfn)) {
3337 if (!printk_ratelimit())
3338 return;
3339 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3340 audit_msg, gfn);
3341 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
805d32de 3342 audit_msg, (long int)(sptep - rev_sp->spt),
08a3732b
MT		 3343 rev_sp->gfn);
3344 dump_stack();
3345 return;
3346 }
3347
2920d728 3348 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
805d32de 3349 rev_sp->role.level);
08a3732b
MT		 3350 if (!*rmapp) {
3351 if (!printk_ratelimit())
3352 return;
3353 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3354 audit_msg, *sptep);
3355 dump_stack();
3356 }
3357 }
3358
3359}
3360
3361void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3362{
3363 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3364}
3365
3366static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
37a7d8b0 3367{
4db35314 3368 struct kvm_mmu_page *sp;
37a7d8b0
AK		 3369 int i;
3370
f05e70ac 3371 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3372 u64 *pt = sp->spt;
37a7d8b0 3373
4db35314 3374 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK		 3375 continue;
3376
3377 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3378 u64 ent = pt[i];
3379
3380 if (!(ent & PT_PRESENT_MASK))
3381 continue;
3382 if (!(ent & PT_WRITABLE_MASK))
3383 continue;
805d32de 3384 inspect_spte_has_rmap(vcpu->kvm, &pt[i]);
37a7d8b0
AK		 3385 }
3386 }
08a3732b 3387 return;
37a7d8b0
AK		 3388}
3389
3390static void audit_rmap(struct kvm_vcpu *vcpu)
3391{
08a3732b
MT		 3392 check_writable_mappings_rmap(vcpu);
3393 count_rmaps(vcpu);
37a7d8b0
AK		 3394}
3395
3396static void audit_write_protection(struct kvm_vcpu *vcpu)
3397{
4db35314 3398 struct kvm_mmu_page *sp;
290fc38d
IE		 3399 struct kvm_memory_slot *slot;
3400 unsigned long *rmapp;
e58b0f9e 3401 u64 *spte;
290fc38d 3402 gfn_t gfn;
37a7d8b0 3403
f05e70ac 3404 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3405 if (sp->role.direct)
37a7d8b0 3406 continue;
e58b0f9e
MT		 3407 if (sp->unsync)
3408 continue;
37a7d8b0 3409
4db35314 3410 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
2843099f 3411 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
290fc38d 3412 rmapp = &slot->rmap[gfn - slot->base_gfn];
e58b0f9e
MT		 3413
3414 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3415 while (spte) {
3416 if (*spte & PT_WRITABLE_MASK)
3417 printk(KERN_ERR "%s: (%s) shadow page has "
3418 "writable mappings: gfn %lx role %x\n",
b8688d51 3419 __func__, audit_msg, sp->gfn,
4db35314 3420 sp->role.word);
e58b0f9e
MT		 3421 spte = rmap_next(vcpu->kvm, rmapp, spte);
3422 }
37a7d8b0
AK		 3423 }
3424}
3425
3426static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3427{
3428 int olddbg = dbg;
3429
3430 dbg = 0;
3431 audit_msg = msg;
3432 audit_rmap(vcpu);
3433 audit_write_protection(vcpu);
2aaf65e8
MT		 3434 if (strcmp("pre pte write", audit_msg) != 0)
3435 audit_mappings(vcpu);
08a3732b 3436 audit_writable_sptes_have_rmaps(vcpu);
37a7d8b0
AK		 3437 dbg = olddbg;
3438}
3439
3440#endif
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