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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
221d059d | 10 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
6aa8b732 | 34 | #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level) |
c7addb90 | 35 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
36 | #ifdef CONFIG_X86_64 |
37 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 38 | #define CMPXCHG cmpxchg |
cea0f0e7 | 39 | #else |
b3e4e63f | 40 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
41 | #define PT_MAX_FULL_LEVELS 2 |
42 | #endif | |
6aa8b732 AK |
43 | #elif PTTYPE == 32 |
44 | #define pt_element_t u32 | |
45 | #define guest_walker guest_walker32 | |
46 | #define FNAME(name) paging##32_##name | |
47 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
48 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
49 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 50 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
6aa8b732 | 51 | #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level) |
c7addb90 | 52 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 53 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 54 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
55 | #else |
56 | #error Invalid PTTYPE value | |
57 | #endif | |
58 | ||
e04da980 JR |
59 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
60 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 61 | |
6aa8b732 AK |
62 | /* |
63 | * The guest_walker structure emulates the behavior of the hardware page | |
64 | * table walker. | |
65 | */ | |
66 | struct guest_walker { | |
67 | int level; | |
cea0f0e7 | 68 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 69 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 70 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 71 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
72 | unsigned pt_access; |
73 | unsigned pte_access; | |
815af8d4 | 74 | gfn_t gfn; |
7993ba43 | 75 | u32 error_code; |
6aa8b732 AK |
76 | }; |
77 | ||
e04da980 | 78 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 79 | { |
e04da980 | 80 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
81 | } |
82 | ||
b3e4e63f MT |
83 | static bool FNAME(cmpxchg_gpte)(struct kvm *kvm, |
84 | gfn_t table_gfn, unsigned index, | |
85 | pt_element_t orig_pte, pt_element_t new_pte) | |
86 | { | |
87 | pt_element_t ret; | |
88 | pt_element_t *table; | |
89 | struct page *page; | |
90 | ||
91 | page = gfn_to_page(kvm, table_gfn); | |
72dc67a6 | 92 | |
b3e4e63f | 93 | table = kmap_atomic(page, KM_USER0); |
b3e4e63f | 94 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
b3e4e63f MT |
95 | kunmap_atomic(table, KM_USER0); |
96 | ||
97 | kvm_release_page_dirty(page); | |
98 | ||
99 | return (ret != orig_pte); | |
100 | } | |
101 | ||
bedbe4ee AK |
102 | static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte) |
103 | { | |
104 | unsigned access; | |
105 | ||
106 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
107 | #if PTTYPE == 64 | |
108 | if (is_nx(vcpu)) | |
109 | access &= ~(gpte >> PT64_NX_SHIFT); | |
110 | #endif | |
111 | return access; | |
112 | } | |
113 | ||
ac79c978 AK |
114 | /* |
115 | * Fetch a guest pte for a guest virtual address | |
116 | */ | |
7993ba43 AK |
117 | static int FNAME(walk_addr)(struct guest_walker *walker, |
118 | struct kvm_vcpu *vcpu, gva_t addr, | |
73b1087e | 119 | int write_fault, int user_fault, int fetch_fault) |
6aa8b732 | 120 | { |
42bf3f0a | 121 | pt_element_t pte; |
cea0f0e7 | 122 | gfn_t table_gfn; |
f59c1d2d | 123 | unsigned index, pt_access, uninitialized_var(pte_access); |
42bf3f0a | 124 | gpa_t pte_gpa; |
f59c1d2d | 125 | bool eperm, present, rsvd_fault; |
6aa8b732 | 126 | |
07420171 AK |
127 | trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault, |
128 | fetch_fault); | |
b3e4e63f | 129 | walk: |
f59c1d2d AK |
130 | present = true; |
131 | eperm = rsvd_fault = false; | |
ad312c7c | 132 | walker->level = vcpu->arch.mmu.root_level; |
5777ed34 | 133 | pte = vcpu->arch.mmu.get_cr3(vcpu); |
1b0973bd | 134 | #if PTTYPE == 64 |
957446af | 135 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
6de4f3ad | 136 | pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3); |
07420171 | 137 | trace_kvm_mmu_paging_element(pte, walker->level); |
f59c1d2d AK |
138 | if (!is_present_gpte(pte)) { |
139 | present = false; | |
140 | goto error; | |
141 | } | |
1b0973bd AK |
142 | --walker->level; |
143 | } | |
144 | #endif | |
a9058ecd | 145 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
5777ed34 | 146 | (vcpu->arch.mmu.get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 147 | |
fe135d2c | 148 | pt_access = ACC_ALL; |
ac79c978 AK |
149 | |
150 | for (;;) { | |
42bf3f0a | 151 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 152 | |
5fb07ddb | 153 | table_gfn = gpte_to_gfn(pte); |
1755fbcc | 154 | pte_gpa = gfn_to_gpa(table_gfn); |
ec8d4eae | 155 | pte_gpa += index * sizeof(pt_element_t); |
42bf3f0a | 156 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 157 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 158 | |
f59c1d2d AK |
159 | if (kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte))) { |
160 | present = false; | |
161 | break; | |
162 | } | |
a6085fba | 163 | |
07420171 | 164 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 165 | |
f59c1d2d AK |
166 | if (!is_present_gpte(pte)) { |
167 | present = false; | |
168 | break; | |
169 | } | |
7993ba43 | 170 | |
3241f22d | 171 | if (is_rsvd_bits_set(&vcpu->arch.mmu, pte, walker->level)) { |
f59c1d2d AK |
172 | rsvd_fault = true; |
173 | break; | |
174 | } | |
82725b20 | 175 | |
8dae4445 | 176 | if (write_fault && !is_writable_pte(pte)) |
7993ba43 | 177 | if (user_fault || is_write_protection(vcpu)) |
f59c1d2d | 178 | eperm = true; |
7993ba43 | 179 | |
42bf3f0a | 180 | if (user_fault && !(pte & PT_USER_MASK)) |
f59c1d2d | 181 | eperm = true; |
7993ba43 | 182 | |
73b1087e | 183 | #if PTTYPE == 64 |
24222c2f | 184 | if (fetch_fault && (pte & PT64_NX_MASK)) |
f59c1d2d | 185 | eperm = true; |
73b1087e AK |
186 | #endif |
187 | ||
f59c1d2d | 188 | if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) { |
07420171 AK |
189 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, |
190 | sizeof(pte)); | |
b3e4e63f MT |
191 | if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, |
192 | index, pte, pte|PT_ACCESSED_MASK)) | |
193 | goto walk; | |
f3b8c964 | 194 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 195 | pte |= PT_ACCESSED_MASK; |
bf3f8e86 | 196 | } |
815af8d4 | 197 | |
bedbe4ee | 198 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
fe135d2c | 199 | |
7819026e MT |
200 | walker->ptes[walker->level - 1] = pte; |
201 | ||
e04da980 JR |
202 | if ((walker->level == PT_PAGE_TABLE_LEVEL) || |
203 | ((walker->level == PT_DIRECTORY_LEVEL) && | |
814a59d2 | 204 | is_large_pte(pte) && |
e04da980 JR |
205 | (PTTYPE == 64 || is_pse(vcpu))) || |
206 | ((walker->level == PT_PDPE_LEVEL) && | |
814a59d2 | 207 | is_large_pte(pte) && |
957446af | 208 | vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL)) { |
e04da980 JR |
209 | int lvl = walker->level; |
210 | ||
211 | walker->gfn = gpte_to_gfn_lvl(pte, lvl); | |
212 | walker->gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) | |
213 | >> PAGE_SHIFT; | |
214 | ||
215 | if (PTTYPE == 32 && | |
216 | walker->level == PT_DIRECTORY_LEVEL && | |
217 | is_cpuid_PSE36()) | |
da928521 | 218 | walker->gfn += pse36_gfn_delta(pte); |
e04da980 | 219 | |
ac79c978 | 220 | break; |
815af8d4 | 221 | } |
ac79c978 | 222 | |
fe135d2c | 223 | pt_access = pte_access; |
ac79c978 AK |
224 | --walker->level; |
225 | } | |
42bf3f0a | 226 | |
f59c1d2d AK |
227 | if (!present || eperm || rsvd_fault) |
228 | goto error; | |
229 | ||
43a3795a | 230 | if (write_fault && !is_dirty_gpte(pte)) { |
b3e4e63f MT |
231 | bool ret; |
232 | ||
07420171 | 233 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
b3e4e63f MT |
234 | ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte, |
235 | pte|PT_DIRTY_MASK); | |
236 | if (ret) | |
237 | goto walk; | |
f3b8c964 | 238 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 239 | pte |= PT_DIRTY_MASK; |
7819026e | 240 | walker->ptes[walker->level - 1] = pte; |
42bf3f0a AK |
241 | } |
242 | ||
fe135d2c AK |
243 | walker->pt_access = pt_access; |
244 | walker->pte_access = pte_access; | |
245 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 246 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
247 | return 1; |
248 | ||
f59c1d2d | 249 | error: |
7993ba43 | 250 | walker->error_code = 0; |
f59c1d2d AK |
251 | if (present) |
252 | walker->error_code |= PFERR_PRESENT_MASK; | |
7993ba43 AK |
253 | if (write_fault) |
254 | walker->error_code |= PFERR_WRITE_MASK; | |
255 | if (user_fault) | |
256 | walker->error_code |= PFERR_USER_MASK; | |
b0eeec29 | 257 | if (fetch_fault && is_nx(vcpu)) |
73b1087e | 258 | walker->error_code |= PFERR_FETCH_MASK; |
82725b20 DE |
259 | if (rsvd_fault) |
260 | walker->error_code |= PFERR_RSVD_MASK; | |
07420171 | 261 | trace_kvm_mmu_walker_error(walker->error_code); |
fe551881 | 262 | return 0; |
6aa8b732 AK |
263 | } |
264 | ||
ac3cd03c | 265 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
489f1d65 | 266 | u64 *spte, const void *pte) |
0028425f AK |
267 | { |
268 | pt_element_t gpte; | |
41074d07 | 269 | unsigned pte_access; |
35149e21 | 270 | pfn_t pfn; |
fbc5d139 | 271 | u64 new_spte; |
0028425f | 272 | |
0028425f | 273 | gpte = *(const pt_element_t *)pte; |
c7addb90 | 274 | if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) { |
fbc5d139 | 275 | if (!is_present_gpte(gpte)) { |
ac3cd03c | 276 | if (sp->unsync) |
fbc5d139 AK |
277 | new_spte = shadow_trap_nonpresent_pte; |
278 | else | |
279 | new_spte = shadow_notrap_nonpresent_pte; | |
280 | __set_spte(spte, new_spte); | |
281 | } | |
c7addb90 AK |
282 | return; |
283 | } | |
b8688d51 | 284 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
ac3cd03c | 285 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
d7824fff AK |
286 | if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn) |
287 | return; | |
35149e21 AL |
288 | pfn = vcpu->arch.update_pte.pfn; |
289 | if (is_error_pfn(pfn)) | |
d7824fff | 290 | return; |
e930bffe AA |
291 | if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq)) |
292 | return; | |
35149e21 | 293 | kvm_get_pfn(pfn); |
1403283a IE |
294 | /* |
295 | * we call mmu_set_spte() with reset_host_protection = true beacuse that | |
296 | * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1). | |
297 | */ | |
ac3cd03c | 298 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, |
cb83cad2 | 299 | is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL, |
1403283a | 300 | gpte_to_gfn(gpte), pfn, true, true); |
0028425f AK |
301 | } |
302 | ||
39c8c672 AK |
303 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
304 | struct guest_walker *gw, int level) | |
305 | { | |
39c8c672 | 306 | pt_element_t curr_pte; |
189be38d XG |
307 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
308 | u64 mask; | |
309 | int r, index; | |
310 | ||
311 | if (level == PT_PAGE_TABLE_LEVEL) { | |
312 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
313 | base_gpa = pte_gpa & ~mask; | |
314 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
315 | ||
316 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
317 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
318 | curr_pte = gw->prefetch_ptes[index]; | |
319 | } else | |
320 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 321 | &curr_pte, sizeof(curr_pte)); |
189be38d | 322 | |
39c8c672 AK |
323 | return r || curr_pte != gw->ptes[level - 1]; |
324 | } | |
325 | ||
189be38d XG |
326 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
327 | u64 *sptep) | |
957ed9ef XG |
328 | { |
329 | struct kvm_mmu_page *sp; | |
3241f22d | 330 | struct kvm_mmu *mmu = &vcpu->arch.mmu; |
189be38d | 331 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 332 | u64 *spte; |
189be38d | 333 | int i; |
957ed9ef XG |
334 | |
335 | sp = page_header(__pa(sptep)); | |
336 | ||
337 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
338 | return; | |
339 | ||
340 | if (sp->role.direct) | |
341 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
342 | ||
343 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
344 | spte = sp->spt + i; |
345 | ||
346 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
347 | pt_element_t gpte; | |
348 | unsigned pte_access; | |
349 | gfn_t gfn; | |
350 | pfn_t pfn; | |
351 | bool dirty; | |
352 | ||
353 | if (spte == sptep) | |
354 | continue; | |
355 | ||
356 | if (*spte != shadow_trap_nonpresent_pte) | |
357 | continue; | |
358 | ||
359 | gpte = gptep[i]; | |
360 | ||
361 | if (!is_present_gpte(gpte) || | |
3241f22d | 362 | is_rsvd_bits_set(mmu, gpte, PT_PAGE_TABLE_LEVEL)) { |
957ed9ef XG |
363 | if (!sp->unsync) |
364 | __set_spte(spte, shadow_notrap_nonpresent_pte); | |
365 | continue; | |
366 | } | |
367 | ||
368 | if (!(gpte & PT_ACCESSED_MASK)) | |
369 | continue; | |
370 | ||
371 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
372 | gfn = gpte_to_gfn(gpte); | |
373 | dirty = is_dirty_gpte(gpte); | |
374 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, | |
375 | (pte_access & ACC_WRITE_MASK) && dirty); | |
376 | if (is_error_pfn(pfn)) { | |
377 | kvm_release_pfn_clean(pfn); | |
378 | break; | |
379 | } | |
380 | ||
381 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, | |
382 | dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn, | |
383 | pfn, true, true); | |
384 | } | |
385 | } | |
386 | ||
6aa8b732 AK |
387 | /* |
388 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
389 | */ | |
e7a04c99 AK |
390 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
391 | struct guest_walker *gw, | |
7e4e4056 | 392 | int user_fault, int write_fault, int hlevel, |
e7a04c99 | 393 | int *ptwrite, pfn_t pfn) |
6aa8b732 | 394 | { |
abb9e0b8 | 395 | unsigned access = gw->pt_access; |
5991b332 | 396 | struct kvm_mmu_page *sp = NULL; |
84754cd8 | 397 | bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]); |
5991b332 | 398 | int top_level; |
84754cd8 | 399 | unsigned direct_access; |
24157aaf | 400 | struct kvm_shadow_walk_iterator it; |
abb9e0b8 | 401 | |
43a3795a | 402 | if (!is_present_gpte(gw->ptes[gw->level - 1])) |
e7a04c99 | 403 | return NULL; |
6aa8b732 | 404 | |
84754cd8 XG |
405 | direct_access = gw->pt_access & gw->pte_access; |
406 | if (!dirty) | |
407 | direct_access &= ~ACC_WRITE_MASK; | |
408 | ||
5991b332 AK |
409 | top_level = vcpu->arch.mmu.root_level; |
410 | if (top_level == PT32E_ROOT_LEVEL) | |
411 | top_level = PT32_ROOT_LEVEL; | |
412 | /* | |
413 | * Verify that the top-level gpte is still there. Since the page | |
414 | * is a root page, it is either write protected (and cannot be | |
415 | * changed from now on) or it is invalid (in which case, we don't | |
416 | * really care if it changes underneath us after this point). | |
417 | */ | |
418 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
419 | goto out_gpte_changed; | |
420 | ||
24157aaf AK |
421 | for (shadow_walk_init(&it, vcpu, addr); |
422 | shadow_walk_okay(&it) && it.level > gw->level; | |
423 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
424 | gfn_t table_gfn; |
425 | ||
24157aaf | 426 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 427 | |
5991b332 | 428 | sp = NULL; |
24157aaf AK |
429 | if (!is_shadow_present_pte(*it.sptep)) { |
430 | table_gfn = gw->table_gfn[it.level - 2]; | |
431 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
432 | false, access, it.sptep); | |
5991b332 | 433 | } |
0b3c9333 AK |
434 | |
435 | /* | |
436 | * Verify that the gpte in the page we've just write | |
437 | * protected is still there. | |
438 | */ | |
24157aaf | 439 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 440 | goto out_gpte_changed; |
abb9e0b8 | 441 | |
5991b332 | 442 | if (sp) |
24157aaf | 443 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 444 | } |
050e6499 | 445 | |
0b3c9333 | 446 | for (; |
24157aaf AK |
447 | shadow_walk_okay(&it) && it.level > hlevel; |
448 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
449 | gfn_t direct_gfn; |
450 | ||
24157aaf | 451 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 452 | |
24157aaf | 453 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 454 | |
24157aaf | 455 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
456 | continue; |
457 | ||
24157aaf | 458 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 459 | |
24157aaf AK |
460 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
461 | true, direct_access, it.sptep); | |
462 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
463 | } |
464 | ||
24157aaf AK |
465 | mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access, |
466 | user_fault, write_fault, dirty, ptwrite, it.level, | |
0b3c9333 | 467 | gw->gfn, pfn, false, true); |
189be38d | 468 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 469 | |
24157aaf | 470 | return it.sptep; |
0b3c9333 AK |
471 | |
472 | out_gpte_changed: | |
5991b332 | 473 | if (sp) |
24157aaf | 474 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 AK |
475 | kvm_release_pfn_clean(pfn); |
476 | return NULL; | |
6aa8b732 AK |
477 | } |
478 | ||
6aa8b732 AK |
479 | /* |
480 | * Page fault handler. There are several causes for a page fault: | |
481 | * - there is no shadow pte for the guest pte | |
482 | * - write access through a shadow pte marked read only so that we can set | |
483 | * the dirty bit | |
484 | * - write access to a shadow pte marked read only so we can update the page | |
485 | * dirty bitmap, when userspace requests it | |
486 | * - mmio access; in this case we will never install a present shadow pte | |
487 | * - normal guest page fault due to the guest pte marked not present, not | |
488 | * writable, or not executable | |
489 | * | |
e2dec939 AK |
490 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
491 | * a negative value on error. | |
6aa8b732 AK |
492 | */ |
493 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, | |
494 | u32 error_code) | |
495 | { | |
496 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 | 497 | int user_fault = error_code & PFERR_USER_MASK; |
73b1087e | 498 | int fetch_fault = error_code & PFERR_FETCH_MASK; |
6aa8b732 | 499 | struct guest_walker walker; |
d555c333 | 500 | u64 *sptep; |
cea0f0e7 | 501 | int write_pt = 0; |
e2dec939 | 502 | int r; |
35149e21 | 503 | pfn_t pfn; |
7e4e4056 | 504 | int level = PT_PAGE_TABLE_LEVEL; |
e930bffe | 505 | unsigned long mmu_seq; |
6aa8b732 | 506 | |
b8688d51 | 507 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 508 | |
e2dec939 AK |
509 | r = mmu_topup_memory_caches(vcpu); |
510 | if (r) | |
511 | return r; | |
714b93da | 512 | |
6aa8b732 | 513 | /* |
a8b876b1 | 514 | * Look up the guest pte for the faulting address. |
6aa8b732 | 515 | */ |
73b1087e AK |
516 | r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault, |
517 | fetch_fault); | |
6aa8b732 AK |
518 | |
519 | /* | |
520 | * The page is not mapped by the guest. Let the guest handle it. | |
521 | */ | |
7993ba43 | 522 | if (!r) { |
b8688d51 | 523 | pgprintk("%s: guest page fault\n", __func__); |
7993ba43 | 524 | inject_page_fault(vcpu, addr, walker.error_code); |
ad312c7c | 525 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
6aa8b732 AK |
526 | return 0; |
527 | } | |
528 | ||
7e4e4056 JR |
529 | if (walker.level >= PT_DIRECTORY_LEVEL) { |
530 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); | |
531 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 532 | } |
7e4e4056 | 533 | |
e930bffe | 534 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 535 | smp_rmb(); |
35149e21 | 536 | pfn = gfn_to_pfn(vcpu->kvm, walker.gfn); |
d7824fff | 537 | |
d196e343 | 538 | /* mmio */ |
bf998156 HY |
539 | if (is_error_pfn(pfn)) |
540 | return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn); | |
d196e343 | 541 | |
aaee2c94 | 542 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
543 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
544 | goto out_unlock; | |
bc32ce21 | 545 | |
8b1fe17c | 546 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
eb787d10 | 547 | kvm_mmu_free_some_pages(vcpu); |
d555c333 | 548 | sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
7e4e4056 | 549 | level, &write_pt, pfn); |
a24e8099 | 550 | (void)sptep; |
b8688d51 | 551 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__, |
d555c333 | 552 | sptep, *sptep, write_pt); |
cea0f0e7 | 553 | |
a25f7e1f | 554 | if (!write_pt) |
ad312c7c | 555 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
a25f7e1f | 556 | |
1165f5fe | 557 | ++vcpu->stat.pf_fixed; |
8b1fe17c | 558 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 559 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 560 | |
cea0f0e7 | 561 | return write_pt; |
e930bffe AA |
562 | |
563 | out_unlock: | |
564 | spin_unlock(&vcpu->kvm->mmu_lock); | |
565 | kvm_release_pfn_clean(pfn); | |
566 | return 0; | |
6aa8b732 AK |
567 | } |
568 | ||
a461930b | 569 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 570 | { |
a461930b | 571 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 572 | struct kvm_mmu_page *sp; |
08e850c6 | 573 | gpa_t pte_gpa = -1; |
a461930b AK |
574 | int level; |
575 | u64 *sptep; | |
4539b358 | 576 | int need_flush = 0; |
a461930b AK |
577 | |
578 | spin_lock(&vcpu->kvm->mmu_lock); | |
a7052897 | 579 | |
a461930b AK |
580 | for_each_shadow_entry(vcpu, gva, iterator) { |
581 | level = iterator.level; | |
582 | sptep = iterator.sptep; | |
ad218f85 | 583 | |
f78978aa | 584 | sp = page_header(__pa(sptep)); |
884a0ff0 | 585 | if (is_last_spte(*sptep, level)) { |
22c9b2d1 | 586 | int offset, shift; |
08e850c6 | 587 | |
f78978aa XG |
588 | if (!sp->unsync) |
589 | break; | |
590 | ||
22c9b2d1 XG |
591 | shift = PAGE_SHIFT - |
592 | (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level; | |
593 | offset = sp->role.quadrant << shift; | |
594 | ||
595 | pte_gpa = (sp->gfn << PAGE_SHIFT) + offset; | |
08e850c6 | 596 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b AK |
597 | |
598 | if (is_shadow_present_pte(*sptep)) { | |
a461930b AK |
599 | if (is_large_pte(*sptep)) |
600 | --vcpu->kvm->stat.lpages; | |
be38d276 AK |
601 | drop_spte(vcpu->kvm, sptep, |
602 | shadow_trap_nonpresent_pte); | |
4539b358 | 603 | need_flush = 1; |
be38d276 AK |
604 | } else |
605 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
a461930b | 606 | break; |
87917239 | 607 | } |
a7052897 | 608 | |
f78978aa | 609 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
610 | break; |
611 | } | |
a7052897 | 612 | |
4539b358 AA |
613 | if (need_flush) |
614 | kvm_flush_remote_tlbs(vcpu->kvm); | |
08e850c6 AK |
615 | |
616 | atomic_inc(&vcpu->kvm->arch.invlpg_counter); | |
617 | ||
ad218f85 | 618 | spin_unlock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
619 | |
620 | if (pte_gpa == -1) | |
621 | return; | |
622 | ||
623 | if (mmu_topup_memory_caches(vcpu)) | |
624 | return; | |
625 | kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0); | |
a7052897 MT |
626 | } |
627 | ||
1871c602 GN |
628 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
629 | u32 *error) | |
6aa8b732 AK |
630 | { |
631 | struct guest_walker walker; | |
e119d117 AK |
632 | gpa_t gpa = UNMAPPED_GVA; |
633 | int r; | |
6aa8b732 | 634 | |
1871c602 GN |
635 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, |
636 | !!(access & PFERR_WRITE_MASK), | |
637 | !!(access & PFERR_USER_MASK), | |
638 | !!(access & PFERR_FETCH_MASK)); | |
6aa8b732 | 639 | |
e119d117 | 640 | if (r) { |
1755fbcc | 641 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 642 | gpa |= vaddr & ~PAGE_MASK; |
1871c602 GN |
643 | } else if (error) |
644 | *error = walker.error_code; | |
6aa8b732 AK |
645 | |
646 | return gpa; | |
647 | } | |
648 | ||
c7addb90 AK |
649 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
650 | struct kvm_mmu_page *sp) | |
651 | { | |
eab9f71f AK |
652 | int i, j, offset, r; |
653 | pt_element_t pt[256 / sizeof(pt_element_t)]; | |
654 | gpa_t pte_gpa; | |
c7addb90 | 655 | |
f6e2c02b | 656 | if (sp->role.direct |
e5a4c8ca | 657 | || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) { |
c7addb90 AK |
658 | nonpaging_prefetch_page(vcpu, sp); |
659 | return; | |
660 | } | |
661 | ||
eab9f71f AK |
662 | pte_gpa = gfn_to_gpa(sp->gfn); |
663 | if (PTTYPE == 32) { | |
e5a4c8ca | 664 | offset = sp->role.quadrant << PT64_LEVEL_BITS; |
eab9f71f AK |
665 | pte_gpa += offset * sizeof(pt_element_t); |
666 | } | |
7ec54588 | 667 | |
eab9f71f AK |
668 | for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) { |
669 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt); | |
670 | pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t); | |
671 | for (j = 0; j < ARRAY_SIZE(pt); ++j) | |
43a3795a | 672 | if (r || is_present_gpte(pt[j])) |
eab9f71f AK |
673 | sp->spt[i+j] = shadow_trap_nonpresent_pte; |
674 | else | |
675 | sp->spt[i+j] = shadow_notrap_nonpresent_pte; | |
7ec54588 | 676 | } |
c7addb90 AK |
677 | } |
678 | ||
e8bc217a MT |
679 | /* |
680 | * Using the cached information from sp->gfns is safe because: | |
681 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
682 | * can't change unless all sptes pointing to it are nuked first. | |
e8bc217a | 683 | */ |
be71e061 XG |
684 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
685 | bool clear_unsync) | |
e8bc217a MT |
686 | { |
687 | int i, offset, nr_present; | |
1403283a | 688 | bool reset_host_protection; |
51fb60d8 | 689 | gpa_t first_pte_gpa; |
e8bc217a MT |
690 | |
691 | offset = nr_present = 0; | |
692 | ||
2032a93d LJ |
693 | /* direct kvm_mmu_page can not be unsync. */ |
694 | BUG_ON(sp->role.direct); | |
695 | ||
e8bc217a MT |
696 | if (PTTYPE == 32) |
697 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
698 | ||
51fb60d8 GJ |
699 | first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); |
700 | ||
e8bc217a MT |
701 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
702 | unsigned pte_access; | |
703 | pt_element_t gpte; | |
704 | gpa_t pte_gpa; | |
f55c3f41 | 705 | gfn_t gfn; |
e8bc217a MT |
706 | |
707 | if (!is_shadow_present_pte(sp->spt[i])) | |
708 | continue; | |
709 | ||
51fb60d8 | 710 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
711 | |
712 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
713 | sizeof(pt_element_t))) | |
714 | return -EINVAL; | |
715 | ||
f55c3f41 | 716 | gfn = gpte_to_gfn(gpte); |
3241f22d | 717 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL) |
fa1de2bf XG |
718 | || gfn != sp->gfns[i] || !is_present_gpte(gpte) |
719 | || !(gpte & PT_ACCESSED_MASK)) { | |
e8bc217a MT |
720 | u64 nonpresent; |
721 | ||
be71e061 | 722 | if (is_present_gpte(gpte) || !clear_unsync) |
e8bc217a MT |
723 | nonpresent = shadow_trap_nonpresent_pte; |
724 | else | |
725 | nonpresent = shadow_notrap_nonpresent_pte; | |
be38d276 | 726 | drop_spte(vcpu->kvm, &sp->spt[i], nonpresent); |
e8bc217a MT |
727 | continue; |
728 | } | |
729 | ||
730 | nr_present++; | |
731 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
1403283a IE |
732 | if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) { |
733 | pte_access &= ~ACC_WRITE_MASK; | |
734 | reset_host_protection = 0; | |
735 | } else { | |
736 | reset_host_protection = 1; | |
737 | } | |
e8bc217a | 738 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, |
7e4e4056 | 739 | is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn, |
1403283a IE |
740 | spte_to_pfn(sp->spt[i]), true, false, |
741 | reset_host_protection); | |
e8bc217a MT |
742 | } |
743 | ||
744 | return !nr_present; | |
745 | } | |
746 | ||
6aa8b732 AK |
747 | #undef pt_element_t |
748 | #undef guest_walker | |
749 | #undef FNAME | |
750 | #undef PT_BASE_ADDR_MASK | |
751 | #undef PT_INDEX | |
6aa8b732 | 752 | #undef PT_LEVEL_MASK |
e04da980 JR |
753 | #undef PT_LVL_ADDR_MASK |
754 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 755 | #undef PT_LEVEL_BITS |
cea0f0e7 | 756 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 757 | #undef gpte_to_gfn |
e04da980 | 758 | #undef gpte_to_gfn_lvl |
b3e4e63f | 759 | #undef CMPXCHG |