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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
47 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
48 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 50 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 51 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 52 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
53 | #else |
54 | #error Invalid PTTYPE value | |
55 | #endif | |
56 | ||
e04da980 JR |
57 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
58 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 59 | |
6aa8b732 AK |
60 | /* |
61 | * The guest_walker structure emulates the behavior of the hardware page | |
62 | * table walker. | |
63 | */ | |
64 | struct guest_walker { | |
65 | int level; | |
8cbc7069 | 66 | unsigned max_level; |
cea0f0e7 | 67 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 68 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 69 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 70 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 71 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
72 | unsigned pt_access; |
73 | unsigned pte_access; | |
815af8d4 | 74 | gfn_t gfn; |
8c28d031 | 75 | struct x86_exception fault; |
6aa8b732 AK |
76 | }; |
77 | ||
e04da980 | 78 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 79 | { |
e04da980 | 80 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
81 | } |
82 | ||
a78484c6 | 83 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
84 | pt_element_t __user *ptep_user, unsigned index, |
85 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 86 | { |
c8cfbb55 | 87 | int npages; |
b3e4e63f MT |
88 | pt_element_t ret; |
89 | pt_element_t *table; | |
90 | struct page *page; | |
91 | ||
c8cfbb55 TY |
92 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page); |
93 | /* Check if the user is doing something meaningless. */ | |
94 | if (unlikely(npages != 1)) | |
a78484c6 RJ |
95 | return -EFAULT; |
96 | ||
8fd75e12 | 97 | table = kmap_atomic(page); |
b3e4e63f | 98 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
8fd75e12 | 99 | kunmap_atomic(table); |
b3e4e63f MT |
100 | |
101 | kvm_release_page_dirty(page); | |
102 | ||
103 | return (ret != orig_pte); | |
104 | } | |
105 | ||
3c8c652a TY |
106 | static bool FNAME(is_last_gpte)(struct guest_walker *walker, |
107 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
108 | pt_element_t gpte) | |
109 | { | |
110 | if (walker->level == PT_PAGE_TABLE_LEVEL) | |
111 | return true; | |
112 | ||
113 | if ((walker->level == PT_DIRECTORY_LEVEL) && is_large_pte(gpte) && | |
114 | (PTTYPE == 64 || is_pse(vcpu))) | |
115 | return true; | |
116 | ||
117 | if ((walker->level == PT_PDPE_LEVEL) && is_large_pte(gpte) && | |
118 | (mmu->root_level == PT64_ROOT_LEVEL)) | |
119 | return true; | |
120 | ||
121 | return false; | |
122 | } | |
123 | ||
8cbc7069 AK |
124 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
125 | struct kvm_mmu *mmu, | |
126 | struct guest_walker *walker, | |
127 | int write_fault) | |
128 | { | |
129 | unsigned level, index; | |
130 | pt_element_t pte, orig_pte; | |
131 | pt_element_t __user *ptep_user; | |
132 | gfn_t table_gfn; | |
133 | int ret; | |
134 | ||
135 | for (level = walker->max_level; level >= walker->level; --level) { | |
136 | pte = orig_pte = walker->ptes[level - 1]; | |
137 | table_gfn = walker->table_gfn[level - 1]; | |
138 | ptep_user = walker->ptep_user[level - 1]; | |
139 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
140 | if (!(pte & PT_ACCESSED_MASK)) { | |
141 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); | |
142 | pte |= PT_ACCESSED_MASK; | |
143 | } | |
144 | if (level == walker->level && write_fault && !is_dirty_gpte(pte)) { | |
145 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); | |
146 | pte |= PT_DIRTY_MASK; | |
147 | } | |
148 | if (pte == orig_pte) | |
149 | continue; | |
150 | ||
151 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); | |
152 | if (ret) | |
153 | return ret; | |
154 | ||
155 | mark_page_dirty(vcpu->kvm, table_gfn); | |
156 | walker->ptes[level] = pte; | |
157 | } | |
158 | return 0; | |
159 | } | |
160 | ||
ac79c978 AK |
161 | /* |
162 | * Fetch a guest pte for a guest virtual address | |
163 | */ | |
1e301feb JR |
164 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
165 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 166 | gva_t addr, u32 access) |
6aa8b732 | 167 | { |
8cbc7069 | 168 | int ret; |
42bf3f0a | 169 | pt_element_t pte; |
b7233635 | 170 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 171 | gfn_t table_gfn; |
97d64b78 | 172 | unsigned index, pt_access, pte_access; |
42bf3f0a | 173 | gpa_t pte_gpa; |
cd46868c | 174 | bool eperm, last_gpte; |
134291bf TY |
175 | int offset; |
176 | const int write_fault = access & PFERR_WRITE_MASK; | |
177 | const int user_fault = access & PFERR_USER_MASK; | |
178 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
179 | u16 errcode = 0; | |
6aa8b732 | 180 | |
6fbc2770 | 181 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 182 | retry_walk: |
134291bf | 183 | eperm = false; |
1e301feb JR |
184 | walker->level = mmu->root_level; |
185 | pte = mmu->get_cr3(vcpu); | |
186 | ||
1b0973bd | 187 | #if PTTYPE == 64 |
1e301feb | 188 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 189 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 190 | trace_kvm_mmu_paging_element(pte, walker->level); |
134291bf | 191 | if (!is_present_gpte(pte)) |
f59c1d2d | 192 | goto error; |
1b0973bd AK |
193 | --walker->level; |
194 | } | |
195 | #endif | |
8cbc7069 | 196 | walker->max_level = walker->level; |
a9058ecd | 197 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 198 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 199 | |
fe135d2c | 200 | pt_access = ACC_ALL; |
ac79c978 AK |
201 | |
202 | for (;;) { | |
6e2ca7d1 TY |
203 | gfn_t real_gfn; |
204 | unsigned long host_addr; | |
205 | ||
42bf3f0a | 206 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 207 | |
5fb07ddb | 208 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
209 | offset = index * sizeof(pt_element_t); |
210 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 211 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 212 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 213 | |
6e2ca7d1 TY |
214 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
215 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
134291bf TY |
216 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
217 | goto error; | |
6e2ca7d1 TY |
218 | real_gfn = gpa_to_gfn(real_gfn); |
219 | ||
220 | host_addr = gfn_to_hva(vcpu->kvm, real_gfn); | |
134291bf TY |
221 | if (unlikely(kvm_is_error_hva(host_addr))) |
222 | goto error; | |
6e2ca7d1 TY |
223 | |
224 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
225 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
226 | goto error; | |
8cbc7069 | 227 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 228 | |
07420171 | 229 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 230 | |
134291bf TY |
231 | if (unlikely(!is_present_gpte(pte))) |
232 | goto error; | |
7993ba43 | 233 | |
781e0743 AK |
234 | if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte, |
235 | walker->level))) { | |
134291bf TY |
236 | errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
237 | goto error; | |
f59c1d2d | 238 | } |
82725b20 | 239 | |
97d64b78 | 240 | pte_access = pt_access & gpte_access(vcpu, pte); |
73b1087e | 241 | |
cd46868c | 242 | last_gpte = FNAME(is_last_gpte)(walker, vcpu, mmu, pte); |
cd46868c | 243 | |
7819026e MT |
244 | walker->ptes[walker->level - 1] = pte; |
245 | ||
cd46868c | 246 | if (last_gpte) { |
e04da980 | 247 | int lvl = walker->level; |
2329d46d JR |
248 | gpa_t real_gpa; |
249 | gfn_t gfn; | |
33770780 | 250 | u32 ac; |
e04da980 | 251 | |
2329d46d JR |
252 | gfn = gpte_to_gfn_lvl(pte, lvl); |
253 | gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT; | |
e04da980 JR |
254 | |
255 | if (PTTYPE == 32 && | |
256 | walker->level == PT_DIRECTORY_LEVEL && | |
257 | is_cpuid_PSE36()) | |
2329d46d JR |
258 | gfn += pse36_gfn_delta(pte); |
259 | ||
33770780 | 260 | ac = write_fault | fetch_fault | user_fault; |
2329d46d JR |
261 | |
262 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), | |
33770780 | 263 | ac); |
2329d46d JR |
264 | if (real_gpa == UNMAPPED_GVA) |
265 | return 0; | |
266 | ||
267 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
e04da980 | 268 | |
ac79c978 | 269 | break; |
815af8d4 | 270 | } |
ac79c978 | 271 | |
97d64b78 | 272 | pt_access &= pte_access; |
ac79c978 AK |
273 | --walker->level; |
274 | } | |
42bf3f0a | 275 | |
97d64b78 | 276 | eperm |= permission_fault(mmu, pte_access, access); |
134291bf TY |
277 | if (unlikely(eperm)) { |
278 | errcode |= PFERR_PRESENT_MASK; | |
f59c1d2d | 279 | goto error; |
134291bf | 280 | } |
f59c1d2d | 281 | |
8ea667f2 AK |
282 | if (!write_fault) |
283 | protect_clean_gpte(&pte_access, pte); | |
a78484c6 | 284 | |
8cbc7069 AK |
285 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault); |
286 | if (unlikely(ret < 0)) | |
287 | goto error; | |
288 | else if (ret) | |
289 | goto retry_walk; | |
42bf3f0a | 290 | |
fe135d2c AK |
291 | walker->pt_access = pt_access; |
292 | walker->pte_access = pte_access; | |
293 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 294 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
295 | return 1; |
296 | ||
f59c1d2d | 297 | error: |
134291bf | 298 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
299 | if (fetch_fault && (mmu->nx || |
300 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 301 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 302 | |
134291bf TY |
303 | walker->fault.vector = PF_VECTOR; |
304 | walker->fault.error_code_valid = true; | |
305 | walker->fault.error_code = errcode; | |
6389ee94 AK |
306 | walker->fault.address = addr; |
307 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 308 | |
8c28d031 | 309 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 310 | return 0; |
6aa8b732 AK |
311 | } |
312 | ||
1e301feb | 313 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 314 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
315 | { |
316 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 317 | access); |
1e301feb JR |
318 | } |
319 | ||
6539e738 JR |
320 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
321 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 322 | u32 access) |
6539e738 JR |
323 | { |
324 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 325 | addr, access); |
6539e738 JR |
326 | } |
327 | ||
407c61c6 XG |
328 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
329 | struct kvm_mmu_page *sp, u64 *spte, | |
330 | pt_element_t gpte) | |
331 | { | |
407c61c6 XG |
332 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) |
333 | goto no_present; | |
334 | ||
c3707958 | 335 | if (!is_present_gpte(gpte)) |
407c61c6 | 336 | goto no_present; |
407c61c6 XG |
337 | |
338 | if (!(gpte & PT_ACCESSED_MASK)) | |
339 | goto no_present; | |
340 | ||
341 | return false; | |
342 | ||
343 | no_present: | |
c3707958 | 344 | drop_spte(vcpu->kvm, spte); |
407c61c6 XG |
345 | return true; |
346 | } | |
347 | ||
ac3cd03c | 348 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 349 | u64 *spte, const void *pte) |
0028425f AK |
350 | { |
351 | pt_element_t gpte; | |
41074d07 | 352 | unsigned pte_access; |
35149e21 | 353 | pfn_t pfn; |
0028425f | 354 | |
0028425f | 355 | gpte = *(const pt_element_t *)pte; |
407c61c6 | 356 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
c7addb90 | 357 | return; |
407c61c6 | 358 | |
b8688d51 | 359 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
3d34adec | 360 | pte_access = sp->role.access & gpte_access(vcpu, gpte); |
8ea667f2 | 361 | protect_clean_gpte(&pte_access, gpte); |
0f53b5b1 | 362 | pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte)); |
cb9aaa30 | 363 | if (mmu_invalid_pfn(pfn)) |
d7824fff | 364 | return; |
0f53b5b1 | 365 | |
1403283a | 366 | /* |
0d2eb44f | 367 | * we call mmu_set_spte() with host_writable = true because that |
1403283a IE |
368 | * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1). |
369 | */ | |
ac3cd03c | 370 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, |
640d9b0d | 371 | NULL, PT_PAGE_TABLE_LEVEL, |
1403283a | 372 | gpte_to_gfn(gpte), pfn, true, true); |
0028425f AK |
373 | } |
374 | ||
39c8c672 AK |
375 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
376 | struct guest_walker *gw, int level) | |
377 | { | |
39c8c672 | 378 | pt_element_t curr_pte; |
189be38d XG |
379 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
380 | u64 mask; | |
381 | int r, index; | |
382 | ||
383 | if (level == PT_PAGE_TABLE_LEVEL) { | |
384 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
385 | base_gpa = pte_gpa & ~mask; | |
386 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
387 | ||
388 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
389 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
390 | curr_pte = gw->prefetch_ptes[index]; | |
391 | } else | |
392 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 393 | &curr_pte, sizeof(curr_pte)); |
189be38d | 394 | |
39c8c672 AK |
395 | return r || curr_pte != gw->ptes[level - 1]; |
396 | } | |
397 | ||
189be38d XG |
398 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
399 | u64 *sptep) | |
957ed9ef XG |
400 | { |
401 | struct kvm_mmu_page *sp; | |
189be38d | 402 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 403 | u64 *spte; |
189be38d | 404 | int i; |
957ed9ef XG |
405 | |
406 | sp = page_header(__pa(sptep)); | |
407 | ||
408 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
409 | return; | |
410 | ||
411 | if (sp->role.direct) | |
412 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
413 | ||
414 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
415 | spte = sp->spt + i; |
416 | ||
417 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
418 | pt_element_t gpte; | |
419 | unsigned pte_access; | |
420 | gfn_t gfn; | |
421 | pfn_t pfn; | |
957ed9ef XG |
422 | |
423 | if (spte == sptep) | |
424 | continue; | |
425 | ||
c3707958 | 426 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
427 | continue; |
428 | ||
429 | gpte = gptep[i]; | |
430 | ||
407c61c6 | 431 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
957ed9ef XG |
432 | continue; |
433 | ||
3d34adec | 434 | pte_access = sp->role.access & gpte_access(vcpu, gpte); |
8ea667f2 | 435 | protect_clean_gpte(&pte_access, gpte); |
957ed9ef | 436 | gfn = gpte_to_gfn(gpte); |
957ed9ef | 437 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
640d9b0d | 438 | pte_access & ACC_WRITE_MASK); |
cb9aaa30 | 439 | if (mmu_invalid_pfn(pfn)) |
957ed9ef | 440 | break; |
957ed9ef XG |
441 | |
442 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, | |
640d9b0d | 443 | NULL, PT_PAGE_TABLE_LEVEL, gfn, |
957ed9ef XG |
444 | pfn, true, true); |
445 | } | |
446 | } | |
447 | ||
6aa8b732 AK |
448 | /* |
449 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
450 | */ | |
e7a04c99 AK |
451 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
452 | struct guest_walker *gw, | |
7e4e4056 | 453 | int user_fault, int write_fault, int hlevel, |
b90a0e6c | 454 | int *emulate, pfn_t pfn, bool map_writable, |
fb67e14f | 455 | bool prefault) |
6aa8b732 | 456 | { |
abb9e0b8 | 457 | unsigned access = gw->pt_access; |
5991b332 | 458 | struct kvm_mmu_page *sp = NULL; |
5991b332 | 459 | int top_level; |
84754cd8 | 460 | unsigned direct_access; |
24157aaf | 461 | struct kvm_shadow_walk_iterator it; |
abb9e0b8 | 462 | |
43a3795a | 463 | if (!is_present_gpte(gw->ptes[gw->level - 1])) |
e7a04c99 | 464 | return NULL; |
6aa8b732 | 465 | |
b36c7a7c | 466 | direct_access = gw->pte_access; |
84754cd8 | 467 | |
5991b332 AK |
468 | top_level = vcpu->arch.mmu.root_level; |
469 | if (top_level == PT32E_ROOT_LEVEL) | |
470 | top_level = PT32_ROOT_LEVEL; | |
471 | /* | |
472 | * Verify that the top-level gpte is still there. Since the page | |
473 | * is a root page, it is either write protected (and cannot be | |
474 | * changed from now on) or it is invalid (in which case, we don't | |
475 | * really care if it changes underneath us after this point). | |
476 | */ | |
477 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
478 | goto out_gpte_changed; | |
479 | ||
24157aaf AK |
480 | for (shadow_walk_init(&it, vcpu, addr); |
481 | shadow_walk_okay(&it) && it.level > gw->level; | |
482 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
483 | gfn_t table_gfn; |
484 | ||
a30f47cb | 485 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 486 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 487 | |
5991b332 | 488 | sp = NULL; |
24157aaf AK |
489 | if (!is_shadow_present_pte(*it.sptep)) { |
490 | table_gfn = gw->table_gfn[it.level - 2]; | |
491 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
492 | false, access, it.sptep); | |
5991b332 | 493 | } |
0b3c9333 AK |
494 | |
495 | /* | |
496 | * Verify that the gpte in the page we've just write | |
497 | * protected is still there. | |
498 | */ | |
24157aaf | 499 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 500 | goto out_gpte_changed; |
abb9e0b8 | 501 | |
5991b332 | 502 | if (sp) |
24157aaf | 503 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 504 | } |
050e6499 | 505 | |
0b3c9333 | 506 | for (; |
24157aaf AK |
507 | shadow_walk_okay(&it) && it.level > hlevel; |
508 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
509 | gfn_t direct_gfn; |
510 | ||
a30f47cb | 511 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 512 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 513 | |
24157aaf | 514 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 515 | |
24157aaf | 516 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
517 | continue; |
518 | ||
24157aaf | 519 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 520 | |
24157aaf AK |
521 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
522 | true, direct_access, it.sptep); | |
523 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
524 | } |
525 | ||
a30f47cb | 526 | clear_sp_write_flooding_count(it.sptep); |
b36c7a7c | 527 | mmu_set_spte(vcpu, it.sptep, access, gw->pte_access, |
b90a0e6c | 528 | user_fault, write_fault, emulate, it.level, |
fb67e14f | 529 | gw->gfn, pfn, prefault, map_writable); |
189be38d | 530 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 531 | |
24157aaf | 532 | return it.sptep; |
0b3c9333 AK |
533 | |
534 | out_gpte_changed: | |
5991b332 | 535 | if (sp) |
24157aaf | 536 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 AK |
537 | kvm_release_pfn_clean(pfn); |
538 | return NULL; | |
6aa8b732 AK |
539 | } |
540 | ||
6aa8b732 AK |
541 | /* |
542 | * Page fault handler. There are several causes for a page fault: | |
543 | * - there is no shadow pte for the guest pte | |
544 | * - write access through a shadow pte marked read only so that we can set | |
545 | * the dirty bit | |
546 | * - write access to a shadow pte marked read only so we can update the page | |
547 | * dirty bitmap, when userspace requests it | |
548 | * - mmio access; in this case we will never install a present shadow pte | |
549 | * - normal guest page fault due to the guest pte marked not present, not | |
550 | * writable, or not executable | |
551 | * | |
e2dec939 AK |
552 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
553 | * a negative value on error. | |
6aa8b732 | 554 | */ |
56028d08 | 555 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 556 | bool prefault) |
6aa8b732 AK |
557 | { |
558 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
559 | int user_fault = error_code & PFERR_USER_MASK; |
560 | struct guest_walker walker; | |
d555c333 | 561 | u64 *sptep; |
b90a0e6c | 562 | int emulate = 0; |
e2dec939 | 563 | int r; |
35149e21 | 564 | pfn_t pfn; |
7e4e4056 | 565 | int level = PT_PAGE_TABLE_LEVEL; |
936a5fe6 | 566 | int force_pt_level; |
e930bffe | 567 | unsigned long mmu_seq; |
612819c3 | 568 | bool map_writable; |
6aa8b732 | 569 | |
b8688d51 | 570 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 571 | |
ce88decf XG |
572 | if (unlikely(error_code & PFERR_RSVD_MASK)) |
573 | return handle_mmio_page_fault(vcpu, addr, error_code, | |
574 | mmu_is_nested(vcpu)); | |
575 | ||
e2dec939 AK |
576 | r = mmu_topup_memory_caches(vcpu); |
577 | if (r) | |
578 | return r; | |
714b93da | 579 | |
6aa8b732 | 580 | /* |
a8b876b1 | 581 | * Look up the guest pte for the faulting address. |
6aa8b732 | 582 | */ |
33770780 | 583 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
584 | |
585 | /* | |
586 | * The page is not mapped by the guest. Let the guest handle it. | |
587 | */ | |
7993ba43 | 588 | if (!r) { |
b8688d51 | 589 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 590 | if (!prefault) |
fb67e14f | 591 | inject_page_fault(vcpu, &walker.fault); |
a30f47cb | 592 | |
6aa8b732 AK |
593 | return 0; |
594 | } | |
595 | ||
936a5fe6 AA |
596 | if (walker.level >= PT_DIRECTORY_LEVEL) |
597 | force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn); | |
598 | else | |
599 | force_pt_level = 1; | |
600 | if (!force_pt_level) { | |
7e4e4056 JR |
601 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); |
602 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 603 | } |
7e4e4056 | 604 | |
e930bffe | 605 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 606 | smp_rmb(); |
af585b92 | 607 | |
78b2c54a | 608 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 609 | &map_writable)) |
af585b92 | 610 | return 0; |
d7824fff | 611 | |
d7c55201 XG |
612 | if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr, |
613 | walker.gfn, pfn, walker.pte_access, &r)) | |
614 | return r; | |
615 | ||
aaee2c94 | 616 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
617 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
618 | goto out_unlock; | |
bc32ce21 | 619 | |
0375f7fa | 620 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
eb787d10 | 621 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
622 | if (!force_pt_level) |
623 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
d555c333 | 624 | sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
b90a0e6c | 625 | level, &emulate, pfn, map_writable, prefault); |
a24e8099 | 626 | (void)sptep; |
b90a0e6c XG |
627 | pgprintk("%s: shadow pte %p %llx emulate %d\n", __func__, |
628 | sptep, *sptep, emulate); | |
cea0f0e7 | 629 | |
1165f5fe | 630 | ++vcpu->stat.pf_fixed; |
0375f7fa | 631 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 632 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 633 | |
b90a0e6c | 634 | return emulate; |
e930bffe AA |
635 | |
636 | out_unlock: | |
637 | spin_unlock(&vcpu->kvm->mmu_lock); | |
638 | kvm_release_pfn_clean(pfn); | |
639 | return 0; | |
6aa8b732 AK |
640 | } |
641 | ||
505aef8f XG |
642 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
643 | { | |
644 | int offset = 0; | |
645 | ||
f71fa31f | 646 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
505aef8f XG |
647 | |
648 | if (PTTYPE == 32) | |
649 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
650 | ||
651 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
652 | } | |
653 | ||
a461930b | 654 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 655 | { |
a461930b | 656 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 657 | struct kvm_mmu_page *sp; |
a461930b AK |
658 | int level; |
659 | u64 *sptep; | |
660 | ||
bebb106a XG |
661 | vcpu_clear_mmio_info(vcpu, gva); |
662 | ||
f57f2ef5 XG |
663 | /* |
664 | * No need to check return value here, rmap_can_add() can | |
665 | * help us to skip pte prefetch later. | |
666 | */ | |
667 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 668 | |
f57f2ef5 | 669 | spin_lock(&vcpu->kvm->mmu_lock); |
a461930b AK |
670 | for_each_shadow_entry(vcpu, gva, iterator) { |
671 | level = iterator.level; | |
672 | sptep = iterator.sptep; | |
ad218f85 | 673 | |
f78978aa | 674 | sp = page_header(__pa(sptep)); |
884a0ff0 | 675 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
676 | pt_element_t gpte; |
677 | gpa_t pte_gpa; | |
678 | ||
f78978aa XG |
679 | if (!sp->unsync) |
680 | break; | |
681 | ||
505aef8f | 682 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 683 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 684 | |
505aef8f XG |
685 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
686 | kvm_flush_remote_tlbs(vcpu->kvm); | |
f57f2ef5 XG |
687 | |
688 | if (!rmap_can_add(vcpu)) | |
689 | break; | |
690 | ||
691 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
692 | sizeof(pt_element_t))) | |
693 | break; | |
694 | ||
695 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 696 | } |
a7052897 | 697 | |
f78978aa | 698 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
699 | break; |
700 | } | |
ad218f85 | 701 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
702 | } |
703 | ||
1871c602 | 704 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 705 | struct x86_exception *exception) |
6aa8b732 AK |
706 | { |
707 | struct guest_walker walker; | |
e119d117 AK |
708 | gpa_t gpa = UNMAPPED_GVA; |
709 | int r; | |
6aa8b732 | 710 | |
33770780 | 711 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 712 | |
e119d117 | 713 | if (r) { |
1755fbcc | 714 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 715 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
716 | } else if (exception) |
717 | *exception = walker.fault; | |
6aa8b732 AK |
718 | |
719 | return gpa; | |
720 | } | |
721 | ||
6539e738 | 722 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
723 | u32 access, |
724 | struct x86_exception *exception) | |
6539e738 JR |
725 | { |
726 | struct guest_walker walker; | |
727 | gpa_t gpa = UNMAPPED_GVA; | |
728 | int r; | |
729 | ||
33770780 | 730 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
731 | |
732 | if (r) { | |
733 | gpa = gfn_to_gpa(walker.gfn); | |
734 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
735 | } else if (exception) |
736 | *exception = walker.fault; | |
6539e738 JR |
737 | |
738 | return gpa; | |
739 | } | |
740 | ||
e8bc217a MT |
741 | /* |
742 | * Using the cached information from sp->gfns is safe because: | |
743 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
744 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
745 | * |
746 | * Note: | |
747 | * We should flush all tlbs if spte is dropped even though guest is | |
748 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
749 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
750 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
751 | * freed pages. | |
752 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. | |
e8bc217a | 753 | */ |
a4a8e6f7 | 754 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 755 | { |
505aef8f | 756 | int i, nr_present = 0; |
9bdbba13 | 757 | bool host_writable; |
51fb60d8 | 758 | gpa_t first_pte_gpa; |
e8bc217a | 759 | |
2032a93d LJ |
760 | /* direct kvm_mmu_page can not be unsync. */ |
761 | BUG_ON(sp->role.direct); | |
762 | ||
505aef8f | 763 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 764 | |
e8bc217a MT |
765 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
766 | unsigned pte_access; | |
767 | pt_element_t gpte; | |
768 | gpa_t pte_gpa; | |
f55c3f41 | 769 | gfn_t gfn; |
e8bc217a | 770 | |
ce88decf | 771 | if (!sp->spt[i]) |
e8bc217a MT |
772 | continue; |
773 | ||
51fb60d8 | 774 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
775 | |
776 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
777 | sizeof(pt_element_t))) | |
778 | return -EINVAL; | |
779 | ||
407c61c6 | 780 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { |
a4ee1ca4 | 781 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
782 | continue; |
783 | } | |
784 | ||
ce88decf XG |
785 | gfn = gpte_to_gfn(gpte); |
786 | pte_access = sp->role.access; | |
3d34adec | 787 | pte_access &= gpte_access(vcpu, gpte); |
8ea667f2 | 788 | protect_clean_gpte(&pte_access, gpte); |
ce88decf XG |
789 | |
790 | if (sync_mmio_spte(&sp->spt[i], gfn, pte_access, &nr_present)) | |
791 | continue; | |
792 | ||
407c61c6 | 793 | if (gfn != sp->gfns[i]) { |
c3707958 | 794 | drop_spte(vcpu->kvm, &sp->spt[i]); |
a4ee1ca4 | 795 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
796 | continue; |
797 | } | |
798 | ||
799 | nr_present++; | |
ce88decf | 800 | |
f8e453b0 XG |
801 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
802 | ||
e8bc217a | 803 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, |
640d9b0d | 804 | PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 805 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 806 | host_writable); |
e8bc217a MT |
807 | } |
808 | ||
809 | return !nr_present; | |
810 | } | |
811 | ||
6aa8b732 AK |
812 | #undef pt_element_t |
813 | #undef guest_walker | |
814 | #undef FNAME | |
815 | #undef PT_BASE_ADDR_MASK | |
816 | #undef PT_INDEX | |
e04da980 JR |
817 | #undef PT_LVL_ADDR_MASK |
818 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 819 | #undef PT_LEVEL_BITS |
cea0f0e7 | 820 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 821 | #undef gpte_to_gfn |
e04da980 | 822 | #undef gpte_to_gfn_lvl |
b3e4e63f | 823 | #undef CMPXCHG |