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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
47 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
48 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 50 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 51 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 52 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
53 | #else |
54 | #error Invalid PTTYPE value | |
55 | #endif | |
56 | ||
e04da980 JR |
57 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
58 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 59 | |
6aa8b732 AK |
60 | /* |
61 | * The guest_walker structure emulates the behavior of the hardware page | |
62 | * table walker. | |
63 | */ | |
64 | struct guest_walker { | |
65 | int level; | |
cea0f0e7 | 66 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 67 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 68 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 69 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
70 | unsigned pt_access; |
71 | unsigned pte_access; | |
815af8d4 | 72 | gfn_t gfn; |
8c28d031 | 73 | struct x86_exception fault; |
6aa8b732 AK |
74 | }; |
75 | ||
e04da980 | 76 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 77 | { |
e04da980 | 78 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
79 | } |
80 | ||
a78484c6 | 81 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
82 | pt_element_t __user *ptep_user, unsigned index, |
83 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 84 | { |
c8cfbb55 | 85 | int npages; |
b3e4e63f MT |
86 | pt_element_t ret; |
87 | pt_element_t *table; | |
88 | struct page *page; | |
89 | ||
c8cfbb55 TY |
90 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page); |
91 | /* Check if the user is doing something meaningless. */ | |
92 | if (unlikely(npages != 1)) | |
a78484c6 RJ |
93 | return -EFAULT; |
94 | ||
8fd75e12 | 95 | table = kmap_atomic(page); |
b3e4e63f | 96 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
8fd75e12 | 97 | kunmap_atomic(table); |
b3e4e63f MT |
98 | |
99 | kvm_release_page_dirty(page); | |
100 | ||
101 | return (ret != orig_pte); | |
102 | } | |
103 | ||
640d9b0d XG |
104 | static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte, |
105 | bool last) | |
bedbe4ee AK |
106 | { |
107 | unsigned access; | |
108 | ||
109 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
640d9b0d XG |
110 | if (last && !is_dirty_gpte(gpte)) |
111 | access &= ~ACC_WRITE_MASK; | |
112 | ||
bedbe4ee | 113 | #if PTTYPE == 64 |
2d48a985 | 114 | if (vcpu->arch.mmu.nx) |
bedbe4ee AK |
115 | access &= ~(gpte >> PT64_NX_SHIFT); |
116 | #endif | |
117 | return access; | |
118 | } | |
119 | ||
3c8c652a TY |
120 | static bool FNAME(is_last_gpte)(struct guest_walker *walker, |
121 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
122 | pt_element_t gpte) | |
123 | { | |
124 | if (walker->level == PT_PAGE_TABLE_LEVEL) | |
125 | return true; | |
126 | ||
127 | if ((walker->level == PT_DIRECTORY_LEVEL) && is_large_pte(gpte) && | |
128 | (PTTYPE == 64 || is_pse(vcpu))) | |
129 | return true; | |
130 | ||
131 | if ((walker->level == PT_PDPE_LEVEL) && is_large_pte(gpte) && | |
132 | (mmu->root_level == PT64_ROOT_LEVEL)) | |
133 | return true; | |
134 | ||
135 | return false; | |
136 | } | |
137 | ||
ac79c978 AK |
138 | /* |
139 | * Fetch a guest pte for a guest virtual address | |
140 | */ | |
1e301feb JR |
141 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
142 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 143 | gva_t addr, u32 access) |
6aa8b732 | 144 | { |
42bf3f0a | 145 | pt_element_t pte; |
b7233635 | 146 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 147 | gfn_t table_gfn; |
f59c1d2d | 148 | unsigned index, pt_access, uninitialized_var(pte_access); |
42bf3f0a | 149 | gpa_t pte_gpa; |
cd46868c | 150 | bool eperm, last_gpte; |
134291bf TY |
151 | int offset; |
152 | const int write_fault = access & PFERR_WRITE_MASK; | |
153 | const int user_fault = access & PFERR_USER_MASK; | |
154 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
155 | u16 errcode = 0; | |
6aa8b732 | 156 | |
07420171 AK |
157 | trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault, |
158 | fetch_fault); | |
92c1c1e8 | 159 | retry_walk: |
134291bf | 160 | eperm = false; |
1e301feb JR |
161 | walker->level = mmu->root_level; |
162 | pte = mmu->get_cr3(vcpu); | |
163 | ||
1b0973bd | 164 | #if PTTYPE == 64 |
1e301feb | 165 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 166 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 167 | trace_kvm_mmu_paging_element(pte, walker->level); |
134291bf | 168 | if (!is_present_gpte(pte)) |
f59c1d2d | 169 | goto error; |
1b0973bd AK |
170 | --walker->level; |
171 | } | |
172 | #endif | |
a9058ecd | 173 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 174 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 175 | |
fe135d2c | 176 | pt_access = ACC_ALL; |
ac79c978 AK |
177 | |
178 | for (;;) { | |
6e2ca7d1 TY |
179 | gfn_t real_gfn; |
180 | unsigned long host_addr; | |
181 | ||
42bf3f0a | 182 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 183 | |
5fb07ddb | 184 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
185 | offset = index * sizeof(pt_element_t); |
186 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 187 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 188 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 189 | |
6e2ca7d1 TY |
190 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
191 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
134291bf TY |
192 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
193 | goto error; | |
6e2ca7d1 TY |
194 | real_gfn = gpa_to_gfn(real_gfn); |
195 | ||
196 | host_addr = gfn_to_hva(vcpu->kvm, real_gfn); | |
134291bf TY |
197 | if (unlikely(kvm_is_error_hva(host_addr))) |
198 | goto error; | |
6e2ca7d1 TY |
199 | |
200 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
201 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
202 | goto error; | |
a6085fba | 203 | |
07420171 | 204 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 205 | |
134291bf TY |
206 | if (unlikely(!is_present_gpte(pte))) |
207 | goto error; | |
7993ba43 | 208 | |
781e0743 AK |
209 | if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte, |
210 | walker->level))) { | |
134291bf TY |
211 | errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
212 | goto error; | |
f59c1d2d | 213 | } |
82725b20 | 214 | |
bebb106a XG |
215 | if (!check_write_user_access(vcpu, write_fault, user_fault, |
216 | pte)) | |
f59c1d2d | 217 | eperm = true; |
7993ba43 | 218 | |
73b1087e | 219 | #if PTTYPE == 64 |
781e0743 | 220 | if (unlikely(fetch_fault && (pte & PT64_NX_MASK))) |
f59c1d2d | 221 | eperm = true; |
73b1087e AK |
222 | #endif |
223 | ||
cd46868c YW |
224 | last_gpte = FNAME(is_last_gpte)(walker, vcpu, mmu, pte); |
225 | if (last_gpte) { | |
226 | pte_access = pt_access & | |
227 | FNAME(gpte_access)(vcpu, pte, true); | |
228 | /* check if the kernel is fetching from user page */ | |
229 | if (unlikely(pte_access & PT_USER_MASK) && | |
230 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
231 | if (fetch_fault && !user_fault) | |
232 | eperm = true; | |
233 | } | |
234 | ||
134291bf | 235 | if (!eperm && unlikely(!(pte & PT_ACCESSED_MASK))) { |
a78484c6 | 236 | int ret; |
07420171 AK |
237 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, |
238 | sizeof(pte)); | |
c8cfbb55 TY |
239 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, |
240 | pte, pte|PT_ACCESSED_MASK); | |
134291bf TY |
241 | if (unlikely(ret < 0)) |
242 | goto error; | |
243 | else if (ret) | |
92c1c1e8 | 244 | goto retry_walk; |
a78484c6 | 245 | |
f3b8c964 | 246 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 247 | pte |= PT_ACCESSED_MASK; |
bf3f8e86 | 248 | } |
815af8d4 | 249 | |
7819026e MT |
250 | walker->ptes[walker->level - 1] = pte; |
251 | ||
cd46868c | 252 | if (last_gpte) { |
e04da980 | 253 | int lvl = walker->level; |
2329d46d JR |
254 | gpa_t real_gpa; |
255 | gfn_t gfn; | |
33770780 | 256 | u32 ac; |
e04da980 | 257 | |
2329d46d JR |
258 | gfn = gpte_to_gfn_lvl(pte, lvl); |
259 | gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT; | |
e04da980 JR |
260 | |
261 | if (PTTYPE == 32 && | |
262 | walker->level == PT_DIRECTORY_LEVEL && | |
263 | is_cpuid_PSE36()) | |
2329d46d JR |
264 | gfn += pse36_gfn_delta(pte); |
265 | ||
33770780 | 266 | ac = write_fault | fetch_fault | user_fault; |
2329d46d JR |
267 | |
268 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), | |
33770780 | 269 | ac); |
2329d46d JR |
270 | if (real_gpa == UNMAPPED_GVA) |
271 | return 0; | |
272 | ||
273 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
e04da980 | 274 | |
ac79c978 | 275 | break; |
815af8d4 | 276 | } |
ac79c978 | 277 | |
640d9b0d | 278 | pt_access &= FNAME(gpte_access)(vcpu, pte, false); |
ac79c978 AK |
279 | --walker->level; |
280 | } | |
42bf3f0a | 281 | |
134291bf TY |
282 | if (unlikely(eperm)) { |
283 | errcode |= PFERR_PRESENT_MASK; | |
f59c1d2d | 284 | goto error; |
134291bf | 285 | } |
f59c1d2d | 286 | |
781e0743 | 287 | if (write_fault && unlikely(!is_dirty_gpte(pte))) { |
a78484c6 | 288 | int ret; |
b3e4e63f | 289 | |
07420171 | 290 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
c8cfbb55 TY |
291 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, |
292 | pte, pte|PT_DIRTY_MASK); | |
134291bf | 293 | if (unlikely(ret < 0)) |
a78484c6 | 294 | goto error; |
134291bf | 295 | else if (ret) |
92c1c1e8 | 296 | goto retry_walk; |
a78484c6 | 297 | |
f3b8c964 | 298 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 299 | pte |= PT_DIRTY_MASK; |
7819026e | 300 | walker->ptes[walker->level - 1] = pte; |
42bf3f0a AK |
301 | } |
302 | ||
fe135d2c AK |
303 | walker->pt_access = pt_access; |
304 | walker->pte_access = pte_access; | |
305 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 306 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
307 | return 1; |
308 | ||
f59c1d2d | 309 | error: |
134291bf | 310 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
311 | if (fetch_fault && (mmu->nx || |
312 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 313 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 314 | |
134291bf TY |
315 | walker->fault.vector = PF_VECTOR; |
316 | walker->fault.error_code_valid = true; | |
317 | walker->fault.error_code = errcode; | |
6389ee94 AK |
318 | walker->fault.address = addr; |
319 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 320 | |
8c28d031 | 321 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 322 | return 0; |
6aa8b732 AK |
323 | } |
324 | ||
1e301feb | 325 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 326 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
327 | { |
328 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 329 | access); |
1e301feb JR |
330 | } |
331 | ||
6539e738 JR |
332 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
333 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 334 | u32 access) |
6539e738 JR |
335 | { |
336 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 337 | addr, access); |
6539e738 JR |
338 | } |
339 | ||
407c61c6 XG |
340 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
341 | struct kvm_mmu_page *sp, u64 *spte, | |
342 | pt_element_t gpte) | |
343 | { | |
407c61c6 XG |
344 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) |
345 | goto no_present; | |
346 | ||
c3707958 | 347 | if (!is_present_gpte(gpte)) |
407c61c6 | 348 | goto no_present; |
407c61c6 XG |
349 | |
350 | if (!(gpte & PT_ACCESSED_MASK)) | |
351 | goto no_present; | |
352 | ||
353 | return false; | |
354 | ||
355 | no_present: | |
c3707958 | 356 | drop_spte(vcpu->kvm, spte); |
407c61c6 XG |
357 | return true; |
358 | } | |
359 | ||
ac3cd03c | 360 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 361 | u64 *spte, const void *pte) |
0028425f AK |
362 | { |
363 | pt_element_t gpte; | |
41074d07 | 364 | unsigned pte_access; |
35149e21 | 365 | pfn_t pfn; |
0028425f | 366 | |
0028425f | 367 | gpte = *(const pt_element_t *)pte; |
407c61c6 | 368 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
c7addb90 | 369 | return; |
407c61c6 | 370 | |
b8688d51 | 371 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
640d9b0d | 372 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte, true); |
0f53b5b1 | 373 | pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte)); |
d7c55201 | 374 | if (mmu_invalid_pfn(pfn)) { |
0f53b5b1 | 375 | kvm_release_pfn_clean(pfn); |
d7824fff | 376 | return; |
0f53b5b1 | 377 | } |
0f53b5b1 | 378 | |
1403283a | 379 | /* |
0d2eb44f | 380 | * we call mmu_set_spte() with host_writable = true because that |
1403283a IE |
381 | * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1). |
382 | */ | |
ac3cd03c | 383 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, |
640d9b0d | 384 | NULL, PT_PAGE_TABLE_LEVEL, |
1403283a | 385 | gpte_to_gfn(gpte), pfn, true, true); |
0028425f AK |
386 | } |
387 | ||
39c8c672 AK |
388 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
389 | struct guest_walker *gw, int level) | |
390 | { | |
39c8c672 | 391 | pt_element_t curr_pte; |
189be38d XG |
392 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
393 | u64 mask; | |
394 | int r, index; | |
395 | ||
396 | if (level == PT_PAGE_TABLE_LEVEL) { | |
397 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
398 | base_gpa = pte_gpa & ~mask; | |
399 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
400 | ||
401 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
402 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
403 | curr_pte = gw->prefetch_ptes[index]; | |
404 | } else | |
405 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 406 | &curr_pte, sizeof(curr_pte)); |
189be38d | 407 | |
39c8c672 AK |
408 | return r || curr_pte != gw->ptes[level - 1]; |
409 | } | |
410 | ||
189be38d XG |
411 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
412 | u64 *sptep) | |
957ed9ef XG |
413 | { |
414 | struct kvm_mmu_page *sp; | |
189be38d | 415 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 416 | u64 *spte; |
189be38d | 417 | int i; |
957ed9ef XG |
418 | |
419 | sp = page_header(__pa(sptep)); | |
420 | ||
421 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
422 | return; | |
423 | ||
424 | if (sp->role.direct) | |
425 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
426 | ||
427 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
428 | spte = sp->spt + i; |
429 | ||
430 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
431 | pt_element_t gpte; | |
432 | unsigned pte_access; | |
433 | gfn_t gfn; | |
434 | pfn_t pfn; | |
957ed9ef XG |
435 | |
436 | if (spte == sptep) | |
437 | continue; | |
438 | ||
c3707958 | 439 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
440 | continue; |
441 | ||
442 | gpte = gptep[i]; | |
443 | ||
407c61c6 | 444 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
957ed9ef XG |
445 | continue; |
446 | ||
640d9b0d XG |
447 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte, |
448 | true); | |
957ed9ef | 449 | gfn = gpte_to_gfn(gpte); |
957ed9ef | 450 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
640d9b0d | 451 | pte_access & ACC_WRITE_MASK); |
d7c55201 | 452 | if (mmu_invalid_pfn(pfn)) { |
957ed9ef XG |
453 | kvm_release_pfn_clean(pfn); |
454 | break; | |
455 | } | |
456 | ||
457 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, | |
640d9b0d | 458 | NULL, PT_PAGE_TABLE_LEVEL, gfn, |
957ed9ef XG |
459 | pfn, true, true); |
460 | } | |
461 | } | |
462 | ||
6aa8b732 AK |
463 | /* |
464 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
465 | */ | |
e7a04c99 AK |
466 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
467 | struct guest_walker *gw, | |
7e4e4056 | 468 | int user_fault, int write_fault, int hlevel, |
b90a0e6c | 469 | int *emulate, pfn_t pfn, bool map_writable, |
fb67e14f | 470 | bool prefault) |
6aa8b732 | 471 | { |
abb9e0b8 | 472 | unsigned access = gw->pt_access; |
5991b332 | 473 | struct kvm_mmu_page *sp = NULL; |
5991b332 | 474 | int top_level; |
84754cd8 | 475 | unsigned direct_access; |
24157aaf | 476 | struct kvm_shadow_walk_iterator it; |
abb9e0b8 | 477 | |
43a3795a | 478 | if (!is_present_gpte(gw->ptes[gw->level - 1])) |
e7a04c99 | 479 | return NULL; |
6aa8b732 | 480 | |
b36c7a7c | 481 | direct_access = gw->pte_access; |
84754cd8 | 482 | |
5991b332 AK |
483 | top_level = vcpu->arch.mmu.root_level; |
484 | if (top_level == PT32E_ROOT_LEVEL) | |
485 | top_level = PT32_ROOT_LEVEL; | |
486 | /* | |
487 | * Verify that the top-level gpte is still there. Since the page | |
488 | * is a root page, it is either write protected (and cannot be | |
489 | * changed from now on) or it is invalid (in which case, we don't | |
490 | * really care if it changes underneath us after this point). | |
491 | */ | |
492 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
493 | goto out_gpte_changed; | |
494 | ||
24157aaf AK |
495 | for (shadow_walk_init(&it, vcpu, addr); |
496 | shadow_walk_okay(&it) && it.level > gw->level; | |
497 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
498 | gfn_t table_gfn; |
499 | ||
a30f47cb | 500 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 501 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 502 | |
5991b332 | 503 | sp = NULL; |
24157aaf AK |
504 | if (!is_shadow_present_pte(*it.sptep)) { |
505 | table_gfn = gw->table_gfn[it.level - 2]; | |
506 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
507 | false, access, it.sptep); | |
5991b332 | 508 | } |
0b3c9333 AK |
509 | |
510 | /* | |
511 | * Verify that the gpte in the page we've just write | |
512 | * protected is still there. | |
513 | */ | |
24157aaf | 514 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 515 | goto out_gpte_changed; |
abb9e0b8 | 516 | |
5991b332 | 517 | if (sp) |
24157aaf | 518 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 519 | } |
050e6499 | 520 | |
0b3c9333 | 521 | for (; |
24157aaf AK |
522 | shadow_walk_okay(&it) && it.level > hlevel; |
523 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
524 | gfn_t direct_gfn; |
525 | ||
a30f47cb | 526 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 527 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 528 | |
24157aaf | 529 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 530 | |
24157aaf | 531 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
532 | continue; |
533 | ||
24157aaf | 534 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 535 | |
24157aaf AK |
536 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
537 | true, direct_access, it.sptep); | |
538 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
539 | } |
540 | ||
a30f47cb | 541 | clear_sp_write_flooding_count(it.sptep); |
b36c7a7c | 542 | mmu_set_spte(vcpu, it.sptep, access, gw->pte_access, |
b90a0e6c | 543 | user_fault, write_fault, emulate, it.level, |
fb67e14f | 544 | gw->gfn, pfn, prefault, map_writable); |
189be38d | 545 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 546 | |
24157aaf | 547 | return it.sptep; |
0b3c9333 AK |
548 | |
549 | out_gpte_changed: | |
5991b332 | 550 | if (sp) |
24157aaf | 551 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 AK |
552 | kvm_release_pfn_clean(pfn); |
553 | return NULL; | |
6aa8b732 AK |
554 | } |
555 | ||
6aa8b732 AK |
556 | /* |
557 | * Page fault handler. There are several causes for a page fault: | |
558 | * - there is no shadow pte for the guest pte | |
559 | * - write access through a shadow pte marked read only so that we can set | |
560 | * the dirty bit | |
561 | * - write access to a shadow pte marked read only so we can update the page | |
562 | * dirty bitmap, when userspace requests it | |
563 | * - mmio access; in this case we will never install a present shadow pte | |
564 | * - normal guest page fault due to the guest pte marked not present, not | |
565 | * writable, or not executable | |
566 | * | |
e2dec939 AK |
567 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
568 | * a negative value on error. | |
6aa8b732 | 569 | */ |
56028d08 | 570 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 571 | bool prefault) |
6aa8b732 AK |
572 | { |
573 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
574 | int user_fault = error_code & PFERR_USER_MASK; |
575 | struct guest_walker walker; | |
d555c333 | 576 | u64 *sptep; |
b90a0e6c | 577 | int emulate = 0; |
e2dec939 | 578 | int r; |
35149e21 | 579 | pfn_t pfn; |
7e4e4056 | 580 | int level = PT_PAGE_TABLE_LEVEL; |
936a5fe6 | 581 | int force_pt_level; |
e930bffe | 582 | unsigned long mmu_seq; |
612819c3 | 583 | bool map_writable; |
6aa8b732 | 584 | |
b8688d51 | 585 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 586 | |
ce88decf XG |
587 | if (unlikely(error_code & PFERR_RSVD_MASK)) |
588 | return handle_mmio_page_fault(vcpu, addr, error_code, | |
589 | mmu_is_nested(vcpu)); | |
590 | ||
e2dec939 AK |
591 | r = mmu_topup_memory_caches(vcpu); |
592 | if (r) | |
593 | return r; | |
714b93da | 594 | |
6aa8b732 | 595 | /* |
a8b876b1 | 596 | * Look up the guest pte for the faulting address. |
6aa8b732 | 597 | */ |
33770780 | 598 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
599 | |
600 | /* | |
601 | * The page is not mapped by the guest. Let the guest handle it. | |
602 | */ | |
7993ba43 | 603 | if (!r) { |
b8688d51 | 604 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 605 | if (!prefault) |
fb67e14f | 606 | inject_page_fault(vcpu, &walker.fault); |
a30f47cb | 607 | |
6aa8b732 AK |
608 | return 0; |
609 | } | |
610 | ||
936a5fe6 AA |
611 | if (walker.level >= PT_DIRECTORY_LEVEL) |
612 | force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn); | |
613 | else | |
614 | force_pt_level = 1; | |
615 | if (!force_pt_level) { | |
7e4e4056 JR |
616 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); |
617 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 618 | } |
7e4e4056 | 619 | |
e930bffe | 620 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 621 | smp_rmb(); |
af585b92 | 622 | |
78b2c54a | 623 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 624 | &map_writable)) |
af585b92 | 625 | return 0; |
d7824fff | 626 | |
d7c55201 XG |
627 | if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr, |
628 | walker.gfn, pfn, walker.pte_access, &r)) | |
629 | return r; | |
630 | ||
aaee2c94 | 631 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
632 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
633 | goto out_unlock; | |
bc32ce21 | 634 | |
0375f7fa | 635 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
eb787d10 | 636 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
637 | if (!force_pt_level) |
638 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
d555c333 | 639 | sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
b90a0e6c | 640 | level, &emulate, pfn, map_writable, prefault); |
a24e8099 | 641 | (void)sptep; |
b90a0e6c XG |
642 | pgprintk("%s: shadow pte %p %llx emulate %d\n", __func__, |
643 | sptep, *sptep, emulate); | |
cea0f0e7 | 644 | |
1165f5fe | 645 | ++vcpu->stat.pf_fixed; |
0375f7fa | 646 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 647 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 648 | |
b90a0e6c | 649 | return emulate; |
e930bffe AA |
650 | |
651 | out_unlock: | |
652 | spin_unlock(&vcpu->kvm->mmu_lock); | |
653 | kvm_release_pfn_clean(pfn); | |
654 | return 0; | |
6aa8b732 AK |
655 | } |
656 | ||
505aef8f XG |
657 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
658 | { | |
659 | int offset = 0; | |
660 | ||
661 | WARN_ON(sp->role.level != 1); | |
662 | ||
663 | if (PTTYPE == 32) | |
664 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
665 | ||
666 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
667 | } | |
668 | ||
a461930b | 669 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 670 | { |
a461930b | 671 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 672 | struct kvm_mmu_page *sp; |
a461930b AK |
673 | int level; |
674 | u64 *sptep; | |
675 | ||
bebb106a XG |
676 | vcpu_clear_mmio_info(vcpu, gva); |
677 | ||
f57f2ef5 XG |
678 | /* |
679 | * No need to check return value here, rmap_can_add() can | |
680 | * help us to skip pte prefetch later. | |
681 | */ | |
682 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 683 | |
f57f2ef5 | 684 | spin_lock(&vcpu->kvm->mmu_lock); |
a461930b AK |
685 | for_each_shadow_entry(vcpu, gva, iterator) { |
686 | level = iterator.level; | |
687 | sptep = iterator.sptep; | |
ad218f85 | 688 | |
f78978aa | 689 | sp = page_header(__pa(sptep)); |
884a0ff0 | 690 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
691 | pt_element_t gpte; |
692 | gpa_t pte_gpa; | |
693 | ||
f78978aa XG |
694 | if (!sp->unsync) |
695 | break; | |
696 | ||
505aef8f | 697 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 698 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 699 | |
505aef8f XG |
700 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
701 | kvm_flush_remote_tlbs(vcpu->kvm); | |
f57f2ef5 XG |
702 | |
703 | if (!rmap_can_add(vcpu)) | |
704 | break; | |
705 | ||
706 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
707 | sizeof(pt_element_t))) | |
708 | break; | |
709 | ||
710 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 711 | } |
a7052897 | 712 | |
f78978aa | 713 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
714 | break; |
715 | } | |
ad218f85 | 716 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
717 | } |
718 | ||
1871c602 | 719 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 720 | struct x86_exception *exception) |
6aa8b732 AK |
721 | { |
722 | struct guest_walker walker; | |
e119d117 AK |
723 | gpa_t gpa = UNMAPPED_GVA; |
724 | int r; | |
6aa8b732 | 725 | |
33770780 | 726 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 727 | |
e119d117 | 728 | if (r) { |
1755fbcc | 729 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 730 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
731 | } else if (exception) |
732 | *exception = walker.fault; | |
6aa8b732 AK |
733 | |
734 | return gpa; | |
735 | } | |
736 | ||
6539e738 | 737 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
738 | u32 access, |
739 | struct x86_exception *exception) | |
6539e738 JR |
740 | { |
741 | struct guest_walker walker; | |
742 | gpa_t gpa = UNMAPPED_GVA; | |
743 | int r; | |
744 | ||
33770780 | 745 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
746 | |
747 | if (r) { | |
748 | gpa = gfn_to_gpa(walker.gfn); | |
749 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
750 | } else if (exception) |
751 | *exception = walker.fault; | |
6539e738 JR |
752 | |
753 | return gpa; | |
754 | } | |
755 | ||
e8bc217a MT |
756 | /* |
757 | * Using the cached information from sp->gfns is safe because: | |
758 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
759 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
760 | * |
761 | * Note: | |
762 | * We should flush all tlbs if spte is dropped even though guest is | |
763 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
764 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
765 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
766 | * freed pages. | |
767 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. | |
e8bc217a | 768 | */ |
a4a8e6f7 | 769 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 770 | { |
505aef8f | 771 | int i, nr_present = 0; |
9bdbba13 | 772 | bool host_writable; |
51fb60d8 | 773 | gpa_t first_pte_gpa; |
e8bc217a | 774 | |
2032a93d LJ |
775 | /* direct kvm_mmu_page can not be unsync. */ |
776 | BUG_ON(sp->role.direct); | |
777 | ||
505aef8f | 778 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 779 | |
e8bc217a MT |
780 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
781 | unsigned pte_access; | |
782 | pt_element_t gpte; | |
783 | gpa_t pte_gpa; | |
f55c3f41 | 784 | gfn_t gfn; |
e8bc217a | 785 | |
ce88decf | 786 | if (!sp->spt[i]) |
e8bc217a MT |
787 | continue; |
788 | ||
51fb60d8 | 789 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
790 | |
791 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
792 | sizeof(pt_element_t))) | |
793 | return -EINVAL; | |
794 | ||
407c61c6 | 795 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { |
a4ee1ca4 | 796 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
797 | continue; |
798 | } | |
799 | ||
ce88decf XG |
800 | gfn = gpte_to_gfn(gpte); |
801 | pte_access = sp->role.access; | |
802 | pte_access &= FNAME(gpte_access)(vcpu, gpte, true); | |
803 | ||
804 | if (sync_mmio_spte(&sp->spt[i], gfn, pte_access, &nr_present)) | |
805 | continue; | |
806 | ||
407c61c6 | 807 | if (gfn != sp->gfns[i]) { |
c3707958 | 808 | drop_spte(vcpu->kvm, &sp->spt[i]); |
a4ee1ca4 | 809 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
810 | continue; |
811 | } | |
812 | ||
813 | nr_present++; | |
ce88decf | 814 | |
f8e453b0 XG |
815 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
816 | ||
e8bc217a | 817 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, |
640d9b0d | 818 | PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 819 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 820 | host_writable); |
e8bc217a MT |
821 | } |
822 | ||
823 | return !nr_present; | |
824 | } | |
825 | ||
6aa8b732 AK |
826 | #undef pt_element_t |
827 | #undef guest_walker | |
828 | #undef FNAME | |
829 | #undef PT_BASE_ADDR_MASK | |
830 | #undef PT_INDEX | |
e04da980 JR |
831 | #undef PT_LVL_ADDR_MASK |
832 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 833 | #undef PT_LEVEL_BITS |
cea0f0e7 | 834 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 835 | #undef gpte_to_gfn |
e04da980 | 836 | #undef gpte_to_gfn_lvl |
b3e4e63f | 837 | #undef CMPXCHG |