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KVM: x86: Prepare MSR bitmaps for userspace tracked MSRs
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / svm / svm.c
CommitLineData
44a95dae
SS		 1#define pr_fmt(fmt) "SVM: " fmt
2
edf88417
AK		 3#include <linux/kvm_host.h>
4
85f455f7 5#include "irq.h"
1d737c8a 6#include "mmu.h"
5fdbf976 7#include "kvm_cache_regs.h"
fe4c7b19 8#include "x86.h"
66f7b72e 9#include "cpuid.h"
25462f7f 10#include "pmu.h"
e495606d 11
6aa8b732 12#include <linux/module.h>
ae759544 13#include <linux/mod_devicetable.h>
9d8f549d 14#include <linux/kernel.h>
6aa8b732
AK		 15#include <linux/vmalloc.h>
16#include <linux/highmem.h>
ef0f6496 17#include <linux/amd-iommu.h>
e8edc6e0 18#include <linux/sched.h>
af658dca 19#include <linux/trace_events.h>
5a0e3ad6 20#include <linux/slab.h>
5881f737 21#include <linux/hashtable.h>
c207aee4 22#include <linux/frame.h>
e9df0942 23#include <linux/psp-sev.h>
1654efcb 24#include <linux/file.h>
89c50580
BS		 25#include <linux/pagemap.h>
26#include <linux/swap.h>
33af3a7e 27#include <linux/rwsem.h>
6aa8b732 28
8221c137 29#include <asm/apic.h>
1018faa6 30#include <asm/perf_event.h>
67ec6607 31#include <asm/tlbflush.h>
e495606d 32#include <asm/desc.h>
facb0139 33#include <asm/debugreg.h>
631bc487 34#include <asm/kvm_para.h>
411b44ba 35#include <asm/irq_remapping.h>
1c164cb3 36#include <asm/mce.h>
28a27752 37#include <asm/spec-ctrl.h>
ba5bade4 38#include <asm/cpu_device_id.h>
6aa8b732 39
63d1142f 40#include <asm/virtext.h>
229456fc 41#include "trace.h"
63d1142f 42
883b0a91
JR		 43#include "svm.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
575b255c 50#ifdef MODULE
ae759544 51static const struct x86_cpu_id svm_cpu_id[] = {
320debe5 52 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
ae759544
JT		 53 {}
54};
55MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
575b255c 56#endif
ae759544 57
6aa8b732
AK		 58#define IOPM_ALLOC_ORDER 2
59#define MSRPM_ALLOC_ORDER 1
60
6aa8b732
AK		 61#define SEG_TYPE_LDT 2
62#define SEG_TYPE_BUSY_TSS16 3
63
6bc31bdc
AP		 64#define SVM_FEATURE_LBRV (1 << 1)
65#define SVM_FEATURE_SVML (1 << 2)
ddce97aa
AP		 66#define SVM_FEATURE_TSC_RATE (1 << 4)
67#define SVM_FEATURE_VMCB_CLEAN (1 << 5)
68#define SVM_FEATURE_FLUSH_ASID (1 << 6)
69#define SVM_FEATURE_DECODE_ASSIST (1 << 7)
6bc31bdc 70#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 71
24e09cbf
JR		 72#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
73
fbc0db76 74#define TSC_RATIO_RSVD 0xffffff0000000000ULL
92a1f12d
JR		 75#define TSC_RATIO_MIN 0x0000000000000001ULL
76#define TSC_RATIO_MAX 0x000000ffffffffffULL
fbc0db76 77
67ec6607
JR		 78static bool erratum_383_found __read_mostly;
79
883b0a91 80u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
323c3d80 81
2b036c6b
BO		 82/*
83 * Set osvw_len to higher value when updated Revision Guides
84 * are published and we know what the new status bits are
85 */
86static uint64_t osvw_len = 4, osvw_status;
87
fbc0db76
JR		 88static DEFINE_PER_CPU(u64, current_tsc_ratio);
89#define TSC_RATIO_DEFAULT 0x0100000000ULL
90
09941fbb 91static const struct svm_direct_access_msrs {
ac72a9b7
JR		 92 u32 index; /* Index of the MSR */
93 bool always; /* True if intercept is always on */
94} direct_access_msrs[] = {
8c06585d 95 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 96 { .index = MSR_IA32_SYSENTER_CS, .always = true },
97#ifdef CONFIG_X86_64
98 { .index = MSR_GS_BASE, .always = true },
99 { .index = MSR_FS_BASE, .always = true },
100 { .index = MSR_KERNEL_GS_BASE, .always = true },
101 { .index = MSR_LSTAR, .always = true },
102 { .index = MSR_CSTAR, .always = true },
103 { .index = MSR_SYSCALL_MASK, .always = true },
104#endif
b2ac58f9 105 { .index = MSR_IA32_SPEC_CTRL, .always = false },
15d45071 106 { .index = MSR_IA32_PRED_CMD, .always = false },
ac72a9b7
JR		 107 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
108 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
109 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
110 { .index = MSR_IA32_LASTINTTOIP, .always = false },
111 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 112};
113
709ddebf
JR		 114/* enable NPT for AMD64 and X86 with PAE */
115#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
883b0a91 116bool npt_enabled = true;
709ddebf 117#else
883b0a91 118bool npt_enabled;
709ddebf 119#endif
6c7dac72 120
8566ac8b
BM		 121/*
122 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
123 * pause_filter_count: On processors that support Pause filtering(indicated
124 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
125 * count value. On VMRUN this value is loaded into an internal counter.
126 * Each time a pause instruction is executed, this counter is decremented
127 * until it reaches zero at which time a #VMEXIT is generated if pause
128 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
129 * Intercept Filtering for more details.
130 * This also indicate if ple logic enabled.
131 *
132 * pause_filter_thresh: In addition, some processor families support advanced
133 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
134 * the amount of time a guest is allowed to execute in a pause loop.
135 * In this mode, a 16-bit pause filter threshold field is added in the
136 * VMCB. The threshold value is a cycle count that is used to reset the
137 * pause counter. As with simple pause filtering, VMRUN loads the pause
138 * count value from VMCB into an internal counter. Then, on each pause
139 * instruction the hardware checks the elapsed number of cycles since
140 * the most recent pause instruction against the pause filter threshold.
141 * If the elapsed cycle count is greater than the pause filter threshold,
142 * then the internal pause count is reloaded from the VMCB and execution
143 * continues. If the elapsed cycle count is less than the pause filter
144 * threshold, then the internal pause count is decremented. If the count
145 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
146 * triggered. If advanced pause filtering is supported and pause filter
147 * threshold field is set to zero, the filter will operate in the simpler,
148 * count only mode.
149 */
150
151static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
152module_param(pause_filter_thresh, ushort, 0444);
153
154static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
155module_param(pause_filter_count, ushort, 0444);
156
157/* Default doubles per-vcpu window every exit. */
158static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
159module_param(pause_filter_count_grow, ushort, 0444);
160
161/* Default resets per-vcpu window every exit to pause_filter_count. */
162static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
163module_param(pause_filter_count_shrink, ushort, 0444);
164
165/* Default is to compute the maximum so we can never overflow. */
166static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
167module_param(pause_filter_count_max, ushort, 0444);
168
e2358851
DB		 169/* allow nested paging (virtualized MMU) for all guests */
170static int npt = true;
6c7dac72 171module_param(npt, int, S_IRUGO);
e3da3acd 172
e2358851
DB		 173/* allow nested virtualization in KVM/SVM */
174static int nested = true;
236de055
AG		 175module_param(nested, int, S_IRUGO);
176
d647eb63
PB		 177/* enable/disable Next RIP Save */
178static int nrips = true;
179module_param(nrips, int, 0444);
180
89c8a498
JN		 181/* enable/disable Virtual VMLOAD VMSAVE */
182static int vls = true;
183module_param(vls, int, 0444);
184
640bd6e5
JN		 185/* enable/disable Virtual GIF */
186static int vgif = true;
187module_param(vgif, int, 0444);
5ea11f2b 188
e9df0942
BS		 189/* enable/disable SEV support */
190static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
191module_param(sev, int, 0444);
192
6f2f8453
PB		 193static bool __read_mostly dump_invalid_vmcb = 0;
194module_param(dump_invalid_vmcb, bool, 0644);
195
7607b717
BS		 196static u8 rsm_ins_bytes[] = "\x0f\xaa";
197
a5c3832d 198static void svm_complete_interrupts(struct vcpu_svm *svm);
44a95dae 199
4866d5e3 200static unsigned long iopm_base;
6aa8b732
AK		 201
202struct kvm_ldttss_desc {
203 u16 limit0;
204 u16 base0;
e0231715
JR		 205 unsigned base1:8, type:5, dpl:2, p:1;
206 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 207 u32 base3;
208 u32 zero1;
209} __attribute__((packed));
210
eaf78265 211DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
6aa8b732 212
09941fbb 213static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
6aa8b732 214
9d8f549d 215#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 216#define MSRS_RANGE_SIZE 2048
217#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
218
883b0a91 219u32 svm_msrpm_offset(u32 msr)
455716fa
JR		 220{
221 u32 offset;
222 int i;
223
224 for (i = 0; i < NUM_MSR_MAPS; i++) {
225 if (msr < msrpm_ranges[i] ||
226 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
227 continue;
228
229 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
230 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
231
232 /* Now we have the u8 offset - but need the u32 offset */
233 return offset / 4;
234 }
235
236 /* MSR not in any range */
237 return MSR_INVALID;
238}
239
6aa8b732
AK		 240#define MAX_INST_SIZE 15
241
6aa8b732
AK		 242static inline void clgi(void)
243{
ac5ffda2 244 asm volatile (__ex("clgi"));
6aa8b732
AK		 245}
246
247static inline void stgi(void)
248{
ac5ffda2 249 asm volatile (__ex("stgi"));
6aa8b732
AK		 250}
251
252static inline void invlpga(unsigned long addr, u32 asid)
253{
ac5ffda2 254 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
6aa8b732
AK		 255}
256
d468d94b 257static int get_max_npt_level(void)
4b16184c
JR		 258{
259#ifdef CONFIG_X86_64
2a7266a8 260 return PT64_ROOT_4LEVEL;
4b16184c
JR		 261#else
262 return PT32E_ROOT_LEVEL;
263#endif
264}
265
883b0a91 266void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
6aa8b732 267{
c513f484 268 struct vcpu_svm *svm = to_svm(vcpu);
6dc696d4 269 vcpu->arch.efer = efer;
9167ab79
PB		 270
271 if (!npt_enabled) {
272 /* Shadow paging assumes NX to be available. */
273 efer |= EFER_NX;
274
275 if (!(efer & EFER_LMA))
276 efer &= ~EFER_LME;
277 }
6aa8b732 278
c513f484
PB		 279 if (!(efer & EFER_SVME)) {
280 svm_leave_nested(svm);
281 svm_set_gif(svm, true);
282 }
283
284 svm->vmcb->save.efer = efer | EFER_SVME;
06e7852c 285 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
6aa8b732
AK		 286}
287
6aa8b732
AK		 288static int is_external_interrupt(u32 info)
289{
290 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
291 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
292}
293
37ccdcbe 294static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 295{
296 struct vcpu_svm *svm = to_svm(vcpu);
297 u32 ret = 0;
298
299 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
37ccdcbe
PB		 300 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
301 return ret;
2809f5d2
GC		 302}
303
304static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
305{
306 struct vcpu_svm *svm = to_svm(vcpu);
307
308 if (mask == 0)
309 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
310 else
311 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
312
313}
314
f8ea7c60 315static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
6aa8b732 316{
a2fa3e9f
GH		 317 struct vcpu_svm *svm = to_svm(vcpu);
318
d647eb63 319 if (nrips && svm->vmcb->control.next_rip != 0) {
d2922422 320 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
6bc31bdc 321 svm->next_rip = svm->vmcb->control.next_rip;
f104765b 322 }
6bc31bdc 323
1957aa63
SC		 324 if (!svm->next_rip) {
325 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
326 return 0;
327 } else {
1957aa63
SC		 328 kvm_rip_write(vcpu, svm->next_rip);
329 }
2809f5d2 330 svm_set_interrupt_shadow(vcpu, 0);
f8ea7c60 331
60fc3d02 332 return 1;
6aa8b732
AK		 333}
334
cfcd20e5 335static void svm_queue_exception(struct kvm_vcpu *vcpu)
116a4752
JK		 336{
337 struct vcpu_svm *svm = to_svm(vcpu);
cfcd20e5
WL		 338 unsigned nr = vcpu->arch.exception.nr;
339 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 340 u32 error_code = vcpu->arch.exception.error_code;
116a4752 341
da998b46
JM		 342 kvm_deliver_exception_payload(&svm->vcpu);
343
d647eb63 344 if (nr == BP_VECTOR && !nrips) {
66b7138f
JK		 345 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
346
347 /*
348 * For guest debugging where we have to reinject #BP if some
349 * INT3 is guest-owned:
350 * Emulate nRIP by moving RIP forward. Will fail if injection
351 * raises a fault that is not intercepted. Still better than
352 * failing in all cases.
353 */
f8ea7c60 354 (void)skip_emulated_instruction(&svm->vcpu);
66b7138f
JK		 355 rip = kvm_rip_read(&svm->vcpu);
356 svm->int3_rip = rip + svm->vmcb->save.cs.base;
357 svm->int3_injected = rip - old_rip;
358 }
359
116a4752
JK		 360 svm->vmcb->control.event_inj = nr
361 | SVM_EVTINJ_VALID
362 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
363 | SVM_EVTINJ_TYPE_EXEPT;
364 svm->vmcb->control.event_inj_err = error_code;
365}
366
67ec6607
JR		 367static void svm_init_erratum_383(void)
368{
369 u32 low, high;
370 int err;
371 u64 val;
372
e6ee94d5 373 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
67ec6607
JR		 374 return;
375
376 /* Use _safe variants to not break nested virtualization */
377 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
378 if (err)
379 return;
380
381 val |= (1ULL << 47);
382
383 low = lower_32_bits(val);
384 high = upper_32_bits(val);
385
386 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
387
388 erratum_383_found = true;
389}
390
2b036c6b
BO		 391static void svm_init_osvw(struct kvm_vcpu *vcpu)
392{
393 /*
394 * Guests should see errata 400 and 415 as fixed (assuming that
395 * HLT and IO instructions are intercepted).
396 */
397 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
398 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
399
400 /*
401 * By increasing VCPU's osvw.length to 3 we are telling the guest that
402 * all osvw.status bits inside that length, including bit 0 (which is
403 * reserved for erratum 298), are valid. However, if host processor's
404 * osvw_len is 0 then osvw_status[0] carries no information. We need to
405 * be conservative here and therefore we tell the guest that erratum 298
406 * is present (because we really don't know).
407 */
408 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
409 vcpu->arch.osvw.status |= 1;
410}
411
6aa8b732
AK		 412static int has_svm(void)
413{
63d1142f 414 const char *msg;
6aa8b732 415
63d1142f 416 if (!cpu_has_svm(&msg)) {
ff81ff10 417 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 418 return 0;
419 }
420
6aa8b732
AK		 421 return 1;
422}
423
13a34e06 424static void svm_hardware_disable(void)
6aa8b732 425{
fbc0db76
JR		 426 /* Make sure we clean up behind us */
427 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
428 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
429
2c8dceeb 430 cpu_svm_disable();
1018faa6
JR		 431
432 amd_pmu_disable_virt();
6aa8b732
AK		 433}
434
13a34e06 435static int svm_hardware_enable(void)
6aa8b732
AK		 436{
437
0fe1e009 438 struct svm_cpu_data *sd;
6aa8b732 439 uint64_t efer;
6aa8b732
AK		 440 struct desc_struct *gdt;
441 int me = raw_smp_processor_id();
442
10474ae8
AG		 443 rdmsrl(MSR_EFER, efer);
444 if (efer & EFER_SVME)
445 return -EBUSY;
446
6aa8b732 447 if (!has_svm()) {
1f5b77f5 448 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
10474ae8 449 return -EINVAL;
6aa8b732 450 }
0fe1e009 451 sd = per_cpu(svm_data, me);
0fe1e009 452 if (!sd) {
1f5b77f5 453 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
10474ae8 454 return -EINVAL;
6aa8b732
AK		 455 }
456
0fe1e009
TH		 457 sd->asid_generation = 1;
458 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
459 sd->next_asid = sd->max_asid + 1;
ed3cd233 460 sd->min_asid = max_sev_asid + 1;
6aa8b732 461
45fc8757 462 gdt = get_current_gdt_rw();
0fe1e009 463 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 464
9962d032 465 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 466
d0316554 467 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 468
fbc0db76
JR		 469 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
470 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
89cbc767 471 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
fbc0db76
JR		 472 }
473
2b036c6b
BO		 474
475 /*
476 * Get OSVW bits.
477 *
478 * Note that it is possible to have a system with mixed processor
479 * revisions and therefore different OSVW bits. If bits are not the same
480 * on different processors then choose the worst case (i.e. if erratum
481 * is present on one processor and not on another then assume that the
482 * erratum is present everywhere).
483 */
484 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
485 uint64_t len, status = 0;
486 int err;
487
488 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
489 if (!err)
490 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
491 &err);
492
493 if (err)
494 osvw_status = osvw_len = 0;
495 else {
496 if (len < osvw_len)
497 osvw_len = len;
498 osvw_status |= status;
499 osvw_status &= (1ULL << osvw_len) - 1;
500 }
501 } else
502 osvw_status = osvw_len = 0;
503
67ec6607
JR		 504 svm_init_erratum_383();
505
1018faa6
JR		 506 amd_pmu_enable_virt();
507
10474ae8 508 return 0;
6aa8b732
AK		 509}
510
0da1db75
JR		 511static void svm_cpu_uninit(int cpu)
512{
0fe1e009 513 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 514
0fe1e009 515 if (!sd)
0da1db75
JR		 516 return;
517
518 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
70cd94e6 519 kfree(sd->sev_vmcbs);
0fe1e009
TH		 520 __free_page(sd->save_area);
521 kfree(sd);
0da1db75
JR		 522}
523
6aa8b732
AK		 524static int svm_cpu_init(int cpu)
525{
0fe1e009 526 struct svm_cpu_data *sd;
6aa8b732 527
0fe1e009
TH		 528 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
529 if (!sd)
6aa8b732 530 return -ENOMEM;
0fe1e009 531 sd->cpu = cpu;
70cd94e6 532 sd->save_area = alloc_page(GFP_KERNEL);
0fe1e009 533 if (!sd->save_area)
d80b64ff 534 goto free_cpu_data;
6aa8b732 535
70cd94e6 536 if (svm_sev_enabled()) {
6da2ec56
KC		 537 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
538 sizeof(void *),
539 GFP_KERNEL);
70cd94e6 540 if (!sd->sev_vmcbs)
d80b64ff 541 goto free_save_area;
70cd94e6
BS		 542 }
543
0fe1e009 544 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 545
546 return 0;
547
d80b64ff
ML		 548free_save_area:
549 __free_page(sd->save_area);
550free_cpu_data:
0fe1e009 551 kfree(sd);
d80b64ff 552 return -ENOMEM;
6aa8b732
AK		 553
554}
555
ac72a9b7
JR		 556static bool valid_msr_intercept(u32 index)
557{
558 int i;
559
560 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
561 if (direct_access_msrs[i].index == index)
562 return true;
563
564 return false;
565}
566
476c9bd8 567static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
b2ac58f9
KA		 568{
569 u8 bit_write;
570 unsigned long tmp;
571 u32 offset;
572 u32 *msrpm;
573
574 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
575 to_svm(vcpu)->msrpm;
576
577 offset = svm_msrpm_offset(msr);
578 bit_write = 2 * (msr & 0x0f) + 1;
579 tmp = msrpm[offset];
580
581 BUG_ON(offset == MSR_INVALID);
582
583 return !!test_bit(bit_write, &tmp);
584}
585
476c9bd8 586static void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
bfc733a7 587 int read, int write)
6aa8b732 588{
455716fa
JR		 589 u8 bit_read, bit_write;
590 unsigned long tmp;
591 u32 offset;
6aa8b732 592
ac72a9b7
JR		 593 /*
594 * If this warning triggers extend the direct_access_msrs list at the
595 * beginning of the file
596 */
597 WARN_ON(!valid_msr_intercept(msr));
598
455716fa
JR		 599 offset = svm_msrpm_offset(msr);
600 bit_read = 2 * (msr & 0x0f);
601 bit_write = 2 * (msr & 0x0f) + 1;
602 tmp = msrpm[offset];
603
604 BUG_ON(offset == MSR_INVALID);
605
606 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
607 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
608
609 msrpm[offset] = tmp;
6aa8b732
AK		 610}
611
476c9bd8 612static u32 *svm_vcpu_alloc_msrpm(void)
6aa8b732 613{
f4c847a9 614 struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
476c9bd8 615 u32 *msrpm;
f4c847a9
ML		 616
617 if (!pages)
618 return NULL;
6aa8b732 619
f4c847a9 620 msrpm = page_address(pages);
f65c229c
JR		 621 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
622
476c9bd8
AL		 623 return msrpm;
624}
625
626static void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
627{
628 int i;
629
ac72a9b7
JR		 630 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
631 if (!direct_access_msrs[i].always)
632 continue;
476c9bd8 633 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
ac72a9b7 634 }
f4c847a9
ML		 635}
636
637static void svm_vcpu_free_msrpm(u32 *msrpm)
638{
639 __free_pages(virt_to_page(msrpm), MSRPM_ALLOC_ORDER);
f65c229c
JR		 640}
641
323c3d80
JR		 642static void add_msr_offset(u32 offset)
643{
644 int i;
645
646 for (i = 0; i < MSRPM_OFFSETS; ++i) {
647
648 /* Offset already in list? */
649 if (msrpm_offsets[i] == offset)
bfc733a7 650 return;
323c3d80
JR		 651
652 /* Slot used by another offset? */
653 if (msrpm_offsets[i] != MSR_INVALID)
654 continue;
655
656 /* Add offset to list */
657 msrpm_offsets[i] = offset;
658
659 return;
6aa8b732 660 }
323c3d80
JR		 661
662 /*
663 * If this BUG triggers the msrpm_offsets table has an overflow. Just
664 * increase MSRPM_OFFSETS in this case.
665 */
bfc733a7 666 BUG();
6aa8b732
AK		 667}
668
323c3d80 669static void init_msrpm_offsets(void)
f65c229c 670{
323c3d80 671 int i;
f65c229c 672
323c3d80
JR		 673 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
674
675 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
676 u32 offset;
677
678 offset = svm_msrpm_offset(direct_access_msrs[i].index);
679 BUG_ON(offset == MSR_INVALID);
680
681 add_msr_offset(offset);
682 }
f65c229c
JR		 683}
684
476c9bd8 685static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
24e09cbf 686{
476c9bd8 687 struct vcpu_svm *svm = to_svm(vcpu);
24e09cbf 688
0dc92119 689 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
476c9bd8
AL		 690 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
691 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
692 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
693 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
24e09cbf
JR		 694}
695
476c9bd8 696static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
24e09cbf 697{
476c9bd8 698 struct vcpu_svm *svm = to_svm(vcpu);
24e09cbf 699
0dc92119 700 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
476c9bd8
AL		 701 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
702 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
703 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
704 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
24e09cbf
JR		 705}
706
883b0a91 707void disable_nmi_singlestep(struct vcpu_svm *svm)
4aebd0e9
LP		 708{
709 svm->nmi_singlestep = false;
640bd6e5 710
ab2f4d73
LP		 711 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
712 /* Clear our flags if they were not set by the guest */
713 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
714 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
715 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
716 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
717 }
4aebd0e9
LP		 718}
719
8566ac8b
BM		 720static void grow_ple_window(struct kvm_vcpu *vcpu)
721{
722 struct vcpu_svm *svm = to_svm(vcpu);
723 struct vmcb_control_area *control = &svm->vmcb->control;
724 int old = control->pause_filter_count;
725
726 control->pause_filter_count = __grow_ple_window(old,
727 pause_filter_count,
728 pause_filter_count_grow,
729 pause_filter_count_max);
730
4f75bcc3 731 if (control->pause_filter_count != old) {
06e7852c 732 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
4f75bcc3
PX		 733 trace_kvm_ple_window_update(vcpu->vcpu_id,
734 control->pause_filter_count, old);
735 }
8566ac8b
BM		 736}
737
738static void shrink_ple_window(struct kvm_vcpu *vcpu)
739{
740 struct vcpu_svm *svm = to_svm(vcpu);
741 struct vmcb_control_area *control = &svm->vmcb->control;
742 int old = control->pause_filter_count;
743
744 control->pause_filter_count =
745 __shrink_ple_window(old,
746 pause_filter_count,
747 pause_filter_count_shrink,
748 pause_filter_count);
4f75bcc3 749 if (control->pause_filter_count != old) {
06e7852c 750 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
4f75bcc3
PX		 751 trace_kvm_ple_window_update(vcpu->vcpu_id,
752 control->pause_filter_count, old);
753 }
8566ac8b
BM		 754}
755
52918ed5
TL		 756/*
757 * The default MMIO mask is a single bit (excluding the present bit),
758 * which could conflict with the memory encryption bit. Check for
759 * memory encryption support and override the default MMIO mask if
760 * memory encryption is enabled.
761 */
762static __init void svm_adjust_mmio_mask(void)
763{
764 unsigned int enc_bit, mask_bit;
765 u64 msr, mask;
766
767 /* If there is no memory encryption support, use existing mask */
768 if (cpuid_eax(0x80000000) < 0x8000001f)
769 return;
770
771 /* If memory encryption is not enabled, use existing mask */
772 rdmsrl(MSR_K8_SYSCFG, msr);
773 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
774 return;
775
776 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
777 mask_bit = boot_cpu_data.x86_phys_bits;
778
779 /* Increment the mask bit if it is the same as the encryption bit */
780 if (enc_bit == mask_bit)
781 mask_bit++;
782
783 /*
784 * If the mask bit location is below 52, then some bits above the
785 * physical addressing limit will always be reserved, so use the
786 * rsvd_bits() function to generate the mask. This mask, along with
787 * the present bit, will be used to generate a page fault with
788 * PFER.RSV = 1.
789 *
790 * If the mask bit location is 52 (or above), then clear the mask.
791 */
792 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
793
e7581cac 794 kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
52918ed5
TL		 795}
796
dd58f3c9
LR		 797static void svm_hardware_teardown(void)
798{
799 int cpu;
800
eaf78265
JR		 801 if (svm_sev_enabled())
802 sev_hardware_teardown();
dd58f3c9
LR		 803
804 for_each_possible_cpu(cpu)
805 svm_cpu_uninit(cpu);
806
807 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
808 iopm_base = 0;
809}
810
9b58b985
SC		 811static __init void svm_set_cpu_caps(void)
812{
813 kvm_set_cpu_caps();
814
408e9a31
PB		 815 supported_xss = 0;
816
a50718cc
SC		 817 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
818 if (nested) {
9b58b985
SC		 819 kvm_cpu_cap_set(X86_FEATURE_SVM);
820
4eb87460 821 if (nrips)
a50718cc
SC		 822 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
823
824 if (npt_enabled)
825 kvm_cpu_cap_set(X86_FEATURE_NPT);
826 }
827
93c380e7
SC		 828 /* CPUID 0x80000008 */
829 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
830 boot_cpu_has(X86_FEATURE_AMD_SSBD))
831 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
4407a797
BM		 832
833 /* Enable INVPCID feature */
834 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
9b58b985
SC		 835}
836
6aa8b732
AK		 837static __init int svm_hardware_setup(void)
838{
839 int cpu;
840 struct page *iopm_pages;
f65c229c 841 void *iopm_va;
6aa8b732
AK		 842 int r;
843
6aa8b732
AK		 844 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
845
846 if (!iopm_pages)
847 return -ENOMEM;
c8681339
AL		 848
849 iopm_va = page_address(iopm_pages);
850 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 851 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
852
323c3d80
JR		 853 init_msrpm_offsets();
854
cfc48181
SC		 855 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
856
50a37eb4
JR		 857 if (boot_cpu_has(X86_FEATURE_NX))
858 kvm_enable_efer_bits(EFER_NX);
859
1b2fd70c
AG		 860 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
861 kvm_enable_efer_bits(EFER_FFXSR);
862
92a1f12d 863 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
92a1f12d 864 kvm_has_tsc_control = true;
bc9b961b
HZ		 865 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
866 kvm_tsc_scaling_ratio_frac_bits = 32;
92a1f12d
JR		 867 }
868
8566ac8b
BM		 869 /* Check for pause filtering support */
870 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
871 pause_filter_count = 0;
872 pause_filter_thresh = 0;
873 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
874 pause_filter_thresh = 0;
875 }
876
236de055
AG		 877 if (nested) {
878 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 879 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 880 }
881
e9df0942
BS		 882 if (sev) {
883 if (boot_cpu_has(X86_FEATURE_SEV) &&
884 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
885 r = sev_hardware_setup();
886 if (r)
887 sev = false;
888 } else {
889 sev = false;
890 }
891 }
892
52918ed5
TL		 893 svm_adjust_mmio_mask();
894
3230bb47 895 for_each_possible_cpu(cpu) {
6aa8b732
AK		 896 r = svm_cpu_init(cpu);
897 if (r)
f65c229c 898 goto err;
6aa8b732 899 }
33bd6a0b 900
2a6b20b8 901 if (!boot_cpu_has(X86_FEATURE_NPT))
e3da3acd
JR		 902 npt_enabled = false;
903
213e0e1f 904 if (npt_enabled && !npt)
6c7dac72 905 npt_enabled = false;
6c7dac72 906
83013059 907 kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
213e0e1f 908 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
e3da3acd 909
d647eb63
PB		 910 if (nrips) {
911 if (!boot_cpu_has(X86_FEATURE_NRIPS))
912 nrips = false;
913 }
914
5b8abf1f
SS		 915 if (avic) {
916 if (!npt_enabled ||
917 !boot_cpu_has(X86_FEATURE_AVIC) ||
5881f737 918 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
5b8abf1f 919 avic = false;
5881f737 920 } else {
5b8abf1f 921 pr_info("AVIC enabled\n");
5881f737 922
5881f737
SS		 923 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
924 }
5b8abf1f 925 }
44a95dae 926
89c8a498
JN		 927 if (vls) {
928 if (!npt_enabled ||
5442c269 929 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
89c8a498
JN		 930 !IS_ENABLED(CONFIG_X86_64)) {
931 vls = false;
932 } else {
933 pr_info("Virtual VMLOAD VMSAVE supported\n");
934 }
935 }
936
640bd6e5
JN		 937 if (vgif) {
938 if (!boot_cpu_has(X86_FEATURE_VGIF))
939 vgif = false;
940 else
941 pr_info("Virtual GIF supported\n");
942 }
943
9b58b985 944 svm_set_cpu_caps();
66a6950f 945
3edd6839
MG		 946 /*
947 * It seems that on AMD processors PTE's accessed bit is
948 * being set by the CPU hardware before the NPF vmexit.
949 * This is not expected behaviour and our tests fail because
950 * of it.
951 * A workaround here is to disable support for
952 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
953 * In this case userspace can know if there is support using
954 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
955 * it
956 * If future AMD CPU models change the behaviour described above,
957 * this variable can be changed accordingly
958 */
959 allow_smaller_maxphyaddr = !npt_enabled;
960
6aa8b732
AK		 961 return 0;
962
f65c229c 963err:
dd58f3c9 964 svm_hardware_teardown();
6aa8b732
AK		 965 return r;
966}
967
6aa8b732
AK		 968static void init_seg(struct vmcb_seg *seg)
969{
970 seg->selector = 0;
971 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 972 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 973 seg->limit = 0xffff;
974 seg->base = 0;
975}
976
977static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
978{
979 seg->selector = 0;
980 seg->attrib = SVM_SELECTOR_P_MASK | type;
981 seg->limit = 0xffff;
982 seg->base = 0;
983}
984
326e7425 985static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
f4e1b3c8
ZA		 986{
987 struct vcpu_svm *svm = to_svm(vcpu);
988 u64 g_tsc_offset = 0;
989
2030753d 990 if (is_guest_mode(vcpu)) {
e79f245d 991 /* Write L1's TSC offset. */
f4e1b3c8
ZA		 992 g_tsc_offset = svm->vmcb->control.tsc_offset -
993 svm->nested.hsave->control.tsc_offset;
994 svm->nested.hsave->control.tsc_offset = offset;
45c3af97
PB		 995 }
996
997 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
998 svm->vmcb->control.tsc_offset - g_tsc_offset,
999 offset);
f4e1b3c8
ZA		 1000
1001 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
116a0a23 1002
06e7852c 1003 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
326e7425 1004 return svm->vmcb->control.tsc_offset;
f4e1b3c8
ZA		 1005}
1006
4407a797
BM		 1007static void svm_check_invpcid(struct vcpu_svm *svm)
1008{
1009 /*
1010 * Intercept INVPCID instruction only if shadow page table is
1011 * enabled. Interception is not required with nested page table
1012 * enabled.
1013 */
1014 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1015 if (!npt_enabled)
1016 svm_set_intercept(svm, INTERCEPT_INVPCID);
1017 else
1018 svm_clr_intercept(svm, INTERCEPT_INVPCID);
1019 }
1020}
1021
5690891b 1022static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 1023{
e6101a96
JR		 1024 struct vmcb_control_area *control = &svm->vmcb->control;
1025 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 1026
4ee546b4 1027 svm->vcpu.arch.hflags = 0;
bff78274 1028
830bd71f
BM		 1029 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1030 svm_set_intercept(svm, INTERCEPT_CR3_READ);
1031 svm_set_intercept(svm, INTERCEPT_CR4_READ);
1032 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1033 svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1034 svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
3bbf3565 1035 if (!kvm_vcpu_apicv_active(&svm->vcpu))
830bd71f 1036 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
6aa8b732 1037
5315c716 1038 set_dr_intercepts(svm);
6aa8b732 1039
18c918c5
JR		 1040 set_exception_intercept(svm, PF_VECTOR);
1041 set_exception_intercept(svm, UD_VECTOR);
1042 set_exception_intercept(svm, MC_VECTOR);
54a20552 1043 set_exception_intercept(svm, AC_VECTOR);
cbdb967a 1044 set_exception_intercept(svm, DB_VECTOR);
9718420e
LA		 1045 /*
1046 * Guest access to VMware backdoor ports could legitimately
1047 * trigger #GP because of TSS I/O permission bitmap.
1048 * We intercept those #GP and allow access to them anyway
1049 * as VMware does.
1050 */
1051 if (enable_vmware_backdoor)
1052 set_exception_intercept(svm, GP_VECTOR);
6aa8b732 1053
a284ba56
JR		 1054 svm_set_intercept(svm, INTERCEPT_INTR);
1055 svm_set_intercept(svm, INTERCEPT_NMI);
1056 svm_set_intercept(svm, INTERCEPT_SMI);
1057 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1058 svm_set_intercept(svm, INTERCEPT_RDPMC);
1059 svm_set_intercept(svm, INTERCEPT_CPUID);
1060 svm_set_intercept(svm, INTERCEPT_INVD);
1061 svm_set_intercept(svm, INTERCEPT_INVLPG);
1062 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1063 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1064 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1065 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1066 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1067 svm_set_intercept(svm, INTERCEPT_VMRUN);
1068 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1069 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1070 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1071 svm_set_intercept(svm, INTERCEPT_STGI);
1072 svm_set_intercept(svm, INTERCEPT_CLGI);
1073 svm_set_intercept(svm, INTERCEPT_SKINIT);
1074 svm_set_intercept(svm, INTERCEPT_WBINVD);
1075 svm_set_intercept(svm, INTERCEPT_XSETBV);
1076 svm_set_intercept(svm, INTERCEPT_RDPRU);
1077 svm_set_intercept(svm, INTERCEPT_RSM);
6aa8b732 1078
4d5422ce 1079 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
a284ba56
JR		 1080 svm_set_intercept(svm, INTERCEPT_MONITOR);
1081 svm_set_intercept(svm, INTERCEPT_MWAIT);
668fffa3
MT		 1082 }
1083
caa057a2 1084 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
a284ba56 1085 svm_set_intercept(svm, INTERCEPT_HLT);
caa057a2 1086
d0ec49d4
TL		 1087 control->iopm_base_pa = __sme_set(iopm_base);
1088 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
6aa8b732
AK		 1089 control->int_ctl = V_INTR_MASKING_MASK;
1090
1091 init_seg(&save->es);
1092 init_seg(&save->ss);
1093 init_seg(&save->ds);
1094 init_seg(&save->fs);
1095 init_seg(&save->gs);
1096
1097 save->cs.selector = 0xf000;
04b66839 1098 save->cs.base = 0xffff0000;
6aa8b732
AK		 1099 /* Executable/Readable Code Segment */
1100 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1101 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1102 save->cs.limit = 0xffff;
6aa8b732
AK		 1103
1104 save->gdtr.limit = 0xffff;
1105 save->idtr.limit = 0xffff;
1106
1107 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1108 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1109
5690891b 1110 svm_set_efer(&svm->vcpu, 0);
d77c26fc 1111 save->dr6 = 0xffff0ff0;
f6e78475 1112 kvm_set_rflags(&svm->vcpu, 2);
6aa8b732 1113 save->rip = 0x0000fff0;
5fdbf976 1114 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 1115
e0231715 1116 /*
18fa000a 1117 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
d28bc9dd 1118 * It also updates the guest-visible cr0 value.
6aa8b732 1119 */
79a8059d 1120 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
ebae871a 1121 kvm_mmu_reset_context(&svm->vcpu);
18fa000a 1122
66aee91a 1123 save->cr4 = X86_CR4_PAE;
6aa8b732 1124 /* rdx = ?? */
709ddebf
JR		 1125
1126 if (npt_enabled) {
1127 /* Setup VMCB for Nested Paging */
cea3a19b 1128 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
a284ba56 1129 svm_clr_intercept(svm, INTERCEPT_INVLPG);
18c918c5 1130 clr_exception_intercept(svm, PF_VECTOR);
830bd71f
BM		 1131 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1132 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
74545705 1133 save->g_pat = svm->vcpu.arch.pat;
709ddebf
JR		 1134 save->cr3 = 0;
1135 save->cr4 = 0;
1136 }
f40f6a45 1137 svm->asid_generation = 0;
1371d904 1138
0dd16b5b 1139 svm->nested.vmcb12_gpa = 0;
2af9194d
JR		 1140 svm->vcpu.arch.hflags = 0;
1141
830f01b0 1142 if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
8566ac8b
BM		 1143 control->pause_filter_count = pause_filter_count;
1144 if (pause_filter_thresh)
1145 control->pause_filter_thresh = pause_filter_thresh;
a284ba56 1146 svm_set_intercept(svm, INTERCEPT_PAUSE);
8566ac8b 1147 } else {
a284ba56 1148 svm_clr_intercept(svm, INTERCEPT_PAUSE);
565d0998
ML		 1149 }
1150
4407a797
BM		 1151 svm_check_invpcid(svm);
1152
67034bb9 1153 if (kvm_vcpu_apicv_active(&svm->vcpu))
44a95dae
SS		 1154 avic_init_vmcb(svm);
1155
89c8a498
JN		 1156 /*
1157 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1158 * in VMCB and clear intercepts to avoid #VMEXIT.
1159 */
1160 if (vls) {
a284ba56
JR		 1161 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1162 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
89c8a498
JN		 1163 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1164 }
1165
640bd6e5 1166 if (vgif) {
a284ba56
JR		 1167 svm_clr_intercept(svm, INTERCEPT_STGI);
1168 svm_clr_intercept(svm, INTERCEPT_CLGI);
640bd6e5
JN		 1169 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1170 }
1171
35c6f649 1172 if (sev_guest(svm->vcpu.kvm)) {
1654efcb 1173 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
35c6f649
BS		 1174 clr_exception_intercept(svm, UD_VECTOR);
1175 }
1654efcb 1176
06e7852c 1177 vmcb_mark_all_dirty(svm->vmcb);
8d28fec4 1178
2af9194d 1179 enable_gif(svm);
44a95dae
SS		 1180
1181}
1182
d28bc9dd 1183static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
04d2cc77
AK		 1184{
1185 struct vcpu_svm *svm = to_svm(vcpu);
66f7b72e
JS		 1186 u32 dummy;
1187 u32 eax = 1;
04d2cc77 1188
b2ac58f9 1189 svm->spec_ctrl = 0;
ccbcd267 1190 svm->virt_spec_ctrl = 0;
b2ac58f9 1191
d28bc9dd
NA		 1192 if (!init_event) {
1193 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1194 MSR_IA32_APICBASE_ENABLE;
1195 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1196 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1197 }
5690891b 1198 init_vmcb(svm);
70433389 1199
f91af517 1200 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
de3cd117 1201 kvm_rdx_write(vcpu, eax);
44a95dae
SS		 1202
1203 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1204 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
04d2cc77
AK		 1205}
1206
987b2594 1207static int svm_create_vcpu(struct kvm_vcpu *vcpu)
6aa8b732 1208{
a2fa3e9f 1209 struct vcpu_svm *svm;
1feaba14 1210 struct page *vmcb_page;
b286d5d8 1211 struct page *hsave_page;
fb3f0f51 1212 int err;
6aa8b732 1213
a9dd6f09
SC		 1214 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1215 svm = to_svm(vcpu);
fb3f0f51 1216
b7af4043 1217 err = -ENOMEM;
0681de1b 1218 vmcb_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1feaba14 1219 if (!vmcb_page)
987b2594 1220 goto out;
6aa8b732 1221
0681de1b 1222 hsave_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
b286d5d8 1223 if (!hsave_page)
8d22b90e 1224 goto error_free_vmcb_page;
b7af4043 1225
dfa20099
SS		 1226 err = avic_init_vcpu(svm);
1227 if (err)
8d22b90e 1228 goto error_free_hsave_page;
44a95dae 1229
8221c137
SS		 1230 /* We initialize this flag to true to make sure that the is_running
1231 * bit would be set the first time the vcpu is loaded.
1232 */
6c3e4422
SS		 1233 if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1234 svm->avic_is_running = true;
8221c137 1235
e6aa9abd 1236 svm->nested.hsave = page_address(hsave_page);
b286d5d8 1237
476c9bd8 1238 svm->msrpm = svm_vcpu_alloc_msrpm();
f4c847a9 1239 if (!svm->msrpm)
8d22b90e 1240 goto error_free_hsave_page;
b7af4043 1241
476c9bd8
AL		 1242 svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1243
1244 svm->nested.msrpm = svm_vcpu_alloc_msrpm();
f4c847a9 1245 if (!svm->nested.msrpm)
8d22b90e 1246 goto error_free_msrpm;
3d6368ef 1247
476c9bd8
AL		 1248 /* We only need the L1 pass-through MSR state, so leave vcpu as NULL */
1249 svm_vcpu_init_msrpm(vcpu, svm->nested.msrpm);
1250
1feaba14 1251 svm->vmcb = page_address(vmcb_page);
1feaba14 1252 svm->vmcb_pa = __sme_set(page_to_pfn(vmcb_page) << PAGE_SHIFT);
a2fa3e9f 1253 svm->asid_generation = 0;
5690891b 1254 init_vmcb(svm);
6aa8b732 1255
7f27179a 1256 svm_init_osvw(vcpu);
bab0c318 1257 vcpu->arch.microcode_version = 0x01000065;
2b036c6b 1258
a9dd6f09 1259 return 0;
36241b8c 1260
8d22b90e 1261error_free_msrpm:
f4c847a9 1262 svm_vcpu_free_msrpm(svm->msrpm);
8d22b90e 1263error_free_hsave_page:
f4c847a9 1264 __free_page(hsave_page);
8d22b90e 1265error_free_vmcb_page:
1feaba14 1266 __free_page(vmcb_page);
987b2594 1267out:
a9dd6f09 1268 return err;
6aa8b732
AK		 1269}
1270
fd65d314
JM		 1271static void svm_clear_current_vmcb(struct vmcb *vmcb)
1272{
1273 int i;
1274
1275 for_each_online_cpu(i)
1276 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1277}
1278
6aa8b732
AK		 1279static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1280{
a2fa3e9f
GH		 1281 struct vcpu_svm *svm = to_svm(vcpu);
1282
fd65d314
JM		 1283 /*
1284 * The vmcb page can be recycled, causing a false negative in
1285 * svm_vcpu_load(). So, ensure that no logical CPU has this
1286 * vmcb page recorded as its current vmcb.
1287 */
1288 svm_clear_current_vmcb(svm->vmcb);
1289
d0ec49d4 1290 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
f65c229c 1291 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 1292 __free_page(virt_to_page(svm->nested.hsave));
1293 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
6aa8b732
AK		 1294}
1295
15ad7146 1296static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1297{
a2fa3e9f 1298 struct vcpu_svm *svm = to_svm(vcpu);
15d45071 1299 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
15ad7146 1300 int i;
0cc5064d 1301
0cc5064d 1302 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 1303 svm->asid_generation = 0;
06e7852c 1304 vmcb_mark_all_dirty(svm->vmcb);
0cc5064d 1305 }
94dfbdb3 1306
82ca2d10
AK		 1307#ifdef CONFIG_X86_64
1308 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1309#endif
dacccfdd
AK		 1310 savesegment(fs, svm->host.fs);
1311 savesegment(gs, svm->host.gs);
1312 svm->host.ldt = kvm_read_ldt();
1313
94dfbdb3 1314 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1315 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
fbc0db76 1316
ad721883
HZ		 1317 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1318 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1319 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1320 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1321 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1322 }
fbc0db76 1323 }
46896c73
PB		 1324 /* This assumes that the kernel never uses MSR_TSC_AUX */
1325 if (static_cpu_has(X86_FEATURE_RDTSCP))
1326 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
8221c137 1327
15d45071
AR		 1328 if (sd->current_vmcb != svm->vmcb) {
1329 sd->current_vmcb = svm->vmcb;
1330 indirect_branch_prediction_barrier();
1331 }
8221c137 1332 avic_vcpu_load(vcpu, cpu);
6aa8b732
AK		 1333}
1334
1335static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1336{
a2fa3e9f 1337 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 1338 int i;
1339
8221c137
SS		 1340 avic_vcpu_put(vcpu);
1341
e1beb1d3 1342 ++vcpu->stat.host_state_reload;
dacccfdd
AK		 1343 kvm_load_ldt(svm->host.ldt);
1344#ifdef CONFIG_X86_64
1345 loadsegment(fs, svm->host.fs);
296f781a 1346 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
893a5ab6 1347 load_gs_index(svm->host.gs);
dacccfdd 1348#else
831ca609 1349#ifdef CONFIG_X86_32_LAZY_GS
dacccfdd 1350 loadsegment(gs, svm->host.gs);
831ca609 1351#endif
dacccfdd 1352#endif
94dfbdb3 1353 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1354 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1355}
1356
6aa8b732
AK		 1357static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1358{
9b611747
LP		 1359 struct vcpu_svm *svm = to_svm(vcpu);
1360 unsigned long rflags = svm->vmcb->save.rflags;
1361
1362 if (svm->nmi_singlestep) {
1363 /* Hide our flags if they were not set by the guest */
1364 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1365 rflags &= ~X86_EFLAGS_TF;
1366 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1367 rflags &= ~X86_EFLAGS_RF;
1368 }
1369 return rflags;
6aa8b732
AK		 1370}
1371
1372static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1373{
9b611747
LP		 1374 if (to_svm(vcpu)->nmi_singlestep)
1375 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1376
ae9fedc7 1377 /*
bb3541f1 1378 * Any change of EFLAGS.VM is accompanied by a reload of SS
ae9fedc7
PB		 1379 * (caused by either a task switch or an inter-privilege IRET),
1380 * so we do not need to update the CPL here.
1381 */
a2fa3e9f 1382 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1383}
1384
6de4f3ad
AK		 1385static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1386{
1387 switch (reg) {
1388 case VCPU_EXREG_PDPTR:
1389 BUG_ON(!npt_enabled);
9f8fe504 1390 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6de4f3ad
AK		 1391 break;
1392 default:
34059c25 1393 WARN_ON_ONCE(1);
6de4f3ad
AK		 1394 }
1395}
1396
e14b7786 1397static void svm_set_vintr(struct vcpu_svm *svm)
64b5bd27
PB		 1398{
1399 struct vmcb_control_area *control;
1400
1401 /* The following fields are ignored when AVIC is enabled */
1402 WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
a284ba56 1403 svm_set_intercept(svm, INTERCEPT_VINTR);
64b5bd27
PB		 1404
1405 /*
1406 * This is just a dummy VINTR to actually cause a vmexit to happen.
1407 * Actual injection of virtual interrupts happens through EVENTINJ.
1408 */
1409 control = &svm->vmcb->control;
1410 control->int_vector = 0x0;
1411 control->int_ctl &= ~V_INTR_PRIO_MASK;
1412 control->int_ctl |= V_IRQ_MASK |
1413 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
06e7852c 1414 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
64b5bd27
PB		 1415}
1416
f0b85051
AG		 1417static void svm_clear_vintr(struct vcpu_svm *svm)
1418{
d8e4e58f 1419 const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
a284ba56 1420 svm_clr_intercept(svm, INTERCEPT_VINTR);
64b5bd27 1421
d8e4e58f
PB		 1422 /* Drop int_ctl fields related to VINTR injection. */
1423 svm->vmcb->control.int_ctl &= mask;
1424 if (is_guest_mode(&svm->vcpu)) {
fb7333df
PB		 1425 svm->nested.hsave->control.int_ctl &= mask;
1426
d8e4e58f
PB		 1427 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1428 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1429 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1430 }
1431
06e7852c 1432 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
f0b85051
AG		 1433}
1434
6aa8b732
AK		 1435static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1436{
a2fa3e9f 1437 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1438
1439 switch (seg) {
1440 case VCPU_SREG_CS: return &save->cs;
1441 case VCPU_SREG_DS: return &save->ds;
1442 case VCPU_SREG_ES: return &save->es;
1443 case VCPU_SREG_FS: return &save->fs;
1444 case VCPU_SREG_GS: return &save->gs;
1445 case VCPU_SREG_SS: return &save->ss;
1446 case VCPU_SREG_TR: return &save->tr;
1447 case VCPU_SREG_LDTR: return &save->ldtr;
1448 }
1449 BUG();
8b6d44c7 1450 return NULL;
6aa8b732
AK		 1451}
1452
1453static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1454{
1455 struct vmcb_seg *s = svm_seg(vcpu, seg);
1456
1457 return s->base;
1458}
1459
1460static void svm_get_segment(struct kvm_vcpu *vcpu,
1461 struct kvm_segment *var, int seg)
1462{
1463 struct vmcb_seg *s = svm_seg(vcpu, seg);
1464
1465 var->base = s->base;
1466 var->limit = s->limit;
1467 var->selector = s->selector;
1468 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1469 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1470 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1471 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1472 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1473 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1474 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
80112c89
JM		 1475
1476 /*
1477 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1478 * However, the SVM spec states that the G bit is not observed by the
1479 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1480 * So let's synthesize a legal G bit for all segments, this helps
1481 * running KVM nested. It also helps cross-vendor migration, because
1482 * Intel's vmentry has a check on the 'G' bit.
1483 */
1484 var->g = s->limit > 0xfffff;
25022acc 1485
e0231715
JR		 1486 /*
1487 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1488 * for cross vendor migration purposes by "not present"
1489 */
8eae9570 1490 var->unusable = !var->present;
19bca6ab 1491
1fbdc7a5 1492 switch (seg) {
1fbdc7a5
AP		 1493 case VCPU_SREG_TR:
1494 /*
1495 * Work around a bug where the busy flag in the tr selector
1496 * isn't exposed
1497 */
c0d09828 1498 var->type |= 0x2;
1fbdc7a5
AP		 1499 break;
1500 case VCPU_SREG_DS:
1501 case VCPU_SREG_ES:
1502 case VCPU_SREG_FS:
1503 case VCPU_SREG_GS:
1504 /*
1505 * The accessed bit must always be set in the segment
1506 * descriptor cache, although it can be cleared in the
1507 * descriptor, the cached bit always remains at 1. Since
1508 * Intel has a check on this, set it here to support
1509 * cross-vendor migration.
1510 */
1511 if (!var->unusable)
1512 var->type |= 0x1;
1513 break;
b586eb02 1514 case VCPU_SREG_SS:
e0231715
JR		 1515 /*
1516 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1517 * descriptor is left as 1, although the whole segment has
1518 * been made unusable. Clear it here to pass an Intel VMX
1519 * entry check when cross vendor migrating.
1520 */
1521 if (var->unusable)
1522 var->db = 0;
d9c1b543 1523 /* This is symmetric with svm_set_segment() */
33b458d2 1524 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
b586eb02 1525 break;
1fbdc7a5 1526 }
6aa8b732
AK		 1527}
1528
2e4d2653
IE		 1529static int svm_get_cpl(struct kvm_vcpu *vcpu)
1530{
1531 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1532
1533 return save->cpl;
1534}
1535
89a27f4d 1536static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1537{
a2fa3e9f
GH		 1538 struct vcpu_svm *svm = to_svm(vcpu);
1539
89a27f4d
GN		 1540 dt->size = svm->vmcb->save.idtr.limit;
1541 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1542}
1543
89a27f4d 1544static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1545{
a2fa3e9f
GH		 1546 struct vcpu_svm *svm = to_svm(vcpu);
1547
89a27f4d
GN		 1548 svm->vmcb->save.idtr.limit = dt->size;
1549 svm->vmcb->save.idtr.base = dt->address ;
06e7852c 1550 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1551}
1552
89a27f4d 1553static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1554{
a2fa3e9f
GH		 1555 struct vcpu_svm *svm = to_svm(vcpu);
1556
89a27f4d
GN		 1557 dt->size = svm->vmcb->save.gdtr.limit;
1558 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1559}
1560
89a27f4d 1561static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1562{
a2fa3e9f
GH		 1563 struct vcpu_svm *svm = to_svm(vcpu);
1564
89a27f4d
GN		 1565 svm->vmcb->save.gdtr.limit = dt->size;
1566 svm->vmcb->save.gdtr.base = dt->address ;
06e7852c 1567 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1568}
1569
d225157b
AK		 1570static void update_cr0_intercept(struct vcpu_svm *svm)
1571{
1572 ulong gcr0 = svm->vcpu.arch.cr0;
1573 u64 *hcr0 = &svm->vmcb->save.cr0;
1574
bd7e5b08
PB		 1575 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1576 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
d225157b 1577
06e7852c 1578 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
d225157b 1579
bd7e5b08 1580 if (gcr0 == *hcr0) {
830bd71f
BM		 1581 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1582 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b 1583 } else {
830bd71f
BM		 1584 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1585 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b
AK		 1586 }
1587}
1588
883b0a91 1589void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 1590{
a2fa3e9f
GH		 1591 struct vcpu_svm *svm = to_svm(vcpu);
1592
05b3e0c2 1593#ifdef CONFIG_X86_64
f6801dff 1594 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1595 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1596 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1597 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1598 }
1599
d77c26fc 1600 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1601 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1602 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1603 }
1604 }
1605#endif
ad312c7c 1606 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1607
1608 if (!npt_enabled)
1609 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21 1610
bcf166a9
PB		 1611 /*
1612 * re-enable caching here because the QEMU bios
1613 * does not do it - this results in some delay at
1614 * reboot
1615 */
1616 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1617 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1618 svm->vmcb->save.cr0 = cr0;
06e7852c 1619 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
d225157b 1620 update_cr0_intercept(svm);
6aa8b732
AK		 1621}
1622
883b0a91 1623int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 1624{
1e02ce4c 1625 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
e5eab0ce
JR		 1626 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1627
5e1746d6
NHE		 1628 if (cr4 & X86_CR4_VMXE)
1629 return 1;
1630
e5eab0ce 1631 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
f55ac304 1632 svm_flush_tlb(vcpu);
6394b649 1633
ec077263
JR		 1634 vcpu->arch.cr4 = cr4;
1635 if (!npt_enabled)
1636 cr4 |= X86_CR4_PAE;
6394b649 1637 cr4 |= host_cr4_mce;
ec077263 1638 to_svm(vcpu)->vmcb->save.cr4 = cr4;
06e7852c 1639 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
5e1746d6 1640 return 0;
6aa8b732
AK		 1641}
1642
1643static void svm_set_segment(struct kvm_vcpu *vcpu,
1644 struct kvm_segment *var, int seg)
1645{
a2fa3e9f 1646 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1647 struct vmcb_seg *s = svm_seg(vcpu, seg);
1648
1649 s->base = var->base;
1650 s->limit = var->limit;
1651 s->selector = var->selector;
d9c1b543
RP		 1652 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1653 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1654 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1655 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1656 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1657 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1658 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1659 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
ae9fedc7
PB		 1660
1661 /*
1662 * This is always accurate, except if SYSRET returned to a segment
1663 * with SS.DPL != 3. Intel does not have this quirk, and always
1664 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1665 * would entail passing the CPL to userspace and back.
1666 */
1667 if (seg == VCPU_SREG_SS)
d9c1b543
RP		 1668 /* This is symmetric with svm_get_segment() */
1669 svm->vmcb->save.cpl = (var->dpl & 3);
6aa8b732 1670
06e7852c 1671 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
6aa8b732
AK		 1672}
1673
6986982f 1674static void update_exception_bitmap(struct kvm_vcpu *vcpu)
6aa8b732 1675{
d0bfb940
JK		 1676 struct vcpu_svm *svm = to_svm(vcpu);
1677
18c918c5 1678 clr_exception_intercept(svm, BP_VECTOR);
44c11430 1679
d0bfb940 1680 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
d0bfb940 1681 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
18c918c5 1682 set_exception_intercept(svm, BP_VECTOR);
6986982f 1683 }
44c11430
GN		 1684}
1685
0fe1e009 1686static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1687{
0fe1e009
TH		 1688 if (sd->next_asid > sd->max_asid) {
1689 ++sd->asid_generation;
4faefff3 1690 sd->next_asid = sd->min_asid;
a2fa3e9f 1691 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1692 }
1693
0fe1e009
TH		 1694 svm->asid_generation = sd->asid_generation;
1695 svm->vmcb->control.asid = sd->next_asid++;
d48086d1 1696
06e7852c 1697 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
6aa8b732
AK		 1698}
1699
d67668e9 1700static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
73aaf249 1701{
d67668e9 1702 struct vmcb *vmcb = svm->vmcb;
73aaf249 1703
d67668e9
PB		 1704 if (unlikely(value != vmcb->save.dr6)) {
1705 vmcb->save.dr6 = value;
06e7852c 1706 vmcb_mark_dirty(vmcb, VMCB_DR);
d67668e9 1707 }
73aaf249
JK		 1708}
1709
facb0139
PB		 1710static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1711{
1712 struct vcpu_svm *svm = to_svm(vcpu);
1713
1714 get_debugreg(vcpu->arch.db[0], 0);
1715 get_debugreg(vcpu->arch.db[1], 1);
1716 get_debugreg(vcpu->arch.db[2], 2);
1717 get_debugreg(vcpu->arch.db[3], 3);
d67668e9
PB		 1718 /*
1719 * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1720 * because db_interception might need it. We can do it before vmentry.
1721 */
5679b803 1722 vcpu->arch.dr6 = svm->vmcb->save.dr6;
facb0139 1723 vcpu->arch.dr7 = svm->vmcb->save.dr7;
facb0139
PB		 1724 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1725 set_dr_intercepts(svm);
1726}
1727
020df079 1728static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1729{
42dbaa5a 1730 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1731
020df079 1732 svm->vmcb->save.dr7 = value;
06e7852c 1733 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
6aa8b732
AK		 1734}
1735
851ba692 1736static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1737{
0ede79e1 1738 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1261bfa3 1739 u64 error_code = svm->vmcb->control.exit_info_1;
6aa8b732 1740
1261bfa3 1741 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
00b10fe1
BS		 1742 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1743 svm->vmcb->control.insn_bytes : NULL,
d0006530
PB		 1744 svm->vmcb->control.insn_len);
1745}
1746
1747static int npf_interception(struct vcpu_svm *svm)
1748{
0ede79e1 1749 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
d0006530
PB		 1750 u64 error_code = svm->vmcb->control.exit_info_1;
1751
1752 trace_kvm_page_fault(fault_address, error_code);
1753 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
00b10fe1
BS		 1754 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1755 svm->vmcb->control.insn_bytes : NULL,
d0006530 1756 svm->vmcb->control.insn_len);
6aa8b732
AK		 1757}
1758
851ba692 1759static int db_interception(struct vcpu_svm *svm)
d0bfb940 1760{
851ba692 1761 struct kvm_run *kvm_run = svm->vcpu.run;
99c22179 1762 struct kvm_vcpu *vcpu = &svm->vcpu;
851ba692 1763
d0bfb940 1764 if (!(svm->vcpu.guest_debug &
44c11430 1765 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1766 !svm->nmi_singlestep) {
d67668e9
PB		 1767 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1768 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
d0bfb940
JK		 1769 return 1;
1770 }
44c11430 1771
6be7d306 1772 if (svm->nmi_singlestep) {
4aebd0e9 1773 disable_nmi_singlestep(svm);
99c22179
VK		 1774 /* Make sure we check for pending NMIs upon entry */
1775 kvm_make_request(KVM_REQ_EVENT, vcpu);
44c11430
GN		 1776 }
1777
1778 if (svm->vcpu.guest_debug &
e0231715 1779 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430 1780 kvm_run->exit_reason = KVM_EXIT_DEBUG;
dee919d1
PB		 1781 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1782 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
44c11430
GN		 1783 kvm_run->debug.arch.pc =
1784 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1785 kvm_run->debug.arch.exception = DB_VECTOR;
1786 return 0;
1787 }
1788
1789 return 1;
d0bfb940
JK		 1790}
1791
851ba692 1792static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1793{
851ba692
AK		 1794 struct kvm_run *kvm_run = svm->vcpu.run;
1795
d0bfb940
JK		 1796 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1797 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1798 kvm_run->debug.arch.exception = BP_VECTOR;
1799 return 0;
1800}
1801
851ba692 1802static int ud_interception(struct vcpu_svm *svm)
7aa81cc0 1803{
082d06ed 1804 return handle_ud(&svm->vcpu);
7aa81cc0
AL		 1805}
1806
54a20552
EN		 1807static int ac_interception(struct vcpu_svm *svm)
1808{
1809 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1810 return 1;
1811}
1812
9718420e
LA		 1813static int gp_interception(struct vcpu_svm *svm)
1814{
1815 struct kvm_vcpu *vcpu = &svm->vcpu;
1816 u32 error_code = svm->vmcb->control.exit_info_1;
9718420e
LA		 1817
1818 WARN_ON_ONCE(!enable_vmware_backdoor);
1819
a6c6ed1e
SC		 1820 /*
1821 * VMware backdoor emulation on #GP interception only handles IN{S},
1822 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1823 */
1824 if (error_code) {
1825 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1826 return 1;
1827 }
60fc3d02 1828 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
9718420e
LA		 1829}
1830
67ec6607
JR		 1831static bool is_erratum_383(void)
1832{
1833 int err, i;
1834 u64 value;
1835
1836 if (!erratum_383_found)
1837 return false;
1838
1839 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1840 if (err)
1841 return false;
1842
1843 /* Bit 62 may or may not be set for this mce */
1844 value &= ~(1ULL << 62);
1845
1846 if (value != 0xb600000000010015ULL)
1847 return false;
1848
1849 /* Clear MCi_STATUS registers */
1850 for (i = 0; i < 6; ++i)
1851 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1852
1853 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1854 if (!err) {
1855 u32 low, high;
1856
1857 value &= ~(1ULL << 2);
1858 low = lower_32_bits(value);
1859 high = upper_32_bits(value);
1860
1861 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1862 }
1863
1864 /* Flush tlb to evict multi-match entries */
1865 __flush_tlb_all();
1866
1867 return true;
1868}
1869
1c164cb3
UB		 1870/*
1871 * Trigger machine check on the host. We assume all the MSRs are already set up
1872 * by the CPU and that we still run on the same CPU as the MCE occurred on.
1873 * We pass a fake environment to the machine check handler because we want
1874 * the guest to be always treated like user space, no matter what context
1875 * it used internally.
1876 */
1877static void kvm_machine_check(void)
1878{
1879#if defined(CONFIG_X86_MCE)
1880 struct pt_regs regs = {
1881 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
1882 .flags = X86_EFLAGS_IF,
1883 };
1884
8cd501c1 1885 do_machine_check(&regs);
1c164cb3
UB		 1886#endif
1887}
1888
fe5913e4 1889static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1890{
67ec6607
JR		 1891 if (is_erratum_383()) {
1892 /*
1893 * Erratum 383 triggered. Guest state is corrupt so kill the
1894 * guest.
1895 */
1896 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1897
a8eeb04a 1898 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1899
1900 return;
1901 }
1902
53371b50
JR		 1903 /*
1904 * On an #MC intercept the MCE handler is not called automatically in
1905 * the host. So do it by hand here.
1906 */
1c164cb3 1907 kvm_machine_check();
fe5913e4
JR		 1908}
1909
1910static int mc_interception(struct vcpu_svm *svm)
1911{
53371b50
JR		 1912 return 1;
1913}
1914
851ba692 1915static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1916{
851ba692
AK		 1917 struct kvm_run *kvm_run = svm->vcpu.run;
1918
46fe4ddd
JR		 1919 /*
1920 * VMCB is undefined after a SHUTDOWN intercept
1921 * so reinitialize it.
1922 */
a2fa3e9f 1923 clear_page(svm->vmcb);
5690891b 1924 init_vmcb(svm);
46fe4ddd
JR		 1925
1926 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1927 return 0;
1928}
1929
851ba692 1930static int io_interception(struct vcpu_svm *svm)
6aa8b732 1931{
cf8f70bf 1932 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1933 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
dca7f128 1934 int size, in, string;
039576c0 1935 unsigned port;
6aa8b732 1936
e756fc62 1937 ++svm->vcpu.stat.io_exits;
e70669ab 1938 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1939 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
8370c3d0 1940 if (string)
60fc3d02 1941 return kvm_emulate_instruction(vcpu, 0);
cf8f70bf 1942
039576c0
AK		 1943 port = io_info >> 16;
1944 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1945 svm->next_rip = svm->vmcb->control.exit_info_2;
cf8f70bf 1946
dca7f128 1947 return kvm_fast_pio(&svm->vcpu, size, port, in);
6aa8b732
AK		 1948}
1949
851ba692 1950static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1951{
1952 return 1;
1953}
1954
851ba692 1955static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1956{
1957 ++svm->vcpu.stat.irq_exits;
1958 return 1;
1959}
1960
851ba692 1961static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1962{
1963 return 1;
1964}
1965
851ba692 1966static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1967{
e756fc62 1968 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1969}
1970
851ba692 1971static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1972{
0d9c055e 1973 return kvm_emulate_hypercall(&svm->vcpu);
02e235bc
AK		 1974}
1975
851ba692 1976static int vmload_interception(struct vcpu_svm *svm)
5542675b 1977{
9966bf68 1978 struct vmcb *nested_vmcb;
8c5fbf1a 1979 struct kvm_host_map map;
b742c1e6 1980 int ret;
9966bf68 1981
5542675b
AG		 1982 if (nested_svm_check_permissions(svm))
1983 return 1;
1984
8c5fbf1a
KA		 1985 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1986 if (ret) {
1987 if (ret == -EINVAL)
1988 kvm_inject_gp(&svm->vcpu, 0);
9966bf68 1989 return 1;
8c5fbf1a
KA		 1990 }
1991
1992 nested_vmcb = map.hva;
9966bf68 1993
b742c1e6 1994 ret = kvm_skip_emulated_instruction(&svm->vcpu);
e3e9ed3d 1995
9966bf68 1996 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
8c5fbf1a 1997 kvm_vcpu_unmap(&svm->vcpu, &map, true);
5542675b 1998
b742c1e6 1999 return ret;
5542675b
AG		 2000}
2001
851ba692 2002static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2003{
9966bf68 2004 struct vmcb *nested_vmcb;
8c5fbf1a 2005 struct kvm_host_map map;
b742c1e6 2006 int ret;
9966bf68 2007
5542675b
AG		 2008 if (nested_svm_check_permissions(svm))
2009 return 1;
2010
8c5fbf1a
KA		 2011 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2012 if (ret) {
2013 if (ret == -EINVAL)
2014 kvm_inject_gp(&svm->vcpu, 0);
9966bf68 2015 return 1;
8c5fbf1a
KA		 2016 }
2017
2018 nested_vmcb = map.hva;
9966bf68 2019
b742c1e6 2020 ret = kvm_skip_emulated_instruction(&svm->vcpu);
e3e9ed3d 2021
9966bf68 2022 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
8c5fbf1a 2023 kvm_vcpu_unmap(&svm->vcpu, &map, true);
5542675b 2024
b742c1e6 2025 return ret;
5542675b
AG		 2026}
2027
851ba692 2028static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2029{
3d6368ef
AG		 2030 if (nested_svm_check_permissions(svm))
2031 return 1;
2032
e7134c1b 2033 return nested_svm_vmrun(svm);
3d6368ef
AG		 2034}
2035
ffdf7f9e
PB		 2036void svm_set_gif(struct vcpu_svm *svm, bool value)
2037{
2038 if (value) {
2039 /*
2040 * If VGIF is enabled, the STGI intercept is only added to
2041 * detect the opening of the SMI/NMI window; remove it now.
2042 * Likewise, clear the VINTR intercept, we will set it
2043 * again while processing KVM_REQ_EVENT if needed.
2044 */
2045 if (vgif_enabled(svm))
a284ba56
JR		 2046 svm_clr_intercept(svm, INTERCEPT_STGI);
2047 if (svm_is_intercept(svm, INTERCEPT_VINTR))
ffdf7f9e
PB		 2048 svm_clear_vintr(svm);
2049
2050 enable_gif(svm);
2051 if (svm->vcpu.arch.smi_pending ||
2052 svm->vcpu.arch.nmi_pending ||
2053 kvm_cpu_has_injectable_intr(&svm->vcpu))
2054 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2055 } else {
2056 disable_gif(svm);
2057
2058 /*
2059 * After a CLGI no interrupts should come. But if vGIF is
2060 * in use, we still rely on the VINTR intercept (rather than
2061 * STGI) to detect an open interrupt window.
2062 */
2063 if (!vgif_enabled(svm))
2064 svm_clear_vintr(svm);
2065 }
2066}
2067
851ba692 2068static int stgi_interception(struct vcpu_svm *svm)
1371d904 2069{
b742c1e6
LP		 2070 int ret;
2071
1371d904
AG		 2072 if (nested_svm_check_permissions(svm))
2073 return 1;
2074
b742c1e6 2075 ret = kvm_skip_emulated_instruction(&svm->vcpu);
ffdf7f9e 2076 svm_set_gif(svm, true);
b742c1e6 2077 return ret;
1371d904
AG		 2078}
2079
851ba692 2080static int clgi_interception(struct vcpu_svm *svm)
1371d904 2081{
b742c1e6
LP		 2082 int ret;
2083
1371d904
AG		 2084 if (nested_svm_check_permissions(svm))
2085 return 1;
2086
b742c1e6 2087 ret = kvm_skip_emulated_instruction(&svm->vcpu);
ffdf7f9e 2088 svm_set_gif(svm, false);
b742c1e6 2089 return ret;
1371d904
AG		 2090}
2091
851ba692 2092static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2093{
2094 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2095
de3cd117
SC		 2096 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2097 kvm_rax_read(&svm->vcpu));
ec1ff790 2098
ff092385 2099 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
de3cd117 2100 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
ff092385 2101
b742c1e6 2102 return kvm_skip_emulated_instruction(&svm->vcpu);
ff092385
AG		 2103}
2104
532a46b9
JR		 2105static int skinit_interception(struct vcpu_svm *svm)
2106{
de3cd117 2107 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
532a46b9
JR		 2108
2109 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2110 return 1;
2111}
2112
dab429a7
DK		 2113static int wbinvd_interception(struct vcpu_svm *svm)
2114{
6affcbed 2115 return kvm_emulate_wbinvd(&svm->vcpu);
dab429a7
DK		 2116}
2117
81dd35d4
JR		 2118static int xsetbv_interception(struct vcpu_svm *svm)
2119{
2120 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
de3cd117 2121 u32 index = kvm_rcx_read(&svm->vcpu);
81dd35d4
JR		 2122
2123 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
b742c1e6 2124 return kvm_skip_emulated_instruction(&svm->vcpu);
81dd35d4
JR		 2125 }
2126
2127 return 1;
2128}
2129
0cb8410b
JM		 2130static int rdpru_interception(struct vcpu_svm *svm)
2131{
2132 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2133 return 1;
2134}
2135
851ba692 2136static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2137{
37817f29 2138 u16 tss_selector;
64a7ec06
GN		 2139 int reason;
2140 int int_type = svm->vmcb->control.exit_int_info &
2141 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2142 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2143 uint32_t type =
2144 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2145 uint32_t idt_v =
2146 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2147 bool has_error_code = false;
2148 u32 error_code = 0;
37817f29
IE		 2149
2150 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2151
37817f29
IE		 2152 if (svm->vmcb->control.exit_info_2 &
2153 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2154 reason = TASK_SWITCH_IRET;
2155 else if (svm->vmcb->control.exit_info_2 &
2156 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2157 reason = TASK_SWITCH_JMP;
fe8e7f83 2158 else if (idt_v)
64a7ec06
GN		 2159 reason = TASK_SWITCH_GATE;
2160 else
2161 reason = TASK_SWITCH_CALL;
2162
fe8e7f83
GN		 2163 if (reason == TASK_SWITCH_GATE) {
2164 switch (type) {
2165 case SVM_EXITINTINFO_TYPE_NMI:
2166 svm->vcpu.arch.nmi_injected = false;
2167 break;
2168 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2169 if (svm->vmcb->control.exit_info_2 &
2170 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2171 has_error_code = true;
2172 error_code =
2173 (u32)svm->vmcb->control.exit_info_2;
2174 }
fe8e7f83
GN		 2175 kvm_clear_exception_queue(&svm->vcpu);
2176 break;
2177 case SVM_EXITINTINFO_TYPE_INTR:
2178 kvm_clear_interrupt_queue(&svm->vcpu);
2179 break;
2180 default:
2181 break;
2182 }
2183 }
64a7ec06 2184
8317c298
GN		 2185 if (reason != TASK_SWITCH_GATE ||
2186 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2187 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f8ea7c60 2188 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
60fc3d02 2189 if (!skip_emulated_instruction(&svm->vcpu))
738fece4 2190 return 0;
f8ea7c60 2191 }
64a7ec06 2192
7f3d35fd
KW		 2193 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2194 int_vec = -1;
2195
1051778f 2196 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
60fc3d02 2197 has_error_code, error_code);
6aa8b732
AK		 2198}
2199
851ba692 2200static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2201{
6a908b62 2202 return kvm_emulate_cpuid(&svm->vcpu);
6aa8b732
AK		 2203}
2204
851ba692 2205static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2206{
2207 ++svm->vcpu.stat.nmi_window_exits;
a284ba56 2208 svm_clr_intercept(svm, INTERCEPT_IRET);
44c11430 2209 svm->vcpu.arch.hflags |= HF_IRET_MASK;
bd3d1ec3 2210 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
f303b4ce 2211 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
95ba8273
GN		 2212 return 1;
2213}
2214
851ba692 2215static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2216{
df4f3108 2217 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
60fc3d02 2218 return kvm_emulate_instruction(&svm->vcpu, 0);
df4f3108
AP		 2219
2220 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
b742c1e6 2221 return kvm_skip_emulated_instruction(&svm->vcpu);
a7052897
MT		 2222}
2223
851ba692 2224static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2225{
60fc3d02 2226 return kvm_emulate_instruction(&svm->vcpu, 0);
6aa8b732
AK		 2227}
2228
7607b717
BS		 2229static int rsm_interception(struct vcpu_svm *svm)
2230{
60fc3d02 2231 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
7607b717
BS		 2232}
2233
332b56e4
AK		 2234static int rdpmc_interception(struct vcpu_svm *svm)
2235{
2236 int err;
2237
d647eb63 2238 if (!nrips)
332b56e4
AK		 2239 return emulate_on_interception(svm);
2240
2241 err = kvm_rdpmc(&svm->vcpu);
6affcbed 2242 return kvm_complete_insn_gp(&svm->vcpu, err);
332b56e4
AK		 2243}
2244
52eb5a6d
XL		 2245static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2246 unsigned long val)
628afd2a
JR		 2247{
2248 unsigned long cr0 = svm->vcpu.arch.cr0;
2249 bool ret = false;
628afd2a
JR		 2250
2251 if (!is_guest_mode(&svm->vcpu) ||
c62e2e94 2252 (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
628afd2a
JR		 2253 return false;
2254
2255 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2256 val &= ~SVM_CR0_SELECTIVE_MASK;
2257
2258 if (cr0 ^ val) {
2259 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2260 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2261 }
2262
2263 return ret;
2264}
2265
7ff76d58
AP		 2266#define CR_VALID (1ULL << 63)
2267
2268static int cr_interception(struct vcpu_svm *svm)
2269{
2270 int reg, cr;
2271 unsigned long val;
2272 int err;
2273
2274 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2275 return emulate_on_interception(svm);
2276
2277 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2278 return emulate_on_interception(svm);
2279
2280 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
5e57518d
DK		 2281 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2282 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2283 else
2284 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
7ff76d58
AP		 2285
2286 err = 0;
2287 if (cr >= 16) { /* mov to cr */
2288 cr -= 16;
2289 val = kvm_register_read(&svm->vcpu, reg);
95b28ac9 2290 trace_kvm_cr_write(cr, val);
7ff76d58
AP		 2291 switch (cr) {
2292 case 0:
628afd2a
JR		 2293 if (!check_selective_cr0_intercepted(svm, val))
2294 err = kvm_set_cr0(&svm->vcpu, val);
977b2d03
JR		 2295 else
2296 return 1;
2297
7ff76d58
AP		 2298 break;
2299 case 3:
2300 err = kvm_set_cr3(&svm->vcpu, val);
2301 break;
2302 case 4:
2303 err = kvm_set_cr4(&svm->vcpu, val);
2304 break;
2305 case 8:
2306 err = kvm_set_cr8(&svm->vcpu, val);
2307 break;
2308 default:
2309 WARN(1, "unhandled write to CR%d", cr);
2310 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2311 return 1;
2312 }
2313 } else { /* mov from cr */
2314 switch (cr) {
2315 case 0:
2316 val = kvm_read_cr0(&svm->vcpu);
2317 break;
2318 case 2:
2319 val = svm->vcpu.arch.cr2;
2320 break;
2321 case 3:
9f8fe504 2322 val = kvm_read_cr3(&svm->vcpu);
7ff76d58
AP		 2323 break;
2324 case 4:
2325 val = kvm_read_cr4(&svm->vcpu);
2326 break;
2327 case 8:
2328 val = kvm_get_cr8(&svm->vcpu);
2329 break;
2330 default:
2331 WARN(1, "unhandled read from CR%d", cr);
2332 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2333 return 1;
2334 }
2335 kvm_register_write(&svm->vcpu, reg, val);
95b28ac9 2336 trace_kvm_cr_read(cr, val);
7ff76d58 2337 }
6affcbed 2338 return kvm_complete_insn_gp(&svm->vcpu, err);
7ff76d58
AP		 2339}
2340
cae3797a
AP		 2341static int dr_interception(struct vcpu_svm *svm)
2342{
2343 int reg, dr;
2344 unsigned long val;
cae3797a 2345
facb0139
PB		 2346 if (svm->vcpu.guest_debug == 0) {
2347 /*
2348 * No more DR vmexits; force a reload of the debug registers
2349 * and reenter on this instruction. The next vmexit will
2350 * retrieve the full state of the debug registers.
2351 */
2352 clr_dr_intercepts(svm);
2353 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2354 return 1;
2355 }
2356
cae3797a
AP		 2357 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2358 return emulate_on_interception(svm);
2359
2360 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2361 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2362
2363 if (dr >= 16) { /* mov to DRn */
16f8a6f9
NA		 2364 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2365 return 1;
cae3797a
AP		 2366 val = kvm_register_read(&svm->vcpu, reg);
2367 kvm_set_dr(&svm->vcpu, dr - 16, val);
2368 } else {
16f8a6f9
NA		 2369 if (!kvm_require_dr(&svm->vcpu, dr))
2370 return 1;
2371 kvm_get_dr(&svm->vcpu, dr, &val);
2372 kvm_register_write(&svm->vcpu, reg, val);
cae3797a
AP		 2373 }
2374
b742c1e6 2375 return kvm_skip_emulated_instruction(&svm->vcpu);
cae3797a
AP		 2376}
2377
851ba692 2378static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2379{
851ba692 2380 struct kvm_run *kvm_run = svm->vcpu.run;
eea1cff9 2381 int r;
851ba692 2382
0a5fff19
GN		 2383 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2384 /* instruction emulation calls kvm_set_cr8() */
7ff76d58 2385 r = cr_interception(svm);
35754c98 2386 if (lapic_in_kernel(&svm->vcpu))
7ff76d58 2387 return r;
0a5fff19 2388 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
7ff76d58 2389 return r;
1d075434
JR		 2390 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2391 return 0;
2392}
2393
801e459a
TL		 2394static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2395{
d1d93fa9
TL		 2396 msr->data = 0;
2397
2398 switch (msr->index) {
2399 case MSR_F10H_DECFG:
2400 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2401 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2402 break;
d574c539
VK		 2403 case MSR_IA32_PERF_CAPABILITIES:
2404 return 0;
d1d93fa9 2405 default:
12bc2132 2406 return KVM_MSR_RET_INVALID;
d1d93fa9
TL		 2407 }
2408
2409 return 0;
801e459a
TL		 2410}
2411
609e36d3 2412static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2413{
a2fa3e9f
GH		 2414 struct vcpu_svm *svm = to_svm(vcpu);
2415
609e36d3 2416 switch (msr_info->index) {
8c06585d 2417 case MSR_STAR:
609e36d3 2418 msr_info->data = svm->vmcb->save.star;
6aa8b732 2419 break;
0e859cac 2420#ifdef CONFIG_X86_64
6aa8b732 2421 case MSR_LSTAR:
609e36d3 2422 msr_info->data = svm->vmcb->save.lstar;
6aa8b732
AK		 2423 break;
2424 case MSR_CSTAR:
609e36d3 2425 msr_info->data = svm->vmcb->save.cstar;
6aa8b732
AK		 2426 break;
2427 case MSR_KERNEL_GS_BASE:
609e36d3 2428 msr_info->data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2429 break;
2430 case MSR_SYSCALL_MASK:
609e36d3 2431 msr_info->data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2432 break;
2433#endif
2434 case MSR_IA32_SYSENTER_CS:
609e36d3 2435 msr_info->data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2436 break;
2437 case MSR_IA32_SYSENTER_EIP:
609e36d3 2438 msr_info->data = svm->sysenter_eip;
6aa8b732
AK		 2439 break;
2440 case MSR_IA32_SYSENTER_ESP:
609e36d3 2441 msr_info->data = svm->sysenter_esp;
6aa8b732 2442 break;
46896c73
PB		 2443 case MSR_TSC_AUX:
2444 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2445 return 1;
2446 msr_info->data = svm->tsc_aux;
2447 break;
e0231715
JR		 2448 /*
2449 * Nobody will change the following 5 values in the VMCB so we can
2450 * safely return them on rdmsr. They will always be 0 until LBRV is
2451 * implemented.
2452 */
a2938c80 2453 case MSR_IA32_DEBUGCTLMSR:
609e36d3 2454 msr_info->data = svm->vmcb->save.dbgctl;
a2938c80
JR		 2455 break;
2456 case MSR_IA32_LASTBRANCHFROMIP:
609e36d3 2457 msr_info->data = svm->vmcb->save.br_from;
a2938c80
JR		 2458 break;
2459 case MSR_IA32_LASTBRANCHTOIP:
609e36d3 2460 msr_info->data = svm->vmcb->save.br_to;
a2938c80
JR		 2461 break;
2462 case MSR_IA32_LASTINTFROMIP:
609e36d3 2463 msr_info->data = svm->vmcb->save.last_excp_from;
a2938c80
JR		 2464 break;
2465 case MSR_IA32_LASTINTTOIP:
609e36d3 2466 msr_info->data = svm->vmcb->save.last_excp_to;
a2938c80 2467 break;
b286d5d8 2468 case MSR_VM_HSAVE_PA:
609e36d3 2469 msr_info->data = svm->nested.hsave_msr;
b286d5d8 2470 break;
eb6f302e 2471 case MSR_VM_CR:
609e36d3 2472 msr_info->data = svm->nested.vm_cr_msr;
eb6f302e 2473 break;
b2ac58f9
KA		 2474 case MSR_IA32_SPEC_CTRL:
2475 if (!msr_info->host_initiated &&
df7e8818
PB		 2476 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2477 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
6ac2f49e
KRW		 2478 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2479 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
b2ac58f9
KA		 2480 return 1;
2481
2482 msr_info->data = svm->spec_ctrl;
2483 break;
bc226f07
TL		 2484 case MSR_AMD64_VIRT_SPEC_CTRL:
2485 if (!msr_info->host_initiated &&
2486 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2487 return 1;
2488
2489 msr_info->data = svm->virt_spec_ctrl;
2490 break;
ae8b7875
BP		 2491 case MSR_F15H_IC_CFG: {
2492
2493 int family, model;
2494
2495 family = guest_cpuid_family(vcpu);
2496 model = guest_cpuid_model(vcpu);
2497
2498 if (family < 0 || model < 0)
2499 return kvm_get_msr_common(vcpu, msr_info);
2500
2501 msr_info->data = 0;
2502
2503 if (family == 0x15 &&
2504 (model >= 0x2 && model < 0x20))
2505 msr_info->data = 0x1E;
2506 }
2507 break;
d1d93fa9
TL		 2508 case MSR_F10H_DECFG:
2509 msr_info->data = svm->msr_decfg;
2510 break;
6aa8b732 2511 default:
609e36d3 2512 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 2513 }
2514 return 0;
2515}
2516
851ba692 2517static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2518{
1edce0a9 2519 return kvm_emulate_rdmsr(&svm->vcpu);
6aa8b732
AK		 2520}
2521
4a810181
JR		 2522static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2523{
2524 struct vcpu_svm *svm = to_svm(vcpu);
2525 int svm_dis, chg_mask;
2526
2527 if (data & ~SVM_VM_CR_VALID_MASK)
2528 return 1;
2529
2530 chg_mask = SVM_VM_CR_VALID_MASK;
2531
2532 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2533 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2534
2535 svm->nested.vm_cr_msr &= ~chg_mask;
2536 svm->nested.vm_cr_msr |= (data & chg_mask);
2537
2538 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2539
2540 /* check for svm_disable while efer.svme is set */
2541 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2542 return 1;
2543
2544 return 0;
2545}
2546
8fe8ab46 2547static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
6aa8b732 2548{
a2fa3e9f
GH		 2549 struct vcpu_svm *svm = to_svm(vcpu);
2550
8fe8ab46
WA		 2551 u32 ecx = msr->index;
2552 u64 data = msr->data;
6aa8b732 2553 switch (ecx) {
15038e14
PB		 2554 case MSR_IA32_CR_PAT:
2555 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2556 return 1;
2557 vcpu->arch.pat = data;
2558 svm->vmcb->save.g_pat = data;
06e7852c 2559 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
15038e14 2560 break;
b2ac58f9
KA		 2561 case MSR_IA32_SPEC_CTRL:
2562 if (!msr->host_initiated &&
df7e8818
PB		 2563 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2564 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
6ac2f49e
KRW		 2565 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2566 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
b2ac58f9
KA		 2567 return 1;
2568
841c2be0 2569 if (kvm_spec_ctrl_test_value(data))
b2ac58f9
KA		 2570 return 1;
2571
2572 svm->spec_ctrl = data;
b2ac58f9
KA		 2573 if (!data)
2574 break;
2575
2576 /*
2577 * For non-nested:
2578 * When it's written (to non-zero) for the first time, pass
2579 * it through.
2580 *
2581 * For nested:
2582 * The handling of the MSR bitmap for L2 guests is done in
2583 * nested_svm_vmrun_msrpm.
2584 * We update the L1 MSR bit as well since it will end up
2585 * touching the MSR anyway now.
2586 */
476c9bd8 2587 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
b2ac58f9 2588 break;
15d45071
AR		 2589 case MSR_IA32_PRED_CMD:
2590 if (!msr->host_initiated &&
e7c587da 2591 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
15d45071
AR		 2592 return 1;
2593
2594 if (data & ~PRED_CMD_IBPB)
2595 return 1;
6441fa61
PB		 2596 if (!boot_cpu_has(X86_FEATURE_AMD_IBPB))
2597 return 1;
15d45071
AR		 2598 if (!data)
2599 break;
2600
2601 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
476c9bd8 2602 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
15d45071 2603 break;
bc226f07
TL		 2604 case MSR_AMD64_VIRT_SPEC_CTRL:
2605 if (!msr->host_initiated &&
2606 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2607 return 1;
2608
2609 if (data & ~SPEC_CTRL_SSBD)
2610 return 1;
2611
2612 svm->virt_spec_ctrl = data;
2613 break;
8c06585d 2614 case MSR_STAR:
a2fa3e9f 2615 svm->vmcb->save.star = data;
6aa8b732 2616 break;
49b14f24 2617#ifdef CONFIG_X86_64
6aa8b732 2618 case MSR_LSTAR:
a2fa3e9f 2619 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2620 break;
2621 case MSR_CSTAR:
a2fa3e9f 2622 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2623 break;
2624 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2625 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2626 break;
2627 case MSR_SYSCALL_MASK:
a2fa3e9f 2628 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2629 break;
2630#endif
2631 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2632 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2633 break;
2634 case MSR_IA32_SYSENTER_EIP:
017cb99e 2635 svm->sysenter_eip = data;
a2fa3e9f 2636 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2637 break;
2638 case MSR_IA32_SYSENTER_ESP:
017cb99e 2639 svm->sysenter_esp = data;
a2fa3e9f 2640 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2641 break;
46896c73
PB		 2642 case MSR_TSC_AUX:
2643 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2644 return 1;
2645
2646 /*
2647 * This is rare, so we update the MSR here instead of using
2648 * direct_access_msrs. Doing that would require a rdmsr in
2649 * svm_vcpu_put.
2650 */
2651 svm->tsc_aux = data;
2652 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2653 break;
a2938c80 2654 case MSR_IA32_DEBUGCTLMSR:
2a6b20b8 2655 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
a737f256
CD		 2656 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2657 __func__, data);
24e09cbf
JR		 2658 break;
2659 }
2660 if (data & DEBUGCTL_RESERVED_BITS)
2661 return 1;
2662
2663 svm->vmcb->save.dbgctl = data;
06e7852c 2664 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
24e09cbf 2665 if (data & (1ULL<<0))
476c9bd8 2666 svm_enable_lbrv(vcpu);
24e09cbf 2667 else
476c9bd8 2668 svm_disable_lbrv(vcpu);
a2938c80 2669 break;
b286d5d8 2670 case MSR_VM_HSAVE_PA:
e6aa9abd 2671 svm->nested.hsave_msr = data;
62b9abaa 2672 break;
3c5d0a44 2673 case MSR_VM_CR:
4a810181 2674 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2675 case MSR_VM_IGNNE:
a737f256 2676 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3c5d0a44 2677 break;
d1d93fa9
TL		 2678 case MSR_F10H_DECFG: {
2679 struct kvm_msr_entry msr_entry;
2680
2681 msr_entry.index = msr->index;
2682 if (svm_get_msr_feature(&msr_entry))
2683 return 1;
2684
2685 /* Check the supported bits */
2686 if (data & ~msr_entry.data)
2687 return 1;
2688
2689 /* Don't allow the guest to change a bit, #GP */
2690 if (!msr->host_initiated && (data ^ msr_entry.data))
2691 return 1;
2692
2693 svm->msr_decfg = data;
2694 break;
2695 }
44a95dae
SS		 2696 case MSR_IA32_APICBASE:
2697 if (kvm_vcpu_apicv_active(vcpu))
2698 avic_update_vapic_bar(to_svm(vcpu), data);
df561f66 2699 fallthrough;
6aa8b732 2700 default:
8fe8ab46 2701 return kvm_set_msr_common(vcpu, msr);
6aa8b732
AK		 2702 }
2703 return 0;
2704}
2705
851ba692 2706static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2707{
1edce0a9 2708 return kvm_emulate_wrmsr(&svm->vcpu);
6aa8b732
AK		 2709}
2710
851ba692 2711static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2712{
e756fc62 2713 if (svm->vmcb->control.exit_info_1)
851ba692 2714 return wrmsr_interception(svm);
6aa8b732 2715 else
851ba692 2716 return rdmsr_interception(svm);
6aa8b732
AK		 2717}
2718
851ba692 2719static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2720{
3842d135 2721 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
f0b85051 2722 svm_clear_vintr(svm);
f3515dc3
SS		 2723
2724 /*
2725 * For AVIC, the only reason to end up here is ExtINTs.
2726 * In this case AVIC was temporarily disabled for
2727 * requesting the IRQ window and we have to re-enable it.
2728 */
2729 svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2730
675acb75 2731 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2732 return 1;
2733}
2734
565d0998
ML		 2735static int pause_interception(struct vcpu_svm *svm)
2736{
de63ad4c
LM		 2737 struct kvm_vcpu *vcpu = &svm->vcpu;
2738 bool in_kernel = (svm_get_cpl(vcpu) == 0);
2739
830f01b0 2740 if (!kvm_pause_in_guest(vcpu->kvm))
8566ac8b
BM		 2741 grow_ple_window(vcpu);
2742
de63ad4c 2743 kvm_vcpu_on_spin(vcpu, in_kernel);
565d0998
ML		 2744 return 1;
2745}
2746
87c00572
GS		 2747static int nop_interception(struct vcpu_svm *svm)
2748{
b742c1e6 2749 return kvm_skip_emulated_instruction(&(svm->vcpu));
87c00572
GS		 2750}
2751
2752static int monitor_interception(struct vcpu_svm *svm)
2753{
2754 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2755 return nop_interception(svm);
2756}
2757
2758static int mwait_interception(struct vcpu_svm *svm)
2759{
2760 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2761 return nop_interception(svm);
2762}
2763
4407a797
BM		 2764static int invpcid_interception(struct vcpu_svm *svm)
2765{
2766 struct kvm_vcpu *vcpu = &svm->vcpu;
2767 unsigned long type;
2768 gva_t gva;
2769
2770 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
2771 kvm_queue_exception(vcpu, UD_VECTOR);
2772 return 1;
2773 }
2774
2775 /*
2776 * For an INVPCID intercept:
2777 * EXITINFO1 provides the linear address of the memory operand.
2778 * EXITINFO2 provides the contents of the register operand.
2779 */
2780 type = svm->vmcb->control.exit_info_2;
2781 gva = svm->vmcb->control.exit_info_1;
2782
2783 if (type > 3) {
2784 kvm_inject_gp(vcpu, 0);
2785 return 1;
2786 }
2787
2788 return kvm_handle_invpcid(vcpu, type, gva);
2789}
2790
09941fbb 2791static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
7ff76d58
AP		 2792 [SVM_EXIT_READ_CR0] = cr_interception,
2793 [SVM_EXIT_READ_CR3] = cr_interception,
2794 [SVM_EXIT_READ_CR4] = cr_interception,
2795 [SVM_EXIT_READ_CR8] = cr_interception,
5e57518d 2796 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
628afd2a 2797 [SVM_EXIT_WRITE_CR0] = cr_interception,
7ff76d58
AP		 2798 [SVM_EXIT_WRITE_CR3] = cr_interception,
2799 [SVM_EXIT_WRITE_CR4] = cr_interception,
e0231715 2800 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
cae3797a
AP		 2801 [SVM_EXIT_READ_DR0] = dr_interception,
2802 [SVM_EXIT_READ_DR1] = dr_interception,
2803 [SVM_EXIT_READ_DR2] = dr_interception,
2804 [SVM_EXIT_READ_DR3] = dr_interception,
2805 [SVM_EXIT_READ_DR4] = dr_interception,
2806 [SVM_EXIT_READ_DR5] = dr_interception,
2807 [SVM_EXIT_READ_DR6] = dr_interception,
2808 [SVM_EXIT_READ_DR7] = dr_interception,
2809 [SVM_EXIT_WRITE_DR0] = dr_interception,
2810 [SVM_EXIT_WRITE_DR1] = dr_interception,
2811 [SVM_EXIT_WRITE_DR2] = dr_interception,
2812 [SVM_EXIT_WRITE_DR3] = dr_interception,
2813 [SVM_EXIT_WRITE_DR4] = dr_interception,
2814 [SVM_EXIT_WRITE_DR5] = dr_interception,
2815 [SVM_EXIT_WRITE_DR6] = dr_interception,
2816 [SVM_EXIT_WRITE_DR7] = dr_interception,
d0bfb940
JK		 2817 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2818 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2819 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715 2820 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
e0231715 2821 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
54a20552 2822 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
9718420e 2823 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
e0231715 2824 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2825 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2826 [SVM_EXIT_SMI] = nop_on_interception,
2827 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2828 [SVM_EXIT_VINTR] = interrupt_window_interception,
332b56e4 2829 [SVM_EXIT_RDPMC] = rdpmc_interception,
6aa8b732 2830 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2831 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2832 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2833 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2834 [SVM_EXIT_HLT] = halt_interception,
a7052897 2835 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2836 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2837 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2838 [SVM_EXIT_MSR] = msr_interception,
2839 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2840 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2841 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2842 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2843 [SVM_EXIT_VMLOAD] = vmload_interception,
2844 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2845 [SVM_EXIT_STGI] = stgi_interception,
2846 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2847 [SVM_EXIT_SKINIT] = skinit_interception,
dab429a7 2848 [SVM_EXIT_WBINVD] = wbinvd_interception,
87c00572
GS		 2849 [SVM_EXIT_MONITOR] = monitor_interception,
2850 [SVM_EXIT_MWAIT] = mwait_interception,
81dd35d4 2851 [SVM_EXIT_XSETBV] = xsetbv_interception,
0cb8410b 2852 [SVM_EXIT_RDPRU] = rdpru_interception,
4407a797 2853 [SVM_EXIT_INVPCID] = invpcid_interception,
d0006530 2854 [SVM_EXIT_NPF] = npf_interception,
7607b717 2855 [SVM_EXIT_RSM] = rsm_interception,
18f40c53
SS		 2856 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
2857 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
6aa8b732
AK		 2858};
2859
ae8cc059 2860static void dump_vmcb(struct kvm_vcpu *vcpu)
3f10c846
JR		 2861{
2862 struct vcpu_svm *svm = to_svm(vcpu);
2863 struct vmcb_control_area *control = &svm->vmcb->control;
2864 struct vmcb_save_area *save = &svm->vmcb->save;
2865
6f2f8453
PB		 2866 if (!dump_invalid_vmcb) {
2867 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2868 return;
2869 }
2870
3f10c846 2871 pr_err("VMCB Control Area:\n");
03bfeeb9
BM		 2872 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
2873 pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
30abaa88
BM		 2874 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
2875 pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
9780d51d 2876 pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
c62e2e94
BM		 2877 pr_err("%-20s%08x %08x\n", "intercepts:",
2878 control->intercepts[INTERCEPT_WORD3],
2879 control->intercepts[INTERCEPT_WORD4]);
ae8cc059 2880 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
1d8fb44a
BM		 2881 pr_err("%-20s%d\n", "pause filter threshold:",
2882 control->pause_filter_thresh);
ae8cc059
JP		 2883 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2884 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
2885 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
2886 pr_err("%-20s%d\n", "asid:", control->asid);
2887 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
2888 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
2889 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
2890 pr_err("%-20s%08x\n", "int_state:", control->int_state);
2891 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
2892 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
2893 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
2894 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
2895 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
2896 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
2897 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
44a95dae 2898 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
ae8cc059
JP		 2899 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
2900 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
0dc92119 2901 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
ae8cc059 2902 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
44a95dae
SS		 2903 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
2904 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
2905 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3f10c846 2906 pr_err("VMCB State Save Area:\n");
ae8cc059
JP		 2907 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2908 "es:",
2909 save->es.selector, save->es.attrib,
2910 save->es.limit, save->es.base);
2911 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2912 "cs:",
2913 save->cs.selector, save->cs.attrib,
2914 save->cs.limit, save->cs.base);
2915 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2916 "ss:",
2917 save->ss.selector, save->ss.attrib,
2918 save->ss.limit, save->ss.base);
2919 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2920 "ds:",
2921 save->ds.selector, save->ds.attrib,
2922 save->ds.limit, save->ds.base);
2923 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2924 "fs:",
2925 save->fs.selector, save->fs.attrib,
2926 save->fs.limit, save->fs.base);
2927 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2928 "gs:",
2929 save->gs.selector, save->gs.attrib,
2930 save->gs.limit, save->gs.base);
2931 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2932 "gdtr:",
2933 save->gdtr.selector, save->gdtr.attrib,
2934 save->gdtr.limit, save->gdtr.base);
2935 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2936 "ldtr:",
2937 save->ldtr.selector, save->ldtr.attrib,
2938 save->ldtr.limit, save->ldtr.base);
2939 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2940 "idtr:",
2941 save->idtr.selector, save->idtr.attrib,
2942 save->idtr.limit, save->idtr.base);
2943 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2944 "tr:",
2945 save->tr.selector, save->tr.attrib,
2946 save->tr.limit, save->tr.base);
3f10c846
JR		 2947 pr_err("cpl: %d efer: %016llx\n",
2948 save->cpl, save->efer);
ae8cc059
JP		 2949 pr_err("%-15s %016llx %-13s %016llx\n",
2950 "cr0:", save->cr0, "cr2:", save->cr2);
2951 pr_err("%-15s %016llx %-13s %016llx\n",
2952 "cr3:", save->cr3, "cr4:", save->cr4);
2953 pr_err("%-15s %016llx %-13s %016llx\n",
2954 "dr6:", save->dr6, "dr7:", save->dr7);
2955 pr_err("%-15s %016llx %-13s %016llx\n",
2956 "rip:", save->rip, "rflags:", save->rflags);
2957 pr_err("%-15s %016llx %-13s %016llx\n",
2958 "rsp:", save->rsp, "rax:", save->rax);
2959 pr_err("%-15s %016llx %-13s %016llx\n",
2960 "star:", save->star, "lstar:", save->lstar);
2961 pr_err("%-15s %016llx %-13s %016llx\n",
2962 "cstar:", save->cstar, "sfmask:", save->sfmask);
2963 pr_err("%-15s %016llx %-13s %016llx\n",
2964 "kernel_gs_base:", save->kernel_gs_base,
2965 "sysenter_cs:", save->sysenter_cs);
2966 pr_err("%-15s %016llx %-13s %016llx\n",
2967 "sysenter_esp:", save->sysenter_esp,
2968 "sysenter_eip:", save->sysenter_eip);
2969 pr_err("%-15s %016llx %-13s %016llx\n",
2970 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
2971 pr_err("%-15s %016llx %-13s %016llx\n",
2972 "br_from:", save->br_from, "br_to:", save->br_to);
2973 pr_err("%-15s %016llx %-13s %016llx\n",
2974 "excp_from:", save->last_excp_from,
2975 "excp_to:", save->last_excp_to);
3f10c846
JR		 2976}
2977
235ba74f
SC		 2978static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
2979 u32 *intr_info, u32 *error_code)
586f9607
AK		 2980{
2981 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2982
2983 *info1 = control->exit_info_1;
2984 *info2 = control->exit_info_2;
235ba74f
SC		 2985 *intr_info = control->exit_int_info;
2986 if ((*intr_info & SVM_EXITINTINFO_VALID) &&
2987 (*intr_info & SVM_EXITINTINFO_VALID_ERR))
2988 *error_code = control->exit_int_info_err;
2989 else
2990 *error_code = 0;
586f9607
AK		 2991}
2992
404d5d7b 2993static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6aa8b732 2994{
04d2cc77 2995 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2996 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2997 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2998
8b89fe1f
PB		 2999 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3000
830bd71f 3001 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
2be4fc7a
JR		 3002 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3003 if (npt_enabled)
3004 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 3005
2030753d 3006 if (is_guest_mode(vcpu)) {
410e4d57
JR		 3007 int vmexit;
3008
cc167bd7 3009 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
d8cabddf 3010
410e4d57
JR		 3011 vmexit = nested_svm_exit_special(svm);
3012
3013 if (vmexit == NESTED_EXIT_CONTINUE)
3014 vmexit = nested_svm_exit_handled(svm);
3015
3016 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 3017 return 1;
cf74a78b
AG		 3018 }
3019
04d2cc77
AK		 3020 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3021 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3022 kvm_run->fail_entry.hardware_entry_failure_reason
3023 = svm->vmcb->control.exit_code;
8a14fe4f 3024 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3f10c846 3025 dump_vmcb(vcpu);
04d2cc77
AK		 3026 return 0;
3027 }
3028
a2fa3e9f 3029 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 3030 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
55c5e464
JR		 3031 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3032 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
6614c7d0 3033 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
6aa8b732 3034 "exit_code 0x%x\n",
b8688d51 3035 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 3036 exit_code);
3037
404d5d7b 3038 if (exit_fastpath != EXIT_FASTPATH_NONE)
1e9e2622 3039 return 1;
404d5d7b
WL		 3040
3041 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 3042 || !svm_exit_handlers[exit_code]) {
7396d337
LA		 3043 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
3044 dump_vmcb(vcpu);
3045 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3046 vcpu->run->internal.suberror =
3047 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
1aa561b1 3048 vcpu->run->internal.ndata = 2;
7396d337 3049 vcpu->run->internal.data[0] = exit_code;
8a14fe4f 3050 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
7396d337 3051 return 0;
6aa8b732
AK		 3052 }
3053
3dcb2a3f
AA		 3054#ifdef CONFIG_RETPOLINE
3055 if (exit_code == SVM_EXIT_MSR)
3056 return msr_interception(svm);
3057 else if (exit_code == SVM_EXIT_VINTR)
3058 return interrupt_window_interception(svm);
3059 else if (exit_code == SVM_EXIT_INTR)
3060 return intr_interception(svm);
3061 else if (exit_code == SVM_EXIT_HLT)
3062 return halt_interception(svm);
3063 else if (exit_code == SVM_EXIT_NPF)
3064 return npf_interception(svm);
3065#endif
851ba692 3066 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 3067}
3068
3069static void reload_tss(struct kvm_vcpu *vcpu)
3070{
73cd6e5f 3071 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
6aa8b732 3072
0fe1e009 3073 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 3074 load_TR_desc();
3075}
3076
e756fc62 3077static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732 3078{
73cd6e5f 3079 struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
6aa8b732 3080
70cd94e6 3081 if (sev_guest(svm->vcpu.kvm))
73cd6e5f 3082 return pre_sev_run(svm, svm->vcpu.cpu);
70cd94e6 3083
4b656b12 3084 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 3085 if (svm->asid_generation != sd->asid_generation)
3086 new_asid(svm, sd);
6aa8b732
AK		 3087}
3088
95ba8273
GN		 3089static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3090{
3091 struct vcpu_svm *svm = to_svm(vcpu);
3092
3093 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3094 vcpu->arch.hflags |= HF_NMI_MASK;
a284ba56 3095 svm_set_intercept(svm, INTERCEPT_IRET);
95ba8273
GN		 3096 ++vcpu->stat.nmi_injections;
3097}
6aa8b732 3098
66fd3f7f 3099static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3100{
3101 struct vcpu_svm *svm = to_svm(vcpu);
3102
2af9194d 3103 BUG_ON(!(gif_set(svm)));
cf74a78b 3104
9fb2d2b4
GN		 3105 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3106 ++vcpu->stat.irq_injections;
3107
219b65dc
AG		 3108 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3109 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3110}
3111
95ba8273 3112static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3113{
3114 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3115
01c3b2b5 3116 if (nested_svm_virtualize_tpr(vcpu))
88ab24ad
JR		 3117 return;
3118
830bd71f 3119 svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
596f3142 3120
95ba8273 3121 if (irr == -1)
aaacfc9a
JR		 3122 return;
3123
95ba8273 3124 if (tpr >= irr)
830bd71f 3125 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
95ba8273 3126}
aaacfc9a 3127
cae96af1 3128bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
95ba8273
GN		 3129{
3130 struct vcpu_svm *svm = to_svm(vcpu);
3131 struct vmcb *vmcb = svm->vmcb;
88c604b6 3132 bool ret;
9c3d370a 3133
cae96af1 3134 if (!gif_set(svm))
bbdad0b5
PB		 3135 return true;
3136
cae96af1
PB		 3137 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3138 return false;
3139
3140 ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3141 (svm->vcpu.arch.hflags & HF_NMI_MASK);
924584cc
JR		 3142
3143 return ret;
aaacfc9a
JR		 3144}
3145
c9d40913 3146static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3147{
3148 struct vcpu_svm *svm = to_svm(vcpu);
3149 if (svm->nested.nested_run_pending)
c9d40913 3150 return -EBUSY;
cae96af1 3151
c300ab9f
PB		 3152 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3153 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
c9d40913 3154 return -EBUSY;
c300ab9f
PB		 3155
3156 return !svm_nmi_blocked(vcpu);
cae96af1
PB		 3157}
3158
3cfc3092
JK		 3159static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3160{
3161 struct vcpu_svm *svm = to_svm(vcpu);
3162
3163 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3164}
3165
3166static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3167{
3168 struct vcpu_svm *svm = to_svm(vcpu);
3169
3170 if (masked) {
3171 svm->vcpu.arch.hflags |= HF_NMI_MASK;
a284ba56 3172 svm_set_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3173 } else {
3174 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
a284ba56 3175 svm_clr_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3176 }
3177}
3178
cae96af1 3179bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
78646121
GN		 3180{
3181 struct vcpu_svm *svm = to_svm(vcpu);
3182 struct vmcb *vmcb = svm->vmcb;
7fcdb510 3183
fc6f7c03 3184 if (!gif_set(svm))
cae96af1 3185 return true;
7fcdb510 3186
fc6f7c03
PB		 3187 if (is_guest_mode(vcpu)) {
3188 /* As long as interrupts are being delivered... */
e9fd761a 3189 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
08245e6d 3190 ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
fc6f7c03
PB		 3191 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3192 return true;
3193
3194 /* ... vmexits aren't blocked by the interrupt shadow */
3195 if (nested_exit_on_intr(svm))
3196 return false;
3197 } else {
3198 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3199 return true;
3200 }
3201
3202 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
cae96af1
PB		 3203}
3204
c9d40913 3205static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3206{
3207 struct vcpu_svm *svm = to_svm(vcpu);
3208 if (svm->nested.nested_run_pending)
c9d40913 3209 return -EBUSY;
cae96af1 3210
c300ab9f
PB		 3211 /*
3212 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3213 * e.g. if the IRQ arrived asynchronously after checking nested events.
3214 */
3215 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
c9d40913 3216 return -EBUSY;
c300ab9f
PB		 3217
3218 return !svm_interrupt_blocked(vcpu);
78646121
GN		 3219}
3220
c9a7953f 3221static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3222{
219b65dc 3223 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3224
e0231715
JR		 3225 /*
3226 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3227 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3228 * get that intercept, this function will be called again though and
640bd6e5
JN		 3229 * we'll get the vintr intercept. However, if the vGIF feature is
3230 * enabled, the STGI interception will not occur. Enable the irq
3231 * window under the assumption that the hardware will set the GIF.
e0231715 3232 */
b518ba9f 3233 if (vgif_enabled(svm) || gif_set(svm)) {
f3515dc3
SS		 3234 /*
3235 * IRQ window is not needed when AVIC is enabled,
3236 * unless we have pending ExtINT since it cannot be injected
3237 * via AVIC. In such case, we need to temporarily disable AVIC,
3238 * and fallback to injecting IRQ via V_IRQ.
3239 */
3240 svm_toggle_avic_for_irq_window(vcpu, false);
219b65dc 3241 svm_set_vintr(svm);
219b65dc 3242 }
85f455f7
ED		 3243}
3244
c9a7953f 3245static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3246{
04d2cc77 3247 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3248
44c11430
GN		 3249 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3250 == HF_NMI_MASK)
c9a7953f 3251 return; /* IRET will cause a vm exit */
44c11430 3252
640bd6e5
JN		 3253 if (!gif_set(svm)) {
3254 if (vgif_enabled(svm))
a284ba56 3255 svm_set_intercept(svm, INTERCEPT_STGI);
1a5e1852 3256 return; /* STGI will cause a vm exit */
640bd6e5 3257 }
1a5e1852 3258
e0231715
JR		 3259 /*
3260 * Something prevents NMI from been injected. Single step over possible
3261 * problem (IRET or exception injection or interrupt shadow)
3262 */
ab2f4d73 3263 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
6be7d306 3264 svm->nmi_singlestep = true;
44c11430 3265 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
c1150d8c
DL		 3266}
3267
cbc94022
IE		 3268static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3269{
3270 return 0;
3271}
3272
2ac52ab8
SC		 3273static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3274{
3275 return 0;
3276}
3277
f55ac304 3278void svm_flush_tlb(struct kvm_vcpu *vcpu)
d9e368d6 3279{
38e5e92f
JR		 3280 struct vcpu_svm *svm = to_svm(vcpu);
3281
4a41e43c
SC		 3282 /*
3283 * Flush only the current ASID even if the TLB flush was invoked via
3284 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3285 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3286 * unconditionally does a TLB flush on both nested VM-Enter and nested
3287 * VM-Exit (via kvm_mmu_reset_context()).
3288 */
38e5e92f
JR		 3289 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3290 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3291 else
3292 svm->asid_generation--;
d9e368d6
AK		 3293}
3294
faff8758
JS		 3295static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3296{
3297 struct vcpu_svm *svm = to_svm(vcpu);
3298
3299 invlpga(gva, svm->vmcb->control.asid);
3300}
3301
04d2cc77
AK		 3302static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3303{
3304}
3305
d7bf8221
JR		 3306static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3307{
3308 struct vcpu_svm *svm = to_svm(vcpu);
3309
01c3b2b5 3310 if (nested_svm_virtualize_tpr(vcpu))
88ab24ad
JR		 3311 return;
3312
830bd71f 3313 if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
d7bf8221 3314 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3315 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3316 }
3317}
3318
649d6864
JR		 3319static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3320{
3321 struct vcpu_svm *svm = to_svm(vcpu);
3322 u64 cr8;
3323
01c3b2b5 3324 if (nested_svm_virtualize_tpr(vcpu) ||
3bbf3565 3325 kvm_vcpu_apicv_active(vcpu))
88ab24ad
JR		 3326 return;
3327
649d6864
JR		 3328 cr8 = kvm_get_cr8(vcpu);
3329 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3330 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3331}
3332
9222be18
GN		 3333static void svm_complete_interrupts(struct vcpu_svm *svm)
3334{
3335 u8 vector;
3336 int type;
3337 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3338 unsigned int3_injected = svm->int3_injected;
3339
3340 svm->int3_injected = 0;
9222be18 3341
bd3d1ec3
AK		 3342 /*
3343 * If we've made progress since setting HF_IRET_MASK, we've
3344 * executed an IRET and can allow NMI injection.
3345 */
3346 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3347 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
44c11430 3348 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3842d135
AK		 3349 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3350 }
44c11430 3351
9222be18
GN		 3352 svm->vcpu.arch.nmi_injected = false;
3353 kvm_clear_exception_queue(&svm->vcpu);
3354 kvm_clear_interrupt_queue(&svm->vcpu);
3355
3356 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3357 return;
3358
3842d135
AK		 3359 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3360
9222be18
GN		 3361 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3362 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3363
3364 switch (type) {
3365 case SVM_EXITINTINFO_TYPE_NMI:
3366 svm->vcpu.arch.nmi_injected = true;
3367 break;
3368 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3369 /*
3370 * In case of software exceptions, do not reinject the vector,
3371 * but re-execute the instruction instead. Rewind RIP first
3372 * if we emulated INT3 before.
3373 */
3374 if (kvm_exception_is_soft(vector)) {
3375 if (vector == BP_VECTOR && int3_injected &&
3376 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3377 kvm_rip_write(&svm->vcpu,
3378 kvm_rip_read(&svm->vcpu) -
3379 int3_injected);
9222be18 3380 break;
66b7138f 3381 }
9222be18
GN		 3382 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3383 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3384 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3385
3386 } else
ce7ddec4 3387 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3388 break;
3389 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3390 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3391 break;
3392 default:
3393 break;
3394 }
3395}
3396
b463a6f7
AK		 3397static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3398{
3399 struct vcpu_svm *svm = to_svm(vcpu);
3400 struct vmcb_control_area *control = &svm->vmcb->control;
3401
3402 control->exit_int_info = control->event_inj;
3403 control->exit_int_info_err = control->event_inj_err;
3404 control->event_inj = 0;
3405 svm_complete_interrupts(svm);
3406}
3407
404d5d7b 3408static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
a9ab13ff 3409{
4e810adb 3410 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
a9ab13ff
WL		 3411 to_svm(vcpu)->vmcb->control.exit_info_1)
3412 return handle_fastpath_set_msr_irqoff(vcpu);
3413
3414 return EXIT_FASTPATH_NONE;
3415}
3416
56a87e5d 3417void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
199cd1d7 3418
135961e0
TG		 3419static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3420 struct vcpu_svm *svm)
3421{
3422 /*
3423 * VMENTER enables interrupts (host state), but the kernel state is
3424 * interrupts disabled when this is invoked. Also tell RCU about
3425 * it. This is the same logic as for exit_to_user_mode().
3426 *
3427 * This ensures that e.g. latency analysis on the host observes
3428 * guest mode as interrupt enabled.
3429 *
3430 * guest_enter_irqoff() informs context tracking about the
3431 * transition to guest mode and if enabled adjusts RCU state
3432 * accordingly.
3433 */
3434 instrumentation_begin();
3435 trace_hardirqs_on_prepare();
3436 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3437 instrumentation_end();
3438
3439 guest_enter_irqoff();
3440 lockdep_hardirqs_on(CALLER_ADDR0);
3441
3442 __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3443
3444#ifdef CONFIG_X86_64
c3f08ed1 3445 native_wrmsrl(MSR_GS_BASE, svm->host.gs_base);
135961e0
TG		 3446#else
3447 loadsegment(fs, svm->host.fs);
3448#ifndef CONFIG_X86_32_LAZY_GS
3449 loadsegment(gs, svm->host.gs);
3450#endif
3451#endif
3452
3453 /*
3454 * VMEXIT disables interrupts (host state), but tracing and lockdep
3455 * have them in state 'on' as recorded before entering guest mode.
3456 * Same as enter_from_user_mode().
3457 *
3458 * guest_exit_irqoff() restores host context and reinstates RCU if
3459 * enabled and required.
3460 *
3461 * This needs to be done before the below as native_read_msr()
3462 * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3463 * into world and some more.
3464 */
3465 lockdep_hardirqs_off(CALLER_ADDR0);
3466 guest_exit_irqoff();
3467
3468 instrumentation_begin();
3469 trace_hardirqs_off_finish();
3470 instrumentation_end();
3471}
3472
b95273f1 3473static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3474{
a2fa3e9f 3475 struct vcpu_svm *svm = to_svm(vcpu);
d9e368d6 3476
2041a06a
JR		 3477 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3478 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3479 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3480
a12713c2
LP		 3481 /*
3482 * Disable singlestep if we're injecting an interrupt/exception.
3483 * We don't want our modified rflags to be pushed on the stack where
3484 * we might not be able to easily reset them if we disabled NMI
3485 * singlestep later.
3486 */
3487 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3488 /*
3489 * Event injection happens before external interrupts cause a
3490 * vmexit and interrupts are disabled here, so smp_send_reschedule
3491 * is enough to force an immediate vmexit.
3492 */
3493 disable_nmi_singlestep(svm);
3494 smp_send_reschedule(vcpu->cpu);
3495 }
3496
e756fc62 3497 pre_svm_run(svm);
6aa8b732 3498
649d6864
JR		 3499 sync_lapic_to_cr8(vcpu);
3500
cda0ffdd 3501 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3502
d67668e9
PB		 3503 /*
3504 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3505 * of a #DB.
3506 */
3507 if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3508 svm_set_dr6(svm, vcpu->arch.dr6);
3509 else
3510 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3511
04d2cc77 3512 clgi();
139a12cf 3513 kvm_load_guest_xsave_state(vcpu);
04d2cc77 3514
010fd37f 3515 kvm_wait_lapic_expire(vcpu);
b6c4bc65 3516
b2ac58f9
KA		 3517 /*
3518 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3519 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3520 * is no need to worry about the conditional branch over the wrmsr
3521 * being speculatively taken.
3522 */
ccbcd267 3523 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
b2ac58f9 3524
135961e0 3525 svm_vcpu_enter_exit(vcpu, svm);
15e6c22f 3526
b2ac58f9
KA		 3527 /*
3528 * We do not use IBRS in the kernel. If this vCPU has used the
3529 * SPEC_CTRL MSR it may have left it on; save the value and
3530 * turn it off. This is much more efficient than blindly adding
3531 * it to the atomic save/restore list. Especially as the former
3532 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3533 *
3534 * For non-nested case:
3535 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3536 * save it.
3537 *
3538 * For nested case:
3539 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3540 * save it.
3541 */
946fbbc1 3542 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
ecb586bd 3543 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b2ac58f9 3544
6aa8b732
AK		 3545 reload_tss(vcpu);
3546
024d83ca
TG		 3547 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3548
13c34e07
AK		 3549 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3550 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3551 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3552 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3553
3781c01c 3554 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
dd60d217 3555 kvm_before_interrupt(&svm->vcpu);
3781c01c 3556
139a12cf 3557 kvm_load_host_xsave_state(vcpu);
3781c01c
JR		 3558 stgi();
3559
3560 /* Any pending NMI will happen here */
3561
3562 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
dd60d217 3563 kvm_after_interrupt(&svm->vcpu);
3781c01c 3564
d7bf8221
JR		 3565 sync_cr8_to_lapic(vcpu);
3566
a2fa3e9f 3567 svm->next_rip = 0;
2d8a42be
PB		 3568 if (is_guest_mode(&svm->vcpu)) {
3569 sync_nested_vmcb_control(svm);
3570 svm->nested.nested_run_pending = 0;
3571 }
9222be18 3572
38e5e92f 3573 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
e42c6828 3574 vmcb_mark_all_clean(svm->vmcb);
38e5e92f 3575
631bc487
GN		 3576 /* if exit due to PF check for async PF */
3577 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
68fd66f1
VK		 3578 svm->vcpu.arch.apf.host_apf_flags =
3579 kvm_read_and_reset_apf_flags();
631bc487 3580
6de4f3ad
AK		 3581 if (npt_enabled) {
3582 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3583 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3584 }
fe5913e4
JR		 3585
3586 /*
3587 * We need to handle MC intercepts here before the vcpu has a chance to
3588 * change the physical cpu
3589 */
3590 if (unlikely(svm->vmcb->control.exit_code ==
3591 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3592 svm_handle_mce(svm);
8d28fec4 3593
e42c6828 3594 svm_complete_interrupts(svm);
4e810adb
WL		 3595
3596 if (is_guest_mode(vcpu))
3597 return EXIT_FASTPATH_NONE;
3598
3599 return svm_exit_handlers_fastpath(vcpu);
6aa8b732
AK		 3600}
3601
2a40b900
SC		 3602static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root,
3603 int root_level)
6aa8b732 3604{
a2fa3e9f 3605 struct vcpu_svm *svm = to_svm(vcpu);
689f3bf2 3606 unsigned long cr3;
a2fa3e9f 3607
689f3bf2
PB		 3608 cr3 = __sme_set(root);
3609 if (npt_enabled) {
3610 svm->vmcb->control.nested_cr3 = cr3;
06e7852c 3611 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
1c97f0a0 3612
689f3bf2 3613 /* Loading L2's CR3 is handled by enter_svm_guest_mode. */
978ce583
PB		 3614 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3615 return;
3616 cr3 = vcpu->arch.cr3;
689f3bf2 3617 }
1c97f0a0 3618
978ce583 3619 svm->vmcb->save.cr3 = cr3;
06e7852c 3620 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1c97f0a0
JR		 3621}
3622
6aa8b732
AK		 3623static int is_disabled(void)
3624{
6031a61c
JR		 3625 u64 vm_cr;
3626
3627 rdmsrl(MSR_VM_CR, vm_cr);
3628 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3629 return 1;
3630
6aa8b732
AK		 3631 return 0;
3632}
3633
102d8325
IM		 3634static void
3635svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3636{
3637 /*
3638 * Patch in the VMMCALL instruction:
3639 */
3640 hypercall[0] = 0x0f;
3641 hypercall[1] = 0x01;
3642 hypercall[2] = 0xd9;
102d8325
IM		 3643}
3644
f257d6dc 3645static int __init svm_check_processor_compat(void)
002c7f7c 3646{
f257d6dc 3647 return 0;
002c7f7c
YS		 3648}
3649
774ead3a
AK		 3650static bool svm_cpu_has_accelerated_tpr(void)
3651{
3652 return false;
3653}
3654
cb97c2d6 3655static bool svm_has_emulated_msr(u32 index)
6d396b55 3656{
e87555e5
VK		 3657 switch (index) {
3658 case MSR_IA32_MCG_EXT_CTL:
95c5c7c7 3659 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
e87555e5
VK		 3660 return false;
3661 default:
3662 break;
3663 }
3664
6d396b55
PB		 3665 return true;
3666}
3667
fc07e76a
PB		 3668static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3669{
3670 return 0;
3671}
3672
7c1b761b 3673static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
0e851880 3674{
6092d3d3
JR		 3675 struct vcpu_svm *svm = to_svm(vcpu);
3676
7204160e 3677 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
96be4e06 3678 boot_cpu_has(X86_FEATURE_XSAVE) &&
7204160e
AL		 3679 boot_cpu_has(X86_FEATURE_XSAVES);
3680
6092d3d3 3681 /* Update nrips enabled cache */
4eb87460
SC		 3682 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3683 guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
46781eae 3684
4407a797
BM		 3685 /* Check again if INVPCID interception if required */
3686 svm_check_invpcid(svm);
3687
46781eae
SS		 3688 if (!kvm_vcpu_apicv_active(vcpu))
3689 return;
3690
cc7f5577
OU		 3691 /*
3692 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3693 * is exposed to the guest, disable AVIC.
3694 */
3695 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3696 kvm_request_apicv_update(vcpu->kvm, false,
3697 APICV_INHIBIT_REASON_X2APIC);
9a0bf054
SS		 3698
3699 /*
3700 * Currently, AVIC does not work with nested virtualization.
3701 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3702 */
3703 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3704 kvm_request_apicv_update(vcpu->kvm, false,
3705 APICV_INHIBIT_REASON_NESTED);
0e851880
SY		 3706}
3707
f5f48ee1
SY		 3708static bool svm_has_wbinvd_exit(void)
3709{
3710 return true;
3711}
3712
8061252e 3713#define PRE_EX(exit) { .exit_code = (exit), \
40e19b51 3714 .stage = X86_ICPT_PRE_EXCEPT, }
cfec82cb 3715#define POST_EX(exit) { .exit_code = (exit), \
40e19b51 3716 .stage = X86_ICPT_POST_EXCEPT, }
d7eb8203 3717#define POST_MEM(exit) { .exit_code = (exit), \
40e19b51 3718 .stage = X86_ICPT_POST_MEMACCESS, }
cfec82cb 3719
09941fbb 3720static const struct __x86_intercept {
cfec82cb
JR		 3721 u32 exit_code;
3722 enum x86_intercept_stage stage;
cfec82cb
JR		 3723} x86_intercept_map[] = {
3724 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
3725 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
3726 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
3727 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
3728 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
3b88e41a
JR		 3729 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
3730 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
dee6bb70
JR		 3731 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
3732 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
3733 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
3734 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
3735 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
3736 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
3737 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
3738 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
01de8b09
JR		 3739 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
3740 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
3741 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
3742 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
3743 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
3744 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
3745 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
3746 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
d7eb8203
JR		 3747 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
3748 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
3749 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
8061252e
JR		 3750 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
3751 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
3752 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
3753 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
3754 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
3755 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
3756 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
3757 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
3758 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
bf608f88
JR		 3759 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
3760 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
3761 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
3762 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
3763 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
3764 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
3765 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
f6511935
JR		 3766 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
3767 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
3768 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
3769 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
02d4160f 3770 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
cfec82cb
JR		 3771};
3772
8061252e 3773#undef PRE_EX
cfec82cb 3774#undef POST_EX
d7eb8203 3775#undef POST_MEM
cfec82cb 3776
8a76d7f2
JR		 3777static int svm_check_intercept(struct kvm_vcpu *vcpu,
3778 struct x86_instruction_info *info,
21f1b8f2
SC		 3779 enum x86_intercept_stage stage,
3780 struct x86_exception *exception)
8a76d7f2 3781{
cfec82cb
JR		 3782 struct vcpu_svm *svm = to_svm(vcpu);
3783 int vmexit, ret = X86EMUL_CONTINUE;
3784 struct __x86_intercept icpt_info;
3785 struct vmcb *vmcb = svm->vmcb;
3786
3787 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3788 goto out;
3789
3790 icpt_info = x86_intercept_map[info->intercept];
3791
40e19b51 3792 if (stage != icpt_info.stage)
cfec82cb
JR		 3793 goto out;
3794
3795 switch (icpt_info.exit_code) {
3796 case SVM_EXIT_READ_CR0:
3797 if (info->intercept == x86_intercept_cr_read)
3798 icpt_info.exit_code += info->modrm_reg;
3799 break;
3800 case SVM_EXIT_WRITE_CR0: {
3801 unsigned long cr0, val;
cfec82cb
JR		 3802
3803 if (info->intercept == x86_intercept_cr_write)
3804 icpt_info.exit_code += info->modrm_reg;
3805
62baf44c
JK		 3806 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3807 info->intercept == x86_intercept_clts)
cfec82cb
JR		 3808 break;
3809
c62e2e94
BM		 3810 if (!(vmcb_is_intercept(&svm->nested.ctl,
3811 INTERCEPT_SELECTIVE_CR0)))
cfec82cb
JR		 3812 break;
3813
3814 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3815 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
3816
3817 if (info->intercept == x86_intercept_lmsw) {
3818 cr0 &= 0xfUL;
3819 val &= 0xfUL;
3820 /* lmsw can't clear PE - catch this here */
3821 if (cr0 & X86_CR0_PE)
3822 val |= X86_CR0_PE;
3823 }
3824
3825 if (cr0 ^ val)
3826 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3827
3828 break;
3829 }
3b88e41a
JR		 3830 case SVM_EXIT_READ_DR0:
3831 case SVM_EXIT_WRITE_DR0:
3832 icpt_info.exit_code += info->modrm_reg;
3833 break;
8061252e
JR		 3834 case SVM_EXIT_MSR:
3835 if (info->intercept == x86_intercept_wrmsr)
3836 vmcb->control.exit_info_1 = 1;
3837 else
3838 vmcb->control.exit_info_1 = 0;
3839 break;
bf608f88
JR		 3840 case SVM_EXIT_PAUSE:
3841 /*
3842 * We get this for NOP only, but pause
3843 * is rep not, check this here
3844 */
3845 if (info->rep_prefix != REPE_PREFIX)
3846 goto out;
49a8afca 3847 break;
f6511935
JR		 3848 case SVM_EXIT_IOIO: {
3849 u64 exit_info;
3850 u32 bytes;
3851
f6511935
JR		 3852 if (info->intercept == x86_intercept_in ||
3853 info->intercept == x86_intercept_ins) {
6cbc5f5a
JK		 3854 exit_info = ((info->src_val & 0xffff) << 16) |
3855 SVM_IOIO_TYPE_MASK;
f6511935 3856 bytes = info->dst_bytes;
6493f157 3857 } else {
6cbc5f5a 3858 exit_info = (info->dst_val & 0xffff) << 16;
6493f157 3859 bytes = info->src_bytes;
f6511935
JR		 3860 }
3861
3862 if (info->intercept == x86_intercept_outs ||
3863 info->intercept == x86_intercept_ins)
3864 exit_info |= SVM_IOIO_STR_MASK;
3865
3866 if (info->rep_prefix)
3867 exit_info |= SVM_IOIO_REP_MASK;
3868
3869 bytes = min(bytes, 4u);
3870
3871 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
3872
3873 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
3874
3875 vmcb->control.exit_info_1 = exit_info;
3876 vmcb->control.exit_info_2 = info->next_rip;
3877
3878 break;
3879 }
cfec82cb
JR		 3880 default:
3881 break;
3882 }
3883
f104765b
BD		 3884 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
3885 if (static_cpu_has(X86_FEATURE_NRIPS))
3886 vmcb->control.next_rip = info->next_rip;
cfec82cb
JR		 3887 vmcb->control.exit_code = icpt_info.exit_code;
3888 vmexit = nested_svm_exit_handled(svm);
3889
3890 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
3891 : X86EMUL_CONTINUE;
3892
3893out:
3894 return ret;
8a76d7f2
JR		 3895}
3896
a9ab13ff 3897static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
a547c6db 3898{
a547c6db
YZ		 3899}
3900
ae97a3b8
RK		 3901static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
3902{
830f01b0 3903 if (!kvm_pause_in_guest(vcpu->kvm))
8566ac8b 3904 shrink_ple_window(vcpu);
ae97a3b8
RK		 3905}
3906
74f16909
BP		 3907static void svm_setup_mce(struct kvm_vcpu *vcpu)
3908{
3909 /* [63:9] are reserved. */
3910 vcpu->arch.mcg_cap &= 0x1ff;
3911}
3912
cae96af1 3913bool svm_smi_blocked(struct kvm_vcpu *vcpu)
72d7b374 3914{
05cade71
LP		 3915 struct vcpu_svm *svm = to_svm(vcpu);
3916
3917 /* Per APM Vol.2 15.22.2 "Response to SMI" */
3918 if (!gif_set(svm))
cae96af1
PB		 3919 return true;
3920
3921 return is_smm(vcpu);
3922}
3923
c9d40913 3924static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3925{
3926 struct vcpu_svm *svm = to_svm(vcpu);
3927 if (svm->nested.nested_run_pending)
c9d40913 3928 return -EBUSY;
05cade71 3929
c300ab9f
PB		 3930 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
3931 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
c9d40913 3932 return -EBUSY;
c300ab9f 3933
cae96af1 3934 return !svm_smi_blocked(vcpu);
72d7b374
LP		 3935}
3936
0234bf88
LP		 3937static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
3938{
05cade71
LP		 3939 struct vcpu_svm *svm = to_svm(vcpu);
3940 int ret;
3941
3942 if (is_guest_mode(vcpu)) {
3943 /* FED8h - SVM Guest */
3944 put_smstate(u64, smstate, 0x7ed8, 1);
3945 /* FEE0h - SVM Guest VMCB Physical Address */
0dd16b5b 3946 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
05cade71
LP		 3947
3948 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3949 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3950 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3951
3952 ret = nested_svm_vmexit(svm);
3953 if (ret)
3954 return ret;
3955 }
0234bf88
LP		 3956 return 0;
3957}
3958
ed19321f 3959static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
0234bf88 3960{
05cade71 3961 struct vcpu_svm *svm = to_svm(vcpu);
8c5fbf1a 3962 struct kvm_host_map map;
59cd9bc5 3963 int ret = 0;
05cade71 3964
3ebb5d26
ML		 3965 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
3966 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
3967 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
0dd16b5b 3968 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
05cade71 3969
3ebb5d26
ML		 3970 if (guest) {
3971 if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3972 return 1;
3973
3974 if (!(saved_efer & EFER_SVME))
3975 return 1;
3976
3977 if (kvm_vcpu_map(&svm->vcpu,
0dd16b5b 3978 gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
3ebb5d26
ML		 3979 return 1;
3980
0dd16b5b 3981 ret = enter_svm_guest_mode(svm, vmcb12_gpa, map.hva);
3ebb5d26
ML		 3982 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3983 }
05cade71 3984 }
59cd9bc5
VK		 3985
3986 return ret;
0234bf88
LP		 3987}
3988
c9d40913 3989static void enable_smi_window(struct kvm_vcpu *vcpu)
cc3d967f
LP		 3990{
3991 struct vcpu_svm *svm = to_svm(vcpu);
3992
3993 if (!gif_set(svm)) {
3994 if (vgif_enabled(svm))
a284ba56 3995 svm_set_intercept(svm, INTERCEPT_STGI);
cc3d967f 3996 /* STGI will cause a vm exit */
c9d40913
PB		 3997 } else {
3998 /* We must be in SMM; RSM will cause a vmexit anyway. */
cc3d967f 3999 }
cc3d967f
LP		 4000}
4001
09e3e2a1 4002static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
05d5a486 4003{
09e3e2a1
SC		 4004 bool smep, smap, is_user;
4005 unsigned long cr4;
e72436bc 4006
05d5a486 4007 /*
118154bd
LA		 4008 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4009 *
4010 * Errata:
4011 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4012 * possible that CPU microcode implementing DecodeAssist will fail
4013 * to read bytes of instruction which caused #NPF. In this case,
4014 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4015 * return 0 instead of the correct guest instruction bytes.
4016 *
4017 * This happens because CPU microcode reading instruction bytes
4018 * uses a special opcode which attempts to read data using CPL=0
4019 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
4020 * fault, it gives up and returns no instruction bytes.
4021 *
4022 * Detection:
4023 * We reach here in case CPU supports DecodeAssist, raised #NPF and
4024 * returned 0 in GuestIntrBytes field of the VMCB.
4025 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4026 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4027 * in case vCPU CPL==3 (Because otherwise guest would have triggered
4028 * a SMEP fault instead of #NPF).
4029 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4030 * As most guests enable SMAP if they have also enabled SMEP, use above
4031 * logic in order to attempt minimize false-positive of detecting errata
4032 * while still preserving all cases semantic correctness.
4033 *
4034 * Workaround:
4035 * To determine what instruction the guest was executing, the hypervisor
4036 * will have to decode the instruction at the instruction pointer.
05d5a486
SB		 4037 *
4038 * In non SEV guest, hypervisor will be able to read the guest
4039 * memory to decode the instruction pointer when insn_len is zero
4040 * so we return true to indicate that decoding is possible.
4041 *
4042 * But in the SEV guest, the guest memory is encrypted with the
4043 * guest specific key and hypervisor will not be able to decode the
4044 * instruction pointer so we will not able to workaround it. Lets
4045 * print the error and request to kill the guest.
4046 */
09e3e2a1
SC		 4047 if (likely(!insn || insn_len))
4048 return true;
4049
4050 /*
4051 * If RIP is invalid, go ahead with emulation which will cause an
4052 * internal error exit.
4053 */
4054 if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4055 return true;
4056
4057 cr4 = kvm_read_cr4(vcpu);
4058 smep = cr4 & X86_CR4_SMEP;
4059 smap = cr4 & X86_CR4_SMAP;
4060 is_user = svm_get_cpl(vcpu) == 3;
118154bd 4061 if (smap && (!smep || is_user)) {
05d5a486
SB		 4062 if (!sev_guest(vcpu->kvm))
4063 return true;
4064
118154bd 4065 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
05d5a486
SB		 4066 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4067 }
4068
4069 return false;
4070}
4071
4b9852f4
LA		 4072static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4073{
4074 struct vcpu_svm *svm = to_svm(vcpu);
4075
4076 /*
4077 * TODO: Last condition latch INIT signals on vCPU when
4078 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
33b22172
PB		 4079 * To properly emulate the INIT intercept,
4080 * svm_check_nested_events() should call nested_svm_vmexit()
4081 * if an INIT signal is pending.
4b9852f4
LA		 4082 */
4083 return !gif_set(svm) ||
c62e2e94 4084 (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4b9852f4
LA		 4085}
4086
eaf78265
JR		 4087static void svm_vm_destroy(struct kvm *kvm)
4088{
4089 avic_vm_destroy(kvm);
4090 sev_vm_destroy(kvm);
4091}
4092
4093static int svm_vm_init(struct kvm *kvm)
4094{
830f01b0
WL		 4095 if (!pause_filter_count || !pause_filter_thresh)
4096 kvm->arch.pause_in_guest = true;
4097
eaf78265
JR		 4098 if (avic) {
4099 int ret = avic_vm_init(kvm);
4100 if (ret)
4101 return ret;
4102 }
4103
4104 kvm_apicv_init(kvm, avic);
4105 return 0;
4106}
4107
9c14ee21 4108static struct kvm_x86_ops svm_x86_ops __initdata = {
dd58f3c9 4109 .hardware_unsetup = svm_hardware_teardown,
6aa8b732
AK		 4110 .hardware_enable = svm_hardware_enable,
4111 .hardware_disable = svm_hardware_disable,
774ead3a 4112 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
bc226f07 4113 .has_emulated_msr = svm_has_emulated_msr,
6aa8b732
AK		 4114
4115 .vcpu_create = svm_create_vcpu,
4116 .vcpu_free = svm_free_vcpu,
04d2cc77 4117 .vcpu_reset = svm_vcpu_reset,
6aa8b732 4118
562b6b08 4119 .vm_size = sizeof(struct kvm_svm),
4e19c36f 4120 .vm_init = svm_vm_init,
1654efcb 4121 .vm_destroy = svm_vm_destroy,
44a95dae 4122
04d2cc77 4123 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 4124 .vcpu_load = svm_vcpu_load,
4125 .vcpu_put = svm_vcpu_put,
8221c137
SS		 4126 .vcpu_blocking = svm_vcpu_blocking,
4127 .vcpu_unblocking = svm_vcpu_unblocking,
6aa8b732 4128
6986982f 4129 .update_exception_bitmap = update_exception_bitmap,
801e459a 4130 .get_msr_feature = svm_get_msr_feature,
6aa8b732
AK		 4131 .get_msr = svm_get_msr,
4132 .set_msr = svm_set_msr,
4133 .get_segment_base = svm_get_segment_base,
4134 .get_segment = svm_get_segment,
4135 .set_segment = svm_set_segment,
2e4d2653 4136 .get_cpl = svm_get_cpl,
1747fb71 4137 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
6aa8b732 4138 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 4139 .set_cr4 = svm_set_cr4,
4140 .set_efer = svm_set_efer,
4141 .get_idt = svm_get_idt,
4142 .set_idt = svm_set_idt,
4143 .get_gdt = svm_get_gdt,
4144 .set_gdt = svm_set_gdt,
020df079 4145 .set_dr7 = svm_set_dr7,
facb0139 4146 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
6de4f3ad 4147 .cache_reg = svm_cache_reg,
6aa8b732
AK		 4148 .get_rflags = svm_get_rflags,
4149 .set_rflags = svm_set_rflags,
be94f6b7 4150
7780938c 4151 .tlb_flush_all = svm_flush_tlb,
eeeb4f67 4152 .tlb_flush_current = svm_flush_tlb,
faff8758 4153 .tlb_flush_gva = svm_flush_tlb_gva,
72b38320 4154 .tlb_flush_guest = svm_flush_tlb,
6aa8b732 4155
6aa8b732 4156 .run = svm_vcpu_run,
04d2cc77 4157 .handle_exit = handle_exit,
6aa8b732 4158 .skip_emulated_instruction = skip_emulated_instruction,
5ef8acbd 4159 .update_emulated_instruction = NULL,
2809f5d2
GC		 4160 .set_interrupt_shadow = svm_set_interrupt_shadow,
4161 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 4162 .patch_hypercall = svm_patch_hypercall,
2a8067f1 4163 .set_irq = svm_set_irq,
95ba8273 4164 .set_nmi = svm_inject_nmi,
298101da 4165 .queue_exception = svm_queue_exception,
b463a6f7 4166 .cancel_injection = svm_cancel_injection,
78646121 4167 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 4168 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 4169 .get_nmi_mask = svm_get_nmi_mask,
4170 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 4171 .enable_nmi_window = enable_nmi_window,
4172 .enable_irq_window = enable_irq_window,
4173 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 4174 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
d62caabb 4175 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
ef8efd7a 4176 .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
2de9d0cc 4177 .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
c7c9c56c 4178 .load_eoi_exitmap = svm_load_eoi_exitmap,
44a95dae
SS		 4179 .hwapic_irr_update = svm_hwapic_irr_update,
4180 .hwapic_isr_update = svm_hwapic_isr_update,
fa59cc00 4181 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
be8ca170 4182 .apicv_post_state_restore = avic_post_state_restore,
cbc94022
IE		 4183
4184 .set_tss_addr = svm_set_tss_addr,
2ac52ab8 4185 .set_identity_map_addr = svm_set_identity_map_addr,
4b12f0de 4186 .get_mt_mask = svm_get_mt_mask,
229456fc 4187
586f9607 4188 .get_exit_info = svm_get_exit_info,
586f9607 4189
7c1b761b 4190 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4e47c7a6 4191
f5f48ee1 4192 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a 4193
326e7425 4194 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
1c97f0a0 4195
727a7e27 4196 .load_mmu_pgd = svm_load_mmu_pgd,
8a76d7f2
JR		 4197
4198 .check_intercept = svm_check_intercept,
95b5a48c 4199 .handle_exit_irqoff = svm_handle_exit_irqoff,
ae97a3b8 4200
d264ee0c
SC		 4201 .request_immediate_exit = __kvm_request_immediate_exit,
4202
ae97a3b8 4203 .sched_in = svm_sched_in,
25462f7f
WH		 4204
4205 .pmu_ops = &amd_pmu_ops,
33b22172
PB		 4206 .nested_ops = &svm_nested_ops,
4207
340d3bc3 4208 .deliver_posted_interrupt = svm_deliver_avic_intr,
17e433b5 4209 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
411b44ba 4210 .update_pi_irte = svm_update_pi_irte,
74f16909 4211 .setup_mce = svm_setup_mce,
0234bf88 4212
72d7b374 4213 .smi_allowed = svm_smi_allowed,
0234bf88
LP		 4214 .pre_enter_smm = svm_pre_enter_smm,
4215 .pre_leave_smm = svm_pre_leave_smm,
cc3d967f 4216 .enable_smi_window = enable_smi_window,
1654efcb
BS		 4217
4218 .mem_enc_op = svm_mem_enc_op,
1e80fdc0
BS		 4219 .mem_enc_reg_region = svm_register_enc_region,
4220 .mem_enc_unreg_region = svm_unregister_enc_region,
57b119da 4221
09e3e2a1 4222 .can_emulate_instruction = svm_can_emulate_instruction,
4b9852f4
LA		 4223
4224 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
6aa8b732
AK		 4225};
4226
d008dfdb
SC		 4227static struct kvm_x86_init_ops svm_init_ops __initdata = {
4228 .cpu_has_kvm_support = has_svm,
4229 .disabled_by_bios = is_disabled,
4230 .hardware_setup = svm_hardware_setup,
4231 .check_processor_compatibility = svm_check_processor_compat,
4232
4233 .runtime_ops = &svm_x86_ops,
6aa8b732
AK		 4234};
4235
4236static int __init svm_init(void)
4237{
d07f46f9
TL		 4238 __unused_size_checks();
4239
d008dfdb 4240 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
0ee75bea 4241 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 4242}
4243
4244static void __exit svm_exit(void)
4245{
cb498ea2 4246 kvm_exit();
6aa8b732
AK		 4247}
4248
4249module_init(svm_init)
4250module_exit(svm_exit)
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