]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - arch/x86/kvm/svm/svm.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
SVM: nSVM: setup nested msr permission bitmap on nested state load
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / svm / svm.c
CommitLineData
44a95dae
SS		 1#define pr_fmt(fmt) "SVM: " fmt
2
edf88417
AK		 3#include <linux/kvm_host.h>
4
85f455f7 5#include "irq.h"
1d737c8a 6#include "mmu.h"
5fdbf976 7#include "kvm_cache_regs.h"
fe4c7b19 8#include "x86.h"
66f7b72e 9#include "cpuid.h"
25462f7f 10#include "pmu.h"
e495606d 11
6aa8b732 12#include <linux/module.h>
ae759544 13#include <linux/mod_devicetable.h>
9d8f549d 14#include <linux/kernel.h>
6aa8b732
AK		 15#include <linux/vmalloc.h>
16#include <linux/highmem.h>
ef0f6496 17#include <linux/amd-iommu.h>
e8edc6e0 18#include <linux/sched.h>
af658dca 19#include <linux/trace_events.h>
5a0e3ad6 20#include <linux/slab.h>
5881f737 21#include <linux/hashtable.h>
c207aee4 22#include <linux/frame.h>
e9df0942 23#include <linux/psp-sev.h>
1654efcb 24#include <linux/file.h>
89c50580
BS		 25#include <linux/pagemap.h>
26#include <linux/swap.h>
33af3a7e 27#include <linux/rwsem.h>
6aa8b732 28
8221c137 29#include <asm/apic.h>
1018faa6 30#include <asm/perf_event.h>
67ec6607 31#include <asm/tlbflush.h>
e495606d 32#include <asm/desc.h>
facb0139 33#include <asm/debugreg.h>
631bc487 34#include <asm/kvm_para.h>
411b44ba 35#include <asm/irq_remapping.h>
1c164cb3 36#include <asm/mce.h>
28a27752 37#include <asm/spec-ctrl.h>
ba5bade4 38#include <asm/cpu_device_id.h>
6aa8b732 39
63d1142f 40#include <asm/virtext.h>
229456fc 41#include "trace.h"
63d1142f 42
883b0a91
JR		 43#include "svm.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
575b255c 50#ifdef MODULE
ae759544 51static const struct x86_cpu_id svm_cpu_id[] = {
320debe5 52 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
ae759544
JT		 53 {}
54};
55MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
575b255c 56#endif
ae759544 57
6aa8b732
AK		 58#define IOPM_ALLOC_ORDER 2
59#define MSRPM_ALLOC_ORDER 1
60
6aa8b732
AK		 61#define SEG_TYPE_LDT 2
62#define SEG_TYPE_BUSY_TSS16 3
63
6bc31bdc
AP		 64#define SVM_FEATURE_LBRV (1 << 1)
65#define SVM_FEATURE_SVML (1 << 2)
ddce97aa
AP		 66#define SVM_FEATURE_TSC_RATE (1 << 4)
67#define SVM_FEATURE_VMCB_CLEAN (1 << 5)
68#define SVM_FEATURE_FLUSH_ASID (1 << 6)
69#define SVM_FEATURE_DECODE_ASSIST (1 << 7)
6bc31bdc 70#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 71
24e09cbf
JR		 72#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
73
fbc0db76 74#define TSC_RATIO_RSVD 0xffffff0000000000ULL
92a1f12d
JR		 75#define TSC_RATIO_MIN 0x0000000000000001ULL
76#define TSC_RATIO_MAX 0x000000ffffffffffULL
fbc0db76 77
67ec6607
JR		 78static bool erratum_383_found __read_mostly;
79
883b0a91 80u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
323c3d80 81
2b036c6b
BO		 82/*
83 * Set osvw_len to higher value when updated Revision Guides
84 * are published and we know what the new status bits are
85 */
86static uint64_t osvw_len = 4, osvw_status;
87
fbc0db76
JR		 88static DEFINE_PER_CPU(u64, current_tsc_ratio);
89#define TSC_RATIO_DEFAULT 0x0100000000ULL
90
09941fbb 91static const struct svm_direct_access_msrs {
ac72a9b7
JR		 92 u32 index; /* Index of the MSR */
93 bool always; /* True if intercept is always on */
94} direct_access_msrs[] = {
8c06585d 95 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 96 { .index = MSR_IA32_SYSENTER_CS, .always = true },
97#ifdef CONFIG_X86_64
98 { .index = MSR_GS_BASE, .always = true },
99 { .index = MSR_FS_BASE, .always = true },
100 { .index = MSR_KERNEL_GS_BASE, .always = true },
101 { .index = MSR_LSTAR, .always = true },
102 { .index = MSR_CSTAR, .always = true },
103 { .index = MSR_SYSCALL_MASK, .always = true },
104#endif
b2ac58f9 105 { .index = MSR_IA32_SPEC_CTRL, .always = false },
15d45071 106 { .index = MSR_IA32_PRED_CMD, .always = false },
ac72a9b7
JR		 107 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
108 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
109 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
110 { .index = MSR_IA32_LASTINTTOIP, .always = false },
111 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 112};
113
709ddebf
JR		 114/* enable NPT for AMD64 and X86 with PAE */
115#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
883b0a91 116bool npt_enabled = true;
709ddebf 117#else
883b0a91 118bool npt_enabled;
709ddebf 119#endif
6c7dac72 120
8566ac8b
BM		 121/*
122 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
123 * pause_filter_count: On processors that support Pause filtering(indicated
124 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
125 * count value. On VMRUN this value is loaded into an internal counter.
126 * Each time a pause instruction is executed, this counter is decremented
127 * until it reaches zero at which time a #VMEXIT is generated if pause
128 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
129 * Intercept Filtering for more details.
130 * This also indicate if ple logic enabled.
131 *
132 * pause_filter_thresh: In addition, some processor families support advanced
133 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
134 * the amount of time a guest is allowed to execute in a pause loop.
135 * In this mode, a 16-bit pause filter threshold field is added in the
136 * VMCB. The threshold value is a cycle count that is used to reset the
137 * pause counter. As with simple pause filtering, VMRUN loads the pause
138 * count value from VMCB into an internal counter. Then, on each pause
139 * instruction the hardware checks the elapsed number of cycles since
140 * the most recent pause instruction against the pause filter threshold.
141 * If the elapsed cycle count is greater than the pause filter threshold,
142 * then the internal pause count is reloaded from the VMCB and execution
143 * continues. If the elapsed cycle count is less than the pause filter
144 * threshold, then the internal pause count is decremented. If the count
145 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
146 * triggered. If advanced pause filtering is supported and pause filter
147 * threshold field is set to zero, the filter will operate in the simpler,
148 * count only mode.
149 */
150
151static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
152module_param(pause_filter_thresh, ushort, 0444);
153
154static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
155module_param(pause_filter_count, ushort, 0444);
156
157/* Default doubles per-vcpu window every exit. */
158static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
159module_param(pause_filter_count_grow, ushort, 0444);
160
161/* Default resets per-vcpu window every exit to pause_filter_count. */
162static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
163module_param(pause_filter_count_shrink, ushort, 0444);
164
165/* Default is to compute the maximum so we can never overflow. */
166static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
167module_param(pause_filter_count_max, ushort, 0444);
168
e2358851
DB		 169/* allow nested paging (virtualized MMU) for all guests */
170static int npt = true;
6c7dac72 171module_param(npt, int, S_IRUGO);
e3da3acd 172
e2358851
DB		 173/* allow nested virtualization in KVM/SVM */
174static int nested = true;
236de055
AG		 175module_param(nested, int, S_IRUGO);
176
d647eb63
PB		 177/* enable/disable Next RIP Save */
178static int nrips = true;
179module_param(nrips, int, 0444);
180
89c8a498
JN		 181/* enable/disable Virtual VMLOAD VMSAVE */
182static int vls = true;
183module_param(vls, int, 0444);
184
640bd6e5
JN		 185/* enable/disable Virtual GIF */
186static int vgif = true;
187module_param(vgif, int, 0444);
5ea11f2b 188
e9df0942
BS		 189/* enable/disable SEV support */
190static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
191module_param(sev, int, 0444);
192
6f2f8453
PB		 193static bool __read_mostly dump_invalid_vmcb = 0;
194module_param(dump_invalid_vmcb, bool, 0644);
195
7607b717
BS		 196static u8 rsm_ins_bytes[] = "\x0f\xaa";
197
a5c3832d 198static void svm_complete_interrupts(struct vcpu_svm *svm);
44a95dae 199
4866d5e3 200static unsigned long iopm_base;
6aa8b732
AK		 201
202struct kvm_ldttss_desc {
203 u16 limit0;
204 u16 base0;
e0231715
JR		 205 unsigned base1:8, type:5, dpl:2, p:1;
206 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 207 u32 base3;
208 u32 zero1;
209} __attribute__((packed));
210
eaf78265 211DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
6aa8b732 212
09941fbb 213static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
6aa8b732 214
9d8f549d 215#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 216#define MSRS_RANGE_SIZE 2048
217#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
218
883b0a91 219u32 svm_msrpm_offset(u32 msr)
455716fa
JR		 220{
221 u32 offset;
222 int i;
223
224 for (i = 0; i < NUM_MSR_MAPS; i++) {
225 if (msr < msrpm_ranges[i] ||
226 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
227 continue;
228
229 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
230 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
231
232 /* Now we have the u8 offset - but need the u32 offset */
233 return offset / 4;
234 }
235
236 /* MSR not in any range */
237 return MSR_INVALID;
238}
239
6aa8b732
AK		 240#define MAX_INST_SIZE 15
241
6aa8b732
AK		 242static inline void clgi(void)
243{
ac5ffda2 244 asm volatile (__ex("clgi"));
6aa8b732
AK		 245}
246
247static inline void stgi(void)
248{
ac5ffda2 249 asm volatile (__ex("stgi"));
6aa8b732
AK		 250}
251
252static inline void invlpga(unsigned long addr, u32 asid)
253{
ac5ffda2 254 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
6aa8b732
AK		 255}
256
d468d94b 257static int get_max_npt_level(void)
4b16184c
JR		 258{
259#ifdef CONFIG_X86_64
2a7266a8 260 return PT64_ROOT_4LEVEL;
4b16184c
JR		 261#else
262 return PT32E_ROOT_LEVEL;
263#endif
264}
265
883b0a91 266void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
6aa8b732 267{
c513f484 268 struct vcpu_svm *svm = to_svm(vcpu);
6dc696d4 269 vcpu->arch.efer = efer;
9167ab79
PB		 270
271 if (!npt_enabled) {
272 /* Shadow paging assumes NX to be available. */
273 efer |= EFER_NX;
274
275 if (!(efer & EFER_LMA))
276 efer &= ~EFER_LME;
277 }
6aa8b732 278
c513f484
PB		 279 if (!(efer & EFER_SVME)) {
280 svm_leave_nested(svm);
281 svm_set_gif(svm, true);
282 }
283
284 svm->vmcb->save.efer = efer | EFER_SVME;
06e7852c 285 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
6aa8b732
AK		 286}
287
6aa8b732
AK		 288static int is_external_interrupt(u32 info)
289{
290 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
291 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
292}
293
37ccdcbe 294static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 295{
296 struct vcpu_svm *svm = to_svm(vcpu);
297 u32 ret = 0;
298
299 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
37ccdcbe
PB		 300 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
301 return ret;
2809f5d2
GC		 302}
303
304static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
305{
306 struct vcpu_svm *svm = to_svm(vcpu);
307
308 if (mask == 0)
309 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
310 else
311 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
312
313}
314
f8ea7c60 315static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
6aa8b732 316{
a2fa3e9f
GH		 317 struct vcpu_svm *svm = to_svm(vcpu);
318
d647eb63 319 if (nrips && svm->vmcb->control.next_rip != 0) {
d2922422 320 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
6bc31bdc 321 svm->next_rip = svm->vmcb->control.next_rip;
f104765b 322 }
6bc31bdc 323
1957aa63
SC		 324 if (!svm->next_rip) {
325 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
326 return 0;
327 } else {
1957aa63
SC		 328 kvm_rip_write(vcpu, svm->next_rip);
329 }
2809f5d2 330 svm_set_interrupt_shadow(vcpu, 0);
f8ea7c60 331
60fc3d02 332 return 1;
6aa8b732
AK		 333}
334
cfcd20e5 335static void svm_queue_exception(struct kvm_vcpu *vcpu)
116a4752
JK		 336{
337 struct vcpu_svm *svm = to_svm(vcpu);
cfcd20e5
WL		 338 unsigned nr = vcpu->arch.exception.nr;
339 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 340 u32 error_code = vcpu->arch.exception.error_code;
116a4752 341
da998b46
JM		 342 kvm_deliver_exception_payload(&svm->vcpu);
343
d647eb63 344 if (nr == BP_VECTOR && !nrips) {
66b7138f
JK		 345 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
346
347 /*
348 * For guest debugging where we have to reinject #BP if some
349 * INT3 is guest-owned:
350 * Emulate nRIP by moving RIP forward. Will fail if injection
351 * raises a fault that is not intercepted. Still better than
352 * failing in all cases.
353 */
f8ea7c60 354 (void)skip_emulated_instruction(&svm->vcpu);
66b7138f
JK		 355 rip = kvm_rip_read(&svm->vcpu);
356 svm->int3_rip = rip + svm->vmcb->save.cs.base;
357 svm->int3_injected = rip - old_rip;
358 }
359
116a4752
JK		 360 svm->vmcb->control.event_inj = nr
361 | SVM_EVTINJ_VALID
362 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
363 | SVM_EVTINJ_TYPE_EXEPT;
364 svm->vmcb->control.event_inj_err = error_code;
365}
366
67ec6607
JR		 367static void svm_init_erratum_383(void)
368{
369 u32 low, high;
370 int err;
371 u64 val;
372
e6ee94d5 373 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
67ec6607
JR		 374 return;
375
376 /* Use _safe variants to not break nested virtualization */
377 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
378 if (err)
379 return;
380
381 val |= (1ULL << 47);
382
383 low = lower_32_bits(val);
384 high = upper_32_bits(val);
385
386 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
387
388 erratum_383_found = true;
389}
390
2b036c6b
BO		 391static void svm_init_osvw(struct kvm_vcpu *vcpu)
392{
393 /*
394 * Guests should see errata 400 and 415 as fixed (assuming that
395 * HLT and IO instructions are intercepted).
396 */
397 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
398 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
399
400 /*
401 * By increasing VCPU's osvw.length to 3 we are telling the guest that
402 * all osvw.status bits inside that length, including bit 0 (which is
403 * reserved for erratum 298), are valid. However, if host processor's
404 * osvw_len is 0 then osvw_status[0] carries no information. We need to
405 * be conservative here and therefore we tell the guest that erratum 298
406 * is present (because we really don't know).
407 */
408 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
409 vcpu->arch.osvw.status |= 1;
410}
411
6aa8b732
AK		 412static int has_svm(void)
413{
63d1142f 414 const char *msg;
6aa8b732 415
63d1142f 416 if (!cpu_has_svm(&msg)) {
ff81ff10 417 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 418 return 0;
419 }
420
6aa8b732
AK		 421 return 1;
422}
423
13a34e06 424static void svm_hardware_disable(void)
6aa8b732 425{
fbc0db76
JR		 426 /* Make sure we clean up behind us */
427 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
428 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
429
2c8dceeb 430 cpu_svm_disable();
1018faa6
JR		 431
432 amd_pmu_disable_virt();
6aa8b732
AK		 433}
434
13a34e06 435static int svm_hardware_enable(void)
6aa8b732
AK		 436{
437
0fe1e009 438 struct svm_cpu_data *sd;
6aa8b732 439 uint64_t efer;
6aa8b732
AK		 440 struct desc_struct *gdt;
441 int me = raw_smp_processor_id();
442
10474ae8
AG		 443 rdmsrl(MSR_EFER, efer);
444 if (efer & EFER_SVME)
445 return -EBUSY;
446
6aa8b732 447 if (!has_svm()) {
1f5b77f5 448 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
10474ae8 449 return -EINVAL;
6aa8b732 450 }
0fe1e009 451 sd = per_cpu(svm_data, me);
0fe1e009 452 if (!sd) {
1f5b77f5 453 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
10474ae8 454 return -EINVAL;
6aa8b732
AK		 455 }
456
0fe1e009
TH		 457 sd->asid_generation = 1;
458 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
459 sd->next_asid = sd->max_asid + 1;
ed3cd233 460 sd->min_asid = max_sev_asid + 1;
6aa8b732 461
45fc8757 462 gdt = get_current_gdt_rw();
0fe1e009 463 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 464
9962d032 465 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 466
d0316554 467 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 468
fbc0db76
JR		 469 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
470 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
89cbc767 471 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
fbc0db76
JR		 472 }
473
2b036c6b
BO		 474
475 /*
476 * Get OSVW bits.
477 *
478 * Note that it is possible to have a system with mixed processor
479 * revisions and therefore different OSVW bits. If bits are not the same
480 * on different processors then choose the worst case (i.e. if erratum
481 * is present on one processor and not on another then assume that the
482 * erratum is present everywhere).
483 */
484 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
485 uint64_t len, status = 0;
486 int err;
487
488 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
489 if (!err)
490 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
491 &err);
492
493 if (err)
494 osvw_status = osvw_len = 0;
495 else {
496 if (len < osvw_len)
497 osvw_len = len;
498 osvw_status |= status;
499 osvw_status &= (1ULL << osvw_len) - 1;
500 }
501 } else
502 osvw_status = osvw_len = 0;
503
67ec6607
JR		 504 svm_init_erratum_383();
505
1018faa6
JR		 506 amd_pmu_enable_virt();
507
10474ae8 508 return 0;
6aa8b732
AK		 509}
510
0da1db75
JR		 511static void svm_cpu_uninit(int cpu)
512{
0fe1e009 513 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 514
0fe1e009 515 if (!sd)
0da1db75
JR		 516 return;
517
518 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
70cd94e6 519 kfree(sd->sev_vmcbs);
0fe1e009
TH		 520 __free_page(sd->save_area);
521 kfree(sd);
0da1db75
JR		 522}
523
6aa8b732
AK		 524static int svm_cpu_init(int cpu)
525{
0fe1e009 526 struct svm_cpu_data *sd;
6aa8b732 527
0fe1e009
TH		 528 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
529 if (!sd)
6aa8b732 530 return -ENOMEM;
0fe1e009 531 sd->cpu = cpu;
70cd94e6 532 sd->save_area = alloc_page(GFP_KERNEL);
0fe1e009 533 if (!sd->save_area)
d80b64ff 534 goto free_cpu_data;
6aa8b732 535
70cd94e6 536 if (svm_sev_enabled()) {
6da2ec56
KC		 537 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
538 sizeof(void *),
539 GFP_KERNEL);
70cd94e6 540 if (!sd->sev_vmcbs)
d80b64ff 541 goto free_save_area;
70cd94e6
BS		 542 }
543
0fe1e009 544 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 545
546 return 0;
547
d80b64ff
ML		 548free_save_area:
549 __free_page(sd->save_area);
550free_cpu_data:
0fe1e009 551 kfree(sd);
d80b64ff 552 return -ENOMEM;
6aa8b732
AK		 553
554}
555
ac72a9b7
JR		 556static bool valid_msr_intercept(u32 index)
557{
558 int i;
559
560 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
561 if (direct_access_msrs[i].index == index)
562 return true;
563
564 return false;
565}
566
b2ac58f9
KA		 567static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
568{
569 u8 bit_write;
570 unsigned long tmp;
571 u32 offset;
572 u32 *msrpm;
573
574 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
575 to_svm(vcpu)->msrpm;
576
577 offset = svm_msrpm_offset(msr);
578 bit_write = 2 * (msr & 0x0f) + 1;
579 tmp = msrpm[offset];
580
581 BUG_ON(offset == MSR_INVALID);
582
583 return !!test_bit(bit_write, &tmp);
584}
585
bfc733a7
RR		 586static void set_msr_interception(u32 *msrpm, unsigned msr,
587 int read, int write)
6aa8b732 588{
455716fa
JR		 589 u8 bit_read, bit_write;
590 unsigned long tmp;
591 u32 offset;
6aa8b732 592
ac72a9b7
JR		 593 /*
594 * If this warning triggers extend the direct_access_msrs list at the
595 * beginning of the file
596 */
597 WARN_ON(!valid_msr_intercept(msr));
598
455716fa
JR		 599 offset = svm_msrpm_offset(msr);
600 bit_read = 2 * (msr & 0x0f);
601 bit_write = 2 * (msr & 0x0f) + 1;
602 tmp = msrpm[offset];
603
604 BUG_ON(offset == MSR_INVALID);
605
606 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
607 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
608
609 msrpm[offset] = tmp;
6aa8b732
AK		 610}
611
f65c229c 612static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 613{
614 int i;
615
f65c229c
JR		 616 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
617
ac72a9b7
JR		 618 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
619 if (!direct_access_msrs[i].always)
620 continue;
621
622 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
623 }
f65c229c
JR		 624}
625
323c3d80
JR		 626static void add_msr_offset(u32 offset)
627{
628 int i;
629
630 for (i = 0; i < MSRPM_OFFSETS; ++i) {
631
632 /* Offset already in list? */
633 if (msrpm_offsets[i] == offset)
bfc733a7 634 return;
323c3d80
JR		 635
636 /* Slot used by another offset? */
637 if (msrpm_offsets[i] != MSR_INVALID)
638 continue;
639
640 /* Add offset to list */
641 msrpm_offsets[i] = offset;
642
643 return;
6aa8b732 644 }
323c3d80
JR		 645
646 /*
647 * If this BUG triggers the msrpm_offsets table has an overflow. Just
648 * increase MSRPM_OFFSETS in this case.
649 */
bfc733a7 650 BUG();
6aa8b732
AK		 651}
652
323c3d80 653static void init_msrpm_offsets(void)
f65c229c 654{
323c3d80 655 int i;
f65c229c 656
323c3d80
JR		 657 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
658
659 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
660 u32 offset;
661
662 offset = svm_msrpm_offset(direct_access_msrs[i].index);
663 BUG_ON(offset == MSR_INVALID);
664
665 add_msr_offset(offset);
666 }
f65c229c
JR		 667}
668
24e09cbf
JR		 669static void svm_enable_lbrv(struct vcpu_svm *svm)
670{
671 u32 *msrpm = svm->msrpm;
672
0dc92119 673 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
24e09cbf
JR		 674 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
675 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
676 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
677 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
678}
679
680static void svm_disable_lbrv(struct vcpu_svm *svm)
681{
682 u32 *msrpm = svm->msrpm;
683
0dc92119 684 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
24e09cbf
JR		 685 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
686 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
687 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
688 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
689}
690
883b0a91 691void disable_nmi_singlestep(struct vcpu_svm *svm)
4aebd0e9
LP		 692{
693 svm->nmi_singlestep = false;
640bd6e5 694
ab2f4d73
LP		 695 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
696 /* Clear our flags if they were not set by the guest */
697 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
698 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
699 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
700 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
701 }
4aebd0e9
LP		 702}
703
8566ac8b
BM		 704static void grow_ple_window(struct kvm_vcpu *vcpu)
705{
706 struct vcpu_svm *svm = to_svm(vcpu);
707 struct vmcb_control_area *control = &svm->vmcb->control;
708 int old = control->pause_filter_count;
709
710 control->pause_filter_count = __grow_ple_window(old,
711 pause_filter_count,
712 pause_filter_count_grow,
713 pause_filter_count_max);
714
4f75bcc3 715 if (control->pause_filter_count != old) {
06e7852c 716 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
4f75bcc3
PX		 717 trace_kvm_ple_window_update(vcpu->vcpu_id,
718 control->pause_filter_count, old);
719 }
8566ac8b
BM		 720}
721
722static void shrink_ple_window(struct kvm_vcpu *vcpu)
723{
724 struct vcpu_svm *svm = to_svm(vcpu);
725 struct vmcb_control_area *control = &svm->vmcb->control;
726 int old = control->pause_filter_count;
727
728 control->pause_filter_count =
729 __shrink_ple_window(old,
730 pause_filter_count,
731 pause_filter_count_shrink,
732 pause_filter_count);
4f75bcc3 733 if (control->pause_filter_count != old) {
06e7852c 734 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
4f75bcc3
PX		 735 trace_kvm_ple_window_update(vcpu->vcpu_id,
736 control->pause_filter_count, old);
737 }
8566ac8b
BM		 738}
739
52918ed5
TL		 740/*
741 * The default MMIO mask is a single bit (excluding the present bit),
742 * which could conflict with the memory encryption bit. Check for
743 * memory encryption support and override the default MMIO mask if
744 * memory encryption is enabled.
745 */
746static __init void svm_adjust_mmio_mask(void)
747{
748 unsigned int enc_bit, mask_bit;
749 u64 msr, mask;
750
751 /* If there is no memory encryption support, use existing mask */
752 if (cpuid_eax(0x80000000) < 0x8000001f)
753 return;
754
755 /* If memory encryption is not enabled, use existing mask */
756 rdmsrl(MSR_K8_SYSCFG, msr);
757 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
758 return;
759
760 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
761 mask_bit = boot_cpu_data.x86_phys_bits;
762
763 /* Increment the mask bit if it is the same as the encryption bit */
764 if (enc_bit == mask_bit)
765 mask_bit++;
766
767 /*
768 * If the mask bit location is below 52, then some bits above the
769 * physical addressing limit will always be reserved, so use the
770 * rsvd_bits() function to generate the mask. This mask, along with
771 * the present bit, will be used to generate a page fault with
772 * PFER.RSV = 1.
773 *
774 * If the mask bit location is 52 (or above), then clear the mask.
775 */
776 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
777
e7581cac 778 kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
52918ed5
TL		 779}
780
dd58f3c9
LR		 781static void svm_hardware_teardown(void)
782{
783 int cpu;
784
eaf78265
JR		 785 if (svm_sev_enabled())
786 sev_hardware_teardown();
dd58f3c9
LR		 787
788 for_each_possible_cpu(cpu)
789 svm_cpu_uninit(cpu);
790
791 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
792 iopm_base = 0;
793}
794
9b58b985
SC		 795static __init void svm_set_cpu_caps(void)
796{
797 kvm_set_cpu_caps();
798
408e9a31
PB		 799 supported_xss = 0;
800
a50718cc
SC		 801 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
802 if (nested) {
9b58b985
SC		 803 kvm_cpu_cap_set(X86_FEATURE_SVM);
804
4eb87460 805 if (nrips)
a50718cc
SC		 806 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
807
808 if (npt_enabled)
809 kvm_cpu_cap_set(X86_FEATURE_NPT);
810 }
811
93c380e7
SC		 812 /* CPUID 0x80000008 */
813 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
814 boot_cpu_has(X86_FEATURE_AMD_SSBD))
815 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
9b58b985
SC		 816}
817
6aa8b732
AK		 818static __init int svm_hardware_setup(void)
819{
820 int cpu;
821 struct page *iopm_pages;
f65c229c 822 void *iopm_va;
6aa8b732
AK		 823 int r;
824
6aa8b732
AK		 825 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
826
827 if (!iopm_pages)
828 return -ENOMEM;
c8681339
AL		 829
830 iopm_va = page_address(iopm_pages);
831 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 832 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
833
323c3d80
JR		 834 init_msrpm_offsets();
835
cfc48181
SC		 836 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
837
50a37eb4
JR		 838 if (boot_cpu_has(X86_FEATURE_NX))
839 kvm_enable_efer_bits(EFER_NX);
840
1b2fd70c
AG		 841 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
842 kvm_enable_efer_bits(EFER_FFXSR);
843
92a1f12d 844 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
92a1f12d 845 kvm_has_tsc_control = true;
bc9b961b
HZ		 846 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
847 kvm_tsc_scaling_ratio_frac_bits = 32;
92a1f12d
JR		 848 }
849
8566ac8b
BM		 850 /* Check for pause filtering support */
851 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
852 pause_filter_count = 0;
853 pause_filter_thresh = 0;
854 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
855 pause_filter_thresh = 0;
856 }
857
236de055
AG		 858 if (nested) {
859 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 860 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 861 }
862
e9df0942
BS		 863 if (sev) {
864 if (boot_cpu_has(X86_FEATURE_SEV) &&
865 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
866 r = sev_hardware_setup();
867 if (r)
868 sev = false;
869 } else {
870 sev = false;
871 }
872 }
873
52918ed5
TL		 874 svm_adjust_mmio_mask();
875
3230bb47 876 for_each_possible_cpu(cpu) {
6aa8b732
AK		 877 r = svm_cpu_init(cpu);
878 if (r)
f65c229c 879 goto err;
6aa8b732 880 }
33bd6a0b 881
2a6b20b8 882 if (!boot_cpu_has(X86_FEATURE_NPT))
e3da3acd
JR		 883 npt_enabled = false;
884
213e0e1f 885 if (npt_enabled && !npt)
6c7dac72 886 npt_enabled = false;
6c7dac72 887
83013059 888 kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
213e0e1f 889 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
e3da3acd 890
d647eb63
PB		 891 if (nrips) {
892 if (!boot_cpu_has(X86_FEATURE_NRIPS))
893 nrips = false;
894 }
895
5b8abf1f
SS		 896 if (avic) {
897 if (!npt_enabled ||
898 !boot_cpu_has(X86_FEATURE_AVIC) ||
5881f737 899 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
5b8abf1f 900 avic = false;
5881f737 901 } else {
5b8abf1f 902 pr_info("AVIC enabled\n");
5881f737 903
5881f737
SS		 904 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
905 }
5b8abf1f 906 }
44a95dae 907
89c8a498
JN		 908 if (vls) {
909 if (!npt_enabled ||
5442c269 910 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
89c8a498
JN		 911 !IS_ENABLED(CONFIG_X86_64)) {
912 vls = false;
913 } else {
914 pr_info("Virtual VMLOAD VMSAVE supported\n");
915 }
916 }
917
640bd6e5
JN		 918 if (vgif) {
919 if (!boot_cpu_has(X86_FEATURE_VGIF))
920 vgif = false;
921 else
922 pr_info("Virtual GIF supported\n");
923 }
924
9b58b985 925 svm_set_cpu_caps();
66a6950f 926
3edd6839
MG		 927 /*
928 * It seems that on AMD processors PTE's accessed bit is
929 * being set by the CPU hardware before the NPF vmexit.
930 * This is not expected behaviour and our tests fail because
931 * of it.
932 * A workaround here is to disable support for
933 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
934 * In this case userspace can know if there is support using
935 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
936 * it
937 * If future AMD CPU models change the behaviour described above,
938 * this variable can be changed accordingly
939 */
940 allow_smaller_maxphyaddr = !npt_enabled;
941
6aa8b732
AK		 942 return 0;
943
f65c229c 944err:
dd58f3c9 945 svm_hardware_teardown();
6aa8b732
AK		 946 return r;
947}
948
6aa8b732
AK		 949static void init_seg(struct vmcb_seg *seg)
950{
951 seg->selector = 0;
952 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 953 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 954 seg->limit = 0xffff;
955 seg->base = 0;
956}
957
958static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
959{
960 seg->selector = 0;
961 seg->attrib = SVM_SELECTOR_P_MASK | type;
962 seg->limit = 0xffff;
963 seg->base = 0;
964}
965
326e7425 966static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
f4e1b3c8
ZA		 967{
968 struct vcpu_svm *svm = to_svm(vcpu);
969 u64 g_tsc_offset = 0;
970
2030753d 971 if (is_guest_mode(vcpu)) {
e79f245d 972 /* Write L1's TSC offset. */
f4e1b3c8
ZA		 973 g_tsc_offset = svm->vmcb->control.tsc_offset -
974 svm->nested.hsave->control.tsc_offset;
975 svm->nested.hsave->control.tsc_offset = offset;
45c3af97
PB		 976 }
977
978 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
979 svm->vmcb->control.tsc_offset - g_tsc_offset,
980 offset);
f4e1b3c8
ZA		 981
982 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
116a0a23 983
06e7852c 984 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
326e7425 985 return svm->vmcb->control.tsc_offset;
f4e1b3c8
ZA		 986}
987
5690891b 988static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 989{
e6101a96
JR		 990 struct vmcb_control_area *control = &svm->vmcb->control;
991 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 992
4ee546b4 993 svm->vcpu.arch.hflags = 0;
bff78274 994
4ee546b4
RJ		 995 set_cr_intercept(svm, INTERCEPT_CR0_READ);
996 set_cr_intercept(svm, INTERCEPT_CR3_READ);
997 set_cr_intercept(svm, INTERCEPT_CR4_READ);
998 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
999 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1000 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
3bbf3565
SS		 1001 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1002 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
6aa8b732 1003
5315c716 1004 set_dr_intercepts(svm);
6aa8b732 1005
18c918c5
JR		 1006 set_exception_intercept(svm, PF_VECTOR);
1007 set_exception_intercept(svm, UD_VECTOR);
1008 set_exception_intercept(svm, MC_VECTOR);
54a20552 1009 set_exception_intercept(svm, AC_VECTOR);
cbdb967a 1010 set_exception_intercept(svm, DB_VECTOR);
9718420e
LA		 1011 /*
1012 * Guest access to VMware backdoor ports could legitimately
1013 * trigger #GP because of TSS I/O permission bitmap.
1014 * We intercept those #GP and allow access to them anyway
1015 * as VMware does.
1016 */
1017 if (enable_vmware_backdoor)
1018 set_exception_intercept(svm, GP_VECTOR);
6aa8b732 1019
a284ba56
JR		 1020 svm_set_intercept(svm, INTERCEPT_INTR);
1021 svm_set_intercept(svm, INTERCEPT_NMI);
1022 svm_set_intercept(svm, INTERCEPT_SMI);
1023 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1024 svm_set_intercept(svm, INTERCEPT_RDPMC);
1025 svm_set_intercept(svm, INTERCEPT_CPUID);
1026 svm_set_intercept(svm, INTERCEPT_INVD);
1027 svm_set_intercept(svm, INTERCEPT_INVLPG);
1028 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1029 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1030 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1031 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1032 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1033 svm_set_intercept(svm, INTERCEPT_VMRUN);
1034 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1035 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1036 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1037 svm_set_intercept(svm, INTERCEPT_STGI);
1038 svm_set_intercept(svm, INTERCEPT_CLGI);
1039 svm_set_intercept(svm, INTERCEPT_SKINIT);
1040 svm_set_intercept(svm, INTERCEPT_WBINVD);
1041 svm_set_intercept(svm, INTERCEPT_XSETBV);
1042 svm_set_intercept(svm, INTERCEPT_RDPRU);
1043 svm_set_intercept(svm, INTERCEPT_RSM);
6aa8b732 1044
4d5422ce 1045 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
a284ba56
JR		 1046 svm_set_intercept(svm, INTERCEPT_MONITOR);
1047 svm_set_intercept(svm, INTERCEPT_MWAIT);
668fffa3
MT		 1048 }
1049
caa057a2 1050 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
a284ba56 1051 svm_set_intercept(svm, INTERCEPT_HLT);
caa057a2 1052
d0ec49d4
TL		 1053 control->iopm_base_pa = __sme_set(iopm_base);
1054 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
6aa8b732
AK		 1055 control->int_ctl = V_INTR_MASKING_MASK;
1056
1057 init_seg(&save->es);
1058 init_seg(&save->ss);
1059 init_seg(&save->ds);
1060 init_seg(&save->fs);
1061 init_seg(&save->gs);
1062
1063 save->cs.selector = 0xf000;
04b66839 1064 save->cs.base = 0xffff0000;
6aa8b732
AK		 1065 /* Executable/Readable Code Segment */
1066 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1067 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1068 save->cs.limit = 0xffff;
6aa8b732
AK		 1069
1070 save->gdtr.limit = 0xffff;
1071 save->idtr.limit = 0xffff;
1072
1073 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1074 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1075
5690891b 1076 svm_set_efer(&svm->vcpu, 0);
d77c26fc 1077 save->dr6 = 0xffff0ff0;
f6e78475 1078 kvm_set_rflags(&svm->vcpu, 2);
6aa8b732 1079 save->rip = 0x0000fff0;
5fdbf976 1080 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 1081
e0231715 1082 /*
18fa000a 1083 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
d28bc9dd 1084 * It also updates the guest-visible cr0 value.
6aa8b732 1085 */
79a8059d 1086 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
ebae871a 1087 kvm_mmu_reset_context(&svm->vcpu);
18fa000a 1088
66aee91a 1089 save->cr4 = X86_CR4_PAE;
6aa8b732 1090 /* rdx = ?? */
709ddebf
JR		 1091
1092 if (npt_enabled) {
1093 /* Setup VMCB for Nested Paging */
cea3a19b 1094 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
a284ba56 1095 svm_clr_intercept(svm, INTERCEPT_INVLPG);
18c918c5 1096 clr_exception_intercept(svm, PF_VECTOR);
4ee546b4
RJ		 1097 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1098 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
74545705 1099 save->g_pat = svm->vcpu.arch.pat;
709ddebf
JR		 1100 save->cr3 = 0;
1101 save->cr4 = 0;
1102 }
f40f6a45 1103 svm->asid_generation = 0;
1371d904 1104
e6aa9abd 1105 svm->nested.vmcb = 0;
2af9194d
JR		 1106 svm->vcpu.arch.hflags = 0;
1107
830f01b0 1108 if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
8566ac8b
BM		 1109 control->pause_filter_count = pause_filter_count;
1110 if (pause_filter_thresh)
1111 control->pause_filter_thresh = pause_filter_thresh;
a284ba56 1112 svm_set_intercept(svm, INTERCEPT_PAUSE);
8566ac8b 1113 } else {
a284ba56 1114 svm_clr_intercept(svm, INTERCEPT_PAUSE);
565d0998
ML		 1115 }
1116
67034bb9 1117 if (kvm_vcpu_apicv_active(&svm->vcpu))
44a95dae
SS		 1118 avic_init_vmcb(svm);
1119
89c8a498
JN		 1120 /*
1121 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1122 * in VMCB and clear intercepts to avoid #VMEXIT.
1123 */
1124 if (vls) {
a284ba56
JR		 1125 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1126 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
89c8a498
JN		 1127 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1128 }
1129
640bd6e5 1130 if (vgif) {
a284ba56
JR		 1131 svm_clr_intercept(svm, INTERCEPT_STGI);
1132 svm_clr_intercept(svm, INTERCEPT_CLGI);
640bd6e5
JN		 1133 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1134 }
1135
35c6f649 1136 if (sev_guest(svm->vcpu.kvm)) {
1654efcb 1137 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
35c6f649
BS		 1138 clr_exception_intercept(svm, UD_VECTOR);
1139 }
1654efcb 1140
06e7852c 1141 vmcb_mark_all_dirty(svm->vmcb);
8d28fec4 1142
2af9194d 1143 enable_gif(svm);
44a95dae
SS		 1144
1145}
1146
d28bc9dd 1147static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
04d2cc77
AK		 1148{
1149 struct vcpu_svm *svm = to_svm(vcpu);
66f7b72e
JS		 1150 u32 dummy;
1151 u32 eax = 1;
04d2cc77 1152
b2ac58f9 1153 svm->spec_ctrl = 0;
ccbcd267 1154 svm->virt_spec_ctrl = 0;
b2ac58f9 1155
d28bc9dd
NA		 1156 if (!init_event) {
1157 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1158 MSR_IA32_APICBASE_ENABLE;
1159 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1160 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1161 }
5690891b 1162 init_vmcb(svm);
70433389 1163
f91af517 1164 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
de3cd117 1165 kvm_rdx_write(vcpu, eax);
44a95dae
SS		 1166
1167 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1168 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
04d2cc77
AK		 1169}
1170
987b2594 1171static int svm_create_vcpu(struct kvm_vcpu *vcpu)
6aa8b732 1172{
a2fa3e9f 1173 struct vcpu_svm *svm;
6aa8b732 1174 struct page *page;
f65c229c 1175 struct page *msrpm_pages;
b286d5d8 1176 struct page *hsave_page;
3d6368ef 1177 struct page *nested_msrpm_pages;
fb3f0f51 1178 int err;
6aa8b732 1179
a9dd6f09
SC		 1180 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1181 svm = to_svm(vcpu);
fb3f0f51 1182
b7af4043 1183 err = -ENOMEM;
1ec69647 1184 page = alloc_page(GFP_KERNEL_ACCOUNT);
b7af4043 1185 if (!page)
987b2594 1186 goto out;
6aa8b732 1187
1ec69647 1188 msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
f65c229c 1189 if (!msrpm_pages)
b7af4043 1190 goto free_page1;
3d6368ef 1191
1ec69647 1192 nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
3d6368ef 1193 if (!nested_msrpm_pages)
b7af4043 1194 goto free_page2;
f65c229c 1195
1ec69647 1196 hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
b286d5d8 1197 if (!hsave_page)
b7af4043
TY		 1198 goto free_page3;
1199
dfa20099
SS		 1200 err = avic_init_vcpu(svm);
1201 if (err)
1202 goto free_page4;
44a95dae 1203
8221c137
SS		 1204 /* We initialize this flag to true to make sure that the is_running
1205 * bit would be set the first time the vcpu is loaded.
1206 */
6c3e4422
SS		 1207 if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1208 svm->avic_is_running = true;
8221c137 1209
e6aa9abd 1210 svm->nested.hsave = page_address(hsave_page);
cc440cda 1211 clear_page(svm->nested.hsave);
b286d5d8 1212
b7af4043
TY		 1213 svm->msrpm = page_address(msrpm_pages);
1214 svm_vcpu_init_msrpm(svm->msrpm);
1215
e6aa9abd 1216 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 1217 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 1218
a2fa3e9f
GH		 1219 svm->vmcb = page_address(page);
1220 clear_page(svm->vmcb);
d0ec49d4 1221 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
a2fa3e9f 1222 svm->asid_generation = 0;
5690891b 1223 init_vmcb(svm);
6aa8b732 1224
7f27179a 1225 svm_init_osvw(vcpu);
bab0c318 1226 vcpu->arch.microcode_version = 0x01000065;
2b036c6b 1227
a9dd6f09 1228 return 0;
36241b8c 1229
44a95dae
SS		 1230free_page4:
1231 __free_page(hsave_page);
b7af4043
TY		 1232free_page3:
1233 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1234free_page2:
1235 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1236free_page1:
1237 __free_page(page);
987b2594 1238out:
a9dd6f09 1239 return err;
6aa8b732
AK		 1240}
1241
fd65d314
JM		 1242static void svm_clear_current_vmcb(struct vmcb *vmcb)
1243{
1244 int i;
1245
1246 for_each_online_cpu(i)
1247 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1248}
1249
6aa8b732
AK		 1250static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1251{
a2fa3e9f
GH		 1252 struct vcpu_svm *svm = to_svm(vcpu);
1253
fd65d314
JM		 1254 /*
1255 * The vmcb page can be recycled, causing a false negative in
1256 * svm_vcpu_load(). So, ensure that no logical CPU has this
1257 * vmcb page recorded as its current vmcb.
1258 */
1259 svm_clear_current_vmcb(svm->vmcb);
1260
d0ec49d4 1261 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
f65c229c 1262 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 1263 __free_page(virt_to_page(svm->nested.hsave));
1264 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
6aa8b732
AK		 1265}
1266
15ad7146 1267static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1268{
a2fa3e9f 1269 struct vcpu_svm *svm = to_svm(vcpu);
15d45071 1270 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
15ad7146 1271 int i;
0cc5064d 1272
0cc5064d 1273 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 1274 svm->asid_generation = 0;
06e7852c 1275 vmcb_mark_all_dirty(svm->vmcb);
0cc5064d 1276 }
94dfbdb3 1277
82ca2d10
AK		 1278#ifdef CONFIG_X86_64
1279 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1280#endif
dacccfdd
AK		 1281 savesegment(fs, svm->host.fs);
1282 savesegment(gs, svm->host.gs);
1283 svm->host.ldt = kvm_read_ldt();
1284
94dfbdb3 1285 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1286 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
fbc0db76 1287
ad721883
HZ		 1288 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1289 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1290 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1291 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1292 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1293 }
fbc0db76 1294 }
46896c73
PB		 1295 /* This assumes that the kernel never uses MSR_TSC_AUX */
1296 if (static_cpu_has(X86_FEATURE_RDTSCP))
1297 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
8221c137 1298
15d45071
AR		 1299 if (sd->current_vmcb != svm->vmcb) {
1300 sd->current_vmcb = svm->vmcb;
1301 indirect_branch_prediction_barrier();
1302 }
8221c137 1303 avic_vcpu_load(vcpu, cpu);
6aa8b732
AK		 1304}
1305
1306static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1307{
a2fa3e9f 1308 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 1309 int i;
1310
8221c137
SS		 1311 avic_vcpu_put(vcpu);
1312
e1beb1d3 1313 ++vcpu->stat.host_state_reload;
dacccfdd
AK		 1314 kvm_load_ldt(svm->host.ldt);
1315#ifdef CONFIG_X86_64
1316 loadsegment(fs, svm->host.fs);
296f781a 1317 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
893a5ab6 1318 load_gs_index(svm->host.gs);
dacccfdd 1319#else
831ca609 1320#ifdef CONFIG_X86_32_LAZY_GS
dacccfdd 1321 loadsegment(gs, svm->host.gs);
831ca609 1322#endif
dacccfdd 1323#endif
94dfbdb3 1324 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1325 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1326}
1327
6aa8b732
AK		 1328static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1329{
9b611747
LP		 1330 struct vcpu_svm *svm = to_svm(vcpu);
1331 unsigned long rflags = svm->vmcb->save.rflags;
1332
1333 if (svm->nmi_singlestep) {
1334 /* Hide our flags if they were not set by the guest */
1335 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1336 rflags &= ~X86_EFLAGS_TF;
1337 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1338 rflags &= ~X86_EFLAGS_RF;
1339 }
1340 return rflags;
6aa8b732
AK		 1341}
1342
1343static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1344{
9b611747
LP		 1345 if (to_svm(vcpu)->nmi_singlestep)
1346 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1347
ae9fedc7 1348 /*
bb3541f1 1349 * Any change of EFLAGS.VM is accompanied by a reload of SS
ae9fedc7
PB		 1350 * (caused by either a task switch or an inter-privilege IRET),
1351 * so we do not need to update the CPL here.
1352 */
a2fa3e9f 1353 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1354}
1355
6de4f3ad
AK		 1356static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1357{
1358 switch (reg) {
1359 case VCPU_EXREG_PDPTR:
1360 BUG_ON(!npt_enabled);
9f8fe504 1361 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6de4f3ad
AK		 1362 break;
1363 default:
34059c25 1364 WARN_ON_ONCE(1);
6de4f3ad
AK		 1365 }
1366}
1367
e14b7786 1368static void svm_set_vintr(struct vcpu_svm *svm)
64b5bd27
PB		 1369{
1370 struct vmcb_control_area *control;
1371
1372 /* The following fields are ignored when AVIC is enabled */
1373 WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
a284ba56 1374 svm_set_intercept(svm, INTERCEPT_VINTR);
64b5bd27
PB		 1375
1376 /*
1377 * This is just a dummy VINTR to actually cause a vmexit to happen.
1378 * Actual injection of virtual interrupts happens through EVENTINJ.
1379 */
1380 control = &svm->vmcb->control;
1381 control->int_vector = 0x0;
1382 control->int_ctl &= ~V_INTR_PRIO_MASK;
1383 control->int_ctl |= V_IRQ_MASK |
1384 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
06e7852c 1385 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
64b5bd27
PB		 1386}
1387
f0b85051
AG		 1388static void svm_clear_vintr(struct vcpu_svm *svm)
1389{
d8e4e58f 1390 const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
a284ba56 1391 svm_clr_intercept(svm, INTERCEPT_VINTR);
64b5bd27 1392
d8e4e58f
PB		 1393 /* Drop int_ctl fields related to VINTR injection. */
1394 svm->vmcb->control.int_ctl &= mask;
1395 if (is_guest_mode(&svm->vcpu)) {
fb7333df
PB		 1396 svm->nested.hsave->control.int_ctl &= mask;
1397
d8e4e58f
PB		 1398 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1399 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1400 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1401 }
1402
06e7852c 1403 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
f0b85051
AG		 1404}
1405
6aa8b732
AK		 1406static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1407{
a2fa3e9f 1408 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1409
1410 switch (seg) {
1411 case VCPU_SREG_CS: return &save->cs;
1412 case VCPU_SREG_DS: return &save->ds;
1413 case VCPU_SREG_ES: return &save->es;
1414 case VCPU_SREG_FS: return &save->fs;
1415 case VCPU_SREG_GS: return &save->gs;
1416 case VCPU_SREG_SS: return &save->ss;
1417 case VCPU_SREG_TR: return &save->tr;
1418 case VCPU_SREG_LDTR: return &save->ldtr;
1419 }
1420 BUG();
8b6d44c7 1421 return NULL;
6aa8b732
AK		 1422}
1423
1424static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1425{
1426 struct vmcb_seg *s = svm_seg(vcpu, seg);
1427
1428 return s->base;
1429}
1430
1431static void svm_get_segment(struct kvm_vcpu *vcpu,
1432 struct kvm_segment *var, int seg)
1433{
1434 struct vmcb_seg *s = svm_seg(vcpu, seg);
1435
1436 var->base = s->base;
1437 var->limit = s->limit;
1438 var->selector = s->selector;
1439 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1440 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1441 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1442 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1443 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1444 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1445 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
80112c89
JM		 1446
1447 /*
1448 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1449 * However, the SVM spec states that the G bit is not observed by the
1450 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1451 * So let's synthesize a legal G bit for all segments, this helps
1452 * running KVM nested. It also helps cross-vendor migration, because
1453 * Intel's vmentry has a check on the 'G' bit.
1454 */
1455 var->g = s->limit > 0xfffff;
25022acc 1456
e0231715
JR		 1457 /*
1458 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1459 * for cross vendor migration purposes by "not present"
1460 */
8eae9570 1461 var->unusable = !var->present;
19bca6ab 1462
1fbdc7a5 1463 switch (seg) {
1fbdc7a5
AP		 1464 case VCPU_SREG_TR:
1465 /*
1466 * Work around a bug where the busy flag in the tr selector
1467 * isn't exposed
1468 */
c0d09828 1469 var->type |= 0x2;
1fbdc7a5
AP		 1470 break;
1471 case VCPU_SREG_DS:
1472 case VCPU_SREG_ES:
1473 case VCPU_SREG_FS:
1474 case VCPU_SREG_GS:
1475 /*
1476 * The accessed bit must always be set in the segment
1477 * descriptor cache, although it can be cleared in the
1478 * descriptor, the cached bit always remains at 1. Since
1479 * Intel has a check on this, set it here to support
1480 * cross-vendor migration.
1481 */
1482 if (!var->unusable)
1483 var->type |= 0x1;
1484 break;
b586eb02 1485 case VCPU_SREG_SS:
e0231715
JR		 1486 /*
1487 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1488 * descriptor is left as 1, although the whole segment has
1489 * been made unusable. Clear it here to pass an Intel VMX
1490 * entry check when cross vendor migrating.
1491 */
1492 if (var->unusable)
1493 var->db = 0;
d9c1b543 1494 /* This is symmetric with svm_set_segment() */
33b458d2 1495 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
b586eb02 1496 break;
1fbdc7a5 1497 }
6aa8b732
AK		 1498}
1499
2e4d2653
IE		 1500static int svm_get_cpl(struct kvm_vcpu *vcpu)
1501{
1502 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1503
1504 return save->cpl;
1505}
1506
89a27f4d 1507static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1508{
a2fa3e9f
GH		 1509 struct vcpu_svm *svm = to_svm(vcpu);
1510
89a27f4d
GN		 1511 dt->size = svm->vmcb->save.idtr.limit;
1512 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1513}
1514
89a27f4d 1515static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1516{
a2fa3e9f
GH		 1517 struct vcpu_svm *svm = to_svm(vcpu);
1518
89a27f4d
GN		 1519 svm->vmcb->save.idtr.limit = dt->size;
1520 svm->vmcb->save.idtr.base = dt->address ;
06e7852c 1521 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1522}
1523
89a27f4d 1524static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1525{
a2fa3e9f
GH		 1526 struct vcpu_svm *svm = to_svm(vcpu);
1527
89a27f4d
GN		 1528 dt->size = svm->vmcb->save.gdtr.limit;
1529 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1530}
1531
89a27f4d 1532static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1533{
a2fa3e9f
GH		 1534 struct vcpu_svm *svm = to_svm(vcpu);
1535
89a27f4d
GN		 1536 svm->vmcb->save.gdtr.limit = dt->size;
1537 svm->vmcb->save.gdtr.base = dt->address ;
06e7852c 1538 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1539}
1540
d225157b
AK		 1541static void update_cr0_intercept(struct vcpu_svm *svm)
1542{
1543 ulong gcr0 = svm->vcpu.arch.cr0;
1544 u64 *hcr0 = &svm->vmcb->save.cr0;
1545
bd7e5b08
PB		 1546 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1547 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
d225157b 1548
06e7852c 1549 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
d225157b 1550
bd7e5b08 1551 if (gcr0 == *hcr0) {
4ee546b4
RJ		 1552 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1553 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b 1554 } else {
4ee546b4
RJ		 1555 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1556 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b
AK		 1557 }
1558}
1559
883b0a91 1560void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 1561{
a2fa3e9f
GH		 1562 struct vcpu_svm *svm = to_svm(vcpu);
1563
05b3e0c2 1564#ifdef CONFIG_X86_64
f6801dff 1565 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1566 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1567 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1568 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1569 }
1570
d77c26fc 1571 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1572 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1573 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1574 }
1575 }
1576#endif
ad312c7c 1577 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1578
1579 if (!npt_enabled)
1580 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21 1581
bcf166a9
PB		 1582 /*
1583 * re-enable caching here because the QEMU bios
1584 * does not do it - this results in some delay at
1585 * reboot
1586 */
1587 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1588 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1589 svm->vmcb->save.cr0 = cr0;
06e7852c 1590 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
d225157b 1591 update_cr0_intercept(svm);
6aa8b732
AK		 1592}
1593
883b0a91 1594int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 1595{
1e02ce4c 1596 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
e5eab0ce
JR		 1597 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1598
5e1746d6
NHE		 1599 if (cr4 & X86_CR4_VMXE)
1600 return 1;
1601
e5eab0ce 1602 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
f55ac304 1603 svm_flush_tlb(vcpu);
6394b649 1604
ec077263
JR		 1605 vcpu->arch.cr4 = cr4;
1606 if (!npt_enabled)
1607 cr4 |= X86_CR4_PAE;
6394b649 1608 cr4 |= host_cr4_mce;
ec077263 1609 to_svm(vcpu)->vmcb->save.cr4 = cr4;
06e7852c 1610 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
5e1746d6 1611 return 0;
6aa8b732
AK		 1612}
1613
1614static void svm_set_segment(struct kvm_vcpu *vcpu,
1615 struct kvm_segment *var, int seg)
1616{
a2fa3e9f 1617 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1618 struct vmcb_seg *s = svm_seg(vcpu, seg);
1619
1620 s->base = var->base;
1621 s->limit = var->limit;
1622 s->selector = var->selector;
d9c1b543
RP		 1623 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1624 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1625 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1626 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1627 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1628 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1629 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1630 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
ae9fedc7
PB		 1631
1632 /*
1633 * This is always accurate, except if SYSRET returned to a segment
1634 * with SS.DPL != 3. Intel does not have this quirk, and always
1635 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1636 * would entail passing the CPL to userspace and back.
1637 */
1638 if (seg == VCPU_SREG_SS)
d9c1b543
RP		 1639 /* This is symmetric with svm_get_segment() */
1640 svm->vmcb->save.cpl = (var->dpl & 3);
6aa8b732 1641
06e7852c 1642 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
6aa8b732
AK		 1643}
1644
6986982f 1645static void update_exception_bitmap(struct kvm_vcpu *vcpu)
6aa8b732 1646{
d0bfb940
JK		 1647 struct vcpu_svm *svm = to_svm(vcpu);
1648
18c918c5 1649 clr_exception_intercept(svm, BP_VECTOR);
44c11430 1650
d0bfb940 1651 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
d0bfb940 1652 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
18c918c5 1653 set_exception_intercept(svm, BP_VECTOR);
6986982f 1654 }
44c11430
GN		 1655}
1656
0fe1e009 1657static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1658{
0fe1e009
TH		 1659 if (sd->next_asid > sd->max_asid) {
1660 ++sd->asid_generation;
4faefff3 1661 sd->next_asid = sd->min_asid;
a2fa3e9f 1662 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1663 }
1664
0fe1e009
TH		 1665 svm->asid_generation = sd->asid_generation;
1666 svm->vmcb->control.asid = sd->next_asid++;
d48086d1 1667
06e7852c 1668 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
6aa8b732
AK		 1669}
1670
d67668e9 1671static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
73aaf249 1672{
d67668e9 1673 struct vmcb *vmcb = svm->vmcb;
73aaf249 1674
d67668e9
PB		 1675 if (unlikely(value != vmcb->save.dr6)) {
1676 vmcb->save.dr6 = value;
06e7852c 1677 vmcb_mark_dirty(vmcb, VMCB_DR);
d67668e9 1678 }
73aaf249
JK		 1679}
1680
facb0139
PB		 1681static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1682{
1683 struct vcpu_svm *svm = to_svm(vcpu);
1684
1685 get_debugreg(vcpu->arch.db[0], 0);
1686 get_debugreg(vcpu->arch.db[1], 1);
1687 get_debugreg(vcpu->arch.db[2], 2);
1688 get_debugreg(vcpu->arch.db[3], 3);
d67668e9
PB		 1689 /*
1690 * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1691 * because db_interception might need it. We can do it before vmentry.
1692 */
5679b803 1693 vcpu->arch.dr6 = svm->vmcb->save.dr6;
facb0139 1694 vcpu->arch.dr7 = svm->vmcb->save.dr7;
facb0139
PB		 1695 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1696 set_dr_intercepts(svm);
1697}
1698
020df079 1699static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1700{
42dbaa5a 1701 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1702
020df079 1703 svm->vmcb->save.dr7 = value;
06e7852c 1704 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
6aa8b732
AK		 1705}
1706
851ba692 1707static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1708{
0ede79e1 1709 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1261bfa3 1710 u64 error_code = svm->vmcb->control.exit_info_1;
6aa8b732 1711
1261bfa3 1712 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
00b10fe1
BS		 1713 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1714 svm->vmcb->control.insn_bytes : NULL,
d0006530
PB		 1715 svm->vmcb->control.insn_len);
1716}
1717
1718static int npf_interception(struct vcpu_svm *svm)
1719{
0ede79e1 1720 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
d0006530
PB		 1721 u64 error_code = svm->vmcb->control.exit_info_1;
1722
1723 trace_kvm_page_fault(fault_address, error_code);
1724 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
00b10fe1
BS		 1725 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1726 svm->vmcb->control.insn_bytes : NULL,
d0006530 1727 svm->vmcb->control.insn_len);
6aa8b732
AK		 1728}
1729
851ba692 1730static int db_interception(struct vcpu_svm *svm)
d0bfb940 1731{
851ba692 1732 struct kvm_run *kvm_run = svm->vcpu.run;
99c22179 1733 struct kvm_vcpu *vcpu = &svm->vcpu;
851ba692 1734
d0bfb940 1735 if (!(svm->vcpu.guest_debug &
44c11430 1736 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1737 !svm->nmi_singlestep) {
d67668e9
PB		 1738 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1739 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
d0bfb940
JK		 1740 return 1;
1741 }
44c11430 1742
6be7d306 1743 if (svm->nmi_singlestep) {
4aebd0e9 1744 disable_nmi_singlestep(svm);
99c22179
VK		 1745 /* Make sure we check for pending NMIs upon entry */
1746 kvm_make_request(KVM_REQ_EVENT, vcpu);
44c11430
GN		 1747 }
1748
1749 if (svm->vcpu.guest_debug &
e0231715 1750 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430 1751 kvm_run->exit_reason = KVM_EXIT_DEBUG;
dee919d1
PB		 1752 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1753 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
44c11430
GN		 1754 kvm_run->debug.arch.pc =
1755 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1756 kvm_run->debug.arch.exception = DB_VECTOR;
1757 return 0;
1758 }
1759
1760 return 1;
d0bfb940
JK		 1761}
1762
851ba692 1763static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1764{
851ba692
AK		 1765 struct kvm_run *kvm_run = svm->vcpu.run;
1766
d0bfb940
JK		 1767 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1768 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1769 kvm_run->debug.arch.exception = BP_VECTOR;
1770 return 0;
1771}
1772
851ba692 1773static int ud_interception(struct vcpu_svm *svm)
7aa81cc0 1774{
082d06ed 1775 return handle_ud(&svm->vcpu);
7aa81cc0
AL		 1776}
1777
54a20552
EN		 1778static int ac_interception(struct vcpu_svm *svm)
1779{
1780 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1781 return 1;
1782}
1783
9718420e
LA		 1784static int gp_interception(struct vcpu_svm *svm)
1785{
1786 struct kvm_vcpu *vcpu = &svm->vcpu;
1787 u32 error_code = svm->vmcb->control.exit_info_1;
9718420e
LA		 1788
1789 WARN_ON_ONCE(!enable_vmware_backdoor);
1790
a6c6ed1e
SC		 1791 /*
1792 * VMware backdoor emulation on #GP interception only handles IN{S},
1793 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1794 */
1795 if (error_code) {
1796 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1797 return 1;
1798 }
60fc3d02 1799 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
9718420e
LA		 1800}
1801
67ec6607
JR		 1802static bool is_erratum_383(void)
1803{
1804 int err, i;
1805 u64 value;
1806
1807 if (!erratum_383_found)
1808 return false;
1809
1810 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1811 if (err)
1812 return false;
1813
1814 /* Bit 62 may or may not be set for this mce */
1815 value &= ~(1ULL << 62);
1816
1817 if (value != 0xb600000000010015ULL)
1818 return false;
1819
1820 /* Clear MCi_STATUS registers */
1821 for (i = 0; i < 6; ++i)
1822 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1823
1824 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1825 if (!err) {
1826 u32 low, high;
1827
1828 value &= ~(1ULL << 2);
1829 low = lower_32_bits(value);
1830 high = upper_32_bits(value);
1831
1832 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1833 }
1834
1835 /* Flush tlb to evict multi-match entries */
1836 __flush_tlb_all();
1837
1838 return true;
1839}
1840
1c164cb3
UB		 1841/*
1842 * Trigger machine check on the host. We assume all the MSRs are already set up
1843 * by the CPU and that we still run on the same CPU as the MCE occurred on.
1844 * We pass a fake environment to the machine check handler because we want
1845 * the guest to be always treated like user space, no matter what context
1846 * it used internally.
1847 */
1848static void kvm_machine_check(void)
1849{
1850#if defined(CONFIG_X86_MCE)
1851 struct pt_regs regs = {
1852 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
1853 .flags = X86_EFLAGS_IF,
1854 };
1855
8cd501c1 1856 do_machine_check(&regs);
1c164cb3
UB		 1857#endif
1858}
1859
fe5913e4 1860static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1861{
67ec6607
JR		 1862 if (is_erratum_383()) {
1863 /*
1864 * Erratum 383 triggered. Guest state is corrupt so kill the
1865 * guest.
1866 */
1867 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1868
a8eeb04a 1869 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1870
1871 return;
1872 }
1873
53371b50
JR		 1874 /*
1875 * On an #MC intercept the MCE handler is not called automatically in
1876 * the host. So do it by hand here.
1877 */
1c164cb3 1878 kvm_machine_check();
fe5913e4
JR		 1879}
1880
1881static int mc_interception(struct vcpu_svm *svm)
1882{
53371b50
JR		 1883 return 1;
1884}
1885
851ba692 1886static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1887{
851ba692
AK		 1888 struct kvm_run *kvm_run = svm->vcpu.run;
1889
46fe4ddd
JR		 1890 /*
1891 * VMCB is undefined after a SHUTDOWN intercept
1892 * so reinitialize it.
1893 */
a2fa3e9f 1894 clear_page(svm->vmcb);
5690891b 1895 init_vmcb(svm);
46fe4ddd
JR		 1896
1897 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1898 return 0;
1899}
1900
851ba692 1901static int io_interception(struct vcpu_svm *svm)
6aa8b732 1902{
cf8f70bf 1903 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1904 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
dca7f128 1905 int size, in, string;
039576c0 1906 unsigned port;
6aa8b732 1907
e756fc62 1908 ++svm->vcpu.stat.io_exits;
e70669ab 1909 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1910 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
8370c3d0 1911 if (string)
60fc3d02 1912 return kvm_emulate_instruction(vcpu, 0);
cf8f70bf 1913
039576c0
AK		 1914 port = io_info >> 16;
1915 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1916 svm->next_rip = svm->vmcb->control.exit_info_2;
cf8f70bf 1917
dca7f128 1918 return kvm_fast_pio(&svm->vcpu, size, port, in);
6aa8b732
AK		 1919}
1920
851ba692 1921static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1922{
1923 return 1;
1924}
1925
851ba692 1926static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1927{
1928 ++svm->vcpu.stat.irq_exits;
1929 return 1;
1930}
1931
851ba692 1932static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1933{
1934 return 1;
1935}
1936
851ba692 1937static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1938{
e756fc62 1939 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1940}
1941
851ba692 1942static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1943{
0d9c055e 1944 return kvm_emulate_hypercall(&svm->vcpu);
02e235bc
AK		 1945}
1946
851ba692 1947static int vmload_interception(struct vcpu_svm *svm)
5542675b 1948{
9966bf68 1949 struct vmcb *nested_vmcb;
8c5fbf1a 1950 struct kvm_host_map map;
b742c1e6 1951 int ret;
9966bf68 1952
5542675b
AG		 1953 if (nested_svm_check_permissions(svm))
1954 return 1;
1955
8c5fbf1a
KA		 1956 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1957 if (ret) {
1958 if (ret == -EINVAL)
1959 kvm_inject_gp(&svm->vcpu, 0);
9966bf68 1960 return 1;
8c5fbf1a
KA		 1961 }
1962
1963 nested_vmcb = map.hva;
9966bf68 1964
b742c1e6 1965 ret = kvm_skip_emulated_instruction(&svm->vcpu);
e3e9ed3d 1966
9966bf68 1967 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
8c5fbf1a 1968 kvm_vcpu_unmap(&svm->vcpu, &map, true);
5542675b 1969
b742c1e6 1970 return ret;
5542675b
AG		 1971}
1972
851ba692 1973static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1974{
9966bf68 1975 struct vmcb *nested_vmcb;
8c5fbf1a 1976 struct kvm_host_map map;
b742c1e6 1977 int ret;
9966bf68 1978
5542675b
AG		 1979 if (nested_svm_check_permissions(svm))
1980 return 1;
1981
8c5fbf1a
KA		 1982 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1983 if (ret) {
1984 if (ret == -EINVAL)
1985 kvm_inject_gp(&svm->vcpu, 0);
9966bf68 1986 return 1;
8c5fbf1a
KA		 1987 }
1988
1989 nested_vmcb = map.hva;
9966bf68 1990
b742c1e6 1991 ret = kvm_skip_emulated_instruction(&svm->vcpu);
e3e9ed3d 1992
9966bf68 1993 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
8c5fbf1a 1994 kvm_vcpu_unmap(&svm->vcpu, &map, true);
5542675b 1995
b742c1e6 1996 return ret;
5542675b
AG		 1997}
1998
851ba692 1999static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2000{
3d6368ef
AG		 2001 if (nested_svm_check_permissions(svm))
2002 return 1;
2003
e7134c1b 2004 return nested_svm_vmrun(svm);
3d6368ef
AG		 2005}
2006
ffdf7f9e
PB		 2007void svm_set_gif(struct vcpu_svm *svm, bool value)
2008{
2009 if (value) {
2010 /*
2011 * If VGIF is enabled, the STGI intercept is only added to
2012 * detect the opening of the SMI/NMI window; remove it now.
2013 * Likewise, clear the VINTR intercept, we will set it
2014 * again while processing KVM_REQ_EVENT if needed.
2015 */
2016 if (vgif_enabled(svm))
a284ba56
JR		 2017 svm_clr_intercept(svm, INTERCEPT_STGI);
2018 if (svm_is_intercept(svm, INTERCEPT_VINTR))
ffdf7f9e
PB		 2019 svm_clear_vintr(svm);
2020
2021 enable_gif(svm);
2022 if (svm->vcpu.arch.smi_pending ||
2023 svm->vcpu.arch.nmi_pending ||
2024 kvm_cpu_has_injectable_intr(&svm->vcpu))
2025 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2026 } else {
2027 disable_gif(svm);
2028
2029 /*
2030 * After a CLGI no interrupts should come. But if vGIF is
2031 * in use, we still rely on the VINTR intercept (rather than
2032 * STGI) to detect an open interrupt window.
2033 */
2034 if (!vgif_enabled(svm))
2035 svm_clear_vintr(svm);
2036 }
2037}
2038
851ba692 2039static int stgi_interception(struct vcpu_svm *svm)
1371d904 2040{
b742c1e6
LP		 2041 int ret;
2042
1371d904
AG		 2043 if (nested_svm_check_permissions(svm))
2044 return 1;
2045
b742c1e6 2046 ret = kvm_skip_emulated_instruction(&svm->vcpu);
ffdf7f9e 2047 svm_set_gif(svm, true);
b742c1e6 2048 return ret;
1371d904
AG		 2049}
2050
851ba692 2051static int clgi_interception(struct vcpu_svm *svm)
1371d904 2052{
b742c1e6
LP		 2053 int ret;
2054
1371d904
AG		 2055 if (nested_svm_check_permissions(svm))
2056 return 1;
2057
b742c1e6 2058 ret = kvm_skip_emulated_instruction(&svm->vcpu);
ffdf7f9e 2059 svm_set_gif(svm, false);
b742c1e6 2060 return ret;
1371d904
AG		 2061}
2062
851ba692 2063static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2064{
2065 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2066
de3cd117
SC		 2067 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2068 kvm_rax_read(&svm->vcpu));
ec1ff790 2069
ff092385 2070 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
de3cd117 2071 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
ff092385 2072
b742c1e6 2073 return kvm_skip_emulated_instruction(&svm->vcpu);
ff092385
AG		 2074}
2075
532a46b9
JR		 2076static int skinit_interception(struct vcpu_svm *svm)
2077{
de3cd117 2078 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
532a46b9
JR		 2079
2080 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2081 return 1;
2082}
2083
dab429a7
DK		 2084static int wbinvd_interception(struct vcpu_svm *svm)
2085{
6affcbed 2086 return kvm_emulate_wbinvd(&svm->vcpu);
dab429a7
DK		 2087}
2088
81dd35d4
JR		 2089static int xsetbv_interception(struct vcpu_svm *svm)
2090{
2091 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
de3cd117 2092 u32 index = kvm_rcx_read(&svm->vcpu);
81dd35d4
JR		 2093
2094 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
b742c1e6 2095 return kvm_skip_emulated_instruction(&svm->vcpu);
81dd35d4
JR		 2096 }
2097
2098 return 1;
2099}
2100
0cb8410b
JM		 2101static int rdpru_interception(struct vcpu_svm *svm)
2102{
2103 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2104 return 1;
2105}
2106
851ba692 2107static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2108{
37817f29 2109 u16 tss_selector;
64a7ec06
GN		 2110 int reason;
2111 int int_type = svm->vmcb->control.exit_int_info &
2112 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2113 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2114 uint32_t type =
2115 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2116 uint32_t idt_v =
2117 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2118 bool has_error_code = false;
2119 u32 error_code = 0;
37817f29
IE		 2120
2121 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2122
37817f29
IE		 2123 if (svm->vmcb->control.exit_info_2 &
2124 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2125 reason = TASK_SWITCH_IRET;
2126 else if (svm->vmcb->control.exit_info_2 &
2127 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2128 reason = TASK_SWITCH_JMP;
fe8e7f83 2129 else if (idt_v)
64a7ec06
GN		 2130 reason = TASK_SWITCH_GATE;
2131 else
2132 reason = TASK_SWITCH_CALL;
2133
fe8e7f83
GN		 2134 if (reason == TASK_SWITCH_GATE) {
2135 switch (type) {
2136 case SVM_EXITINTINFO_TYPE_NMI:
2137 svm->vcpu.arch.nmi_injected = false;
2138 break;
2139 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2140 if (svm->vmcb->control.exit_info_2 &
2141 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2142 has_error_code = true;
2143 error_code =
2144 (u32)svm->vmcb->control.exit_info_2;
2145 }
fe8e7f83
GN		 2146 kvm_clear_exception_queue(&svm->vcpu);
2147 break;
2148 case SVM_EXITINTINFO_TYPE_INTR:
2149 kvm_clear_interrupt_queue(&svm->vcpu);
2150 break;
2151 default:
2152 break;
2153 }
2154 }
64a7ec06 2155
8317c298
GN		 2156 if (reason != TASK_SWITCH_GATE ||
2157 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2158 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f8ea7c60 2159 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
60fc3d02 2160 if (!skip_emulated_instruction(&svm->vcpu))
738fece4 2161 return 0;
f8ea7c60 2162 }
64a7ec06 2163
7f3d35fd
KW		 2164 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2165 int_vec = -1;
2166
1051778f 2167 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
60fc3d02 2168 has_error_code, error_code);
6aa8b732
AK		 2169}
2170
851ba692 2171static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2172{
6a908b62 2173 return kvm_emulate_cpuid(&svm->vcpu);
6aa8b732
AK		 2174}
2175
851ba692 2176static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2177{
2178 ++svm->vcpu.stat.nmi_window_exits;
a284ba56 2179 svm_clr_intercept(svm, INTERCEPT_IRET);
44c11430 2180 svm->vcpu.arch.hflags |= HF_IRET_MASK;
bd3d1ec3 2181 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
f303b4ce 2182 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
95ba8273
GN		 2183 return 1;
2184}
2185
851ba692 2186static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2187{
df4f3108 2188 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
60fc3d02 2189 return kvm_emulate_instruction(&svm->vcpu, 0);
df4f3108
AP		 2190
2191 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
b742c1e6 2192 return kvm_skip_emulated_instruction(&svm->vcpu);
a7052897
MT		 2193}
2194
851ba692 2195static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2196{
60fc3d02 2197 return kvm_emulate_instruction(&svm->vcpu, 0);
6aa8b732
AK		 2198}
2199
7607b717
BS		 2200static int rsm_interception(struct vcpu_svm *svm)
2201{
60fc3d02 2202 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
7607b717
BS		 2203}
2204
332b56e4
AK		 2205static int rdpmc_interception(struct vcpu_svm *svm)
2206{
2207 int err;
2208
d647eb63 2209 if (!nrips)
332b56e4
AK		 2210 return emulate_on_interception(svm);
2211
2212 err = kvm_rdpmc(&svm->vcpu);
6affcbed 2213 return kvm_complete_insn_gp(&svm->vcpu, err);
332b56e4
AK		 2214}
2215
52eb5a6d
XL		 2216static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2217 unsigned long val)
628afd2a
JR		 2218{
2219 unsigned long cr0 = svm->vcpu.arch.cr0;
2220 bool ret = false;
2221 u64 intercept;
2222
e670bf68 2223 intercept = svm->nested.ctl.intercept;
628afd2a
JR		 2224
2225 if (!is_guest_mode(&svm->vcpu) ||
2226 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2227 return false;
2228
2229 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2230 val &= ~SVM_CR0_SELECTIVE_MASK;
2231
2232 if (cr0 ^ val) {
2233 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2234 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2235 }
2236
2237 return ret;
2238}
2239
7ff76d58
AP		 2240#define CR_VALID (1ULL << 63)
2241
2242static int cr_interception(struct vcpu_svm *svm)
2243{
2244 int reg, cr;
2245 unsigned long val;
2246 int err;
2247
2248 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2249 return emulate_on_interception(svm);
2250
2251 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2252 return emulate_on_interception(svm);
2253
2254 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
5e57518d
DK		 2255 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2256 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2257 else
2258 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
7ff76d58
AP		 2259
2260 err = 0;
2261 if (cr >= 16) { /* mov to cr */
2262 cr -= 16;
2263 val = kvm_register_read(&svm->vcpu, reg);
2264 switch (cr) {
2265 case 0:
628afd2a
JR		 2266 if (!check_selective_cr0_intercepted(svm, val))
2267 err = kvm_set_cr0(&svm->vcpu, val);
977b2d03
JR		 2268 else
2269 return 1;
2270
7ff76d58
AP		 2271 break;
2272 case 3:
2273 err = kvm_set_cr3(&svm->vcpu, val);
2274 break;
2275 case 4:
2276 err = kvm_set_cr4(&svm->vcpu, val);
2277 break;
2278 case 8:
2279 err = kvm_set_cr8(&svm->vcpu, val);
2280 break;
2281 default:
2282 WARN(1, "unhandled write to CR%d", cr);
2283 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2284 return 1;
2285 }
2286 } else { /* mov from cr */
2287 switch (cr) {
2288 case 0:
2289 val = kvm_read_cr0(&svm->vcpu);
2290 break;
2291 case 2:
2292 val = svm->vcpu.arch.cr2;
2293 break;
2294 case 3:
9f8fe504 2295 val = kvm_read_cr3(&svm->vcpu);
7ff76d58
AP		 2296 break;
2297 case 4:
2298 val = kvm_read_cr4(&svm->vcpu);
2299 break;
2300 case 8:
2301 val = kvm_get_cr8(&svm->vcpu);
2302 break;
2303 default:
2304 WARN(1, "unhandled read from CR%d", cr);
2305 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2306 return 1;
2307 }
2308 kvm_register_write(&svm->vcpu, reg, val);
2309 }
6affcbed 2310 return kvm_complete_insn_gp(&svm->vcpu, err);
7ff76d58
AP		 2311}
2312
cae3797a
AP		 2313static int dr_interception(struct vcpu_svm *svm)
2314{
2315 int reg, dr;
2316 unsigned long val;
cae3797a 2317
facb0139
PB		 2318 if (svm->vcpu.guest_debug == 0) {
2319 /*
2320 * No more DR vmexits; force a reload of the debug registers
2321 * and reenter on this instruction. The next vmexit will
2322 * retrieve the full state of the debug registers.
2323 */
2324 clr_dr_intercepts(svm);
2325 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2326 return 1;
2327 }
2328
cae3797a
AP		 2329 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2330 return emulate_on_interception(svm);
2331
2332 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2333 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2334
2335 if (dr >= 16) { /* mov to DRn */
16f8a6f9
NA		 2336 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2337 return 1;
cae3797a
AP		 2338 val = kvm_register_read(&svm->vcpu, reg);
2339 kvm_set_dr(&svm->vcpu, dr - 16, val);
2340 } else {
16f8a6f9
NA		 2341 if (!kvm_require_dr(&svm->vcpu, dr))
2342 return 1;
2343 kvm_get_dr(&svm->vcpu, dr, &val);
2344 kvm_register_write(&svm->vcpu, reg, val);
cae3797a
AP		 2345 }
2346
b742c1e6 2347 return kvm_skip_emulated_instruction(&svm->vcpu);
cae3797a
AP		 2348}
2349
851ba692 2350static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2351{
851ba692 2352 struct kvm_run *kvm_run = svm->vcpu.run;
eea1cff9 2353 int r;
851ba692 2354
0a5fff19
GN		 2355 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2356 /* instruction emulation calls kvm_set_cr8() */
7ff76d58 2357 r = cr_interception(svm);
35754c98 2358 if (lapic_in_kernel(&svm->vcpu))
7ff76d58 2359 return r;
0a5fff19 2360 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
7ff76d58 2361 return r;
1d075434
JR		 2362 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2363 return 0;
2364}
2365
801e459a
TL		 2366static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2367{
d1d93fa9
TL		 2368 msr->data = 0;
2369
2370 switch (msr->index) {
2371 case MSR_F10H_DECFG:
2372 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2373 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2374 break;
d574c539
VK		 2375 case MSR_IA32_PERF_CAPABILITIES:
2376 return 0;
d1d93fa9 2377 default:
12bc2132 2378 return KVM_MSR_RET_INVALID;
d1d93fa9
TL		 2379 }
2380
2381 return 0;
801e459a
TL		 2382}
2383
609e36d3 2384static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2385{
a2fa3e9f
GH		 2386 struct vcpu_svm *svm = to_svm(vcpu);
2387
609e36d3 2388 switch (msr_info->index) {
8c06585d 2389 case MSR_STAR:
609e36d3 2390 msr_info->data = svm->vmcb->save.star;
6aa8b732 2391 break;
0e859cac 2392#ifdef CONFIG_X86_64
6aa8b732 2393 case MSR_LSTAR:
609e36d3 2394 msr_info->data = svm->vmcb->save.lstar;
6aa8b732
AK		 2395 break;
2396 case MSR_CSTAR:
609e36d3 2397 msr_info->data = svm->vmcb->save.cstar;
6aa8b732
AK		 2398 break;
2399 case MSR_KERNEL_GS_BASE:
609e36d3 2400 msr_info->data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2401 break;
2402 case MSR_SYSCALL_MASK:
609e36d3 2403 msr_info->data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2404 break;
2405#endif
2406 case MSR_IA32_SYSENTER_CS:
609e36d3 2407 msr_info->data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2408 break;
2409 case MSR_IA32_SYSENTER_EIP:
609e36d3 2410 msr_info->data = svm->sysenter_eip;
6aa8b732
AK		 2411 break;
2412 case MSR_IA32_SYSENTER_ESP:
609e36d3 2413 msr_info->data = svm->sysenter_esp;
6aa8b732 2414 break;
46896c73
PB		 2415 case MSR_TSC_AUX:
2416 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2417 return 1;
2418 msr_info->data = svm->tsc_aux;
2419 break;
e0231715
JR		 2420 /*
2421 * Nobody will change the following 5 values in the VMCB so we can
2422 * safely return them on rdmsr. They will always be 0 until LBRV is
2423 * implemented.
2424 */
a2938c80 2425 case MSR_IA32_DEBUGCTLMSR:
609e36d3 2426 msr_info->data = svm->vmcb->save.dbgctl;
a2938c80
JR		 2427 break;
2428 case MSR_IA32_LASTBRANCHFROMIP:
609e36d3 2429 msr_info->data = svm->vmcb->save.br_from;
a2938c80
JR		 2430 break;
2431 case MSR_IA32_LASTBRANCHTOIP:
609e36d3 2432 msr_info->data = svm->vmcb->save.br_to;
a2938c80
JR		 2433 break;
2434 case MSR_IA32_LASTINTFROMIP:
609e36d3 2435 msr_info->data = svm->vmcb->save.last_excp_from;
a2938c80
JR		 2436 break;
2437 case MSR_IA32_LASTINTTOIP:
609e36d3 2438 msr_info->data = svm->vmcb->save.last_excp_to;
a2938c80 2439 break;
b286d5d8 2440 case MSR_VM_HSAVE_PA:
609e36d3 2441 msr_info->data = svm->nested.hsave_msr;
b286d5d8 2442 break;
eb6f302e 2443 case MSR_VM_CR:
609e36d3 2444 msr_info->data = svm->nested.vm_cr_msr;
eb6f302e 2445 break;
b2ac58f9
KA		 2446 case MSR_IA32_SPEC_CTRL:
2447 if (!msr_info->host_initiated &&
df7e8818
PB		 2448 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2449 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
6ac2f49e
KRW		 2450 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2451 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
b2ac58f9
KA		 2452 return 1;
2453
2454 msr_info->data = svm->spec_ctrl;
2455 break;
bc226f07
TL		 2456 case MSR_AMD64_VIRT_SPEC_CTRL:
2457 if (!msr_info->host_initiated &&
2458 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2459 return 1;
2460
2461 msr_info->data = svm->virt_spec_ctrl;
2462 break;
ae8b7875
BP		 2463 case MSR_F15H_IC_CFG: {
2464
2465 int family, model;
2466
2467 family = guest_cpuid_family(vcpu);
2468 model = guest_cpuid_model(vcpu);
2469
2470 if (family < 0 || model < 0)
2471 return kvm_get_msr_common(vcpu, msr_info);
2472
2473 msr_info->data = 0;
2474
2475 if (family == 0x15 &&
2476 (model >= 0x2 && model < 0x20))
2477 msr_info->data = 0x1E;
2478 }
2479 break;
d1d93fa9
TL		 2480 case MSR_F10H_DECFG:
2481 msr_info->data = svm->msr_decfg;
2482 break;
6aa8b732 2483 default:
609e36d3 2484 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 2485 }
2486 return 0;
2487}
2488
851ba692 2489static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2490{
1edce0a9 2491 return kvm_emulate_rdmsr(&svm->vcpu);
6aa8b732
AK		 2492}
2493
4a810181
JR		 2494static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2495{
2496 struct vcpu_svm *svm = to_svm(vcpu);
2497 int svm_dis, chg_mask;
2498
2499 if (data & ~SVM_VM_CR_VALID_MASK)
2500 return 1;
2501
2502 chg_mask = SVM_VM_CR_VALID_MASK;
2503
2504 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2505 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2506
2507 svm->nested.vm_cr_msr &= ~chg_mask;
2508 svm->nested.vm_cr_msr |= (data & chg_mask);
2509
2510 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2511
2512 /* check for svm_disable while efer.svme is set */
2513 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2514 return 1;
2515
2516 return 0;
2517}
2518
8fe8ab46 2519static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
6aa8b732 2520{
a2fa3e9f
GH		 2521 struct vcpu_svm *svm = to_svm(vcpu);
2522
8fe8ab46
WA		 2523 u32 ecx = msr->index;
2524 u64 data = msr->data;
6aa8b732 2525 switch (ecx) {
15038e14
PB		 2526 case MSR_IA32_CR_PAT:
2527 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2528 return 1;
2529 vcpu->arch.pat = data;
2530 svm->vmcb->save.g_pat = data;
06e7852c 2531 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
15038e14 2532 break;
b2ac58f9
KA		 2533 case MSR_IA32_SPEC_CTRL:
2534 if (!msr->host_initiated &&
df7e8818
PB		 2535 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2536 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
6ac2f49e
KRW		 2537 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2538 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
b2ac58f9
KA		 2539 return 1;
2540
841c2be0 2541 if (kvm_spec_ctrl_test_value(data))
b2ac58f9
KA		 2542 return 1;
2543
2544 svm->spec_ctrl = data;
b2ac58f9
KA		 2545 if (!data)
2546 break;
2547
2548 /*
2549 * For non-nested:
2550 * When it's written (to non-zero) for the first time, pass
2551 * it through.
2552 *
2553 * For nested:
2554 * The handling of the MSR bitmap for L2 guests is done in
2555 * nested_svm_vmrun_msrpm.
2556 * We update the L1 MSR bit as well since it will end up
2557 * touching the MSR anyway now.
2558 */
2559 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2560 break;
15d45071
AR		 2561 case MSR_IA32_PRED_CMD:
2562 if (!msr->host_initiated &&
e7c587da 2563 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
15d45071
AR		 2564 return 1;
2565
2566 if (data & ~PRED_CMD_IBPB)
2567 return 1;
6441fa61
PB		 2568 if (!boot_cpu_has(X86_FEATURE_AMD_IBPB))
2569 return 1;
15d45071
AR		 2570 if (!data)
2571 break;
2572
2573 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
15d45071
AR		 2574 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2575 break;
bc226f07
TL		 2576 case MSR_AMD64_VIRT_SPEC_CTRL:
2577 if (!msr->host_initiated &&
2578 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2579 return 1;
2580
2581 if (data & ~SPEC_CTRL_SSBD)
2582 return 1;
2583
2584 svm->virt_spec_ctrl = data;
2585 break;
8c06585d 2586 case MSR_STAR:
a2fa3e9f 2587 svm->vmcb->save.star = data;
6aa8b732 2588 break;
49b14f24 2589#ifdef CONFIG_X86_64
6aa8b732 2590 case MSR_LSTAR:
a2fa3e9f 2591 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2592 break;
2593 case MSR_CSTAR:
a2fa3e9f 2594 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2595 break;
2596 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2597 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2598 break;
2599 case MSR_SYSCALL_MASK:
a2fa3e9f 2600 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2601 break;
2602#endif
2603 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2604 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2605 break;
2606 case MSR_IA32_SYSENTER_EIP:
017cb99e 2607 svm->sysenter_eip = data;
a2fa3e9f 2608 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2609 break;
2610 case MSR_IA32_SYSENTER_ESP:
017cb99e 2611 svm->sysenter_esp = data;
a2fa3e9f 2612 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2613 break;
46896c73
PB		 2614 case MSR_TSC_AUX:
2615 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2616 return 1;
2617
2618 /*
2619 * This is rare, so we update the MSR here instead of using
2620 * direct_access_msrs. Doing that would require a rdmsr in
2621 * svm_vcpu_put.
2622 */
2623 svm->tsc_aux = data;
2624 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2625 break;
a2938c80 2626 case MSR_IA32_DEBUGCTLMSR:
2a6b20b8 2627 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
a737f256
CD		 2628 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2629 __func__, data);
24e09cbf
JR		 2630 break;
2631 }
2632 if (data & DEBUGCTL_RESERVED_BITS)
2633 return 1;
2634
2635 svm->vmcb->save.dbgctl = data;
06e7852c 2636 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
24e09cbf
JR		 2637 if (data & (1ULL<<0))
2638 svm_enable_lbrv(svm);
2639 else
2640 svm_disable_lbrv(svm);
a2938c80 2641 break;
b286d5d8 2642 case MSR_VM_HSAVE_PA:
e6aa9abd 2643 svm->nested.hsave_msr = data;
62b9abaa 2644 break;
3c5d0a44 2645 case MSR_VM_CR:
4a810181 2646 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2647 case MSR_VM_IGNNE:
a737f256 2648 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3c5d0a44 2649 break;
d1d93fa9
TL		 2650 case MSR_F10H_DECFG: {
2651 struct kvm_msr_entry msr_entry;
2652
2653 msr_entry.index = msr->index;
2654 if (svm_get_msr_feature(&msr_entry))
2655 return 1;
2656
2657 /* Check the supported bits */
2658 if (data & ~msr_entry.data)
2659 return 1;
2660
2661 /* Don't allow the guest to change a bit, #GP */
2662 if (!msr->host_initiated && (data ^ msr_entry.data))
2663 return 1;
2664
2665 svm->msr_decfg = data;
2666 break;
2667 }
44a95dae
SS		 2668 case MSR_IA32_APICBASE:
2669 if (kvm_vcpu_apicv_active(vcpu))
2670 avic_update_vapic_bar(to_svm(vcpu), data);
b2869f28 2671 /* Fall through */
6aa8b732 2672 default:
8fe8ab46 2673 return kvm_set_msr_common(vcpu, msr);
6aa8b732
AK		 2674 }
2675 return 0;
2676}
2677
851ba692 2678static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2679{
1edce0a9 2680 return kvm_emulate_wrmsr(&svm->vcpu);
6aa8b732
AK		 2681}
2682
851ba692 2683static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2684{
e756fc62 2685 if (svm->vmcb->control.exit_info_1)
851ba692 2686 return wrmsr_interception(svm);
6aa8b732 2687 else
851ba692 2688 return rdmsr_interception(svm);
6aa8b732
AK		 2689}
2690
851ba692 2691static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2692{
3842d135 2693 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
f0b85051 2694 svm_clear_vintr(svm);
f3515dc3
SS		 2695
2696 /*
2697 * For AVIC, the only reason to end up here is ExtINTs.
2698 * In this case AVIC was temporarily disabled for
2699 * requesting the IRQ window and we have to re-enable it.
2700 */
2701 svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2702
675acb75 2703 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2704 return 1;
2705}
2706
565d0998
ML		 2707static int pause_interception(struct vcpu_svm *svm)
2708{
de63ad4c
LM		 2709 struct kvm_vcpu *vcpu = &svm->vcpu;
2710 bool in_kernel = (svm_get_cpl(vcpu) == 0);
2711
830f01b0 2712 if (!kvm_pause_in_guest(vcpu->kvm))
8566ac8b
BM		 2713 grow_ple_window(vcpu);
2714
de63ad4c 2715 kvm_vcpu_on_spin(vcpu, in_kernel);
565d0998
ML		 2716 return 1;
2717}
2718
87c00572
GS		 2719static int nop_interception(struct vcpu_svm *svm)
2720{
b742c1e6 2721 return kvm_skip_emulated_instruction(&(svm->vcpu));
87c00572
GS		 2722}
2723
2724static int monitor_interception(struct vcpu_svm *svm)
2725{
2726 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2727 return nop_interception(svm);
2728}
2729
2730static int mwait_interception(struct vcpu_svm *svm)
2731{
2732 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2733 return nop_interception(svm);
2734}
2735
09941fbb 2736static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
7ff76d58
AP		 2737 [SVM_EXIT_READ_CR0] = cr_interception,
2738 [SVM_EXIT_READ_CR3] = cr_interception,
2739 [SVM_EXIT_READ_CR4] = cr_interception,
2740 [SVM_EXIT_READ_CR8] = cr_interception,
5e57518d 2741 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
628afd2a 2742 [SVM_EXIT_WRITE_CR0] = cr_interception,
7ff76d58
AP		 2743 [SVM_EXIT_WRITE_CR3] = cr_interception,
2744 [SVM_EXIT_WRITE_CR4] = cr_interception,
e0231715 2745 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
cae3797a
AP		 2746 [SVM_EXIT_READ_DR0] = dr_interception,
2747 [SVM_EXIT_READ_DR1] = dr_interception,
2748 [SVM_EXIT_READ_DR2] = dr_interception,
2749 [SVM_EXIT_READ_DR3] = dr_interception,
2750 [SVM_EXIT_READ_DR4] = dr_interception,
2751 [SVM_EXIT_READ_DR5] = dr_interception,
2752 [SVM_EXIT_READ_DR6] = dr_interception,
2753 [SVM_EXIT_READ_DR7] = dr_interception,
2754 [SVM_EXIT_WRITE_DR0] = dr_interception,
2755 [SVM_EXIT_WRITE_DR1] = dr_interception,
2756 [SVM_EXIT_WRITE_DR2] = dr_interception,
2757 [SVM_EXIT_WRITE_DR3] = dr_interception,
2758 [SVM_EXIT_WRITE_DR4] = dr_interception,
2759 [SVM_EXIT_WRITE_DR5] = dr_interception,
2760 [SVM_EXIT_WRITE_DR6] = dr_interception,
2761 [SVM_EXIT_WRITE_DR7] = dr_interception,
d0bfb940
JK		 2762 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2763 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2764 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715 2765 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
e0231715 2766 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
54a20552 2767 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
9718420e 2768 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
e0231715 2769 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2770 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2771 [SVM_EXIT_SMI] = nop_on_interception,
2772 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2773 [SVM_EXIT_VINTR] = interrupt_window_interception,
332b56e4 2774 [SVM_EXIT_RDPMC] = rdpmc_interception,
6aa8b732 2775 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2776 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2777 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2778 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2779 [SVM_EXIT_HLT] = halt_interception,
a7052897 2780 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2781 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2782 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2783 [SVM_EXIT_MSR] = msr_interception,
2784 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2785 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2786 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2787 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2788 [SVM_EXIT_VMLOAD] = vmload_interception,
2789 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2790 [SVM_EXIT_STGI] = stgi_interception,
2791 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2792 [SVM_EXIT_SKINIT] = skinit_interception,
dab429a7 2793 [SVM_EXIT_WBINVD] = wbinvd_interception,
87c00572
GS		 2794 [SVM_EXIT_MONITOR] = monitor_interception,
2795 [SVM_EXIT_MWAIT] = mwait_interception,
81dd35d4 2796 [SVM_EXIT_XSETBV] = xsetbv_interception,
0cb8410b 2797 [SVM_EXIT_RDPRU] = rdpru_interception,
d0006530 2798 [SVM_EXIT_NPF] = npf_interception,
7607b717 2799 [SVM_EXIT_RSM] = rsm_interception,
18f40c53
SS		 2800 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
2801 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
6aa8b732
AK		 2802};
2803
ae8cc059 2804static void dump_vmcb(struct kvm_vcpu *vcpu)
3f10c846
JR		 2805{
2806 struct vcpu_svm *svm = to_svm(vcpu);
2807 struct vmcb_control_area *control = &svm->vmcb->control;
2808 struct vmcb_save_area *save = &svm->vmcb->save;
2809
6f2f8453
PB		 2810 if (!dump_invalid_vmcb) {
2811 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2812 return;
2813 }
2814
3f10c846 2815 pr_err("VMCB Control Area:\n");
ae8cc059
JP		 2816 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
2817 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
2818 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
2819 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
2820 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
2821 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
2822 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
1d8fb44a
BM		 2823 pr_err("%-20s%d\n", "pause filter threshold:",
2824 control->pause_filter_thresh);
ae8cc059
JP		 2825 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2826 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
2827 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
2828 pr_err("%-20s%d\n", "asid:", control->asid);
2829 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
2830 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
2831 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
2832 pr_err("%-20s%08x\n", "int_state:", control->int_state);
2833 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
2834 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
2835 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
2836 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
2837 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
2838 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
2839 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
44a95dae 2840 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
ae8cc059
JP		 2841 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
2842 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
0dc92119 2843 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
ae8cc059 2844 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
44a95dae
SS		 2845 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
2846 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
2847 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3f10c846 2848 pr_err("VMCB State Save Area:\n");
ae8cc059
JP		 2849 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2850 "es:",
2851 save->es.selector, save->es.attrib,
2852 save->es.limit, save->es.base);
2853 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2854 "cs:",
2855 save->cs.selector, save->cs.attrib,
2856 save->cs.limit, save->cs.base);
2857 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2858 "ss:",
2859 save->ss.selector, save->ss.attrib,
2860 save->ss.limit, save->ss.base);
2861 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2862 "ds:",
2863 save->ds.selector, save->ds.attrib,
2864 save->ds.limit, save->ds.base);
2865 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2866 "fs:",
2867 save->fs.selector, save->fs.attrib,
2868 save->fs.limit, save->fs.base);
2869 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2870 "gs:",
2871 save->gs.selector, save->gs.attrib,
2872 save->gs.limit, save->gs.base);
2873 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2874 "gdtr:",
2875 save->gdtr.selector, save->gdtr.attrib,
2876 save->gdtr.limit, save->gdtr.base);
2877 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2878 "ldtr:",
2879 save->ldtr.selector, save->ldtr.attrib,
2880 save->ldtr.limit, save->ldtr.base);
2881 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2882 "idtr:",
2883 save->idtr.selector, save->idtr.attrib,
2884 save->idtr.limit, save->idtr.base);
2885 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2886 "tr:",
2887 save->tr.selector, save->tr.attrib,
2888 save->tr.limit, save->tr.base);
3f10c846
JR		 2889 pr_err("cpl: %d efer: %016llx\n",
2890 save->cpl, save->efer);
ae8cc059
JP		 2891 pr_err("%-15s %016llx %-13s %016llx\n",
2892 "cr0:", save->cr0, "cr2:", save->cr2);
2893 pr_err("%-15s %016llx %-13s %016llx\n",
2894 "cr3:", save->cr3, "cr4:", save->cr4);
2895 pr_err("%-15s %016llx %-13s %016llx\n",
2896 "dr6:", save->dr6, "dr7:", save->dr7);
2897 pr_err("%-15s %016llx %-13s %016llx\n",
2898 "rip:", save->rip, "rflags:", save->rflags);
2899 pr_err("%-15s %016llx %-13s %016llx\n",
2900 "rsp:", save->rsp, "rax:", save->rax);
2901 pr_err("%-15s %016llx %-13s %016llx\n",
2902 "star:", save->star, "lstar:", save->lstar);
2903 pr_err("%-15s %016llx %-13s %016llx\n",
2904 "cstar:", save->cstar, "sfmask:", save->sfmask);
2905 pr_err("%-15s %016llx %-13s %016llx\n",
2906 "kernel_gs_base:", save->kernel_gs_base,
2907 "sysenter_cs:", save->sysenter_cs);
2908 pr_err("%-15s %016llx %-13s %016llx\n",
2909 "sysenter_esp:", save->sysenter_esp,
2910 "sysenter_eip:", save->sysenter_eip);
2911 pr_err("%-15s %016llx %-13s %016llx\n",
2912 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
2913 pr_err("%-15s %016llx %-13s %016llx\n",
2914 "br_from:", save->br_from, "br_to:", save->br_to);
2915 pr_err("%-15s %016llx %-13s %016llx\n",
2916 "excp_from:", save->last_excp_from,
2917 "excp_to:", save->last_excp_to);
3f10c846
JR		 2918}
2919
586f9607
AK		 2920static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
2921{
2922 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2923
2924 *info1 = control->exit_info_1;
2925 *info2 = control->exit_info_2;
2926}
2927
404d5d7b 2928static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6aa8b732 2929{
04d2cc77 2930 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2931 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2932 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2933
8b89fe1f
PB		 2934 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
2935
4ee546b4 2936 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
2be4fc7a
JR		 2937 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2938 if (npt_enabled)
2939 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 2940
2030753d 2941 if (is_guest_mode(vcpu)) {
410e4d57
JR		 2942 int vmexit;
2943
d8cabddf
JR		 2944 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2945 svm->vmcb->control.exit_info_1,
2946 svm->vmcb->control.exit_info_2,
2947 svm->vmcb->control.exit_int_info,
e097e5ff
SH		 2948 svm->vmcb->control.exit_int_info_err,
2949 KVM_ISA_SVM);
d8cabddf 2950
410e4d57
JR		 2951 vmexit = nested_svm_exit_special(svm);
2952
2953 if (vmexit == NESTED_EXIT_CONTINUE)
2954 vmexit = nested_svm_exit_handled(svm);
2955
2956 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2957 return 1;
cf74a78b
AG		 2958 }
2959
04d2cc77
AK		 2960 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2961 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2962 kvm_run->fail_entry.hardware_entry_failure_reason
2963 = svm->vmcb->control.exit_code;
8a14fe4f 2964 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3f10c846 2965 dump_vmcb(vcpu);
04d2cc77
AK		 2966 return 0;
2967 }
2968
a2fa3e9f 2969 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2970 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
55c5e464
JR		 2971 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
2972 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
6614c7d0 2973 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
6aa8b732 2974 "exit_code 0x%x\n",
b8688d51 2975 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2976 exit_code);
2977
404d5d7b 2978 if (exit_fastpath != EXIT_FASTPATH_NONE)
1e9e2622 2979 return 1;
404d5d7b
WL		 2980
2981 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2982 || !svm_exit_handlers[exit_code]) {
7396d337
LA		 2983 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
2984 dump_vmcb(vcpu);
2985 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2986 vcpu->run->internal.suberror =
2987 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
1aa561b1 2988 vcpu->run->internal.ndata = 2;
7396d337 2989 vcpu->run->internal.data[0] = exit_code;
8a14fe4f 2990 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
7396d337 2991 return 0;
6aa8b732
AK		 2992 }
2993
3dcb2a3f
AA		 2994#ifdef CONFIG_RETPOLINE
2995 if (exit_code == SVM_EXIT_MSR)
2996 return msr_interception(svm);
2997 else if (exit_code == SVM_EXIT_VINTR)
2998 return interrupt_window_interception(svm);
2999 else if (exit_code == SVM_EXIT_INTR)
3000 return intr_interception(svm);
3001 else if (exit_code == SVM_EXIT_HLT)
3002 return halt_interception(svm);
3003 else if (exit_code == SVM_EXIT_NPF)
3004 return npf_interception(svm);
3005#endif
851ba692 3006 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 3007}
3008
3009static void reload_tss(struct kvm_vcpu *vcpu)
3010{
73cd6e5f 3011 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
6aa8b732 3012
0fe1e009 3013 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 3014 load_TR_desc();
3015}
3016
e756fc62 3017static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732 3018{
73cd6e5f 3019 struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
6aa8b732 3020
70cd94e6 3021 if (sev_guest(svm->vcpu.kvm))
73cd6e5f 3022 return pre_sev_run(svm, svm->vcpu.cpu);
70cd94e6 3023
4b656b12 3024 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 3025 if (svm->asid_generation != sd->asid_generation)
3026 new_asid(svm, sd);
6aa8b732
AK		 3027}
3028
95ba8273
GN		 3029static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3030{
3031 struct vcpu_svm *svm = to_svm(vcpu);
3032
3033 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3034 vcpu->arch.hflags |= HF_NMI_MASK;
a284ba56 3035 svm_set_intercept(svm, INTERCEPT_IRET);
95ba8273
GN		 3036 ++vcpu->stat.nmi_injections;
3037}
6aa8b732 3038
66fd3f7f 3039static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3040{
3041 struct vcpu_svm *svm = to_svm(vcpu);
3042
2af9194d 3043 BUG_ON(!(gif_set(svm)));
cf74a78b 3044
9fb2d2b4
GN		 3045 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3046 ++vcpu->stat.irq_injections;
3047
219b65dc
AG		 3048 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3049 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3050}
3051
95ba8273 3052static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3053{
3054 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3055
01c3b2b5 3056 if (nested_svm_virtualize_tpr(vcpu))
88ab24ad
JR		 3057 return;
3058
596f3142
RK		 3059 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3060
95ba8273 3061 if (irr == -1)
aaacfc9a
JR		 3062 return;
3063
95ba8273 3064 if (tpr >= irr)
4ee546b4 3065 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
95ba8273 3066}
aaacfc9a 3067
cae96af1 3068bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
95ba8273
GN		 3069{
3070 struct vcpu_svm *svm = to_svm(vcpu);
3071 struct vmcb *vmcb = svm->vmcb;
88c604b6 3072 bool ret;
9c3d370a 3073
cae96af1 3074 if (!gif_set(svm))
bbdad0b5
PB		 3075 return true;
3076
cae96af1
PB		 3077 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3078 return false;
3079
3080 ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3081 (svm->vcpu.arch.hflags & HF_NMI_MASK);
924584cc
JR		 3082
3083 return ret;
aaacfc9a
JR		 3084}
3085
c9d40913 3086static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3087{
3088 struct vcpu_svm *svm = to_svm(vcpu);
3089 if (svm->nested.nested_run_pending)
c9d40913 3090 return -EBUSY;
cae96af1 3091
c300ab9f
PB		 3092 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3093 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
c9d40913 3094 return -EBUSY;
c300ab9f
PB		 3095
3096 return !svm_nmi_blocked(vcpu);
cae96af1
PB		 3097}
3098
3cfc3092
JK		 3099static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3100{
3101 struct vcpu_svm *svm = to_svm(vcpu);
3102
3103 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3104}
3105
3106static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3107{
3108 struct vcpu_svm *svm = to_svm(vcpu);
3109
3110 if (masked) {
3111 svm->vcpu.arch.hflags |= HF_NMI_MASK;
a284ba56 3112 svm_set_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3113 } else {
3114 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
a284ba56 3115 svm_clr_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3116 }
3117}
3118
cae96af1 3119bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
78646121
GN		 3120{
3121 struct vcpu_svm *svm = to_svm(vcpu);
3122 struct vmcb *vmcb = svm->vmcb;
7fcdb510 3123
fc6f7c03 3124 if (!gif_set(svm))
cae96af1 3125 return true;
7fcdb510 3126
fc6f7c03
PB		 3127 if (is_guest_mode(vcpu)) {
3128 /* As long as interrupts are being delivered... */
e9fd761a 3129 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
08245e6d 3130 ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
fc6f7c03
PB		 3131 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3132 return true;
3133
3134 /* ... vmexits aren't blocked by the interrupt shadow */
3135 if (nested_exit_on_intr(svm))
3136 return false;
3137 } else {
3138 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3139 return true;
3140 }
3141
3142 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
cae96af1
PB		 3143}
3144
c9d40913 3145static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3146{
3147 struct vcpu_svm *svm = to_svm(vcpu);
3148 if (svm->nested.nested_run_pending)
c9d40913 3149 return -EBUSY;
cae96af1 3150
c300ab9f
PB		 3151 /*
3152 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3153 * e.g. if the IRQ arrived asynchronously after checking nested events.
3154 */
3155 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
c9d40913 3156 return -EBUSY;
c300ab9f
PB		 3157
3158 return !svm_interrupt_blocked(vcpu);
78646121
GN		 3159}
3160
c9a7953f 3161static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3162{
219b65dc 3163 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3164
e0231715
JR		 3165 /*
3166 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3167 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3168 * get that intercept, this function will be called again though and
640bd6e5
JN		 3169 * we'll get the vintr intercept. However, if the vGIF feature is
3170 * enabled, the STGI interception will not occur. Enable the irq
3171 * window under the assumption that the hardware will set the GIF.
e0231715 3172 */
b518ba9f 3173 if (vgif_enabled(svm) || gif_set(svm)) {
f3515dc3
SS		 3174 /*
3175 * IRQ window is not needed when AVIC is enabled,
3176 * unless we have pending ExtINT since it cannot be injected
3177 * via AVIC. In such case, we need to temporarily disable AVIC,
3178 * and fallback to injecting IRQ via V_IRQ.
3179 */
3180 svm_toggle_avic_for_irq_window(vcpu, false);
219b65dc 3181 svm_set_vintr(svm);
219b65dc 3182 }
85f455f7
ED		 3183}
3184
c9a7953f 3185static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3186{
04d2cc77 3187 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3188
44c11430
GN		 3189 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3190 == HF_NMI_MASK)
c9a7953f 3191 return; /* IRET will cause a vm exit */
44c11430 3192
640bd6e5
JN		 3193 if (!gif_set(svm)) {
3194 if (vgif_enabled(svm))
a284ba56 3195 svm_set_intercept(svm, INTERCEPT_STGI);
1a5e1852 3196 return; /* STGI will cause a vm exit */
640bd6e5 3197 }
1a5e1852 3198
e0231715
JR		 3199 /*
3200 * Something prevents NMI from been injected. Single step over possible
3201 * problem (IRET or exception injection or interrupt shadow)
3202 */
ab2f4d73 3203 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
6be7d306 3204 svm->nmi_singlestep = true;
44c11430 3205 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
c1150d8c
DL		 3206}
3207
cbc94022
IE		 3208static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3209{
3210 return 0;
3211}
3212
2ac52ab8
SC		 3213static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3214{
3215 return 0;
3216}
3217
f55ac304 3218void svm_flush_tlb(struct kvm_vcpu *vcpu)
d9e368d6 3219{
38e5e92f
JR		 3220 struct vcpu_svm *svm = to_svm(vcpu);
3221
4a41e43c
SC		 3222 /*
3223 * Flush only the current ASID even if the TLB flush was invoked via
3224 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3225 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3226 * unconditionally does a TLB flush on both nested VM-Enter and nested
3227 * VM-Exit (via kvm_mmu_reset_context()).
3228 */
38e5e92f
JR		 3229 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3230 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3231 else
3232 svm->asid_generation--;
d9e368d6
AK		 3233}
3234
faff8758
JS		 3235static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3236{
3237 struct vcpu_svm *svm = to_svm(vcpu);
3238
3239 invlpga(gva, svm->vmcb->control.asid);
3240}
3241
04d2cc77
AK		 3242static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3243{
3244}
3245
d7bf8221
JR		 3246static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3247{
3248 struct vcpu_svm *svm = to_svm(vcpu);
3249
01c3b2b5 3250 if (nested_svm_virtualize_tpr(vcpu))
88ab24ad
JR		 3251 return;
3252
4ee546b4 3253 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
d7bf8221 3254 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3255 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3256 }
3257}
3258
649d6864
JR		 3259static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3260{
3261 struct vcpu_svm *svm = to_svm(vcpu);
3262 u64 cr8;
3263
01c3b2b5 3264 if (nested_svm_virtualize_tpr(vcpu) ||
3bbf3565 3265 kvm_vcpu_apicv_active(vcpu))
88ab24ad
JR		 3266 return;
3267
649d6864
JR		 3268 cr8 = kvm_get_cr8(vcpu);
3269 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3270 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3271}
3272
9222be18
GN		 3273static void svm_complete_interrupts(struct vcpu_svm *svm)
3274{
3275 u8 vector;
3276 int type;
3277 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3278 unsigned int3_injected = svm->int3_injected;
3279
3280 svm->int3_injected = 0;
9222be18 3281
bd3d1ec3
AK		 3282 /*
3283 * If we've made progress since setting HF_IRET_MASK, we've
3284 * executed an IRET and can allow NMI injection.
3285 */
3286 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3287 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
44c11430 3288 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3842d135
AK		 3289 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3290 }
44c11430 3291
9222be18
GN		 3292 svm->vcpu.arch.nmi_injected = false;
3293 kvm_clear_exception_queue(&svm->vcpu);
3294 kvm_clear_interrupt_queue(&svm->vcpu);
3295
3296 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3297 return;
3298
3842d135
AK		 3299 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3300
9222be18
GN		 3301 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3302 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3303
3304 switch (type) {
3305 case SVM_EXITINTINFO_TYPE_NMI:
3306 svm->vcpu.arch.nmi_injected = true;
3307 break;
3308 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3309 /*
3310 * In case of software exceptions, do not reinject the vector,
3311 * but re-execute the instruction instead. Rewind RIP first
3312 * if we emulated INT3 before.
3313 */
3314 if (kvm_exception_is_soft(vector)) {
3315 if (vector == BP_VECTOR && int3_injected &&
3316 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3317 kvm_rip_write(&svm->vcpu,
3318 kvm_rip_read(&svm->vcpu) -
3319 int3_injected);
9222be18 3320 break;
66b7138f 3321 }
9222be18
GN		 3322 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3323 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3324 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3325
3326 } else
ce7ddec4 3327 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3328 break;
3329 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3330 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3331 break;
3332 default:
3333 break;
3334 }
3335}
3336
b463a6f7
AK		 3337static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3338{
3339 struct vcpu_svm *svm = to_svm(vcpu);
3340 struct vmcb_control_area *control = &svm->vmcb->control;
3341
3342 control->exit_int_info = control->event_inj;
3343 control->exit_int_info_err = control->event_inj_err;
3344 control->event_inj = 0;
3345 svm_complete_interrupts(svm);
3346}
3347
404d5d7b 3348static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
a9ab13ff
WL		 3349{
3350 if (!is_guest_mode(vcpu) &&
3351 to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3352 to_svm(vcpu)->vmcb->control.exit_info_1)
3353 return handle_fastpath_set_msr_irqoff(vcpu);
3354
3355 return EXIT_FASTPATH_NONE;
3356}
3357
56a87e5d 3358void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
199cd1d7 3359
135961e0
TG		 3360static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3361 struct vcpu_svm *svm)
3362{
3363 /*
3364 * VMENTER enables interrupts (host state), but the kernel state is
3365 * interrupts disabled when this is invoked. Also tell RCU about
3366 * it. This is the same logic as for exit_to_user_mode().
3367 *
3368 * This ensures that e.g. latency analysis on the host observes
3369 * guest mode as interrupt enabled.
3370 *
3371 * guest_enter_irqoff() informs context tracking about the
3372 * transition to guest mode and if enabled adjusts RCU state
3373 * accordingly.
3374 */
3375 instrumentation_begin();
3376 trace_hardirqs_on_prepare();
3377 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3378 instrumentation_end();
3379
3380 guest_enter_irqoff();
3381 lockdep_hardirqs_on(CALLER_ADDR0);
3382
3383 __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3384
3385#ifdef CONFIG_X86_64
c3f08ed1 3386 native_wrmsrl(MSR_GS_BASE, svm->host.gs_base);
135961e0
TG		 3387#else
3388 loadsegment(fs, svm->host.fs);
3389#ifndef CONFIG_X86_32_LAZY_GS
3390 loadsegment(gs, svm->host.gs);
3391#endif
3392#endif
3393
3394 /*
3395 * VMEXIT disables interrupts (host state), but tracing and lockdep
3396 * have them in state 'on' as recorded before entering guest mode.
3397 * Same as enter_from_user_mode().
3398 *
3399 * guest_exit_irqoff() restores host context and reinstates RCU if
3400 * enabled and required.
3401 *
3402 * This needs to be done before the below as native_read_msr()
3403 * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3404 * into world and some more.
3405 */
3406 lockdep_hardirqs_off(CALLER_ADDR0);
3407 guest_exit_irqoff();
3408
3409 instrumentation_begin();
3410 trace_hardirqs_off_finish();
3411 instrumentation_end();
3412}
3413
b95273f1 3414static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3415{
404d5d7b 3416 fastpath_t exit_fastpath;
a2fa3e9f 3417 struct vcpu_svm *svm = to_svm(vcpu);
d9e368d6 3418
2041a06a
JR		 3419 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3420 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3421 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3422
a12713c2
LP		 3423 /*
3424 * Disable singlestep if we're injecting an interrupt/exception.
3425 * We don't want our modified rflags to be pushed on the stack where
3426 * we might not be able to easily reset them if we disabled NMI
3427 * singlestep later.
3428 */
3429 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3430 /*
3431 * Event injection happens before external interrupts cause a
3432 * vmexit and interrupts are disabled here, so smp_send_reschedule
3433 * is enough to force an immediate vmexit.
3434 */
3435 disable_nmi_singlestep(svm);
3436 smp_send_reschedule(vcpu->cpu);
3437 }
3438
e756fc62 3439 pre_svm_run(svm);
6aa8b732 3440
649d6864
JR		 3441 sync_lapic_to_cr8(vcpu);
3442
cda0ffdd 3443 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3444
d67668e9
PB		 3445 /*
3446 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3447 * of a #DB.
3448 */
3449 if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3450 svm_set_dr6(svm, vcpu->arch.dr6);
3451 else
3452 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3453
04d2cc77 3454 clgi();
139a12cf 3455 kvm_load_guest_xsave_state(vcpu);
04d2cc77 3456
b6c4bc65
WL		 3457 if (lapic_in_kernel(vcpu) &&
3458 vcpu->arch.apic->lapic_timer.timer_advance_ns)
3459 kvm_wait_lapic_expire(vcpu);
3460
b2ac58f9
KA		 3461 /*
3462 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3463 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3464 * is no need to worry about the conditional branch over the wrmsr
3465 * being speculatively taken.
3466 */
ccbcd267 3467 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
b2ac58f9 3468
135961e0 3469 svm_vcpu_enter_exit(vcpu, svm);
15e6c22f 3470
b2ac58f9
KA		 3471 /*
3472 * We do not use IBRS in the kernel. If this vCPU has used the
3473 * SPEC_CTRL MSR it may have left it on; save the value and
3474 * turn it off. This is much more efficient than blindly adding
3475 * it to the atomic save/restore list. Especially as the former
3476 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3477 *
3478 * For non-nested case:
3479 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3480 * save it.
3481 *
3482 * For nested case:
3483 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3484 * save it.
3485 */
946fbbc1 3486 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
ecb586bd 3487 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b2ac58f9 3488
6aa8b732
AK		 3489 reload_tss(vcpu);
3490
024d83ca
TG		 3491 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3492
13c34e07
AK		 3493 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3494 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3495 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3496 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3497
3781c01c 3498 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
dd60d217 3499 kvm_before_interrupt(&svm->vcpu);
3781c01c 3500
139a12cf 3501 kvm_load_host_xsave_state(vcpu);
3781c01c
JR		 3502 stgi();
3503
3504 /* Any pending NMI will happen here */
3505
3506 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
dd60d217 3507 kvm_after_interrupt(&svm->vcpu);
3781c01c 3508
d7bf8221
JR		 3509 sync_cr8_to_lapic(vcpu);
3510
a2fa3e9f 3511 svm->next_rip = 0;
2d8a42be
PB		 3512 if (is_guest_mode(&svm->vcpu)) {
3513 sync_nested_vmcb_control(svm);
3514 svm->nested.nested_run_pending = 0;
3515 }
9222be18 3516
38e5e92f 3517 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
e42c6828 3518 vmcb_mark_all_clean(svm->vmcb);
38e5e92f 3519
631bc487
GN		 3520 /* if exit due to PF check for async PF */
3521 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
68fd66f1
VK		 3522 svm->vcpu.arch.apf.host_apf_flags =
3523 kvm_read_and_reset_apf_flags();
631bc487 3524
6de4f3ad
AK		 3525 if (npt_enabled) {
3526 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3527 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3528 }
fe5913e4
JR		 3529
3530 /*
3531 * We need to handle MC intercepts here before the vcpu has a chance to
3532 * change the physical cpu
3533 */
3534 if (unlikely(svm->vmcb->control.exit_code ==
3535 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3536 svm_handle_mce(svm);
8d28fec4 3537
e42c6828
WL		 3538 svm_complete_interrupts(svm);
3539 exit_fastpath = svm_exit_handlers_fastpath(vcpu);
a9ab13ff 3540 return exit_fastpath;
6aa8b732
AK		 3541}
3542
2a40b900
SC		 3543static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root,
3544 int root_level)
6aa8b732 3545{
a2fa3e9f 3546 struct vcpu_svm *svm = to_svm(vcpu);
689f3bf2 3547 unsigned long cr3;
a2fa3e9f 3548
689f3bf2
PB		 3549 cr3 = __sme_set(root);
3550 if (npt_enabled) {
3551 svm->vmcb->control.nested_cr3 = cr3;
06e7852c 3552 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
1c97f0a0 3553
689f3bf2 3554 /* Loading L2's CR3 is handled by enter_svm_guest_mode. */
978ce583
PB		 3555 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3556 return;
3557 cr3 = vcpu->arch.cr3;
689f3bf2 3558 }
1c97f0a0 3559
978ce583 3560 svm->vmcb->save.cr3 = cr3;
06e7852c 3561 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1c97f0a0
JR		 3562}
3563
6aa8b732
AK		 3564static int is_disabled(void)
3565{
6031a61c
JR		 3566 u64 vm_cr;
3567
3568 rdmsrl(MSR_VM_CR, vm_cr);
3569 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3570 return 1;
3571
6aa8b732
AK		 3572 return 0;
3573}
3574
102d8325
IM		 3575static void
3576svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3577{
3578 /*
3579 * Patch in the VMMCALL instruction:
3580 */
3581 hypercall[0] = 0x0f;
3582 hypercall[1] = 0x01;
3583 hypercall[2] = 0xd9;
102d8325
IM		 3584}
3585
f257d6dc 3586static int __init svm_check_processor_compat(void)
002c7f7c 3587{
f257d6dc 3588 return 0;
002c7f7c
YS		 3589}
3590
774ead3a
AK		 3591static bool svm_cpu_has_accelerated_tpr(void)
3592{
3593 return false;
3594}
3595
cb97c2d6 3596static bool svm_has_emulated_msr(u32 index)
6d396b55 3597{
e87555e5
VK		 3598 switch (index) {
3599 case MSR_IA32_MCG_EXT_CTL:
95c5c7c7 3600 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
e87555e5
VK		 3601 return false;
3602 default:
3603 break;
3604 }
3605
6d396b55
PB		 3606 return true;
3607}
3608
fc07e76a
PB		 3609static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3610{
3611 return 0;
3612}
3613
7c1b761b 3614static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
0e851880 3615{
6092d3d3
JR		 3616 struct vcpu_svm *svm = to_svm(vcpu);
3617
7204160e 3618 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
96be4e06 3619 boot_cpu_has(X86_FEATURE_XSAVE) &&
7204160e
AL		 3620 boot_cpu_has(X86_FEATURE_XSAVES);
3621
6092d3d3 3622 /* Update nrips enabled cache */
4eb87460
SC		 3623 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3624 guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
46781eae
SS		 3625
3626 if (!kvm_vcpu_apicv_active(vcpu))
3627 return;
3628
cc7f5577
OU		 3629 /*
3630 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3631 * is exposed to the guest, disable AVIC.
3632 */
3633 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3634 kvm_request_apicv_update(vcpu->kvm, false,
3635 APICV_INHIBIT_REASON_X2APIC);
9a0bf054
SS		 3636
3637 /*
3638 * Currently, AVIC does not work with nested virtualization.
3639 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3640 */
3641 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3642 kvm_request_apicv_update(vcpu->kvm, false,
3643 APICV_INHIBIT_REASON_NESTED);
0e851880
SY		 3644}
3645
f5f48ee1
SY		 3646static bool svm_has_wbinvd_exit(void)
3647{
3648 return true;
3649}
3650
8061252e 3651#define PRE_EX(exit) { .exit_code = (exit), \
40e19b51 3652 .stage = X86_ICPT_PRE_EXCEPT, }
cfec82cb 3653#define POST_EX(exit) { .exit_code = (exit), \
40e19b51 3654 .stage = X86_ICPT_POST_EXCEPT, }
d7eb8203 3655#define POST_MEM(exit) { .exit_code = (exit), \
40e19b51 3656 .stage = X86_ICPT_POST_MEMACCESS, }
cfec82cb 3657
09941fbb 3658static const struct __x86_intercept {
cfec82cb
JR		 3659 u32 exit_code;
3660 enum x86_intercept_stage stage;
cfec82cb
JR		 3661} x86_intercept_map[] = {
3662 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
3663 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
3664 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
3665 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
3666 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
3b88e41a
JR		 3667 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
3668 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
dee6bb70
JR		 3669 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
3670 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
3671 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
3672 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
3673 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
3674 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
3675 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
3676 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
01de8b09
JR		 3677 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
3678 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
3679 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
3680 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
3681 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
3682 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
3683 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
3684 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
d7eb8203
JR		 3685 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
3686 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
3687 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
8061252e
JR		 3688 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
3689 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
3690 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
3691 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
3692 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
3693 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
3694 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
3695 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
3696 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
bf608f88
JR		 3697 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
3698 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
3699 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
3700 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
3701 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
3702 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
3703 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
f6511935
JR		 3704 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
3705 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
3706 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
3707 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
02d4160f 3708 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
cfec82cb
JR		 3709};
3710
8061252e 3711#undef PRE_EX
cfec82cb 3712#undef POST_EX
d7eb8203 3713#undef POST_MEM
cfec82cb 3714
8a76d7f2
JR		 3715static int svm_check_intercept(struct kvm_vcpu *vcpu,
3716 struct x86_instruction_info *info,
21f1b8f2
SC		 3717 enum x86_intercept_stage stage,
3718 struct x86_exception *exception)
8a76d7f2 3719{
cfec82cb
JR		 3720 struct vcpu_svm *svm = to_svm(vcpu);
3721 int vmexit, ret = X86EMUL_CONTINUE;
3722 struct __x86_intercept icpt_info;
3723 struct vmcb *vmcb = svm->vmcb;
3724
3725 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3726 goto out;
3727
3728 icpt_info = x86_intercept_map[info->intercept];
3729
40e19b51 3730 if (stage != icpt_info.stage)
cfec82cb
JR		 3731 goto out;
3732
3733 switch (icpt_info.exit_code) {
3734 case SVM_EXIT_READ_CR0:
3735 if (info->intercept == x86_intercept_cr_read)
3736 icpt_info.exit_code += info->modrm_reg;
3737 break;
3738 case SVM_EXIT_WRITE_CR0: {
3739 unsigned long cr0, val;
3740 u64 intercept;
3741
3742 if (info->intercept == x86_intercept_cr_write)
3743 icpt_info.exit_code += info->modrm_reg;
3744
62baf44c
JK		 3745 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3746 info->intercept == x86_intercept_clts)
cfec82cb
JR		 3747 break;
3748
e670bf68 3749 intercept = svm->nested.ctl.intercept;
cfec82cb
JR		 3750
3751 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
3752 break;
3753
3754 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3755 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
3756
3757 if (info->intercept == x86_intercept_lmsw) {
3758 cr0 &= 0xfUL;
3759 val &= 0xfUL;
3760 /* lmsw can't clear PE - catch this here */
3761 if (cr0 & X86_CR0_PE)
3762 val |= X86_CR0_PE;
3763 }
3764
3765 if (cr0 ^ val)
3766 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3767
3768 break;
3769 }
3b88e41a
JR		 3770 case SVM_EXIT_READ_DR0:
3771 case SVM_EXIT_WRITE_DR0:
3772 icpt_info.exit_code += info->modrm_reg;
3773 break;
8061252e
JR		 3774 case SVM_EXIT_MSR:
3775 if (info->intercept == x86_intercept_wrmsr)
3776 vmcb->control.exit_info_1 = 1;
3777 else
3778 vmcb->control.exit_info_1 = 0;
3779 break;
bf608f88
JR		 3780 case SVM_EXIT_PAUSE:
3781 /*
3782 * We get this for NOP only, but pause
3783 * is rep not, check this here
3784 */
3785 if (info->rep_prefix != REPE_PREFIX)
3786 goto out;
49a8afca 3787 break;
f6511935
JR		 3788 case SVM_EXIT_IOIO: {
3789 u64 exit_info;
3790 u32 bytes;
3791
f6511935
JR		 3792 if (info->intercept == x86_intercept_in ||
3793 info->intercept == x86_intercept_ins) {
6cbc5f5a
JK		 3794 exit_info = ((info->src_val & 0xffff) << 16) |
3795 SVM_IOIO_TYPE_MASK;
f6511935 3796 bytes = info->dst_bytes;
6493f157 3797 } else {
6cbc5f5a 3798 exit_info = (info->dst_val & 0xffff) << 16;
6493f157 3799 bytes = info->src_bytes;
f6511935
JR		 3800 }
3801
3802 if (info->intercept == x86_intercept_outs ||
3803 info->intercept == x86_intercept_ins)
3804 exit_info |= SVM_IOIO_STR_MASK;
3805
3806 if (info->rep_prefix)
3807 exit_info |= SVM_IOIO_REP_MASK;
3808
3809 bytes = min(bytes, 4u);
3810
3811 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
3812
3813 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
3814
3815 vmcb->control.exit_info_1 = exit_info;
3816 vmcb->control.exit_info_2 = info->next_rip;
3817
3818 break;
3819 }
cfec82cb
JR		 3820 default:
3821 break;
3822 }
3823
f104765b
BD		 3824 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
3825 if (static_cpu_has(X86_FEATURE_NRIPS))
3826 vmcb->control.next_rip = info->next_rip;
cfec82cb
JR		 3827 vmcb->control.exit_code = icpt_info.exit_code;
3828 vmexit = nested_svm_exit_handled(svm);
3829
3830 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
3831 : X86EMUL_CONTINUE;
3832
3833out:
3834 return ret;
8a76d7f2
JR		 3835}
3836
a9ab13ff 3837static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
a547c6db 3838{
a547c6db
YZ		 3839}
3840
ae97a3b8
RK		 3841static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
3842{
830f01b0 3843 if (!kvm_pause_in_guest(vcpu->kvm))
8566ac8b 3844 shrink_ple_window(vcpu);
ae97a3b8
RK		 3845}
3846
74f16909
BP		 3847static void svm_setup_mce(struct kvm_vcpu *vcpu)
3848{
3849 /* [63:9] are reserved. */
3850 vcpu->arch.mcg_cap &= 0x1ff;
3851}
3852
cae96af1 3853bool svm_smi_blocked(struct kvm_vcpu *vcpu)
72d7b374 3854{
05cade71
LP		 3855 struct vcpu_svm *svm = to_svm(vcpu);
3856
3857 /* Per APM Vol.2 15.22.2 "Response to SMI" */
3858 if (!gif_set(svm))
cae96af1
PB		 3859 return true;
3860
3861 return is_smm(vcpu);
3862}
3863
c9d40913 3864static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3865{
3866 struct vcpu_svm *svm = to_svm(vcpu);
3867 if (svm->nested.nested_run_pending)
c9d40913 3868 return -EBUSY;
05cade71 3869
c300ab9f
PB		 3870 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
3871 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
c9d40913 3872 return -EBUSY;
c300ab9f 3873
cae96af1 3874 return !svm_smi_blocked(vcpu);
72d7b374
LP		 3875}
3876
0234bf88
LP		 3877static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
3878{
05cade71
LP		 3879 struct vcpu_svm *svm = to_svm(vcpu);
3880 int ret;
3881
3882 if (is_guest_mode(vcpu)) {
3883 /* FED8h - SVM Guest */
3884 put_smstate(u64, smstate, 0x7ed8, 1);
3885 /* FEE0h - SVM Guest VMCB Physical Address */
3886 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
3887
3888 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3889 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3890 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3891
3892 ret = nested_svm_vmexit(svm);
3893 if (ret)
3894 return ret;
3895 }
0234bf88
LP		 3896 return 0;
3897}
3898
ed19321f 3899static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
0234bf88 3900{
05cade71
LP		 3901 struct vcpu_svm *svm = to_svm(vcpu);
3902 struct vmcb *nested_vmcb;
8c5fbf1a 3903 struct kvm_host_map map;
ed19321f
SC		 3904 u64 guest;
3905 u64 vmcb;
59cd9bc5 3906 int ret = 0;
05cade71 3907
ed19321f
SC		 3908 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
3909 vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
05cade71 3910
ed19321f 3911 if (guest) {
8c5fbf1a 3912 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
9ec19493 3913 return 1;
8c5fbf1a 3914 nested_vmcb = map.hva;
59cd9bc5 3915 ret = enter_svm_guest_mode(svm, vmcb, nested_vmcb);
69c9dfa2 3916 kvm_vcpu_unmap(&svm->vcpu, &map, true);
05cade71 3917 }
59cd9bc5
VK		 3918
3919 return ret;
0234bf88
LP		 3920}
3921
c9d40913 3922static void enable_smi_window(struct kvm_vcpu *vcpu)
cc3d967f
LP		 3923{
3924 struct vcpu_svm *svm = to_svm(vcpu);
3925
3926 if (!gif_set(svm)) {
3927 if (vgif_enabled(svm))
a284ba56 3928 svm_set_intercept(svm, INTERCEPT_STGI);
cc3d967f 3929 /* STGI will cause a vm exit */
c9d40913
PB		 3930 } else {
3931 /* We must be in SMM; RSM will cause a vmexit anyway. */
cc3d967f 3932 }
cc3d967f
LP		 3933}
3934
05d5a486
SB		 3935static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
3936{
118154bd
LA		 3937 unsigned long cr4 = kvm_read_cr4(vcpu);
3938 bool smep = cr4 & X86_CR4_SMEP;
3939 bool smap = cr4 & X86_CR4_SMAP;
3940 bool is_user = svm_get_cpl(vcpu) == 3;
05d5a486 3941
e72436bc
PB		 3942 /*
3943 * If RIP is invalid, go ahead with emulation which will cause an
3944 * internal error exit.
3945 */
3946 if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
3947 return true;
3948
05d5a486 3949 /*
118154bd
LA		 3950 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
3951 *
3952 * Errata:
3953 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
3954 * possible that CPU microcode implementing DecodeAssist will fail
3955 * to read bytes of instruction which caused #NPF. In this case,
3956 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
3957 * return 0 instead of the correct guest instruction bytes.
3958 *
3959 * This happens because CPU microcode reading instruction bytes
3960 * uses a special opcode which attempts to read data using CPL=0
3961 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
3962 * fault, it gives up and returns no instruction bytes.
3963 *
3964 * Detection:
3965 * We reach here in case CPU supports DecodeAssist, raised #NPF and
3966 * returned 0 in GuestIntrBytes field of the VMCB.
3967 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
3968 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
3969 * in case vCPU CPL==3 (Because otherwise guest would have triggered
3970 * a SMEP fault instead of #NPF).
3971 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
3972 * As most guests enable SMAP if they have also enabled SMEP, use above
3973 * logic in order to attempt minimize false-positive of detecting errata
3974 * while still preserving all cases semantic correctness.
3975 *
3976 * Workaround:
3977 * To determine what instruction the guest was executing, the hypervisor
3978 * will have to decode the instruction at the instruction pointer.
05d5a486
SB		 3979 *
3980 * In non SEV guest, hypervisor will be able to read the guest
3981 * memory to decode the instruction pointer when insn_len is zero
3982 * so we return true to indicate that decoding is possible.
3983 *
3984 * But in the SEV guest, the guest memory is encrypted with the
3985 * guest specific key and hypervisor will not be able to decode the
3986 * instruction pointer so we will not able to workaround it. Lets
3987 * print the error and request to kill the guest.
3988 */
118154bd 3989 if (smap && (!smep || is_user)) {
05d5a486
SB		 3990 if (!sev_guest(vcpu->kvm))
3991 return true;
3992
118154bd 3993 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
05d5a486
SB		 3994 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3995 }
3996
3997 return false;
3998}
3999
4b9852f4
LA		 4000static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4001{
4002 struct vcpu_svm *svm = to_svm(vcpu);
4003
4004 /*
4005 * TODO: Last condition latch INIT signals on vCPU when
4006 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
33b22172
PB		 4007 * To properly emulate the INIT intercept,
4008 * svm_check_nested_events() should call nested_svm_vmexit()
4009 * if an INIT signal is pending.
4b9852f4
LA		 4010 */
4011 return !gif_set(svm) ||
4012 (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT));
4013}
4014
eaf78265
JR		 4015static void svm_vm_destroy(struct kvm *kvm)
4016{
4017 avic_vm_destroy(kvm);
4018 sev_vm_destroy(kvm);
4019}
4020
4021static int svm_vm_init(struct kvm *kvm)
4022{
830f01b0
WL		 4023 if (!pause_filter_count || !pause_filter_thresh)
4024 kvm->arch.pause_in_guest = true;
4025
eaf78265
JR		 4026 if (avic) {
4027 int ret = avic_vm_init(kvm);
4028 if (ret)
4029 return ret;
4030 }
4031
4032 kvm_apicv_init(kvm, avic);
4033 return 0;
4034}
4035
9c14ee21 4036static struct kvm_x86_ops svm_x86_ops __initdata = {
dd58f3c9 4037 .hardware_unsetup = svm_hardware_teardown,
6aa8b732
AK		 4038 .hardware_enable = svm_hardware_enable,
4039 .hardware_disable = svm_hardware_disable,
774ead3a 4040 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
bc226f07 4041 .has_emulated_msr = svm_has_emulated_msr,
6aa8b732
AK		 4042
4043 .vcpu_create = svm_create_vcpu,
4044 .vcpu_free = svm_free_vcpu,
04d2cc77 4045 .vcpu_reset = svm_vcpu_reset,
6aa8b732 4046
562b6b08 4047 .vm_size = sizeof(struct kvm_svm),
4e19c36f 4048 .vm_init = svm_vm_init,
1654efcb 4049 .vm_destroy = svm_vm_destroy,
44a95dae 4050
04d2cc77 4051 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 4052 .vcpu_load = svm_vcpu_load,
4053 .vcpu_put = svm_vcpu_put,
8221c137
SS		 4054 .vcpu_blocking = svm_vcpu_blocking,
4055 .vcpu_unblocking = svm_vcpu_unblocking,
6aa8b732 4056
6986982f 4057 .update_exception_bitmap = update_exception_bitmap,
801e459a 4058 .get_msr_feature = svm_get_msr_feature,
6aa8b732
AK		 4059 .get_msr = svm_get_msr,
4060 .set_msr = svm_set_msr,
4061 .get_segment_base = svm_get_segment_base,
4062 .get_segment = svm_get_segment,
4063 .set_segment = svm_set_segment,
2e4d2653 4064 .get_cpl = svm_get_cpl,
1747fb71 4065 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
6aa8b732 4066 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 4067 .set_cr4 = svm_set_cr4,
4068 .set_efer = svm_set_efer,
4069 .get_idt = svm_get_idt,
4070 .set_idt = svm_set_idt,
4071 .get_gdt = svm_get_gdt,
4072 .set_gdt = svm_set_gdt,
020df079 4073 .set_dr7 = svm_set_dr7,
facb0139 4074 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
6de4f3ad 4075 .cache_reg = svm_cache_reg,
6aa8b732
AK		 4076 .get_rflags = svm_get_rflags,
4077 .set_rflags = svm_set_rflags,
be94f6b7 4078
7780938c 4079 .tlb_flush_all = svm_flush_tlb,
eeeb4f67 4080 .tlb_flush_current = svm_flush_tlb,
faff8758 4081 .tlb_flush_gva = svm_flush_tlb_gva,
72b38320 4082 .tlb_flush_guest = svm_flush_tlb,
6aa8b732 4083
6aa8b732 4084 .run = svm_vcpu_run,
04d2cc77 4085 .handle_exit = handle_exit,
6aa8b732 4086 .skip_emulated_instruction = skip_emulated_instruction,
5ef8acbd 4087 .update_emulated_instruction = NULL,
2809f5d2
GC		 4088 .set_interrupt_shadow = svm_set_interrupt_shadow,
4089 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 4090 .patch_hypercall = svm_patch_hypercall,
2a8067f1 4091 .set_irq = svm_set_irq,
95ba8273 4092 .set_nmi = svm_inject_nmi,
298101da 4093 .queue_exception = svm_queue_exception,
b463a6f7 4094 .cancel_injection = svm_cancel_injection,
78646121 4095 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 4096 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 4097 .get_nmi_mask = svm_get_nmi_mask,
4098 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 4099 .enable_nmi_window = enable_nmi_window,
4100 .enable_irq_window = enable_irq_window,
4101 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 4102 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
d62caabb 4103 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
ef8efd7a 4104 .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
2de9d0cc 4105 .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
c7c9c56c 4106 .load_eoi_exitmap = svm_load_eoi_exitmap,
44a95dae
SS		 4107 .hwapic_irr_update = svm_hwapic_irr_update,
4108 .hwapic_isr_update = svm_hwapic_isr_update,
fa59cc00 4109 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
be8ca170 4110 .apicv_post_state_restore = avic_post_state_restore,
cbc94022
IE		 4111
4112 .set_tss_addr = svm_set_tss_addr,
2ac52ab8 4113 .set_identity_map_addr = svm_set_identity_map_addr,
4b12f0de 4114 .get_mt_mask = svm_get_mt_mask,
229456fc 4115
586f9607 4116 .get_exit_info = svm_get_exit_info,
586f9607 4117
7c1b761b 4118 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4e47c7a6 4119
f5f48ee1 4120 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a 4121
326e7425 4122 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
1c97f0a0 4123
727a7e27 4124 .load_mmu_pgd = svm_load_mmu_pgd,
8a76d7f2
JR		 4125
4126 .check_intercept = svm_check_intercept,
95b5a48c 4127 .handle_exit_irqoff = svm_handle_exit_irqoff,
ae97a3b8 4128
d264ee0c
SC		 4129 .request_immediate_exit = __kvm_request_immediate_exit,
4130
ae97a3b8 4131 .sched_in = svm_sched_in,
25462f7f
WH		 4132
4133 .pmu_ops = &amd_pmu_ops,
33b22172
PB		 4134 .nested_ops = &svm_nested_ops,
4135
340d3bc3 4136 .deliver_posted_interrupt = svm_deliver_avic_intr,
17e433b5 4137 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
411b44ba 4138 .update_pi_irte = svm_update_pi_irte,
74f16909 4139 .setup_mce = svm_setup_mce,
0234bf88 4140
72d7b374 4141 .smi_allowed = svm_smi_allowed,
0234bf88
LP		 4142 .pre_enter_smm = svm_pre_enter_smm,
4143 .pre_leave_smm = svm_pre_leave_smm,
cc3d967f 4144 .enable_smi_window = enable_smi_window,
1654efcb
BS		 4145
4146 .mem_enc_op = svm_mem_enc_op,
1e80fdc0
BS		 4147 .mem_enc_reg_region = svm_register_enc_region,
4148 .mem_enc_unreg_region = svm_unregister_enc_region,
57b119da 4149
05d5a486 4150 .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
4b9852f4
LA		 4151
4152 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
6aa8b732
AK		 4153};
4154
d008dfdb
SC		 4155static struct kvm_x86_init_ops svm_init_ops __initdata = {
4156 .cpu_has_kvm_support = has_svm,
4157 .disabled_by_bios = is_disabled,
4158 .hardware_setup = svm_hardware_setup,
4159 .check_processor_compatibility = svm_check_processor_compat,
4160
4161 .runtime_ops = &svm_x86_ops,
6aa8b732
AK		 4162};
4163
4164static int __init svm_init(void)
4165{
d008dfdb 4166 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
0ee75bea 4167 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 4168}
4169
4170static void __exit svm_exit(void)
4171{
cb498ea2 4172 kvm_exit();
6aa8b732
AK		 4173}
4174
4175module_init(svm_init)
4176module_exit(svm_exit)
Ubuntu Hirsute Linux kernel mirror