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KVM: X86: Move handling of INVPCID types to x86
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / svm / svm.c
CommitLineData
44a95dae
SS		 1#define pr_fmt(fmt) "SVM: " fmt
2
edf88417
AK		 3#include <linux/kvm_host.h>
4
85f455f7 5#include "irq.h"
1d737c8a 6#include "mmu.h"
5fdbf976 7#include "kvm_cache_regs.h"
fe4c7b19 8#include "x86.h"
66f7b72e 9#include "cpuid.h"
25462f7f 10#include "pmu.h"
e495606d 11
6aa8b732 12#include <linux/module.h>
ae759544 13#include <linux/mod_devicetable.h>
9d8f549d 14#include <linux/kernel.h>
6aa8b732
AK		 15#include <linux/vmalloc.h>
16#include <linux/highmem.h>
ef0f6496 17#include <linux/amd-iommu.h>
e8edc6e0 18#include <linux/sched.h>
af658dca 19#include <linux/trace_events.h>
5a0e3ad6 20#include <linux/slab.h>
5881f737 21#include <linux/hashtable.h>
c207aee4 22#include <linux/frame.h>
e9df0942 23#include <linux/psp-sev.h>
1654efcb 24#include <linux/file.h>
89c50580
BS		 25#include <linux/pagemap.h>
26#include <linux/swap.h>
33af3a7e 27#include <linux/rwsem.h>
6aa8b732 28
8221c137 29#include <asm/apic.h>
1018faa6 30#include <asm/perf_event.h>
67ec6607 31#include <asm/tlbflush.h>
e495606d 32#include <asm/desc.h>
facb0139 33#include <asm/debugreg.h>
631bc487 34#include <asm/kvm_para.h>
411b44ba 35#include <asm/irq_remapping.h>
1c164cb3 36#include <asm/mce.h>
28a27752 37#include <asm/spec-ctrl.h>
ba5bade4 38#include <asm/cpu_device_id.h>
6aa8b732 39
63d1142f 40#include <asm/virtext.h>
229456fc 41#include "trace.h"
63d1142f 42
883b0a91
JR		 43#include "svm.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
575b255c 50#ifdef MODULE
ae759544 51static const struct x86_cpu_id svm_cpu_id[] = {
320debe5 52 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
ae759544
JT		 53 {}
54};
55MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
575b255c 56#endif
ae759544 57
6aa8b732
AK		 58#define IOPM_ALLOC_ORDER 2
59#define MSRPM_ALLOC_ORDER 1
60
6aa8b732
AK		 61#define SEG_TYPE_LDT 2
62#define SEG_TYPE_BUSY_TSS16 3
63
6bc31bdc
AP		 64#define SVM_FEATURE_LBRV (1 << 1)
65#define SVM_FEATURE_SVML (1 << 2)
ddce97aa
AP		 66#define SVM_FEATURE_TSC_RATE (1 << 4)
67#define SVM_FEATURE_VMCB_CLEAN (1 << 5)
68#define SVM_FEATURE_FLUSH_ASID (1 << 6)
69#define SVM_FEATURE_DECODE_ASSIST (1 << 7)
6bc31bdc 70#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 71
24e09cbf
JR		 72#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
73
fbc0db76 74#define TSC_RATIO_RSVD 0xffffff0000000000ULL
92a1f12d
JR		 75#define TSC_RATIO_MIN 0x0000000000000001ULL
76#define TSC_RATIO_MAX 0x000000ffffffffffULL
fbc0db76 77
67ec6607
JR		 78static bool erratum_383_found __read_mostly;
79
883b0a91 80u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
323c3d80 81
2b036c6b
BO		 82/*
83 * Set osvw_len to higher value when updated Revision Guides
84 * are published and we know what the new status bits are
85 */
86static uint64_t osvw_len = 4, osvw_status;
87
fbc0db76
JR		 88static DEFINE_PER_CPU(u64, current_tsc_ratio);
89#define TSC_RATIO_DEFAULT 0x0100000000ULL
90
09941fbb 91static const struct svm_direct_access_msrs {
ac72a9b7
JR		 92 u32 index; /* Index of the MSR */
93 bool always; /* True if intercept is always on */
94} direct_access_msrs[] = {
8c06585d 95 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 96 { .index = MSR_IA32_SYSENTER_CS, .always = true },
97#ifdef CONFIG_X86_64
98 { .index = MSR_GS_BASE, .always = true },
99 { .index = MSR_FS_BASE, .always = true },
100 { .index = MSR_KERNEL_GS_BASE, .always = true },
101 { .index = MSR_LSTAR, .always = true },
102 { .index = MSR_CSTAR, .always = true },
103 { .index = MSR_SYSCALL_MASK, .always = true },
104#endif
b2ac58f9 105 { .index = MSR_IA32_SPEC_CTRL, .always = false },
15d45071 106 { .index = MSR_IA32_PRED_CMD, .always = false },
ac72a9b7
JR		 107 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
108 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
109 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
110 { .index = MSR_IA32_LASTINTTOIP, .always = false },
111 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 112};
113
709ddebf
JR		 114/* enable NPT for AMD64 and X86 with PAE */
115#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
883b0a91 116bool npt_enabled = true;
709ddebf 117#else
883b0a91 118bool npt_enabled;
709ddebf 119#endif
6c7dac72 120
8566ac8b
BM		 121/*
122 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
123 * pause_filter_count: On processors that support Pause filtering(indicated
124 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
125 * count value. On VMRUN this value is loaded into an internal counter.
126 * Each time a pause instruction is executed, this counter is decremented
127 * until it reaches zero at which time a #VMEXIT is generated if pause
128 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
129 * Intercept Filtering for more details.
130 * This also indicate if ple logic enabled.
131 *
132 * pause_filter_thresh: In addition, some processor families support advanced
133 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
134 * the amount of time a guest is allowed to execute in a pause loop.
135 * In this mode, a 16-bit pause filter threshold field is added in the
136 * VMCB. The threshold value is a cycle count that is used to reset the
137 * pause counter. As with simple pause filtering, VMRUN loads the pause
138 * count value from VMCB into an internal counter. Then, on each pause
139 * instruction the hardware checks the elapsed number of cycles since
140 * the most recent pause instruction against the pause filter threshold.
141 * If the elapsed cycle count is greater than the pause filter threshold,
142 * then the internal pause count is reloaded from the VMCB and execution
143 * continues. If the elapsed cycle count is less than the pause filter
144 * threshold, then the internal pause count is decremented. If the count
145 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
146 * triggered. If advanced pause filtering is supported and pause filter
147 * threshold field is set to zero, the filter will operate in the simpler,
148 * count only mode.
149 */
150
151static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
152module_param(pause_filter_thresh, ushort, 0444);
153
154static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
155module_param(pause_filter_count, ushort, 0444);
156
157/* Default doubles per-vcpu window every exit. */
158static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
159module_param(pause_filter_count_grow, ushort, 0444);
160
161/* Default resets per-vcpu window every exit to pause_filter_count. */
162static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
163module_param(pause_filter_count_shrink, ushort, 0444);
164
165/* Default is to compute the maximum so we can never overflow. */
166static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
167module_param(pause_filter_count_max, ushort, 0444);
168
e2358851
DB		 169/* allow nested paging (virtualized MMU) for all guests */
170static int npt = true;
6c7dac72 171module_param(npt, int, S_IRUGO);
e3da3acd 172
e2358851
DB		 173/* allow nested virtualization in KVM/SVM */
174static int nested = true;
236de055
AG		 175module_param(nested, int, S_IRUGO);
176
d647eb63
PB		 177/* enable/disable Next RIP Save */
178static int nrips = true;
179module_param(nrips, int, 0444);
180
89c8a498
JN		 181/* enable/disable Virtual VMLOAD VMSAVE */
182static int vls = true;
183module_param(vls, int, 0444);
184
640bd6e5
JN		 185/* enable/disable Virtual GIF */
186static int vgif = true;
187module_param(vgif, int, 0444);
5ea11f2b 188
e9df0942
BS		 189/* enable/disable SEV support */
190static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
191module_param(sev, int, 0444);
192
6f2f8453
PB		 193static bool __read_mostly dump_invalid_vmcb = 0;
194module_param(dump_invalid_vmcb, bool, 0644);
195
7607b717
BS		 196static u8 rsm_ins_bytes[] = "\x0f\xaa";
197
a5c3832d 198static void svm_complete_interrupts(struct vcpu_svm *svm);
44a95dae 199
4866d5e3 200static unsigned long iopm_base;
6aa8b732
AK		 201
202struct kvm_ldttss_desc {
203 u16 limit0;
204 u16 base0;
e0231715
JR		 205 unsigned base1:8, type:5, dpl:2, p:1;
206 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 207 u32 base3;
208 u32 zero1;
209} __attribute__((packed));
210
eaf78265 211DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
6aa8b732 212
09941fbb 213static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
6aa8b732 214
9d8f549d 215#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 216#define MSRS_RANGE_SIZE 2048
217#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
218
883b0a91 219u32 svm_msrpm_offset(u32 msr)
455716fa
JR		 220{
221 u32 offset;
222 int i;
223
224 for (i = 0; i < NUM_MSR_MAPS; i++) {
225 if (msr < msrpm_ranges[i] ||
226 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
227 continue;
228
229 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
230 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
231
232 /* Now we have the u8 offset - but need the u32 offset */
233 return offset / 4;
234 }
235
236 /* MSR not in any range */
237 return MSR_INVALID;
238}
239
6aa8b732
AK		 240#define MAX_INST_SIZE 15
241
6aa8b732
AK		 242static inline void clgi(void)
243{
ac5ffda2 244 asm volatile (__ex("clgi"));
6aa8b732
AK		 245}
246
247static inline void stgi(void)
248{
ac5ffda2 249 asm volatile (__ex("stgi"));
6aa8b732
AK		 250}
251
252static inline void invlpga(unsigned long addr, u32 asid)
253{
ac5ffda2 254 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
6aa8b732
AK		 255}
256
d468d94b 257static int get_max_npt_level(void)
4b16184c
JR		 258{
259#ifdef CONFIG_X86_64
2a7266a8 260 return PT64_ROOT_4LEVEL;
4b16184c
JR		 261#else
262 return PT32E_ROOT_LEVEL;
263#endif
264}
265
883b0a91 266void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
6aa8b732 267{
c513f484 268 struct vcpu_svm *svm = to_svm(vcpu);
6dc696d4 269 vcpu->arch.efer = efer;
9167ab79
PB		 270
271 if (!npt_enabled) {
272 /* Shadow paging assumes NX to be available. */
273 efer |= EFER_NX;
274
275 if (!(efer & EFER_LMA))
276 efer &= ~EFER_LME;
277 }
6aa8b732 278
c513f484
PB		 279 if (!(efer & EFER_SVME)) {
280 svm_leave_nested(svm);
281 svm_set_gif(svm, true);
282 }
283
284 svm->vmcb->save.efer = efer | EFER_SVME;
06e7852c 285 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
6aa8b732
AK		 286}
287
6aa8b732
AK		 288static int is_external_interrupt(u32 info)
289{
290 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
291 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
292}
293
37ccdcbe 294static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 295{
296 struct vcpu_svm *svm = to_svm(vcpu);
297 u32 ret = 0;
298
299 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
37ccdcbe
PB		 300 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
301 return ret;
2809f5d2
GC		 302}
303
304static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
305{
306 struct vcpu_svm *svm = to_svm(vcpu);
307
308 if (mask == 0)
309 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
310 else
311 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
312
313}
314
f8ea7c60 315static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
6aa8b732 316{
a2fa3e9f
GH		 317 struct vcpu_svm *svm = to_svm(vcpu);
318
d647eb63 319 if (nrips && svm->vmcb->control.next_rip != 0) {
d2922422 320 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
6bc31bdc 321 svm->next_rip = svm->vmcb->control.next_rip;
f104765b 322 }
6bc31bdc 323
1957aa63
SC		 324 if (!svm->next_rip) {
325 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
326 return 0;
327 } else {
1957aa63
SC		 328 kvm_rip_write(vcpu, svm->next_rip);
329 }
2809f5d2 330 svm_set_interrupt_shadow(vcpu, 0);
f8ea7c60 331
60fc3d02 332 return 1;
6aa8b732
AK		 333}
334
cfcd20e5 335static void svm_queue_exception(struct kvm_vcpu *vcpu)
116a4752
JK		 336{
337 struct vcpu_svm *svm = to_svm(vcpu);
cfcd20e5
WL		 338 unsigned nr = vcpu->arch.exception.nr;
339 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 340 u32 error_code = vcpu->arch.exception.error_code;
116a4752 341
da998b46
JM		 342 kvm_deliver_exception_payload(&svm->vcpu);
343
d647eb63 344 if (nr == BP_VECTOR && !nrips) {
66b7138f
JK		 345 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
346
347 /*
348 * For guest debugging where we have to reinject #BP if some
349 * INT3 is guest-owned:
350 * Emulate nRIP by moving RIP forward. Will fail if injection
351 * raises a fault that is not intercepted. Still better than
352 * failing in all cases.
353 */
f8ea7c60 354 (void)skip_emulated_instruction(&svm->vcpu);
66b7138f
JK		 355 rip = kvm_rip_read(&svm->vcpu);
356 svm->int3_rip = rip + svm->vmcb->save.cs.base;
357 svm->int3_injected = rip - old_rip;
358 }
359
116a4752
JK		 360 svm->vmcb->control.event_inj = nr
361 | SVM_EVTINJ_VALID
362 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
363 | SVM_EVTINJ_TYPE_EXEPT;
364 svm->vmcb->control.event_inj_err = error_code;
365}
366
67ec6607
JR		 367static void svm_init_erratum_383(void)
368{
369 u32 low, high;
370 int err;
371 u64 val;
372
e6ee94d5 373 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
67ec6607
JR		 374 return;
375
376 /* Use _safe variants to not break nested virtualization */
377 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
378 if (err)
379 return;
380
381 val |= (1ULL << 47);
382
383 low = lower_32_bits(val);
384 high = upper_32_bits(val);
385
386 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
387
388 erratum_383_found = true;
389}
390
2b036c6b
BO		 391static void svm_init_osvw(struct kvm_vcpu *vcpu)
392{
393 /*
394 * Guests should see errata 400 and 415 as fixed (assuming that
395 * HLT and IO instructions are intercepted).
396 */
397 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
398 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
399
400 /*
401 * By increasing VCPU's osvw.length to 3 we are telling the guest that
402 * all osvw.status bits inside that length, including bit 0 (which is
403 * reserved for erratum 298), are valid. However, if host processor's
404 * osvw_len is 0 then osvw_status[0] carries no information. We need to
405 * be conservative here and therefore we tell the guest that erratum 298
406 * is present (because we really don't know).
407 */
408 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
409 vcpu->arch.osvw.status |= 1;
410}
411
6aa8b732
AK		 412static int has_svm(void)
413{
63d1142f 414 const char *msg;
6aa8b732 415
63d1142f 416 if (!cpu_has_svm(&msg)) {
ff81ff10 417 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 418 return 0;
419 }
420
6aa8b732
AK		 421 return 1;
422}
423
13a34e06 424static void svm_hardware_disable(void)
6aa8b732 425{
fbc0db76
JR		 426 /* Make sure we clean up behind us */
427 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
428 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
429
2c8dceeb 430 cpu_svm_disable();
1018faa6
JR		 431
432 amd_pmu_disable_virt();
6aa8b732
AK		 433}
434
13a34e06 435static int svm_hardware_enable(void)
6aa8b732
AK		 436{
437
0fe1e009 438 struct svm_cpu_data *sd;
6aa8b732 439 uint64_t efer;
6aa8b732
AK		 440 struct desc_struct *gdt;
441 int me = raw_smp_processor_id();
442
10474ae8
AG		 443 rdmsrl(MSR_EFER, efer);
444 if (efer & EFER_SVME)
445 return -EBUSY;
446
6aa8b732 447 if (!has_svm()) {
1f5b77f5 448 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
10474ae8 449 return -EINVAL;
6aa8b732 450 }
0fe1e009 451 sd = per_cpu(svm_data, me);
0fe1e009 452 if (!sd) {
1f5b77f5 453 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
10474ae8 454 return -EINVAL;
6aa8b732
AK		 455 }
456
0fe1e009
TH		 457 sd->asid_generation = 1;
458 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
459 sd->next_asid = sd->max_asid + 1;
ed3cd233 460 sd->min_asid = max_sev_asid + 1;
6aa8b732 461
45fc8757 462 gdt = get_current_gdt_rw();
0fe1e009 463 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 464
9962d032 465 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 466
d0316554 467 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 468
fbc0db76
JR		 469 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
470 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
89cbc767 471 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
fbc0db76
JR		 472 }
473
2b036c6b
BO		 474
475 /*
476 * Get OSVW bits.
477 *
478 * Note that it is possible to have a system with mixed processor
479 * revisions and therefore different OSVW bits. If bits are not the same
480 * on different processors then choose the worst case (i.e. if erratum
481 * is present on one processor and not on another then assume that the
482 * erratum is present everywhere).
483 */
484 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
485 uint64_t len, status = 0;
486 int err;
487
488 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
489 if (!err)
490 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
491 &err);
492
493 if (err)
494 osvw_status = osvw_len = 0;
495 else {
496 if (len < osvw_len)
497 osvw_len = len;
498 osvw_status |= status;
499 osvw_status &= (1ULL << osvw_len) - 1;
500 }
501 } else
502 osvw_status = osvw_len = 0;
503
67ec6607
JR		 504 svm_init_erratum_383();
505
1018faa6
JR		 506 amd_pmu_enable_virt();
507
10474ae8 508 return 0;
6aa8b732
AK		 509}
510
0da1db75
JR		 511static void svm_cpu_uninit(int cpu)
512{
0fe1e009 513 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 514
0fe1e009 515 if (!sd)
0da1db75
JR		 516 return;
517
518 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
70cd94e6 519 kfree(sd->sev_vmcbs);
0fe1e009
TH		 520 __free_page(sd->save_area);
521 kfree(sd);
0da1db75
JR		 522}
523
6aa8b732
AK		 524static int svm_cpu_init(int cpu)
525{
0fe1e009 526 struct svm_cpu_data *sd;
6aa8b732 527
0fe1e009
TH		 528 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
529 if (!sd)
6aa8b732 530 return -ENOMEM;
0fe1e009 531 sd->cpu = cpu;
70cd94e6 532 sd->save_area = alloc_page(GFP_KERNEL);
0fe1e009 533 if (!sd->save_area)
d80b64ff 534 goto free_cpu_data;
6aa8b732 535
70cd94e6 536 if (svm_sev_enabled()) {
6da2ec56
KC		 537 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
538 sizeof(void *),
539 GFP_KERNEL);
70cd94e6 540 if (!sd->sev_vmcbs)
d80b64ff 541 goto free_save_area;
70cd94e6
BS		 542 }
543
0fe1e009 544 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 545
546 return 0;
547
d80b64ff
ML		 548free_save_area:
549 __free_page(sd->save_area);
550free_cpu_data:
0fe1e009 551 kfree(sd);
d80b64ff 552 return -ENOMEM;
6aa8b732
AK		 553
554}
555
ac72a9b7
JR		 556static bool valid_msr_intercept(u32 index)
557{
558 int i;
559
560 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
561 if (direct_access_msrs[i].index == index)
562 return true;
563
564 return false;
565}
566
b2ac58f9
KA		 567static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
568{
569 u8 bit_write;
570 unsigned long tmp;
571 u32 offset;
572 u32 *msrpm;
573
574 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
575 to_svm(vcpu)->msrpm;
576
577 offset = svm_msrpm_offset(msr);
578 bit_write = 2 * (msr & 0x0f) + 1;
579 tmp = msrpm[offset];
580
581 BUG_ON(offset == MSR_INVALID);
582
583 return !!test_bit(bit_write, &tmp);
584}
585
bfc733a7
RR		 586static void set_msr_interception(u32 *msrpm, unsigned msr,
587 int read, int write)
6aa8b732 588{
455716fa
JR		 589 u8 bit_read, bit_write;
590 unsigned long tmp;
591 u32 offset;
6aa8b732 592
ac72a9b7
JR		 593 /*
594 * If this warning triggers extend the direct_access_msrs list at the
595 * beginning of the file
596 */
597 WARN_ON(!valid_msr_intercept(msr));
598
455716fa
JR		 599 offset = svm_msrpm_offset(msr);
600 bit_read = 2 * (msr & 0x0f);
601 bit_write = 2 * (msr & 0x0f) + 1;
602 tmp = msrpm[offset];
603
604 BUG_ON(offset == MSR_INVALID);
605
606 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
607 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
608
609 msrpm[offset] = tmp;
6aa8b732
AK		 610}
611
f4c847a9 612static u32 *svm_vcpu_init_msrpm(void)
6aa8b732
AK		 613{
614 int i;
f4c847a9
ML		 615 u32 *msrpm;
616 struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
617
618 if (!pages)
619 return NULL;
6aa8b732 620
f4c847a9 621 msrpm = page_address(pages);
f65c229c
JR		 622 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
623
ac72a9b7
JR		 624 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
625 if (!direct_access_msrs[i].always)
626 continue;
ac72a9b7
JR		 627 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
628 }
f4c847a9
ML		 629 return msrpm;
630}
631
632static void svm_vcpu_free_msrpm(u32 *msrpm)
633{
634 __free_pages(virt_to_page(msrpm), MSRPM_ALLOC_ORDER);
f65c229c
JR		 635}
636
323c3d80
JR		 637static void add_msr_offset(u32 offset)
638{
639 int i;
640
641 for (i = 0; i < MSRPM_OFFSETS; ++i) {
642
643 /* Offset already in list? */
644 if (msrpm_offsets[i] == offset)
bfc733a7 645 return;
323c3d80
JR		 646
647 /* Slot used by another offset? */
648 if (msrpm_offsets[i] != MSR_INVALID)
649 continue;
650
651 /* Add offset to list */
652 msrpm_offsets[i] = offset;
653
654 return;
6aa8b732 655 }
323c3d80
JR		 656
657 /*
658 * If this BUG triggers the msrpm_offsets table has an overflow. Just
659 * increase MSRPM_OFFSETS in this case.
660 */
bfc733a7 661 BUG();
6aa8b732
AK		 662}
663
323c3d80 664static void init_msrpm_offsets(void)
f65c229c 665{
323c3d80 666 int i;
f65c229c 667
323c3d80
JR		 668 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
669
670 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
671 u32 offset;
672
673 offset = svm_msrpm_offset(direct_access_msrs[i].index);
674 BUG_ON(offset == MSR_INVALID);
675
676 add_msr_offset(offset);
677 }
f65c229c
JR		 678}
679
24e09cbf
JR		 680static void svm_enable_lbrv(struct vcpu_svm *svm)
681{
682 u32 *msrpm = svm->msrpm;
683
0dc92119 684 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
24e09cbf
JR		 685 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
686 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
687 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
688 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
689}
690
691static void svm_disable_lbrv(struct vcpu_svm *svm)
692{
693 u32 *msrpm = svm->msrpm;
694
0dc92119 695 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
24e09cbf
JR		 696 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
697 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
698 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
699 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
700}
701
883b0a91 702void disable_nmi_singlestep(struct vcpu_svm *svm)
4aebd0e9
LP		 703{
704 svm->nmi_singlestep = false;
640bd6e5 705
ab2f4d73
LP		 706 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
707 /* Clear our flags if they were not set by the guest */
708 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
709 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
710 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
711 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
712 }
4aebd0e9
LP		 713}
714
8566ac8b
BM		 715static void grow_ple_window(struct kvm_vcpu *vcpu)
716{
717 struct vcpu_svm *svm = to_svm(vcpu);
718 struct vmcb_control_area *control = &svm->vmcb->control;
719 int old = control->pause_filter_count;
720
721 control->pause_filter_count = __grow_ple_window(old,
722 pause_filter_count,
723 pause_filter_count_grow,
724 pause_filter_count_max);
725
4f75bcc3 726 if (control->pause_filter_count != old) {
06e7852c 727 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
4f75bcc3
PX		 728 trace_kvm_ple_window_update(vcpu->vcpu_id,
729 control->pause_filter_count, old);
730 }
8566ac8b
BM		 731}
732
733static void shrink_ple_window(struct kvm_vcpu *vcpu)
734{
735 struct vcpu_svm *svm = to_svm(vcpu);
736 struct vmcb_control_area *control = &svm->vmcb->control;
737 int old = control->pause_filter_count;
738
739 control->pause_filter_count =
740 __shrink_ple_window(old,
741 pause_filter_count,
742 pause_filter_count_shrink,
743 pause_filter_count);
4f75bcc3 744 if (control->pause_filter_count != old) {
06e7852c 745 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
4f75bcc3
PX		 746 trace_kvm_ple_window_update(vcpu->vcpu_id,
747 control->pause_filter_count, old);
748 }
8566ac8b
BM		 749}
750
52918ed5
TL		 751/*
752 * The default MMIO mask is a single bit (excluding the present bit),
753 * which could conflict with the memory encryption bit. Check for
754 * memory encryption support and override the default MMIO mask if
755 * memory encryption is enabled.
756 */
757static __init void svm_adjust_mmio_mask(void)
758{
759 unsigned int enc_bit, mask_bit;
760 u64 msr, mask;
761
762 /* If there is no memory encryption support, use existing mask */
763 if (cpuid_eax(0x80000000) < 0x8000001f)
764 return;
765
766 /* If memory encryption is not enabled, use existing mask */
767 rdmsrl(MSR_K8_SYSCFG, msr);
768 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
769 return;
770
771 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
772 mask_bit = boot_cpu_data.x86_phys_bits;
773
774 /* Increment the mask bit if it is the same as the encryption bit */
775 if (enc_bit == mask_bit)
776 mask_bit++;
777
778 /*
779 * If the mask bit location is below 52, then some bits above the
780 * physical addressing limit will always be reserved, so use the
781 * rsvd_bits() function to generate the mask. This mask, along with
782 * the present bit, will be used to generate a page fault with
783 * PFER.RSV = 1.
784 *
785 * If the mask bit location is 52 (or above), then clear the mask.
786 */
787 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
788
e7581cac 789 kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
52918ed5
TL		 790}
791
dd58f3c9
LR		 792static void svm_hardware_teardown(void)
793{
794 int cpu;
795
eaf78265
JR		 796 if (svm_sev_enabled())
797 sev_hardware_teardown();
dd58f3c9
LR		 798
799 for_each_possible_cpu(cpu)
800 svm_cpu_uninit(cpu);
801
802 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
803 iopm_base = 0;
804}
805
9b58b985
SC		 806static __init void svm_set_cpu_caps(void)
807{
808 kvm_set_cpu_caps();
809
408e9a31
PB		 810 supported_xss = 0;
811
a50718cc
SC		 812 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
813 if (nested) {
9b58b985
SC		 814 kvm_cpu_cap_set(X86_FEATURE_SVM);
815
4eb87460 816 if (nrips)
a50718cc
SC		 817 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
818
819 if (npt_enabled)
820 kvm_cpu_cap_set(X86_FEATURE_NPT);
821 }
822
93c380e7
SC		 823 /* CPUID 0x80000008 */
824 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
825 boot_cpu_has(X86_FEATURE_AMD_SSBD))
826 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
9b58b985
SC		 827}
828
6aa8b732
AK		 829static __init int svm_hardware_setup(void)
830{
831 int cpu;
832 struct page *iopm_pages;
f65c229c 833 void *iopm_va;
6aa8b732
AK		 834 int r;
835
6aa8b732
AK		 836 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
837
838 if (!iopm_pages)
839 return -ENOMEM;
c8681339
AL		 840
841 iopm_va = page_address(iopm_pages);
842 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 843 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
844
323c3d80
JR		 845 init_msrpm_offsets();
846
cfc48181
SC		 847 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
848
50a37eb4
JR		 849 if (boot_cpu_has(X86_FEATURE_NX))
850 kvm_enable_efer_bits(EFER_NX);
851
1b2fd70c
AG		 852 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
853 kvm_enable_efer_bits(EFER_FFXSR);
854
92a1f12d 855 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
92a1f12d 856 kvm_has_tsc_control = true;
bc9b961b
HZ		 857 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
858 kvm_tsc_scaling_ratio_frac_bits = 32;
92a1f12d
JR		 859 }
860
8566ac8b
BM		 861 /* Check for pause filtering support */
862 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
863 pause_filter_count = 0;
864 pause_filter_thresh = 0;
865 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
866 pause_filter_thresh = 0;
867 }
868
236de055
AG		 869 if (nested) {
870 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 871 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 872 }
873
e9df0942
BS		 874 if (sev) {
875 if (boot_cpu_has(X86_FEATURE_SEV) &&
876 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
877 r = sev_hardware_setup();
878 if (r)
879 sev = false;
880 } else {
881 sev = false;
882 }
883 }
884
52918ed5
TL		 885 svm_adjust_mmio_mask();
886
3230bb47 887 for_each_possible_cpu(cpu) {
6aa8b732
AK		 888 r = svm_cpu_init(cpu);
889 if (r)
f65c229c 890 goto err;
6aa8b732 891 }
33bd6a0b 892
2a6b20b8 893 if (!boot_cpu_has(X86_FEATURE_NPT))
e3da3acd
JR		 894 npt_enabled = false;
895
213e0e1f 896 if (npt_enabled && !npt)
6c7dac72 897 npt_enabled = false;
6c7dac72 898
83013059 899 kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
213e0e1f 900 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
e3da3acd 901
d647eb63
PB		 902 if (nrips) {
903 if (!boot_cpu_has(X86_FEATURE_NRIPS))
904 nrips = false;
905 }
906
5b8abf1f
SS		 907 if (avic) {
908 if (!npt_enabled ||
909 !boot_cpu_has(X86_FEATURE_AVIC) ||
5881f737 910 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
5b8abf1f 911 avic = false;
5881f737 912 } else {
5b8abf1f 913 pr_info("AVIC enabled\n");
5881f737 914
5881f737
SS		 915 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
916 }
5b8abf1f 917 }
44a95dae 918
89c8a498
JN		 919 if (vls) {
920 if (!npt_enabled ||
5442c269 921 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
89c8a498
JN		 922 !IS_ENABLED(CONFIG_X86_64)) {
923 vls = false;
924 } else {
925 pr_info("Virtual VMLOAD VMSAVE supported\n");
926 }
927 }
928
640bd6e5
JN		 929 if (vgif) {
930 if (!boot_cpu_has(X86_FEATURE_VGIF))
931 vgif = false;
932 else
933 pr_info("Virtual GIF supported\n");
934 }
935
9b58b985 936 svm_set_cpu_caps();
66a6950f 937
3edd6839
MG		 938 /*
939 * It seems that on AMD processors PTE's accessed bit is
940 * being set by the CPU hardware before the NPF vmexit.
941 * This is not expected behaviour and our tests fail because
942 * of it.
943 * A workaround here is to disable support for
944 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
945 * In this case userspace can know if there is support using
946 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
947 * it
948 * If future AMD CPU models change the behaviour described above,
949 * this variable can be changed accordingly
950 */
951 allow_smaller_maxphyaddr = !npt_enabled;
952
6aa8b732
AK		 953 return 0;
954
f65c229c 955err:
dd58f3c9 956 svm_hardware_teardown();
6aa8b732
AK		 957 return r;
958}
959
6aa8b732
AK		 960static void init_seg(struct vmcb_seg *seg)
961{
962 seg->selector = 0;
963 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 964 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 965 seg->limit = 0xffff;
966 seg->base = 0;
967}
968
969static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
970{
971 seg->selector = 0;
972 seg->attrib = SVM_SELECTOR_P_MASK | type;
973 seg->limit = 0xffff;
974 seg->base = 0;
975}
976
326e7425 977static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
f4e1b3c8
ZA		 978{
979 struct vcpu_svm *svm = to_svm(vcpu);
980 u64 g_tsc_offset = 0;
981
2030753d 982 if (is_guest_mode(vcpu)) {
e79f245d 983 /* Write L1's TSC offset. */
f4e1b3c8
ZA		 984 g_tsc_offset = svm->vmcb->control.tsc_offset -
985 svm->nested.hsave->control.tsc_offset;
986 svm->nested.hsave->control.tsc_offset = offset;
45c3af97
PB		 987 }
988
989 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
990 svm->vmcb->control.tsc_offset - g_tsc_offset,
991 offset);
f4e1b3c8
ZA		 992
993 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
116a0a23 994
06e7852c 995 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
326e7425 996 return svm->vmcb->control.tsc_offset;
f4e1b3c8
ZA		 997}
998
5690891b 999static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 1000{
e6101a96
JR		 1001 struct vmcb_control_area *control = &svm->vmcb->control;
1002 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 1003
4ee546b4 1004 svm->vcpu.arch.hflags = 0;
bff78274 1005
830bd71f
BM		 1006 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1007 svm_set_intercept(svm, INTERCEPT_CR3_READ);
1008 svm_set_intercept(svm, INTERCEPT_CR4_READ);
1009 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1010 svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1011 svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
3bbf3565 1012 if (!kvm_vcpu_apicv_active(&svm->vcpu))
830bd71f 1013 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
6aa8b732 1014
5315c716 1015 set_dr_intercepts(svm);
6aa8b732 1016
18c918c5
JR		 1017 set_exception_intercept(svm, PF_VECTOR);
1018 set_exception_intercept(svm, UD_VECTOR);
1019 set_exception_intercept(svm, MC_VECTOR);
54a20552 1020 set_exception_intercept(svm, AC_VECTOR);
cbdb967a 1021 set_exception_intercept(svm, DB_VECTOR);
9718420e
LA		 1022 /*
1023 * Guest access to VMware backdoor ports could legitimately
1024 * trigger #GP because of TSS I/O permission bitmap.
1025 * We intercept those #GP and allow access to them anyway
1026 * as VMware does.
1027 */
1028 if (enable_vmware_backdoor)
1029 set_exception_intercept(svm, GP_VECTOR);
6aa8b732 1030
a284ba56
JR		 1031 svm_set_intercept(svm, INTERCEPT_INTR);
1032 svm_set_intercept(svm, INTERCEPT_NMI);
1033 svm_set_intercept(svm, INTERCEPT_SMI);
1034 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1035 svm_set_intercept(svm, INTERCEPT_RDPMC);
1036 svm_set_intercept(svm, INTERCEPT_CPUID);
1037 svm_set_intercept(svm, INTERCEPT_INVD);
1038 svm_set_intercept(svm, INTERCEPT_INVLPG);
1039 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1040 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1041 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1042 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1043 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1044 svm_set_intercept(svm, INTERCEPT_VMRUN);
1045 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1046 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1047 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1048 svm_set_intercept(svm, INTERCEPT_STGI);
1049 svm_set_intercept(svm, INTERCEPT_CLGI);
1050 svm_set_intercept(svm, INTERCEPT_SKINIT);
1051 svm_set_intercept(svm, INTERCEPT_WBINVD);
1052 svm_set_intercept(svm, INTERCEPT_XSETBV);
1053 svm_set_intercept(svm, INTERCEPT_RDPRU);
1054 svm_set_intercept(svm, INTERCEPT_RSM);
6aa8b732 1055
4d5422ce 1056 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
a284ba56
JR		 1057 svm_set_intercept(svm, INTERCEPT_MONITOR);
1058 svm_set_intercept(svm, INTERCEPT_MWAIT);
668fffa3
MT		 1059 }
1060
caa057a2 1061 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
a284ba56 1062 svm_set_intercept(svm, INTERCEPT_HLT);
caa057a2 1063
d0ec49d4
TL		 1064 control->iopm_base_pa = __sme_set(iopm_base);
1065 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
6aa8b732
AK		 1066 control->int_ctl = V_INTR_MASKING_MASK;
1067
1068 init_seg(&save->es);
1069 init_seg(&save->ss);
1070 init_seg(&save->ds);
1071 init_seg(&save->fs);
1072 init_seg(&save->gs);
1073
1074 save->cs.selector = 0xf000;
04b66839 1075 save->cs.base = 0xffff0000;
6aa8b732
AK		 1076 /* Executable/Readable Code Segment */
1077 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1078 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1079 save->cs.limit = 0xffff;
6aa8b732
AK		 1080
1081 save->gdtr.limit = 0xffff;
1082 save->idtr.limit = 0xffff;
1083
1084 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1085 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1086
5690891b 1087 svm_set_efer(&svm->vcpu, 0);
d77c26fc 1088 save->dr6 = 0xffff0ff0;
f6e78475 1089 kvm_set_rflags(&svm->vcpu, 2);
6aa8b732 1090 save->rip = 0x0000fff0;
5fdbf976 1091 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 1092
e0231715 1093 /*
18fa000a 1094 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
d28bc9dd 1095 * It also updates the guest-visible cr0 value.
6aa8b732 1096 */
79a8059d 1097 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
ebae871a 1098 kvm_mmu_reset_context(&svm->vcpu);
18fa000a 1099
66aee91a 1100 save->cr4 = X86_CR4_PAE;
6aa8b732 1101 /* rdx = ?? */
709ddebf
JR		 1102
1103 if (npt_enabled) {
1104 /* Setup VMCB for Nested Paging */
cea3a19b 1105 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
a284ba56 1106 svm_clr_intercept(svm, INTERCEPT_INVLPG);
18c918c5 1107 clr_exception_intercept(svm, PF_VECTOR);
830bd71f
BM		 1108 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1109 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
74545705 1110 save->g_pat = svm->vcpu.arch.pat;
709ddebf
JR		 1111 save->cr3 = 0;
1112 save->cr4 = 0;
1113 }
f40f6a45 1114 svm->asid_generation = 0;
1371d904 1115
0dd16b5b 1116 svm->nested.vmcb12_gpa = 0;
2af9194d
JR		 1117 svm->vcpu.arch.hflags = 0;
1118
830f01b0 1119 if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
8566ac8b
BM		 1120 control->pause_filter_count = pause_filter_count;
1121 if (pause_filter_thresh)
1122 control->pause_filter_thresh = pause_filter_thresh;
a284ba56 1123 svm_set_intercept(svm, INTERCEPT_PAUSE);
8566ac8b 1124 } else {
a284ba56 1125 svm_clr_intercept(svm, INTERCEPT_PAUSE);
565d0998
ML		 1126 }
1127
67034bb9 1128 if (kvm_vcpu_apicv_active(&svm->vcpu))
44a95dae
SS		 1129 avic_init_vmcb(svm);
1130
89c8a498
JN		 1131 /*
1132 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1133 * in VMCB and clear intercepts to avoid #VMEXIT.
1134 */
1135 if (vls) {
a284ba56
JR		 1136 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1137 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
89c8a498
JN		 1138 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1139 }
1140
640bd6e5 1141 if (vgif) {
a284ba56
JR		 1142 svm_clr_intercept(svm, INTERCEPT_STGI);
1143 svm_clr_intercept(svm, INTERCEPT_CLGI);
640bd6e5
JN		 1144 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1145 }
1146
35c6f649 1147 if (sev_guest(svm->vcpu.kvm)) {
1654efcb 1148 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
35c6f649
BS		 1149 clr_exception_intercept(svm, UD_VECTOR);
1150 }
1654efcb 1151
06e7852c 1152 vmcb_mark_all_dirty(svm->vmcb);
8d28fec4 1153
2af9194d 1154 enable_gif(svm);
44a95dae
SS		 1155
1156}
1157
d28bc9dd 1158static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
04d2cc77
AK		 1159{
1160 struct vcpu_svm *svm = to_svm(vcpu);
66f7b72e
JS		 1161 u32 dummy;
1162 u32 eax = 1;
04d2cc77 1163
b2ac58f9 1164 svm->spec_ctrl = 0;
ccbcd267 1165 svm->virt_spec_ctrl = 0;
b2ac58f9 1166
d28bc9dd
NA		 1167 if (!init_event) {
1168 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1169 MSR_IA32_APICBASE_ENABLE;
1170 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1171 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1172 }
5690891b 1173 init_vmcb(svm);
70433389 1174
f91af517 1175 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
de3cd117 1176 kvm_rdx_write(vcpu, eax);
44a95dae
SS		 1177
1178 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1179 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
04d2cc77
AK		 1180}
1181
987b2594 1182static int svm_create_vcpu(struct kvm_vcpu *vcpu)
6aa8b732 1183{
a2fa3e9f 1184 struct vcpu_svm *svm;
1feaba14 1185 struct page *vmcb_page;
b286d5d8 1186 struct page *hsave_page;
fb3f0f51 1187 int err;
6aa8b732 1188
a9dd6f09
SC		 1189 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1190 svm = to_svm(vcpu);
fb3f0f51 1191
b7af4043 1192 err = -ENOMEM;
0681de1b 1193 vmcb_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1feaba14 1194 if (!vmcb_page)
987b2594 1195 goto out;
6aa8b732 1196
0681de1b 1197 hsave_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
b286d5d8 1198 if (!hsave_page)
8d22b90e 1199 goto error_free_vmcb_page;
b7af4043 1200
dfa20099
SS		 1201 err = avic_init_vcpu(svm);
1202 if (err)
8d22b90e 1203 goto error_free_hsave_page;
44a95dae 1204
8221c137
SS		 1205 /* We initialize this flag to true to make sure that the is_running
1206 * bit would be set the first time the vcpu is loaded.
1207 */
6c3e4422
SS		 1208 if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1209 svm->avic_is_running = true;
8221c137 1210
e6aa9abd 1211 svm->nested.hsave = page_address(hsave_page);
b286d5d8 1212
f4c847a9
ML		 1213 svm->msrpm = svm_vcpu_init_msrpm();
1214 if (!svm->msrpm)
8d22b90e 1215 goto error_free_hsave_page;
b7af4043 1216
f4c847a9
ML		 1217 svm->nested.msrpm = svm_vcpu_init_msrpm();
1218 if (!svm->nested.msrpm)
8d22b90e 1219 goto error_free_msrpm;
3d6368ef 1220
1feaba14 1221 svm->vmcb = page_address(vmcb_page);
1feaba14 1222 svm->vmcb_pa = __sme_set(page_to_pfn(vmcb_page) << PAGE_SHIFT);
a2fa3e9f 1223 svm->asid_generation = 0;
5690891b 1224 init_vmcb(svm);
6aa8b732 1225
7f27179a 1226 svm_init_osvw(vcpu);
bab0c318 1227 vcpu->arch.microcode_version = 0x01000065;
2b036c6b 1228
a9dd6f09 1229 return 0;
36241b8c 1230
8d22b90e 1231error_free_msrpm:
f4c847a9 1232 svm_vcpu_free_msrpm(svm->msrpm);
8d22b90e 1233error_free_hsave_page:
f4c847a9 1234 __free_page(hsave_page);
8d22b90e 1235error_free_vmcb_page:
1feaba14 1236 __free_page(vmcb_page);
987b2594 1237out:
a9dd6f09 1238 return err;
6aa8b732
AK		 1239}
1240
fd65d314
JM		 1241static void svm_clear_current_vmcb(struct vmcb *vmcb)
1242{
1243 int i;
1244
1245 for_each_online_cpu(i)
1246 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1247}
1248
6aa8b732
AK		 1249static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1250{
a2fa3e9f
GH		 1251 struct vcpu_svm *svm = to_svm(vcpu);
1252
fd65d314
JM		 1253 /*
1254 * The vmcb page can be recycled, causing a false negative in
1255 * svm_vcpu_load(). So, ensure that no logical CPU has this
1256 * vmcb page recorded as its current vmcb.
1257 */
1258 svm_clear_current_vmcb(svm->vmcb);
1259
d0ec49d4 1260 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
f65c229c 1261 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 1262 __free_page(virt_to_page(svm->nested.hsave));
1263 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
6aa8b732
AK		 1264}
1265
15ad7146 1266static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1267{
a2fa3e9f 1268 struct vcpu_svm *svm = to_svm(vcpu);
15d45071 1269 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
15ad7146 1270 int i;
0cc5064d 1271
0cc5064d 1272 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 1273 svm->asid_generation = 0;
06e7852c 1274 vmcb_mark_all_dirty(svm->vmcb);
0cc5064d 1275 }
94dfbdb3 1276
82ca2d10
AK		 1277#ifdef CONFIG_X86_64
1278 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1279#endif
dacccfdd
AK		 1280 savesegment(fs, svm->host.fs);
1281 savesegment(gs, svm->host.gs);
1282 svm->host.ldt = kvm_read_ldt();
1283
94dfbdb3 1284 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1285 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
fbc0db76 1286
ad721883
HZ		 1287 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1288 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1289 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1290 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1291 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1292 }
fbc0db76 1293 }
46896c73
PB		 1294 /* This assumes that the kernel never uses MSR_TSC_AUX */
1295 if (static_cpu_has(X86_FEATURE_RDTSCP))
1296 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
8221c137 1297
15d45071
AR		 1298 if (sd->current_vmcb != svm->vmcb) {
1299 sd->current_vmcb = svm->vmcb;
1300 indirect_branch_prediction_barrier();
1301 }
8221c137 1302 avic_vcpu_load(vcpu, cpu);
6aa8b732
AK		 1303}
1304
1305static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1306{
a2fa3e9f 1307 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 1308 int i;
1309
8221c137
SS		 1310 avic_vcpu_put(vcpu);
1311
e1beb1d3 1312 ++vcpu->stat.host_state_reload;
dacccfdd
AK		 1313 kvm_load_ldt(svm->host.ldt);
1314#ifdef CONFIG_X86_64
1315 loadsegment(fs, svm->host.fs);
296f781a 1316 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
893a5ab6 1317 load_gs_index(svm->host.gs);
dacccfdd 1318#else
831ca609 1319#ifdef CONFIG_X86_32_LAZY_GS
dacccfdd 1320 loadsegment(gs, svm->host.gs);
831ca609 1321#endif
dacccfdd 1322#endif
94dfbdb3 1323 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1324 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1325}
1326
6aa8b732
AK		 1327static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1328{
9b611747
LP		 1329 struct vcpu_svm *svm = to_svm(vcpu);
1330 unsigned long rflags = svm->vmcb->save.rflags;
1331
1332 if (svm->nmi_singlestep) {
1333 /* Hide our flags if they were not set by the guest */
1334 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1335 rflags &= ~X86_EFLAGS_TF;
1336 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1337 rflags &= ~X86_EFLAGS_RF;
1338 }
1339 return rflags;
6aa8b732
AK		 1340}
1341
1342static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1343{
9b611747
LP		 1344 if (to_svm(vcpu)->nmi_singlestep)
1345 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1346
ae9fedc7 1347 /*
bb3541f1 1348 * Any change of EFLAGS.VM is accompanied by a reload of SS
ae9fedc7
PB		 1349 * (caused by either a task switch or an inter-privilege IRET),
1350 * so we do not need to update the CPL here.
1351 */
a2fa3e9f 1352 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1353}
1354
6de4f3ad
AK		 1355static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1356{
1357 switch (reg) {
1358 case VCPU_EXREG_PDPTR:
1359 BUG_ON(!npt_enabled);
9f8fe504 1360 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6de4f3ad
AK		 1361 break;
1362 default:
34059c25 1363 WARN_ON_ONCE(1);
6de4f3ad
AK		 1364 }
1365}
1366
e14b7786 1367static void svm_set_vintr(struct vcpu_svm *svm)
64b5bd27
PB		 1368{
1369 struct vmcb_control_area *control;
1370
1371 /* The following fields are ignored when AVIC is enabled */
1372 WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
a284ba56 1373 svm_set_intercept(svm, INTERCEPT_VINTR);
64b5bd27
PB		 1374
1375 /*
1376 * This is just a dummy VINTR to actually cause a vmexit to happen.
1377 * Actual injection of virtual interrupts happens through EVENTINJ.
1378 */
1379 control = &svm->vmcb->control;
1380 control->int_vector = 0x0;
1381 control->int_ctl &= ~V_INTR_PRIO_MASK;
1382 control->int_ctl |= V_IRQ_MASK |
1383 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
06e7852c 1384 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
64b5bd27
PB		 1385}
1386
f0b85051
AG		 1387static void svm_clear_vintr(struct vcpu_svm *svm)
1388{
d8e4e58f 1389 const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
a284ba56 1390 svm_clr_intercept(svm, INTERCEPT_VINTR);
64b5bd27 1391
d8e4e58f
PB		 1392 /* Drop int_ctl fields related to VINTR injection. */
1393 svm->vmcb->control.int_ctl &= mask;
1394 if (is_guest_mode(&svm->vcpu)) {
fb7333df
PB		 1395 svm->nested.hsave->control.int_ctl &= mask;
1396
d8e4e58f
PB		 1397 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1398 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1399 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1400 }
1401
06e7852c 1402 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
f0b85051
AG		 1403}
1404
6aa8b732
AK		 1405static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1406{
a2fa3e9f 1407 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1408
1409 switch (seg) {
1410 case VCPU_SREG_CS: return &save->cs;
1411 case VCPU_SREG_DS: return &save->ds;
1412 case VCPU_SREG_ES: return &save->es;
1413 case VCPU_SREG_FS: return &save->fs;
1414 case VCPU_SREG_GS: return &save->gs;
1415 case VCPU_SREG_SS: return &save->ss;
1416 case VCPU_SREG_TR: return &save->tr;
1417 case VCPU_SREG_LDTR: return &save->ldtr;
1418 }
1419 BUG();
8b6d44c7 1420 return NULL;
6aa8b732
AK		 1421}
1422
1423static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1424{
1425 struct vmcb_seg *s = svm_seg(vcpu, seg);
1426
1427 return s->base;
1428}
1429
1430static void svm_get_segment(struct kvm_vcpu *vcpu,
1431 struct kvm_segment *var, int seg)
1432{
1433 struct vmcb_seg *s = svm_seg(vcpu, seg);
1434
1435 var->base = s->base;
1436 var->limit = s->limit;
1437 var->selector = s->selector;
1438 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1439 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1440 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1441 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1442 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1443 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1444 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
80112c89
JM		 1445
1446 /*
1447 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1448 * However, the SVM spec states that the G bit is not observed by the
1449 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1450 * So let's synthesize a legal G bit for all segments, this helps
1451 * running KVM nested. It also helps cross-vendor migration, because
1452 * Intel's vmentry has a check on the 'G' bit.
1453 */
1454 var->g = s->limit > 0xfffff;
25022acc 1455
e0231715
JR		 1456 /*
1457 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1458 * for cross vendor migration purposes by "not present"
1459 */
8eae9570 1460 var->unusable = !var->present;
19bca6ab 1461
1fbdc7a5 1462 switch (seg) {
1fbdc7a5
AP		 1463 case VCPU_SREG_TR:
1464 /*
1465 * Work around a bug where the busy flag in the tr selector
1466 * isn't exposed
1467 */
c0d09828 1468 var->type |= 0x2;
1fbdc7a5
AP		 1469 break;
1470 case VCPU_SREG_DS:
1471 case VCPU_SREG_ES:
1472 case VCPU_SREG_FS:
1473 case VCPU_SREG_GS:
1474 /*
1475 * The accessed bit must always be set in the segment
1476 * descriptor cache, although it can be cleared in the
1477 * descriptor, the cached bit always remains at 1. Since
1478 * Intel has a check on this, set it here to support
1479 * cross-vendor migration.
1480 */
1481 if (!var->unusable)
1482 var->type |= 0x1;
1483 break;
b586eb02 1484 case VCPU_SREG_SS:
e0231715
JR		 1485 /*
1486 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1487 * descriptor is left as 1, although the whole segment has
1488 * been made unusable. Clear it here to pass an Intel VMX
1489 * entry check when cross vendor migrating.
1490 */
1491 if (var->unusable)
1492 var->db = 0;
d9c1b543 1493 /* This is symmetric with svm_set_segment() */
33b458d2 1494 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
b586eb02 1495 break;
1fbdc7a5 1496 }
6aa8b732
AK		 1497}
1498
2e4d2653
IE		 1499static int svm_get_cpl(struct kvm_vcpu *vcpu)
1500{
1501 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1502
1503 return save->cpl;
1504}
1505
89a27f4d 1506static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1507{
a2fa3e9f
GH		 1508 struct vcpu_svm *svm = to_svm(vcpu);
1509
89a27f4d
GN		 1510 dt->size = svm->vmcb->save.idtr.limit;
1511 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1512}
1513
89a27f4d 1514static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1515{
a2fa3e9f
GH		 1516 struct vcpu_svm *svm = to_svm(vcpu);
1517
89a27f4d
GN		 1518 svm->vmcb->save.idtr.limit = dt->size;
1519 svm->vmcb->save.idtr.base = dt->address ;
06e7852c 1520 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1521}
1522
89a27f4d 1523static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1524{
a2fa3e9f
GH		 1525 struct vcpu_svm *svm = to_svm(vcpu);
1526
89a27f4d
GN		 1527 dt->size = svm->vmcb->save.gdtr.limit;
1528 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1529}
1530
89a27f4d 1531static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1532{
a2fa3e9f
GH		 1533 struct vcpu_svm *svm = to_svm(vcpu);
1534
89a27f4d
GN		 1535 svm->vmcb->save.gdtr.limit = dt->size;
1536 svm->vmcb->save.gdtr.base = dt->address ;
06e7852c 1537 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1538}
1539
d225157b
AK		 1540static void update_cr0_intercept(struct vcpu_svm *svm)
1541{
1542 ulong gcr0 = svm->vcpu.arch.cr0;
1543 u64 *hcr0 = &svm->vmcb->save.cr0;
1544
bd7e5b08
PB		 1545 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1546 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
d225157b 1547
06e7852c 1548 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
d225157b 1549
bd7e5b08 1550 if (gcr0 == *hcr0) {
830bd71f
BM		 1551 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1552 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b 1553 } else {
830bd71f
BM		 1554 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1555 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b
AK		 1556 }
1557}
1558
883b0a91 1559void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 1560{
a2fa3e9f
GH		 1561 struct vcpu_svm *svm = to_svm(vcpu);
1562
05b3e0c2 1563#ifdef CONFIG_X86_64
f6801dff 1564 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1565 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1566 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1567 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1568 }
1569
d77c26fc 1570 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1571 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1572 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1573 }
1574 }
1575#endif
ad312c7c 1576 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1577
1578 if (!npt_enabled)
1579 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21 1580
bcf166a9
PB		 1581 /*
1582 * re-enable caching here because the QEMU bios
1583 * does not do it - this results in some delay at
1584 * reboot
1585 */
1586 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1587 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1588 svm->vmcb->save.cr0 = cr0;
06e7852c 1589 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
d225157b 1590 update_cr0_intercept(svm);
6aa8b732
AK		 1591}
1592
883b0a91 1593int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 1594{
1e02ce4c 1595 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
e5eab0ce
JR		 1596 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1597
5e1746d6
NHE		 1598 if (cr4 & X86_CR4_VMXE)
1599 return 1;
1600
e5eab0ce 1601 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
f55ac304 1602 svm_flush_tlb(vcpu);
6394b649 1603
ec077263
JR		 1604 vcpu->arch.cr4 = cr4;
1605 if (!npt_enabled)
1606 cr4 |= X86_CR4_PAE;
6394b649 1607 cr4 |= host_cr4_mce;
ec077263 1608 to_svm(vcpu)->vmcb->save.cr4 = cr4;
06e7852c 1609 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
5e1746d6 1610 return 0;
6aa8b732
AK		 1611}
1612
1613static void svm_set_segment(struct kvm_vcpu *vcpu,
1614 struct kvm_segment *var, int seg)
1615{
a2fa3e9f 1616 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1617 struct vmcb_seg *s = svm_seg(vcpu, seg);
1618
1619 s->base = var->base;
1620 s->limit = var->limit;
1621 s->selector = var->selector;
d9c1b543
RP		 1622 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1623 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1624 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1625 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1626 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1627 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1628 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1629 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
ae9fedc7
PB		 1630
1631 /*
1632 * This is always accurate, except if SYSRET returned to a segment
1633 * with SS.DPL != 3. Intel does not have this quirk, and always
1634 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1635 * would entail passing the CPL to userspace and back.
1636 */
1637 if (seg == VCPU_SREG_SS)
d9c1b543
RP		 1638 /* This is symmetric with svm_get_segment() */
1639 svm->vmcb->save.cpl = (var->dpl & 3);
6aa8b732 1640
06e7852c 1641 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
6aa8b732
AK		 1642}
1643
6986982f 1644static void update_exception_bitmap(struct kvm_vcpu *vcpu)
6aa8b732 1645{
d0bfb940
JK		 1646 struct vcpu_svm *svm = to_svm(vcpu);
1647
18c918c5 1648 clr_exception_intercept(svm, BP_VECTOR);
44c11430 1649
d0bfb940 1650 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
d0bfb940 1651 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
18c918c5 1652 set_exception_intercept(svm, BP_VECTOR);
6986982f 1653 }
44c11430
GN		 1654}
1655
0fe1e009 1656static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1657{
0fe1e009
TH		 1658 if (sd->next_asid > sd->max_asid) {
1659 ++sd->asid_generation;
4faefff3 1660 sd->next_asid = sd->min_asid;
a2fa3e9f 1661 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1662 }
1663
0fe1e009
TH		 1664 svm->asid_generation = sd->asid_generation;
1665 svm->vmcb->control.asid = sd->next_asid++;
d48086d1 1666
06e7852c 1667 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
6aa8b732
AK		 1668}
1669
d67668e9 1670static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
73aaf249 1671{
d67668e9 1672 struct vmcb *vmcb = svm->vmcb;
73aaf249 1673
d67668e9
PB		 1674 if (unlikely(value != vmcb->save.dr6)) {
1675 vmcb->save.dr6 = value;
06e7852c 1676 vmcb_mark_dirty(vmcb, VMCB_DR);
d67668e9 1677 }
73aaf249
JK		 1678}
1679
facb0139
PB		 1680static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1681{
1682 struct vcpu_svm *svm = to_svm(vcpu);
1683
1684 get_debugreg(vcpu->arch.db[0], 0);
1685 get_debugreg(vcpu->arch.db[1], 1);
1686 get_debugreg(vcpu->arch.db[2], 2);
1687 get_debugreg(vcpu->arch.db[3], 3);
d67668e9
PB		 1688 /*
1689 * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1690 * because db_interception might need it. We can do it before vmentry.
1691 */
5679b803 1692 vcpu->arch.dr6 = svm->vmcb->save.dr6;
facb0139 1693 vcpu->arch.dr7 = svm->vmcb->save.dr7;
facb0139
PB		 1694 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1695 set_dr_intercepts(svm);
1696}
1697
020df079 1698static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1699{
42dbaa5a 1700 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1701
020df079 1702 svm->vmcb->save.dr7 = value;
06e7852c 1703 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
6aa8b732
AK		 1704}
1705
851ba692 1706static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1707{
0ede79e1 1708 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1261bfa3 1709 u64 error_code = svm->vmcb->control.exit_info_1;
6aa8b732 1710
1261bfa3 1711 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
00b10fe1
BS		 1712 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1713 svm->vmcb->control.insn_bytes : NULL,
d0006530
PB		 1714 svm->vmcb->control.insn_len);
1715}
1716
1717static int npf_interception(struct vcpu_svm *svm)
1718{
0ede79e1 1719 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
d0006530
PB		 1720 u64 error_code = svm->vmcb->control.exit_info_1;
1721
1722 trace_kvm_page_fault(fault_address, error_code);
1723 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
00b10fe1
BS		 1724 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1725 svm->vmcb->control.insn_bytes : NULL,
d0006530 1726 svm->vmcb->control.insn_len);
6aa8b732
AK		 1727}
1728
851ba692 1729static int db_interception(struct vcpu_svm *svm)
d0bfb940 1730{
851ba692 1731 struct kvm_run *kvm_run = svm->vcpu.run;
99c22179 1732 struct kvm_vcpu *vcpu = &svm->vcpu;
851ba692 1733
d0bfb940 1734 if (!(svm->vcpu.guest_debug &
44c11430 1735 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1736 !svm->nmi_singlestep) {
d67668e9
PB		 1737 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1738 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
d0bfb940
JK		 1739 return 1;
1740 }
44c11430 1741
6be7d306 1742 if (svm->nmi_singlestep) {
4aebd0e9 1743 disable_nmi_singlestep(svm);
99c22179
VK		 1744 /* Make sure we check for pending NMIs upon entry */
1745 kvm_make_request(KVM_REQ_EVENT, vcpu);
44c11430
GN		 1746 }
1747
1748 if (svm->vcpu.guest_debug &
e0231715 1749 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430 1750 kvm_run->exit_reason = KVM_EXIT_DEBUG;
dee919d1
PB		 1751 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1752 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
44c11430
GN		 1753 kvm_run->debug.arch.pc =
1754 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1755 kvm_run->debug.arch.exception = DB_VECTOR;
1756 return 0;
1757 }
1758
1759 return 1;
d0bfb940
JK		 1760}
1761
851ba692 1762static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1763{
851ba692
AK		 1764 struct kvm_run *kvm_run = svm->vcpu.run;
1765
d0bfb940
JK		 1766 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1767 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1768 kvm_run->debug.arch.exception = BP_VECTOR;
1769 return 0;
1770}
1771
851ba692 1772static int ud_interception(struct vcpu_svm *svm)
7aa81cc0 1773{
082d06ed 1774 return handle_ud(&svm->vcpu);
7aa81cc0
AL		 1775}
1776
54a20552
EN		 1777static int ac_interception(struct vcpu_svm *svm)
1778{
1779 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1780 return 1;
1781}
1782
9718420e
LA		 1783static int gp_interception(struct vcpu_svm *svm)
1784{
1785 struct kvm_vcpu *vcpu = &svm->vcpu;
1786 u32 error_code = svm->vmcb->control.exit_info_1;
9718420e
LA		 1787
1788 WARN_ON_ONCE(!enable_vmware_backdoor);
1789
a6c6ed1e
SC		 1790 /*
1791 * VMware backdoor emulation on #GP interception only handles IN{S},
1792 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1793 */
1794 if (error_code) {
1795 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1796 return 1;
1797 }
60fc3d02 1798 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
9718420e
LA		 1799}
1800
67ec6607
JR		 1801static bool is_erratum_383(void)
1802{
1803 int err, i;
1804 u64 value;
1805
1806 if (!erratum_383_found)
1807 return false;
1808
1809 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1810 if (err)
1811 return false;
1812
1813 /* Bit 62 may or may not be set for this mce */
1814 value &= ~(1ULL << 62);
1815
1816 if (value != 0xb600000000010015ULL)
1817 return false;
1818
1819 /* Clear MCi_STATUS registers */
1820 for (i = 0; i < 6; ++i)
1821 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1822
1823 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1824 if (!err) {
1825 u32 low, high;
1826
1827 value &= ~(1ULL << 2);
1828 low = lower_32_bits(value);
1829 high = upper_32_bits(value);
1830
1831 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1832 }
1833
1834 /* Flush tlb to evict multi-match entries */
1835 __flush_tlb_all();
1836
1837 return true;
1838}
1839
1c164cb3
UB		 1840/*
1841 * Trigger machine check on the host. We assume all the MSRs are already set up
1842 * by the CPU and that we still run on the same CPU as the MCE occurred on.
1843 * We pass a fake environment to the machine check handler because we want
1844 * the guest to be always treated like user space, no matter what context
1845 * it used internally.
1846 */
1847static void kvm_machine_check(void)
1848{
1849#if defined(CONFIG_X86_MCE)
1850 struct pt_regs regs = {
1851 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
1852 .flags = X86_EFLAGS_IF,
1853 };
1854
8cd501c1 1855 do_machine_check(&regs);
1c164cb3
UB		 1856#endif
1857}
1858
fe5913e4 1859static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1860{
67ec6607
JR		 1861 if (is_erratum_383()) {
1862 /*
1863 * Erratum 383 triggered. Guest state is corrupt so kill the
1864 * guest.
1865 */
1866 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1867
a8eeb04a 1868 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1869
1870 return;
1871 }
1872
53371b50
JR		 1873 /*
1874 * On an #MC intercept the MCE handler is not called automatically in
1875 * the host. So do it by hand here.
1876 */
1c164cb3 1877 kvm_machine_check();
fe5913e4
JR		 1878}
1879
1880static int mc_interception(struct vcpu_svm *svm)
1881{
53371b50
JR		 1882 return 1;
1883}
1884
851ba692 1885static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1886{
851ba692
AK		 1887 struct kvm_run *kvm_run = svm->vcpu.run;
1888
46fe4ddd
JR		 1889 /*
1890 * VMCB is undefined after a SHUTDOWN intercept
1891 * so reinitialize it.
1892 */
a2fa3e9f 1893 clear_page(svm->vmcb);
5690891b 1894 init_vmcb(svm);
46fe4ddd
JR		 1895
1896 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1897 return 0;
1898}
1899
851ba692 1900static int io_interception(struct vcpu_svm *svm)
6aa8b732 1901{
cf8f70bf 1902 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1903 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
dca7f128 1904 int size, in, string;
039576c0 1905 unsigned port;
6aa8b732 1906
e756fc62 1907 ++svm->vcpu.stat.io_exits;
e70669ab 1908 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1909 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
8370c3d0 1910 if (string)
60fc3d02 1911 return kvm_emulate_instruction(vcpu, 0);
cf8f70bf 1912
039576c0
AK		 1913 port = io_info >> 16;
1914 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1915 svm->next_rip = svm->vmcb->control.exit_info_2;
cf8f70bf 1916
dca7f128 1917 return kvm_fast_pio(&svm->vcpu, size, port, in);
6aa8b732
AK		 1918}
1919
851ba692 1920static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1921{
1922 return 1;
1923}
1924
851ba692 1925static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1926{
1927 ++svm->vcpu.stat.irq_exits;
1928 return 1;
1929}
1930
851ba692 1931static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1932{
1933 return 1;
1934}
1935
851ba692 1936static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1937{
e756fc62 1938 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1939}
1940
851ba692 1941static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1942{
0d9c055e 1943 return kvm_emulate_hypercall(&svm->vcpu);
02e235bc
AK		 1944}
1945
851ba692 1946static int vmload_interception(struct vcpu_svm *svm)
5542675b 1947{
9966bf68 1948 struct vmcb *nested_vmcb;
8c5fbf1a 1949 struct kvm_host_map map;
b742c1e6 1950 int ret;
9966bf68 1951
5542675b
AG		 1952 if (nested_svm_check_permissions(svm))
1953 return 1;
1954
8c5fbf1a
KA		 1955 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1956 if (ret) {
1957 if (ret == -EINVAL)
1958 kvm_inject_gp(&svm->vcpu, 0);
9966bf68 1959 return 1;
8c5fbf1a
KA		 1960 }
1961
1962 nested_vmcb = map.hva;
9966bf68 1963
b742c1e6 1964 ret = kvm_skip_emulated_instruction(&svm->vcpu);
e3e9ed3d 1965
9966bf68 1966 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
8c5fbf1a 1967 kvm_vcpu_unmap(&svm->vcpu, &map, true);
5542675b 1968
b742c1e6 1969 return ret;
5542675b
AG		 1970}
1971
851ba692 1972static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1973{
9966bf68 1974 struct vmcb *nested_vmcb;
8c5fbf1a 1975 struct kvm_host_map map;
b742c1e6 1976 int ret;
9966bf68 1977
5542675b
AG		 1978 if (nested_svm_check_permissions(svm))
1979 return 1;
1980
8c5fbf1a
KA		 1981 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1982 if (ret) {
1983 if (ret == -EINVAL)
1984 kvm_inject_gp(&svm->vcpu, 0);
9966bf68 1985 return 1;
8c5fbf1a
KA		 1986 }
1987
1988 nested_vmcb = map.hva;
9966bf68 1989
b742c1e6 1990 ret = kvm_skip_emulated_instruction(&svm->vcpu);
e3e9ed3d 1991
9966bf68 1992 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
8c5fbf1a 1993 kvm_vcpu_unmap(&svm->vcpu, &map, true);
5542675b 1994
b742c1e6 1995 return ret;
5542675b
AG		 1996}
1997
851ba692 1998static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 1999{
3d6368ef
AG		 2000 if (nested_svm_check_permissions(svm))
2001 return 1;
2002
e7134c1b 2003 return nested_svm_vmrun(svm);
3d6368ef
AG		 2004}
2005
ffdf7f9e
PB		 2006void svm_set_gif(struct vcpu_svm *svm, bool value)
2007{
2008 if (value) {
2009 /*
2010 * If VGIF is enabled, the STGI intercept is only added to
2011 * detect the opening of the SMI/NMI window; remove it now.
2012 * Likewise, clear the VINTR intercept, we will set it
2013 * again while processing KVM_REQ_EVENT if needed.
2014 */
2015 if (vgif_enabled(svm))
a284ba56
JR		 2016 svm_clr_intercept(svm, INTERCEPT_STGI);
2017 if (svm_is_intercept(svm, INTERCEPT_VINTR))
ffdf7f9e
PB		 2018 svm_clear_vintr(svm);
2019
2020 enable_gif(svm);
2021 if (svm->vcpu.arch.smi_pending ||
2022 svm->vcpu.arch.nmi_pending ||
2023 kvm_cpu_has_injectable_intr(&svm->vcpu))
2024 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2025 } else {
2026 disable_gif(svm);
2027
2028 /*
2029 * After a CLGI no interrupts should come. But if vGIF is
2030 * in use, we still rely on the VINTR intercept (rather than
2031 * STGI) to detect an open interrupt window.
2032 */
2033 if (!vgif_enabled(svm))
2034 svm_clear_vintr(svm);
2035 }
2036}
2037
851ba692 2038static int stgi_interception(struct vcpu_svm *svm)
1371d904 2039{
b742c1e6
LP		 2040 int ret;
2041
1371d904
AG		 2042 if (nested_svm_check_permissions(svm))
2043 return 1;
2044
b742c1e6 2045 ret = kvm_skip_emulated_instruction(&svm->vcpu);
ffdf7f9e 2046 svm_set_gif(svm, true);
b742c1e6 2047 return ret;
1371d904
AG		 2048}
2049
851ba692 2050static int clgi_interception(struct vcpu_svm *svm)
1371d904 2051{
b742c1e6
LP		 2052 int ret;
2053
1371d904
AG		 2054 if (nested_svm_check_permissions(svm))
2055 return 1;
2056
b742c1e6 2057 ret = kvm_skip_emulated_instruction(&svm->vcpu);
ffdf7f9e 2058 svm_set_gif(svm, false);
b742c1e6 2059 return ret;
1371d904
AG		 2060}
2061
851ba692 2062static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2063{
2064 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2065
de3cd117
SC		 2066 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2067 kvm_rax_read(&svm->vcpu));
ec1ff790 2068
ff092385 2069 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
de3cd117 2070 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
ff092385 2071
b742c1e6 2072 return kvm_skip_emulated_instruction(&svm->vcpu);
ff092385
AG		 2073}
2074
532a46b9
JR		 2075static int skinit_interception(struct vcpu_svm *svm)
2076{
de3cd117 2077 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
532a46b9
JR		 2078
2079 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2080 return 1;
2081}
2082
dab429a7
DK		 2083static int wbinvd_interception(struct vcpu_svm *svm)
2084{
6affcbed 2085 return kvm_emulate_wbinvd(&svm->vcpu);
dab429a7
DK		 2086}
2087
81dd35d4
JR		 2088static int xsetbv_interception(struct vcpu_svm *svm)
2089{
2090 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
de3cd117 2091 u32 index = kvm_rcx_read(&svm->vcpu);
81dd35d4
JR		 2092
2093 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
b742c1e6 2094 return kvm_skip_emulated_instruction(&svm->vcpu);
81dd35d4
JR		 2095 }
2096
2097 return 1;
2098}
2099
0cb8410b
JM		 2100static int rdpru_interception(struct vcpu_svm *svm)
2101{
2102 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2103 return 1;
2104}
2105
851ba692 2106static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2107{
37817f29 2108 u16 tss_selector;
64a7ec06
GN		 2109 int reason;
2110 int int_type = svm->vmcb->control.exit_int_info &
2111 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2112 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2113 uint32_t type =
2114 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2115 uint32_t idt_v =
2116 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2117 bool has_error_code = false;
2118 u32 error_code = 0;
37817f29
IE		 2119
2120 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2121
37817f29
IE		 2122 if (svm->vmcb->control.exit_info_2 &
2123 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2124 reason = TASK_SWITCH_IRET;
2125 else if (svm->vmcb->control.exit_info_2 &
2126 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2127 reason = TASK_SWITCH_JMP;
fe8e7f83 2128 else if (idt_v)
64a7ec06
GN		 2129 reason = TASK_SWITCH_GATE;
2130 else
2131 reason = TASK_SWITCH_CALL;
2132
fe8e7f83
GN		 2133 if (reason == TASK_SWITCH_GATE) {
2134 switch (type) {
2135 case SVM_EXITINTINFO_TYPE_NMI:
2136 svm->vcpu.arch.nmi_injected = false;
2137 break;
2138 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2139 if (svm->vmcb->control.exit_info_2 &
2140 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2141 has_error_code = true;
2142 error_code =
2143 (u32)svm->vmcb->control.exit_info_2;
2144 }
fe8e7f83
GN		 2145 kvm_clear_exception_queue(&svm->vcpu);
2146 break;
2147 case SVM_EXITINTINFO_TYPE_INTR:
2148 kvm_clear_interrupt_queue(&svm->vcpu);
2149 break;
2150 default:
2151 break;
2152 }
2153 }
64a7ec06 2154
8317c298
GN		 2155 if (reason != TASK_SWITCH_GATE ||
2156 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2157 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f8ea7c60 2158 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
60fc3d02 2159 if (!skip_emulated_instruction(&svm->vcpu))
738fece4 2160 return 0;
f8ea7c60 2161 }
64a7ec06 2162
7f3d35fd
KW		 2163 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2164 int_vec = -1;
2165
1051778f 2166 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
60fc3d02 2167 has_error_code, error_code);
6aa8b732
AK		 2168}
2169
851ba692 2170static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2171{
6a908b62 2172 return kvm_emulate_cpuid(&svm->vcpu);
6aa8b732
AK		 2173}
2174
851ba692 2175static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2176{
2177 ++svm->vcpu.stat.nmi_window_exits;
a284ba56 2178 svm_clr_intercept(svm, INTERCEPT_IRET);
44c11430 2179 svm->vcpu.arch.hflags |= HF_IRET_MASK;
bd3d1ec3 2180 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
f303b4ce 2181 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
95ba8273
GN		 2182 return 1;
2183}
2184
851ba692 2185static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2186{
df4f3108 2187 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
60fc3d02 2188 return kvm_emulate_instruction(&svm->vcpu, 0);
df4f3108
AP		 2189
2190 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
b742c1e6 2191 return kvm_skip_emulated_instruction(&svm->vcpu);
a7052897
MT		 2192}
2193
851ba692 2194static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2195{
60fc3d02 2196 return kvm_emulate_instruction(&svm->vcpu, 0);
6aa8b732
AK		 2197}
2198
7607b717
BS		 2199static int rsm_interception(struct vcpu_svm *svm)
2200{
60fc3d02 2201 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
7607b717
BS		 2202}
2203
332b56e4
AK		 2204static int rdpmc_interception(struct vcpu_svm *svm)
2205{
2206 int err;
2207
d647eb63 2208 if (!nrips)
332b56e4
AK		 2209 return emulate_on_interception(svm);
2210
2211 err = kvm_rdpmc(&svm->vcpu);
6affcbed 2212 return kvm_complete_insn_gp(&svm->vcpu, err);
332b56e4
AK		 2213}
2214
52eb5a6d
XL		 2215static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2216 unsigned long val)
628afd2a
JR		 2217{
2218 unsigned long cr0 = svm->vcpu.arch.cr0;
2219 bool ret = false;
628afd2a
JR		 2220
2221 if (!is_guest_mode(&svm->vcpu) ||
c62e2e94 2222 (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
628afd2a
JR		 2223 return false;
2224
2225 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2226 val &= ~SVM_CR0_SELECTIVE_MASK;
2227
2228 if (cr0 ^ val) {
2229 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2230 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2231 }
2232
2233 return ret;
2234}
2235
7ff76d58
AP		 2236#define CR_VALID (1ULL << 63)
2237
2238static int cr_interception(struct vcpu_svm *svm)
2239{
2240 int reg, cr;
2241 unsigned long val;
2242 int err;
2243
2244 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2245 return emulate_on_interception(svm);
2246
2247 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2248 return emulate_on_interception(svm);
2249
2250 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
5e57518d
DK		 2251 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2252 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2253 else
2254 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
7ff76d58
AP		 2255
2256 err = 0;
2257 if (cr >= 16) { /* mov to cr */
2258 cr -= 16;
2259 val = kvm_register_read(&svm->vcpu, reg);
2260 switch (cr) {
2261 case 0:
628afd2a
JR		 2262 if (!check_selective_cr0_intercepted(svm, val))
2263 err = kvm_set_cr0(&svm->vcpu, val);
977b2d03
JR		 2264 else
2265 return 1;
2266
7ff76d58
AP		 2267 break;
2268 case 3:
2269 err = kvm_set_cr3(&svm->vcpu, val);
2270 break;
2271 case 4:
2272 err = kvm_set_cr4(&svm->vcpu, val);
2273 break;
2274 case 8:
2275 err = kvm_set_cr8(&svm->vcpu, val);
2276 break;
2277 default:
2278 WARN(1, "unhandled write to CR%d", cr);
2279 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2280 return 1;
2281 }
2282 } else { /* mov from cr */
2283 switch (cr) {
2284 case 0:
2285 val = kvm_read_cr0(&svm->vcpu);
2286 break;
2287 case 2:
2288 val = svm->vcpu.arch.cr2;
2289 break;
2290 case 3:
9f8fe504 2291 val = kvm_read_cr3(&svm->vcpu);
7ff76d58
AP		 2292 break;
2293 case 4:
2294 val = kvm_read_cr4(&svm->vcpu);
2295 break;
2296 case 8:
2297 val = kvm_get_cr8(&svm->vcpu);
2298 break;
2299 default:
2300 WARN(1, "unhandled read from CR%d", cr);
2301 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2302 return 1;
2303 }
2304 kvm_register_write(&svm->vcpu, reg, val);
2305 }
6affcbed 2306 return kvm_complete_insn_gp(&svm->vcpu, err);
7ff76d58
AP		 2307}
2308
cae3797a
AP		 2309static int dr_interception(struct vcpu_svm *svm)
2310{
2311 int reg, dr;
2312 unsigned long val;
cae3797a 2313
facb0139
PB		 2314 if (svm->vcpu.guest_debug == 0) {
2315 /*
2316 * No more DR vmexits; force a reload of the debug registers
2317 * and reenter on this instruction. The next vmexit will
2318 * retrieve the full state of the debug registers.
2319 */
2320 clr_dr_intercepts(svm);
2321 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2322 return 1;
2323 }
2324
cae3797a
AP		 2325 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2326 return emulate_on_interception(svm);
2327
2328 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2329 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2330
2331 if (dr >= 16) { /* mov to DRn */
16f8a6f9
NA		 2332 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2333 return 1;
cae3797a
AP		 2334 val = kvm_register_read(&svm->vcpu, reg);
2335 kvm_set_dr(&svm->vcpu, dr - 16, val);
2336 } else {
16f8a6f9
NA		 2337 if (!kvm_require_dr(&svm->vcpu, dr))
2338 return 1;
2339 kvm_get_dr(&svm->vcpu, dr, &val);
2340 kvm_register_write(&svm->vcpu, reg, val);
cae3797a
AP		 2341 }
2342
b742c1e6 2343 return kvm_skip_emulated_instruction(&svm->vcpu);
cae3797a
AP		 2344}
2345
851ba692 2346static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2347{
851ba692 2348 struct kvm_run *kvm_run = svm->vcpu.run;
eea1cff9 2349 int r;
851ba692 2350
0a5fff19
GN		 2351 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2352 /* instruction emulation calls kvm_set_cr8() */
7ff76d58 2353 r = cr_interception(svm);
35754c98 2354 if (lapic_in_kernel(&svm->vcpu))
7ff76d58 2355 return r;
0a5fff19 2356 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
7ff76d58 2357 return r;
1d075434
JR		 2358 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2359 return 0;
2360}
2361
801e459a
TL		 2362static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2363{
d1d93fa9
TL		 2364 msr->data = 0;
2365
2366 switch (msr->index) {
2367 case MSR_F10H_DECFG:
2368 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2369 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2370 break;
d574c539
VK		 2371 case MSR_IA32_PERF_CAPABILITIES:
2372 return 0;
d1d93fa9 2373 default:
12bc2132 2374 return KVM_MSR_RET_INVALID;
d1d93fa9
TL		 2375 }
2376
2377 return 0;
801e459a
TL		 2378}
2379
609e36d3 2380static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2381{
a2fa3e9f
GH		 2382 struct vcpu_svm *svm = to_svm(vcpu);
2383
609e36d3 2384 switch (msr_info->index) {
8c06585d 2385 case MSR_STAR:
609e36d3 2386 msr_info->data = svm->vmcb->save.star;
6aa8b732 2387 break;
0e859cac 2388#ifdef CONFIG_X86_64
6aa8b732 2389 case MSR_LSTAR:
609e36d3 2390 msr_info->data = svm->vmcb->save.lstar;
6aa8b732
AK		 2391 break;
2392 case MSR_CSTAR:
609e36d3 2393 msr_info->data = svm->vmcb->save.cstar;
6aa8b732
AK		 2394 break;
2395 case MSR_KERNEL_GS_BASE:
609e36d3 2396 msr_info->data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2397 break;
2398 case MSR_SYSCALL_MASK:
609e36d3 2399 msr_info->data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2400 break;
2401#endif
2402 case MSR_IA32_SYSENTER_CS:
609e36d3 2403 msr_info->data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2404 break;
2405 case MSR_IA32_SYSENTER_EIP:
609e36d3 2406 msr_info->data = svm->sysenter_eip;
6aa8b732
AK		 2407 break;
2408 case MSR_IA32_SYSENTER_ESP:
609e36d3 2409 msr_info->data = svm->sysenter_esp;
6aa8b732 2410 break;
46896c73
PB		 2411 case MSR_TSC_AUX:
2412 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2413 return 1;
2414 msr_info->data = svm->tsc_aux;
2415 break;
e0231715
JR		 2416 /*
2417 * Nobody will change the following 5 values in the VMCB so we can
2418 * safely return them on rdmsr. They will always be 0 until LBRV is
2419 * implemented.
2420 */
a2938c80 2421 case MSR_IA32_DEBUGCTLMSR:
609e36d3 2422 msr_info->data = svm->vmcb->save.dbgctl;
a2938c80
JR		 2423 break;
2424 case MSR_IA32_LASTBRANCHFROMIP:
609e36d3 2425 msr_info->data = svm->vmcb->save.br_from;
a2938c80
JR		 2426 break;
2427 case MSR_IA32_LASTBRANCHTOIP:
609e36d3 2428 msr_info->data = svm->vmcb->save.br_to;
a2938c80
JR		 2429 break;
2430 case MSR_IA32_LASTINTFROMIP:
609e36d3 2431 msr_info->data = svm->vmcb->save.last_excp_from;
a2938c80
JR		 2432 break;
2433 case MSR_IA32_LASTINTTOIP:
609e36d3 2434 msr_info->data = svm->vmcb->save.last_excp_to;
a2938c80 2435 break;
b286d5d8 2436 case MSR_VM_HSAVE_PA:
609e36d3 2437 msr_info->data = svm->nested.hsave_msr;
b286d5d8 2438 break;
eb6f302e 2439 case MSR_VM_CR:
609e36d3 2440 msr_info->data = svm->nested.vm_cr_msr;
eb6f302e 2441 break;
b2ac58f9
KA		 2442 case MSR_IA32_SPEC_CTRL:
2443 if (!msr_info->host_initiated &&
df7e8818
PB		 2444 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2445 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
6ac2f49e
KRW		 2446 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2447 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
b2ac58f9
KA		 2448 return 1;
2449
2450 msr_info->data = svm->spec_ctrl;
2451 break;
bc226f07
TL		 2452 case MSR_AMD64_VIRT_SPEC_CTRL:
2453 if (!msr_info->host_initiated &&
2454 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2455 return 1;
2456
2457 msr_info->data = svm->virt_spec_ctrl;
2458 break;
ae8b7875
BP		 2459 case MSR_F15H_IC_CFG: {
2460
2461 int family, model;
2462
2463 family = guest_cpuid_family(vcpu);
2464 model = guest_cpuid_model(vcpu);
2465
2466 if (family < 0 || model < 0)
2467 return kvm_get_msr_common(vcpu, msr_info);
2468
2469 msr_info->data = 0;
2470
2471 if (family == 0x15 &&
2472 (model >= 0x2 && model < 0x20))
2473 msr_info->data = 0x1E;
2474 }
2475 break;
d1d93fa9
TL		 2476 case MSR_F10H_DECFG:
2477 msr_info->data = svm->msr_decfg;
2478 break;
6aa8b732 2479 default:
609e36d3 2480 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 2481 }
2482 return 0;
2483}
2484
851ba692 2485static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2486{
1edce0a9 2487 return kvm_emulate_rdmsr(&svm->vcpu);
6aa8b732
AK		 2488}
2489
4a810181
JR		 2490static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2491{
2492 struct vcpu_svm *svm = to_svm(vcpu);
2493 int svm_dis, chg_mask;
2494
2495 if (data & ~SVM_VM_CR_VALID_MASK)
2496 return 1;
2497
2498 chg_mask = SVM_VM_CR_VALID_MASK;
2499
2500 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2501 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2502
2503 svm->nested.vm_cr_msr &= ~chg_mask;
2504 svm->nested.vm_cr_msr |= (data & chg_mask);
2505
2506 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2507
2508 /* check for svm_disable while efer.svme is set */
2509 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2510 return 1;
2511
2512 return 0;
2513}
2514
8fe8ab46 2515static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
6aa8b732 2516{
a2fa3e9f
GH		 2517 struct vcpu_svm *svm = to_svm(vcpu);
2518
8fe8ab46
WA		 2519 u32 ecx = msr->index;
2520 u64 data = msr->data;
6aa8b732 2521 switch (ecx) {
15038e14
PB		 2522 case MSR_IA32_CR_PAT:
2523 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2524 return 1;
2525 vcpu->arch.pat = data;
2526 svm->vmcb->save.g_pat = data;
06e7852c 2527 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
15038e14 2528 break;
b2ac58f9
KA		 2529 case MSR_IA32_SPEC_CTRL:
2530 if (!msr->host_initiated &&
df7e8818
PB		 2531 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2532 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
6ac2f49e
KRW		 2533 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2534 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
b2ac58f9
KA		 2535 return 1;
2536
841c2be0 2537 if (kvm_spec_ctrl_test_value(data))
b2ac58f9
KA		 2538 return 1;
2539
2540 svm->spec_ctrl = data;
b2ac58f9
KA		 2541 if (!data)
2542 break;
2543
2544 /*
2545 * For non-nested:
2546 * When it's written (to non-zero) for the first time, pass
2547 * it through.
2548 *
2549 * For nested:
2550 * The handling of the MSR bitmap for L2 guests is done in
2551 * nested_svm_vmrun_msrpm.
2552 * We update the L1 MSR bit as well since it will end up
2553 * touching the MSR anyway now.
2554 */
2555 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2556 break;
15d45071
AR		 2557 case MSR_IA32_PRED_CMD:
2558 if (!msr->host_initiated &&
e7c587da 2559 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
15d45071
AR		 2560 return 1;
2561
2562 if (data & ~PRED_CMD_IBPB)
2563 return 1;
6441fa61
PB		 2564 if (!boot_cpu_has(X86_FEATURE_AMD_IBPB))
2565 return 1;
15d45071
AR		 2566 if (!data)
2567 break;
2568
2569 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
15d45071
AR		 2570 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2571 break;
bc226f07
TL		 2572 case MSR_AMD64_VIRT_SPEC_CTRL:
2573 if (!msr->host_initiated &&
2574 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2575 return 1;
2576
2577 if (data & ~SPEC_CTRL_SSBD)
2578 return 1;
2579
2580 svm->virt_spec_ctrl = data;
2581 break;
8c06585d 2582 case MSR_STAR:
a2fa3e9f 2583 svm->vmcb->save.star = data;
6aa8b732 2584 break;
49b14f24 2585#ifdef CONFIG_X86_64
6aa8b732 2586 case MSR_LSTAR:
a2fa3e9f 2587 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2588 break;
2589 case MSR_CSTAR:
a2fa3e9f 2590 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2591 break;
2592 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2593 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2594 break;
2595 case MSR_SYSCALL_MASK:
a2fa3e9f 2596 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2597 break;
2598#endif
2599 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2600 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2601 break;
2602 case MSR_IA32_SYSENTER_EIP:
017cb99e 2603 svm->sysenter_eip = data;
a2fa3e9f 2604 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2605 break;
2606 case MSR_IA32_SYSENTER_ESP:
017cb99e 2607 svm->sysenter_esp = data;
a2fa3e9f 2608 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2609 break;
46896c73
PB		 2610 case MSR_TSC_AUX:
2611 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2612 return 1;
2613
2614 /*
2615 * This is rare, so we update the MSR here instead of using
2616 * direct_access_msrs. Doing that would require a rdmsr in
2617 * svm_vcpu_put.
2618 */
2619 svm->tsc_aux = data;
2620 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2621 break;
a2938c80 2622 case MSR_IA32_DEBUGCTLMSR:
2a6b20b8 2623 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
a737f256
CD		 2624 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2625 __func__, data);
24e09cbf
JR		 2626 break;
2627 }
2628 if (data & DEBUGCTL_RESERVED_BITS)
2629 return 1;
2630
2631 svm->vmcb->save.dbgctl = data;
06e7852c 2632 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
24e09cbf
JR		 2633 if (data & (1ULL<<0))
2634 svm_enable_lbrv(svm);
2635 else
2636 svm_disable_lbrv(svm);
a2938c80 2637 break;
b286d5d8 2638 case MSR_VM_HSAVE_PA:
e6aa9abd 2639 svm->nested.hsave_msr = data;
62b9abaa 2640 break;
3c5d0a44 2641 case MSR_VM_CR:
4a810181 2642 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2643 case MSR_VM_IGNNE:
a737f256 2644 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3c5d0a44 2645 break;
d1d93fa9
TL		 2646 case MSR_F10H_DECFG: {
2647 struct kvm_msr_entry msr_entry;
2648
2649 msr_entry.index = msr->index;
2650 if (svm_get_msr_feature(&msr_entry))
2651 return 1;
2652
2653 /* Check the supported bits */
2654 if (data & ~msr_entry.data)
2655 return 1;
2656
2657 /* Don't allow the guest to change a bit, #GP */
2658 if (!msr->host_initiated && (data ^ msr_entry.data))
2659 return 1;
2660
2661 svm->msr_decfg = data;
2662 break;
2663 }
44a95dae
SS		 2664 case MSR_IA32_APICBASE:
2665 if (kvm_vcpu_apicv_active(vcpu))
2666 avic_update_vapic_bar(to_svm(vcpu), data);
df561f66 2667 fallthrough;
6aa8b732 2668 default:
8fe8ab46 2669 return kvm_set_msr_common(vcpu, msr);
6aa8b732
AK		 2670 }
2671 return 0;
2672}
2673
851ba692 2674static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2675{
1edce0a9 2676 return kvm_emulate_wrmsr(&svm->vcpu);
6aa8b732
AK		 2677}
2678
851ba692 2679static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2680{
e756fc62 2681 if (svm->vmcb->control.exit_info_1)
851ba692 2682 return wrmsr_interception(svm);
6aa8b732 2683 else
851ba692 2684 return rdmsr_interception(svm);
6aa8b732
AK		 2685}
2686
851ba692 2687static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2688{
3842d135 2689 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
f0b85051 2690 svm_clear_vintr(svm);
f3515dc3
SS		 2691
2692 /*
2693 * For AVIC, the only reason to end up here is ExtINTs.
2694 * In this case AVIC was temporarily disabled for
2695 * requesting the IRQ window and we have to re-enable it.
2696 */
2697 svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2698
675acb75 2699 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2700 return 1;
2701}
2702
565d0998
ML		 2703static int pause_interception(struct vcpu_svm *svm)
2704{
de63ad4c
LM		 2705 struct kvm_vcpu *vcpu = &svm->vcpu;
2706 bool in_kernel = (svm_get_cpl(vcpu) == 0);
2707
830f01b0 2708 if (!kvm_pause_in_guest(vcpu->kvm))
8566ac8b
BM		 2709 grow_ple_window(vcpu);
2710
de63ad4c 2711 kvm_vcpu_on_spin(vcpu, in_kernel);
565d0998
ML		 2712 return 1;
2713}
2714
87c00572
GS		 2715static int nop_interception(struct vcpu_svm *svm)
2716{
b742c1e6 2717 return kvm_skip_emulated_instruction(&(svm->vcpu));
87c00572
GS		 2718}
2719
2720static int monitor_interception(struct vcpu_svm *svm)
2721{
2722 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2723 return nop_interception(svm);
2724}
2725
2726static int mwait_interception(struct vcpu_svm *svm)
2727{
2728 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2729 return nop_interception(svm);
2730}
2731
09941fbb 2732static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
7ff76d58
AP		 2733 [SVM_EXIT_READ_CR0] = cr_interception,
2734 [SVM_EXIT_READ_CR3] = cr_interception,
2735 [SVM_EXIT_READ_CR4] = cr_interception,
2736 [SVM_EXIT_READ_CR8] = cr_interception,
5e57518d 2737 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
628afd2a 2738 [SVM_EXIT_WRITE_CR0] = cr_interception,
7ff76d58
AP		 2739 [SVM_EXIT_WRITE_CR3] = cr_interception,
2740 [SVM_EXIT_WRITE_CR4] = cr_interception,
e0231715 2741 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
cae3797a
AP		 2742 [SVM_EXIT_READ_DR0] = dr_interception,
2743 [SVM_EXIT_READ_DR1] = dr_interception,
2744 [SVM_EXIT_READ_DR2] = dr_interception,
2745 [SVM_EXIT_READ_DR3] = dr_interception,
2746 [SVM_EXIT_READ_DR4] = dr_interception,
2747 [SVM_EXIT_READ_DR5] = dr_interception,
2748 [SVM_EXIT_READ_DR6] = dr_interception,
2749 [SVM_EXIT_READ_DR7] = dr_interception,
2750 [SVM_EXIT_WRITE_DR0] = dr_interception,
2751 [SVM_EXIT_WRITE_DR1] = dr_interception,
2752 [SVM_EXIT_WRITE_DR2] = dr_interception,
2753 [SVM_EXIT_WRITE_DR3] = dr_interception,
2754 [SVM_EXIT_WRITE_DR4] = dr_interception,
2755 [SVM_EXIT_WRITE_DR5] = dr_interception,
2756 [SVM_EXIT_WRITE_DR6] = dr_interception,
2757 [SVM_EXIT_WRITE_DR7] = dr_interception,
d0bfb940
JK		 2758 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2759 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2760 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715 2761 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
e0231715 2762 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
54a20552 2763 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
9718420e 2764 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
e0231715 2765 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2766 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2767 [SVM_EXIT_SMI] = nop_on_interception,
2768 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2769 [SVM_EXIT_VINTR] = interrupt_window_interception,
332b56e4 2770 [SVM_EXIT_RDPMC] = rdpmc_interception,
6aa8b732 2771 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2772 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2773 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2774 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2775 [SVM_EXIT_HLT] = halt_interception,
a7052897 2776 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2777 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2778 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2779 [SVM_EXIT_MSR] = msr_interception,
2780 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2781 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2782 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2783 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2784 [SVM_EXIT_VMLOAD] = vmload_interception,
2785 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2786 [SVM_EXIT_STGI] = stgi_interception,
2787 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2788 [SVM_EXIT_SKINIT] = skinit_interception,
dab429a7 2789 [SVM_EXIT_WBINVD] = wbinvd_interception,
87c00572
GS		 2790 [SVM_EXIT_MONITOR] = monitor_interception,
2791 [SVM_EXIT_MWAIT] = mwait_interception,
81dd35d4 2792 [SVM_EXIT_XSETBV] = xsetbv_interception,
0cb8410b 2793 [SVM_EXIT_RDPRU] = rdpru_interception,
d0006530 2794 [SVM_EXIT_NPF] = npf_interception,
7607b717 2795 [SVM_EXIT_RSM] = rsm_interception,
18f40c53
SS		 2796 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
2797 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
6aa8b732
AK		 2798};
2799
ae8cc059 2800static void dump_vmcb(struct kvm_vcpu *vcpu)
3f10c846
JR		 2801{
2802 struct vcpu_svm *svm = to_svm(vcpu);
2803 struct vmcb_control_area *control = &svm->vmcb->control;
2804 struct vmcb_save_area *save = &svm->vmcb->save;
2805
6f2f8453
PB		 2806 if (!dump_invalid_vmcb) {
2807 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2808 return;
2809 }
2810
3f10c846 2811 pr_err("VMCB Control Area:\n");
03bfeeb9
BM		 2812 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
2813 pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
30abaa88
BM		 2814 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
2815 pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
9780d51d 2816 pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
c62e2e94
BM		 2817 pr_err("%-20s%08x %08x\n", "intercepts:",
2818 control->intercepts[INTERCEPT_WORD3],
2819 control->intercepts[INTERCEPT_WORD4]);
ae8cc059 2820 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
1d8fb44a
BM		 2821 pr_err("%-20s%d\n", "pause filter threshold:",
2822 control->pause_filter_thresh);
ae8cc059
JP		 2823 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2824 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
2825 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
2826 pr_err("%-20s%d\n", "asid:", control->asid);
2827 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
2828 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
2829 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
2830 pr_err("%-20s%08x\n", "int_state:", control->int_state);
2831 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
2832 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
2833 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
2834 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
2835 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
2836 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
2837 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
44a95dae 2838 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
ae8cc059
JP		 2839 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
2840 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
0dc92119 2841 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
ae8cc059 2842 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
44a95dae
SS		 2843 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
2844 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
2845 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3f10c846 2846 pr_err("VMCB State Save Area:\n");
ae8cc059
JP		 2847 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2848 "es:",
2849 save->es.selector, save->es.attrib,
2850 save->es.limit, save->es.base);
2851 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2852 "cs:",
2853 save->cs.selector, save->cs.attrib,
2854 save->cs.limit, save->cs.base);
2855 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2856 "ss:",
2857 save->ss.selector, save->ss.attrib,
2858 save->ss.limit, save->ss.base);
2859 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2860 "ds:",
2861 save->ds.selector, save->ds.attrib,
2862 save->ds.limit, save->ds.base);
2863 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2864 "fs:",
2865 save->fs.selector, save->fs.attrib,
2866 save->fs.limit, save->fs.base);
2867 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2868 "gs:",
2869 save->gs.selector, save->gs.attrib,
2870 save->gs.limit, save->gs.base);
2871 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2872 "gdtr:",
2873 save->gdtr.selector, save->gdtr.attrib,
2874 save->gdtr.limit, save->gdtr.base);
2875 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2876 "ldtr:",
2877 save->ldtr.selector, save->ldtr.attrib,
2878 save->ldtr.limit, save->ldtr.base);
2879 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2880 "idtr:",
2881 save->idtr.selector, save->idtr.attrib,
2882 save->idtr.limit, save->idtr.base);
2883 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2884 "tr:",
2885 save->tr.selector, save->tr.attrib,
2886 save->tr.limit, save->tr.base);
3f10c846
JR		 2887 pr_err("cpl: %d efer: %016llx\n",
2888 save->cpl, save->efer);
ae8cc059
JP		 2889 pr_err("%-15s %016llx %-13s %016llx\n",
2890 "cr0:", save->cr0, "cr2:", save->cr2);
2891 pr_err("%-15s %016llx %-13s %016llx\n",
2892 "cr3:", save->cr3, "cr4:", save->cr4);
2893 pr_err("%-15s %016llx %-13s %016llx\n",
2894 "dr6:", save->dr6, "dr7:", save->dr7);
2895 pr_err("%-15s %016llx %-13s %016llx\n",
2896 "rip:", save->rip, "rflags:", save->rflags);
2897 pr_err("%-15s %016llx %-13s %016llx\n",
2898 "rsp:", save->rsp, "rax:", save->rax);
2899 pr_err("%-15s %016llx %-13s %016llx\n",
2900 "star:", save->star, "lstar:", save->lstar);
2901 pr_err("%-15s %016llx %-13s %016llx\n",
2902 "cstar:", save->cstar, "sfmask:", save->sfmask);
2903 pr_err("%-15s %016llx %-13s %016llx\n",
2904 "kernel_gs_base:", save->kernel_gs_base,
2905 "sysenter_cs:", save->sysenter_cs);
2906 pr_err("%-15s %016llx %-13s %016llx\n",
2907 "sysenter_esp:", save->sysenter_esp,
2908 "sysenter_eip:", save->sysenter_eip);
2909 pr_err("%-15s %016llx %-13s %016llx\n",
2910 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
2911 pr_err("%-15s %016llx %-13s %016llx\n",
2912 "br_from:", save->br_from, "br_to:", save->br_to);
2913 pr_err("%-15s %016llx %-13s %016llx\n",
2914 "excp_from:", save->last_excp_from,
2915 "excp_to:", save->last_excp_to);
3f10c846
JR		 2916}
2917
586f9607
AK		 2918static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
2919{
2920 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2921
2922 *info1 = control->exit_info_1;
2923 *info2 = control->exit_info_2;
2924}
2925
404d5d7b 2926static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6aa8b732 2927{
04d2cc77 2928 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2929 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2930 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2931
8b89fe1f
PB		 2932 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
2933
830bd71f 2934 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
2be4fc7a
JR		 2935 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2936 if (npt_enabled)
2937 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 2938
2030753d 2939 if (is_guest_mode(vcpu)) {
410e4d57
JR		 2940 int vmexit;
2941
d8cabddf
JR		 2942 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2943 svm->vmcb->control.exit_info_1,
2944 svm->vmcb->control.exit_info_2,
2945 svm->vmcb->control.exit_int_info,
e097e5ff
SH		 2946 svm->vmcb->control.exit_int_info_err,
2947 KVM_ISA_SVM);
d8cabddf 2948
410e4d57
JR		 2949 vmexit = nested_svm_exit_special(svm);
2950
2951 if (vmexit == NESTED_EXIT_CONTINUE)
2952 vmexit = nested_svm_exit_handled(svm);
2953
2954 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2955 return 1;
cf74a78b
AG		 2956 }
2957
04d2cc77
AK		 2958 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2959 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2960 kvm_run->fail_entry.hardware_entry_failure_reason
2961 = svm->vmcb->control.exit_code;
8a14fe4f 2962 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3f10c846 2963 dump_vmcb(vcpu);
04d2cc77
AK		 2964 return 0;
2965 }
2966
a2fa3e9f 2967 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2968 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
55c5e464
JR		 2969 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
2970 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
6614c7d0 2971 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
6aa8b732 2972 "exit_code 0x%x\n",
b8688d51 2973 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2974 exit_code);
2975
404d5d7b 2976 if (exit_fastpath != EXIT_FASTPATH_NONE)
1e9e2622 2977 return 1;
404d5d7b
WL		 2978
2979 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2980 || !svm_exit_handlers[exit_code]) {
7396d337
LA		 2981 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
2982 dump_vmcb(vcpu);
2983 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2984 vcpu->run->internal.suberror =
2985 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
1aa561b1 2986 vcpu->run->internal.ndata = 2;
7396d337 2987 vcpu->run->internal.data[0] = exit_code;
8a14fe4f 2988 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
7396d337 2989 return 0;
6aa8b732
AK		 2990 }
2991
3dcb2a3f
AA		 2992#ifdef CONFIG_RETPOLINE
2993 if (exit_code == SVM_EXIT_MSR)
2994 return msr_interception(svm);
2995 else if (exit_code == SVM_EXIT_VINTR)
2996 return interrupt_window_interception(svm);
2997 else if (exit_code == SVM_EXIT_INTR)
2998 return intr_interception(svm);
2999 else if (exit_code == SVM_EXIT_HLT)
3000 return halt_interception(svm);
3001 else if (exit_code == SVM_EXIT_NPF)
3002 return npf_interception(svm);
3003#endif
851ba692 3004 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 3005}
3006
3007static void reload_tss(struct kvm_vcpu *vcpu)
3008{
73cd6e5f 3009 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
6aa8b732 3010
0fe1e009 3011 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 3012 load_TR_desc();
3013}
3014
e756fc62 3015static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732 3016{
73cd6e5f 3017 struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
6aa8b732 3018
70cd94e6 3019 if (sev_guest(svm->vcpu.kvm))
73cd6e5f 3020 return pre_sev_run(svm, svm->vcpu.cpu);
70cd94e6 3021
4b656b12 3022 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 3023 if (svm->asid_generation != sd->asid_generation)
3024 new_asid(svm, sd);
6aa8b732
AK		 3025}
3026
95ba8273
GN		 3027static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3028{
3029 struct vcpu_svm *svm = to_svm(vcpu);
3030
3031 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3032 vcpu->arch.hflags |= HF_NMI_MASK;
a284ba56 3033 svm_set_intercept(svm, INTERCEPT_IRET);
95ba8273
GN		 3034 ++vcpu->stat.nmi_injections;
3035}
6aa8b732 3036
66fd3f7f 3037static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3038{
3039 struct vcpu_svm *svm = to_svm(vcpu);
3040
2af9194d 3041 BUG_ON(!(gif_set(svm)));
cf74a78b 3042
9fb2d2b4
GN		 3043 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3044 ++vcpu->stat.irq_injections;
3045
219b65dc
AG		 3046 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3047 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3048}
3049
95ba8273 3050static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3051{
3052 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3053
01c3b2b5 3054 if (nested_svm_virtualize_tpr(vcpu))
88ab24ad
JR		 3055 return;
3056
830bd71f 3057 svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
596f3142 3058
95ba8273 3059 if (irr == -1)
aaacfc9a
JR		 3060 return;
3061
95ba8273 3062 if (tpr >= irr)
830bd71f 3063 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
95ba8273 3064}
aaacfc9a 3065
cae96af1 3066bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
95ba8273
GN		 3067{
3068 struct vcpu_svm *svm = to_svm(vcpu);
3069 struct vmcb *vmcb = svm->vmcb;
88c604b6 3070 bool ret;
9c3d370a 3071
cae96af1 3072 if (!gif_set(svm))
bbdad0b5
PB		 3073 return true;
3074
cae96af1
PB		 3075 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3076 return false;
3077
3078 ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3079 (svm->vcpu.arch.hflags & HF_NMI_MASK);
924584cc
JR		 3080
3081 return ret;
aaacfc9a
JR		 3082}
3083
c9d40913 3084static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3085{
3086 struct vcpu_svm *svm = to_svm(vcpu);
3087 if (svm->nested.nested_run_pending)
c9d40913 3088 return -EBUSY;
cae96af1 3089
c300ab9f
PB		 3090 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3091 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
c9d40913 3092 return -EBUSY;
c300ab9f
PB		 3093
3094 return !svm_nmi_blocked(vcpu);
cae96af1
PB		 3095}
3096
3cfc3092
JK		 3097static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3098{
3099 struct vcpu_svm *svm = to_svm(vcpu);
3100
3101 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3102}
3103
3104static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3105{
3106 struct vcpu_svm *svm = to_svm(vcpu);
3107
3108 if (masked) {
3109 svm->vcpu.arch.hflags |= HF_NMI_MASK;
a284ba56 3110 svm_set_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3111 } else {
3112 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
a284ba56 3113 svm_clr_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3114 }
3115}
3116
cae96af1 3117bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
78646121
GN		 3118{
3119 struct vcpu_svm *svm = to_svm(vcpu);
3120 struct vmcb *vmcb = svm->vmcb;
7fcdb510 3121
fc6f7c03 3122 if (!gif_set(svm))
cae96af1 3123 return true;
7fcdb510 3124
fc6f7c03
PB		 3125 if (is_guest_mode(vcpu)) {
3126 /* As long as interrupts are being delivered... */
e9fd761a 3127 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
08245e6d 3128 ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
fc6f7c03
PB		 3129 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3130 return true;
3131
3132 /* ... vmexits aren't blocked by the interrupt shadow */
3133 if (nested_exit_on_intr(svm))
3134 return false;
3135 } else {
3136 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3137 return true;
3138 }
3139
3140 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
cae96af1
PB		 3141}
3142
c9d40913 3143static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3144{
3145 struct vcpu_svm *svm = to_svm(vcpu);
3146 if (svm->nested.nested_run_pending)
c9d40913 3147 return -EBUSY;
cae96af1 3148
c300ab9f
PB		 3149 /*
3150 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3151 * e.g. if the IRQ arrived asynchronously after checking nested events.
3152 */
3153 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
c9d40913 3154 return -EBUSY;
c300ab9f
PB		 3155
3156 return !svm_interrupt_blocked(vcpu);
78646121
GN		 3157}
3158
c9a7953f 3159static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3160{
219b65dc 3161 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3162
e0231715
JR		 3163 /*
3164 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3165 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3166 * get that intercept, this function will be called again though and
640bd6e5
JN		 3167 * we'll get the vintr intercept. However, if the vGIF feature is
3168 * enabled, the STGI interception will not occur. Enable the irq
3169 * window under the assumption that the hardware will set the GIF.
e0231715 3170 */
b518ba9f 3171 if (vgif_enabled(svm) || gif_set(svm)) {
f3515dc3
SS		 3172 /*
3173 * IRQ window is not needed when AVIC is enabled,
3174 * unless we have pending ExtINT since it cannot be injected
3175 * via AVIC. In such case, we need to temporarily disable AVIC,
3176 * and fallback to injecting IRQ via V_IRQ.
3177 */
3178 svm_toggle_avic_for_irq_window(vcpu, false);
219b65dc 3179 svm_set_vintr(svm);
219b65dc 3180 }
85f455f7
ED		 3181}
3182
c9a7953f 3183static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3184{
04d2cc77 3185 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3186
44c11430
GN		 3187 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3188 == HF_NMI_MASK)
c9a7953f 3189 return; /* IRET will cause a vm exit */
44c11430 3190
640bd6e5
JN		 3191 if (!gif_set(svm)) {
3192 if (vgif_enabled(svm))
a284ba56 3193 svm_set_intercept(svm, INTERCEPT_STGI);
1a5e1852 3194 return; /* STGI will cause a vm exit */
640bd6e5 3195 }
1a5e1852 3196
e0231715
JR		 3197 /*
3198 * Something prevents NMI from been injected. Single step over possible
3199 * problem (IRET or exception injection or interrupt shadow)
3200 */
ab2f4d73 3201 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
6be7d306 3202 svm->nmi_singlestep = true;
44c11430 3203 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
c1150d8c
DL		 3204}
3205
cbc94022
IE		 3206static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3207{
3208 return 0;
3209}
3210
2ac52ab8
SC		 3211static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3212{
3213 return 0;
3214}
3215
f55ac304 3216void svm_flush_tlb(struct kvm_vcpu *vcpu)
d9e368d6 3217{
38e5e92f
JR		 3218 struct vcpu_svm *svm = to_svm(vcpu);
3219
4a41e43c
SC		 3220 /*
3221 * Flush only the current ASID even if the TLB flush was invoked via
3222 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3223 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3224 * unconditionally does a TLB flush on both nested VM-Enter and nested
3225 * VM-Exit (via kvm_mmu_reset_context()).
3226 */
38e5e92f
JR		 3227 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3228 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3229 else
3230 svm->asid_generation--;
d9e368d6
AK		 3231}
3232
faff8758
JS		 3233static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3234{
3235 struct vcpu_svm *svm = to_svm(vcpu);
3236
3237 invlpga(gva, svm->vmcb->control.asid);
3238}
3239
04d2cc77
AK		 3240static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3241{
3242}
3243
d7bf8221
JR		 3244static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3245{
3246 struct vcpu_svm *svm = to_svm(vcpu);
3247
01c3b2b5 3248 if (nested_svm_virtualize_tpr(vcpu))
88ab24ad
JR		 3249 return;
3250
830bd71f 3251 if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
d7bf8221 3252 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3253 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3254 }
3255}
3256
649d6864
JR		 3257static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3258{
3259 struct vcpu_svm *svm = to_svm(vcpu);
3260 u64 cr8;
3261
01c3b2b5 3262 if (nested_svm_virtualize_tpr(vcpu) ||
3bbf3565 3263 kvm_vcpu_apicv_active(vcpu))
88ab24ad
JR		 3264 return;
3265
649d6864
JR		 3266 cr8 = kvm_get_cr8(vcpu);
3267 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3268 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3269}
3270
9222be18
GN		 3271static void svm_complete_interrupts(struct vcpu_svm *svm)
3272{
3273 u8 vector;
3274 int type;
3275 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3276 unsigned int3_injected = svm->int3_injected;
3277
3278 svm->int3_injected = 0;
9222be18 3279
bd3d1ec3
AK		 3280 /*
3281 * If we've made progress since setting HF_IRET_MASK, we've
3282 * executed an IRET and can allow NMI injection.
3283 */
3284 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3285 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
44c11430 3286 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3842d135
AK		 3287 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3288 }
44c11430 3289
9222be18
GN		 3290 svm->vcpu.arch.nmi_injected = false;
3291 kvm_clear_exception_queue(&svm->vcpu);
3292 kvm_clear_interrupt_queue(&svm->vcpu);
3293
3294 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3295 return;
3296
3842d135
AK		 3297 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3298
9222be18
GN		 3299 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3300 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3301
3302 switch (type) {
3303 case SVM_EXITINTINFO_TYPE_NMI:
3304 svm->vcpu.arch.nmi_injected = true;
3305 break;
3306 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3307 /*
3308 * In case of software exceptions, do not reinject the vector,
3309 * but re-execute the instruction instead. Rewind RIP first
3310 * if we emulated INT3 before.
3311 */
3312 if (kvm_exception_is_soft(vector)) {
3313 if (vector == BP_VECTOR && int3_injected &&
3314 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3315 kvm_rip_write(&svm->vcpu,
3316 kvm_rip_read(&svm->vcpu) -
3317 int3_injected);
9222be18 3318 break;
66b7138f 3319 }
9222be18
GN		 3320 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3321 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3322 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3323
3324 } else
ce7ddec4 3325 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3326 break;
3327 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3328 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3329 break;
3330 default:
3331 break;
3332 }
3333}
3334
b463a6f7
AK		 3335static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3336{
3337 struct vcpu_svm *svm = to_svm(vcpu);
3338 struct vmcb_control_area *control = &svm->vmcb->control;
3339
3340 control->exit_int_info = control->event_inj;
3341 control->exit_int_info_err = control->event_inj_err;
3342 control->event_inj = 0;
3343 svm_complete_interrupts(svm);
3344}
3345
404d5d7b 3346static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
a9ab13ff
WL		 3347{
3348 if (!is_guest_mode(vcpu) &&
3349 to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3350 to_svm(vcpu)->vmcb->control.exit_info_1)
3351 return handle_fastpath_set_msr_irqoff(vcpu);
3352
3353 return EXIT_FASTPATH_NONE;
3354}
3355
56a87e5d 3356void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
199cd1d7 3357
135961e0
TG		 3358static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3359 struct vcpu_svm *svm)
3360{
3361 /*
3362 * VMENTER enables interrupts (host state), but the kernel state is
3363 * interrupts disabled when this is invoked. Also tell RCU about
3364 * it. This is the same logic as for exit_to_user_mode().
3365 *
3366 * This ensures that e.g. latency analysis on the host observes
3367 * guest mode as interrupt enabled.
3368 *
3369 * guest_enter_irqoff() informs context tracking about the
3370 * transition to guest mode and if enabled adjusts RCU state
3371 * accordingly.
3372 */
3373 instrumentation_begin();
3374 trace_hardirqs_on_prepare();
3375 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3376 instrumentation_end();
3377
3378 guest_enter_irqoff();
3379 lockdep_hardirqs_on(CALLER_ADDR0);
3380
3381 __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3382
3383#ifdef CONFIG_X86_64
c3f08ed1 3384 native_wrmsrl(MSR_GS_BASE, svm->host.gs_base);
135961e0
TG		 3385#else
3386 loadsegment(fs, svm->host.fs);
3387#ifndef CONFIG_X86_32_LAZY_GS
3388 loadsegment(gs, svm->host.gs);
3389#endif
3390#endif
3391
3392 /*
3393 * VMEXIT disables interrupts (host state), but tracing and lockdep
3394 * have them in state 'on' as recorded before entering guest mode.
3395 * Same as enter_from_user_mode().
3396 *
3397 * guest_exit_irqoff() restores host context and reinstates RCU if
3398 * enabled and required.
3399 *
3400 * This needs to be done before the below as native_read_msr()
3401 * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3402 * into world and some more.
3403 */
3404 lockdep_hardirqs_off(CALLER_ADDR0);
3405 guest_exit_irqoff();
3406
3407 instrumentation_begin();
3408 trace_hardirqs_off_finish();
3409 instrumentation_end();
3410}
3411
b95273f1 3412static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3413{
404d5d7b 3414 fastpath_t exit_fastpath;
a2fa3e9f 3415 struct vcpu_svm *svm = to_svm(vcpu);
d9e368d6 3416
2041a06a
JR		 3417 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3418 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3419 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3420
a12713c2
LP		 3421 /*
3422 * Disable singlestep if we're injecting an interrupt/exception.
3423 * We don't want our modified rflags to be pushed on the stack where
3424 * we might not be able to easily reset them if we disabled NMI
3425 * singlestep later.
3426 */
3427 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3428 /*
3429 * Event injection happens before external interrupts cause a
3430 * vmexit and interrupts are disabled here, so smp_send_reschedule
3431 * is enough to force an immediate vmexit.
3432 */
3433 disable_nmi_singlestep(svm);
3434 smp_send_reschedule(vcpu->cpu);
3435 }
3436
e756fc62 3437 pre_svm_run(svm);
6aa8b732 3438
649d6864
JR		 3439 sync_lapic_to_cr8(vcpu);
3440
cda0ffdd 3441 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3442
d67668e9
PB		 3443 /*
3444 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3445 * of a #DB.
3446 */
3447 if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3448 svm_set_dr6(svm, vcpu->arch.dr6);
3449 else
3450 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3451
04d2cc77 3452 clgi();
139a12cf 3453 kvm_load_guest_xsave_state(vcpu);
04d2cc77 3454
010fd37f 3455 kvm_wait_lapic_expire(vcpu);
b6c4bc65 3456
b2ac58f9
KA		 3457 /*
3458 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3459 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3460 * is no need to worry about the conditional branch over the wrmsr
3461 * being speculatively taken.
3462 */
ccbcd267 3463 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
b2ac58f9 3464
135961e0 3465 svm_vcpu_enter_exit(vcpu, svm);
15e6c22f 3466
b2ac58f9
KA		 3467 /*
3468 * We do not use IBRS in the kernel. If this vCPU has used the
3469 * SPEC_CTRL MSR it may have left it on; save the value and
3470 * turn it off. This is much more efficient than blindly adding
3471 * it to the atomic save/restore list. Especially as the former
3472 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3473 *
3474 * For non-nested case:
3475 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3476 * save it.
3477 *
3478 * For nested case:
3479 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3480 * save it.
3481 */
946fbbc1 3482 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
ecb586bd 3483 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b2ac58f9 3484
6aa8b732
AK		 3485 reload_tss(vcpu);
3486
024d83ca
TG		 3487 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3488
13c34e07
AK		 3489 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3490 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3491 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3492 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3493
3781c01c 3494 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
dd60d217 3495 kvm_before_interrupt(&svm->vcpu);
3781c01c 3496
139a12cf 3497 kvm_load_host_xsave_state(vcpu);
3781c01c
JR		 3498 stgi();
3499
3500 /* Any pending NMI will happen here */
3501
3502 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
dd60d217 3503 kvm_after_interrupt(&svm->vcpu);
3781c01c 3504
d7bf8221
JR		 3505 sync_cr8_to_lapic(vcpu);
3506
a2fa3e9f 3507 svm->next_rip = 0;
2d8a42be
PB		 3508 if (is_guest_mode(&svm->vcpu)) {
3509 sync_nested_vmcb_control(svm);
3510 svm->nested.nested_run_pending = 0;
3511 }
9222be18 3512
38e5e92f 3513 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
e42c6828 3514 vmcb_mark_all_clean(svm->vmcb);
38e5e92f 3515
631bc487
GN		 3516 /* if exit due to PF check for async PF */
3517 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
68fd66f1
VK		 3518 svm->vcpu.arch.apf.host_apf_flags =
3519 kvm_read_and_reset_apf_flags();
631bc487 3520
6de4f3ad
AK		 3521 if (npt_enabled) {
3522 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3523 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3524 }
fe5913e4
JR		 3525
3526 /*
3527 * We need to handle MC intercepts here before the vcpu has a chance to
3528 * change the physical cpu
3529 */
3530 if (unlikely(svm->vmcb->control.exit_code ==
3531 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3532 svm_handle_mce(svm);
8d28fec4 3533
e42c6828
WL		 3534 svm_complete_interrupts(svm);
3535 exit_fastpath = svm_exit_handlers_fastpath(vcpu);
a9ab13ff 3536 return exit_fastpath;
6aa8b732
AK		 3537}
3538
2a40b900
SC		 3539static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root,
3540 int root_level)
6aa8b732 3541{
a2fa3e9f 3542 struct vcpu_svm *svm = to_svm(vcpu);
689f3bf2 3543 unsigned long cr3;
a2fa3e9f 3544
689f3bf2
PB		 3545 cr3 = __sme_set(root);
3546 if (npt_enabled) {
3547 svm->vmcb->control.nested_cr3 = cr3;
06e7852c 3548 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
1c97f0a0 3549
689f3bf2 3550 /* Loading L2's CR3 is handled by enter_svm_guest_mode. */
978ce583
PB		 3551 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3552 return;
3553 cr3 = vcpu->arch.cr3;
689f3bf2 3554 }
1c97f0a0 3555
978ce583 3556 svm->vmcb->save.cr3 = cr3;
06e7852c 3557 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1c97f0a0
JR		 3558}
3559
6aa8b732
AK		 3560static int is_disabled(void)
3561{
6031a61c
JR		 3562 u64 vm_cr;
3563
3564 rdmsrl(MSR_VM_CR, vm_cr);
3565 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3566 return 1;
3567
6aa8b732
AK		 3568 return 0;
3569}
3570
102d8325
IM		 3571static void
3572svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3573{
3574 /*
3575 * Patch in the VMMCALL instruction:
3576 */
3577 hypercall[0] = 0x0f;
3578 hypercall[1] = 0x01;
3579 hypercall[2] = 0xd9;
102d8325
IM		 3580}
3581
f257d6dc 3582static int __init svm_check_processor_compat(void)
002c7f7c 3583{
f257d6dc 3584 return 0;
002c7f7c
YS		 3585}
3586
774ead3a
AK		 3587static bool svm_cpu_has_accelerated_tpr(void)
3588{
3589 return false;
3590}
3591
cb97c2d6 3592static bool svm_has_emulated_msr(u32 index)
6d396b55 3593{
e87555e5
VK		 3594 switch (index) {
3595 case MSR_IA32_MCG_EXT_CTL:
95c5c7c7 3596 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
e87555e5
VK		 3597 return false;
3598 default:
3599 break;
3600 }
3601
6d396b55
PB		 3602 return true;
3603}
3604
fc07e76a
PB		 3605static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3606{
3607 return 0;
3608}
3609
7c1b761b 3610static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
0e851880 3611{
6092d3d3
JR		 3612 struct vcpu_svm *svm = to_svm(vcpu);
3613
7204160e 3614 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
96be4e06 3615 boot_cpu_has(X86_FEATURE_XSAVE) &&
7204160e
AL		 3616 boot_cpu_has(X86_FEATURE_XSAVES);
3617
6092d3d3 3618 /* Update nrips enabled cache */
4eb87460
SC		 3619 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3620 guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
46781eae
SS		 3621
3622 if (!kvm_vcpu_apicv_active(vcpu))
3623 return;
3624
cc7f5577
OU		 3625 /*
3626 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3627 * is exposed to the guest, disable AVIC.
3628 */
3629 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3630 kvm_request_apicv_update(vcpu->kvm, false,
3631 APICV_INHIBIT_REASON_X2APIC);
9a0bf054
SS		 3632
3633 /*
3634 * Currently, AVIC does not work with nested virtualization.
3635 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3636 */
3637 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3638 kvm_request_apicv_update(vcpu->kvm, false,
3639 APICV_INHIBIT_REASON_NESTED);
0e851880
SY		 3640}
3641
f5f48ee1
SY		 3642static bool svm_has_wbinvd_exit(void)
3643{
3644 return true;
3645}
3646
8061252e 3647#define PRE_EX(exit) { .exit_code = (exit), \
40e19b51 3648 .stage = X86_ICPT_PRE_EXCEPT, }
cfec82cb 3649#define POST_EX(exit) { .exit_code = (exit), \
40e19b51 3650 .stage = X86_ICPT_POST_EXCEPT, }
d7eb8203 3651#define POST_MEM(exit) { .exit_code = (exit), \
40e19b51 3652 .stage = X86_ICPT_POST_MEMACCESS, }
cfec82cb 3653
09941fbb 3654static const struct __x86_intercept {
cfec82cb
JR		 3655 u32 exit_code;
3656 enum x86_intercept_stage stage;
cfec82cb
JR		 3657} x86_intercept_map[] = {
3658 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
3659 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
3660 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
3661 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
3662 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
3b88e41a
JR		 3663 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
3664 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
dee6bb70
JR		 3665 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
3666 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
3667 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
3668 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
3669 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
3670 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
3671 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
3672 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
01de8b09
JR		 3673 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
3674 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
3675 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
3676 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
3677 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
3678 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
3679 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
3680 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
d7eb8203
JR		 3681 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
3682 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
3683 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
8061252e
JR		 3684 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
3685 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
3686 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
3687 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
3688 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
3689 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
3690 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
3691 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
3692 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
bf608f88
JR		 3693 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
3694 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
3695 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
3696 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
3697 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
3698 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
3699 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
f6511935
JR		 3700 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
3701 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
3702 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
3703 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
02d4160f 3704 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
cfec82cb
JR		 3705};
3706
8061252e 3707#undef PRE_EX
cfec82cb 3708#undef POST_EX
d7eb8203 3709#undef POST_MEM
cfec82cb 3710
8a76d7f2
JR		 3711static int svm_check_intercept(struct kvm_vcpu *vcpu,
3712 struct x86_instruction_info *info,
21f1b8f2
SC		 3713 enum x86_intercept_stage stage,
3714 struct x86_exception *exception)
8a76d7f2 3715{
cfec82cb
JR		 3716 struct vcpu_svm *svm = to_svm(vcpu);
3717 int vmexit, ret = X86EMUL_CONTINUE;
3718 struct __x86_intercept icpt_info;
3719 struct vmcb *vmcb = svm->vmcb;
3720
3721 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3722 goto out;
3723
3724 icpt_info = x86_intercept_map[info->intercept];
3725
40e19b51 3726 if (stage != icpt_info.stage)
cfec82cb
JR		 3727 goto out;
3728
3729 switch (icpt_info.exit_code) {
3730 case SVM_EXIT_READ_CR0:
3731 if (info->intercept == x86_intercept_cr_read)
3732 icpt_info.exit_code += info->modrm_reg;
3733 break;
3734 case SVM_EXIT_WRITE_CR0: {
3735 unsigned long cr0, val;
cfec82cb
JR		 3736
3737 if (info->intercept == x86_intercept_cr_write)
3738 icpt_info.exit_code += info->modrm_reg;
3739
62baf44c
JK		 3740 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3741 info->intercept == x86_intercept_clts)
cfec82cb
JR		 3742 break;
3743
c62e2e94
BM		 3744 if (!(vmcb_is_intercept(&svm->nested.ctl,
3745 INTERCEPT_SELECTIVE_CR0)))
cfec82cb
JR		 3746 break;
3747
3748 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3749 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
3750
3751 if (info->intercept == x86_intercept_lmsw) {
3752 cr0 &= 0xfUL;
3753 val &= 0xfUL;
3754 /* lmsw can't clear PE - catch this here */
3755 if (cr0 & X86_CR0_PE)
3756 val |= X86_CR0_PE;
3757 }
3758
3759 if (cr0 ^ val)
3760 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3761
3762 break;
3763 }
3b88e41a
JR		 3764 case SVM_EXIT_READ_DR0:
3765 case SVM_EXIT_WRITE_DR0:
3766 icpt_info.exit_code += info->modrm_reg;
3767 break;
8061252e
JR		 3768 case SVM_EXIT_MSR:
3769 if (info->intercept == x86_intercept_wrmsr)
3770 vmcb->control.exit_info_1 = 1;
3771 else
3772 vmcb->control.exit_info_1 = 0;
3773 break;
bf608f88
JR		 3774 case SVM_EXIT_PAUSE:
3775 /*
3776 * We get this for NOP only, but pause
3777 * is rep not, check this here
3778 */
3779 if (info->rep_prefix != REPE_PREFIX)
3780 goto out;
49a8afca 3781 break;
f6511935
JR		 3782 case SVM_EXIT_IOIO: {
3783 u64 exit_info;
3784 u32 bytes;
3785
f6511935
JR		 3786 if (info->intercept == x86_intercept_in ||
3787 info->intercept == x86_intercept_ins) {
6cbc5f5a
JK		 3788 exit_info = ((info->src_val & 0xffff) << 16) |
3789 SVM_IOIO_TYPE_MASK;
f6511935 3790 bytes = info->dst_bytes;
6493f157 3791 } else {
6cbc5f5a 3792 exit_info = (info->dst_val & 0xffff) << 16;
6493f157 3793 bytes = info->src_bytes;
f6511935
JR		 3794 }
3795
3796 if (info->intercept == x86_intercept_outs ||
3797 info->intercept == x86_intercept_ins)
3798 exit_info |= SVM_IOIO_STR_MASK;
3799
3800 if (info->rep_prefix)
3801 exit_info |= SVM_IOIO_REP_MASK;
3802
3803 bytes = min(bytes, 4u);
3804
3805 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
3806
3807 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
3808
3809 vmcb->control.exit_info_1 = exit_info;
3810 vmcb->control.exit_info_2 = info->next_rip;
3811
3812 break;
3813 }
cfec82cb
JR		 3814 default:
3815 break;
3816 }
3817
f104765b
BD		 3818 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
3819 if (static_cpu_has(X86_FEATURE_NRIPS))
3820 vmcb->control.next_rip = info->next_rip;
cfec82cb
JR		 3821 vmcb->control.exit_code = icpt_info.exit_code;
3822 vmexit = nested_svm_exit_handled(svm);
3823
3824 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
3825 : X86EMUL_CONTINUE;
3826
3827out:
3828 return ret;
8a76d7f2
JR		 3829}
3830
a9ab13ff 3831static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
a547c6db 3832{
a547c6db
YZ		 3833}
3834
ae97a3b8
RK		 3835static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
3836{
830f01b0 3837 if (!kvm_pause_in_guest(vcpu->kvm))
8566ac8b 3838 shrink_ple_window(vcpu);
ae97a3b8
RK		 3839}
3840
74f16909
BP		 3841static void svm_setup_mce(struct kvm_vcpu *vcpu)
3842{
3843 /* [63:9] are reserved. */
3844 vcpu->arch.mcg_cap &= 0x1ff;
3845}
3846
cae96af1 3847bool svm_smi_blocked(struct kvm_vcpu *vcpu)
72d7b374 3848{
05cade71
LP		 3849 struct vcpu_svm *svm = to_svm(vcpu);
3850
3851 /* Per APM Vol.2 15.22.2 "Response to SMI" */
3852 if (!gif_set(svm))
cae96af1
PB		 3853 return true;
3854
3855 return is_smm(vcpu);
3856}
3857
c9d40913 3858static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3859{
3860 struct vcpu_svm *svm = to_svm(vcpu);
3861 if (svm->nested.nested_run_pending)
c9d40913 3862 return -EBUSY;
05cade71 3863
c300ab9f
PB		 3864 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
3865 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
c9d40913 3866 return -EBUSY;
c300ab9f 3867
cae96af1 3868 return !svm_smi_blocked(vcpu);
72d7b374
LP		 3869}
3870
0234bf88
LP		 3871static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
3872{
05cade71
LP		 3873 struct vcpu_svm *svm = to_svm(vcpu);
3874 int ret;
3875
3876 if (is_guest_mode(vcpu)) {
3877 /* FED8h - SVM Guest */
3878 put_smstate(u64, smstate, 0x7ed8, 1);
3879 /* FEE0h - SVM Guest VMCB Physical Address */
0dd16b5b 3880 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
05cade71
LP		 3881
3882 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3883 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3884 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3885
3886 ret = nested_svm_vmexit(svm);
3887 if (ret)
3888 return ret;
3889 }
0234bf88
LP		 3890 return 0;
3891}
3892
ed19321f 3893static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
0234bf88 3894{
05cade71 3895 struct vcpu_svm *svm = to_svm(vcpu);
8c5fbf1a 3896 struct kvm_host_map map;
59cd9bc5 3897 int ret = 0;
05cade71 3898
3ebb5d26
ML		 3899 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
3900 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
3901 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
0dd16b5b 3902 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
05cade71 3903
3ebb5d26
ML		 3904 if (guest) {
3905 if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3906 return 1;
3907
3908 if (!(saved_efer & EFER_SVME))
3909 return 1;
3910
3911 if (kvm_vcpu_map(&svm->vcpu,
0dd16b5b 3912 gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
3ebb5d26
ML		 3913 return 1;
3914
0dd16b5b 3915 ret = enter_svm_guest_mode(svm, vmcb12_gpa, map.hva);
3ebb5d26
ML		 3916 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3917 }
05cade71 3918 }
59cd9bc5
VK		 3919
3920 return ret;
0234bf88
LP		 3921}
3922
c9d40913 3923static void enable_smi_window(struct kvm_vcpu *vcpu)
cc3d967f
LP		 3924{
3925 struct vcpu_svm *svm = to_svm(vcpu);
3926
3927 if (!gif_set(svm)) {
3928 if (vgif_enabled(svm))
a284ba56 3929 svm_set_intercept(svm, INTERCEPT_STGI);
cc3d967f 3930 /* STGI will cause a vm exit */
c9d40913
PB		 3931 } else {
3932 /* We must be in SMM; RSM will cause a vmexit anyway. */
cc3d967f 3933 }
cc3d967f
LP		 3934}
3935
05d5a486
SB		 3936static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
3937{
118154bd
LA		 3938 unsigned long cr4 = kvm_read_cr4(vcpu);
3939 bool smep = cr4 & X86_CR4_SMEP;
3940 bool smap = cr4 & X86_CR4_SMAP;
3941 bool is_user = svm_get_cpl(vcpu) == 3;
05d5a486 3942
e72436bc
PB		 3943 /*
3944 * If RIP is invalid, go ahead with emulation which will cause an
3945 * internal error exit.
3946 */
3947 if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
3948 return true;
3949
05d5a486 3950 /*
118154bd
LA		 3951 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
3952 *
3953 * Errata:
3954 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
3955 * possible that CPU microcode implementing DecodeAssist will fail
3956 * to read bytes of instruction which caused #NPF. In this case,
3957 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
3958 * return 0 instead of the correct guest instruction bytes.
3959 *
3960 * This happens because CPU microcode reading instruction bytes
3961 * uses a special opcode which attempts to read data using CPL=0
3962 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
3963 * fault, it gives up and returns no instruction bytes.
3964 *
3965 * Detection:
3966 * We reach here in case CPU supports DecodeAssist, raised #NPF and
3967 * returned 0 in GuestIntrBytes field of the VMCB.
3968 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
3969 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
3970 * in case vCPU CPL==3 (Because otherwise guest would have triggered
3971 * a SMEP fault instead of #NPF).
3972 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
3973 * As most guests enable SMAP if they have also enabled SMEP, use above
3974 * logic in order to attempt minimize false-positive of detecting errata
3975 * while still preserving all cases semantic correctness.
3976 *
3977 * Workaround:
3978 * To determine what instruction the guest was executing, the hypervisor
3979 * will have to decode the instruction at the instruction pointer.
05d5a486
SB		 3980 *
3981 * In non SEV guest, hypervisor will be able to read the guest
3982 * memory to decode the instruction pointer when insn_len is zero
3983 * so we return true to indicate that decoding is possible.
3984 *
3985 * But in the SEV guest, the guest memory is encrypted with the
3986 * guest specific key and hypervisor will not be able to decode the
3987 * instruction pointer so we will not able to workaround it. Lets
3988 * print the error and request to kill the guest.
3989 */
118154bd 3990 if (smap && (!smep || is_user)) {
05d5a486
SB		 3991 if (!sev_guest(vcpu->kvm))
3992 return true;
3993
118154bd 3994 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
05d5a486
SB		 3995 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3996 }
3997
3998 return false;
3999}
4000
4b9852f4
LA		 4001static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4002{
4003 struct vcpu_svm *svm = to_svm(vcpu);
4004
4005 /*
4006 * TODO: Last condition latch INIT signals on vCPU when
4007 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
33b22172
PB		 4008 * To properly emulate the INIT intercept,
4009 * svm_check_nested_events() should call nested_svm_vmexit()
4010 * if an INIT signal is pending.
4b9852f4
LA		 4011 */
4012 return !gif_set(svm) ||
c62e2e94 4013 (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4b9852f4
LA		 4014}
4015
eaf78265
JR		 4016static void svm_vm_destroy(struct kvm *kvm)
4017{
4018 avic_vm_destroy(kvm);
4019 sev_vm_destroy(kvm);
4020}
4021
4022static int svm_vm_init(struct kvm *kvm)
4023{
830f01b0
WL		 4024 if (!pause_filter_count || !pause_filter_thresh)
4025 kvm->arch.pause_in_guest = true;
4026
eaf78265
JR		 4027 if (avic) {
4028 int ret = avic_vm_init(kvm);
4029 if (ret)
4030 return ret;
4031 }
4032
4033 kvm_apicv_init(kvm, avic);
4034 return 0;
4035}
4036
9c14ee21 4037static struct kvm_x86_ops svm_x86_ops __initdata = {
dd58f3c9 4038 .hardware_unsetup = svm_hardware_teardown,
6aa8b732
AK		 4039 .hardware_enable = svm_hardware_enable,
4040 .hardware_disable = svm_hardware_disable,
774ead3a 4041 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
bc226f07 4042 .has_emulated_msr = svm_has_emulated_msr,
6aa8b732
AK		 4043
4044 .vcpu_create = svm_create_vcpu,
4045 .vcpu_free = svm_free_vcpu,
04d2cc77 4046 .vcpu_reset = svm_vcpu_reset,
6aa8b732 4047
562b6b08 4048 .vm_size = sizeof(struct kvm_svm),
4e19c36f 4049 .vm_init = svm_vm_init,
1654efcb 4050 .vm_destroy = svm_vm_destroy,
44a95dae 4051
04d2cc77 4052 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 4053 .vcpu_load = svm_vcpu_load,
4054 .vcpu_put = svm_vcpu_put,
8221c137
SS		 4055 .vcpu_blocking = svm_vcpu_blocking,
4056 .vcpu_unblocking = svm_vcpu_unblocking,
6aa8b732 4057
6986982f 4058 .update_exception_bitmap = update_exception_bitmap,
801e459a 4059 .get_msr_feature = svm_get_msr_feature,
6aa8b732
AK		 4060 .get_msr = svm_get_msr,
4061 .set_msr = svm_set_msr,
4062 .get_segment_base = svm_get_segment_base,
4063 .get_segment = svm_get_segment,
4064 .set_segment = svm_set_segment,
2e4d2653 4065 .get_cpl = svm_get_cpl,
1747fb71 4066 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
6aa8b732 4067 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 4068 .set_cr4 = svm_set_cr4,
4069 .set_efer = svm_set_efer,
4070 .get_idt = svm_get_idt,
4071 .set_idt = svm_set_idt,
4072 .get_gdt = svm_get_gdt,
4073 .set_gdt = svm_set_gdt,
020df079 4074 .set_dr7 = svm_set_dr7,
facb0139 4075 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
6de4f3ad 4076 .cache_reg = svm_cache_reg,
6aa8b732
AK		 4077 .get_rflags = svm_get_rflags,
4078 .set_rflags = svm_set_rflags,
be94f6b7 4079
7780938c 4080 .tlb_flush_all = svm_flush_tlb,
eeeb4f67 4081 .tlb_flush_current = svm_flush_tlb,
faff8758 4082 .tlb_flush_gva = svm_flush_tlb_gva,
72b38320 4083 .tlb_flush_guest = svm_flush_tlb,
6aa8b732 4084
6aa8b732 4085 .run = svm_vcpu_run,
04d2cc77 4086 .handle_exit = handle_exit,
6aa8b732 4087 .skip_emulated_instruction = skip_emulated_instruction,
5ef8acbd 4088 .update_emulated_instruction = NULL,
2809f5d2
GC		 4089 .set_interrupt_shadow = svm_set_interrupt_shadow,
4090 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 4091 .patch_hypercall = svm_patch_hypercall,
2a8067f1 4092 .set_irq = svm_set_irq,
95ba8273 4093 .set_nmi = svm_inject_nmi,
298101da 4094 .queue_exception = svm_queue_exception,
b463a6f7 4095 .cancel_injection = svm_cancel_injection,
78646121 4096 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 4097 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 4098 .get_nmi_mask = svm_get_nmi_mask,
4099 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 4100 .enable_nmi_window = enable_nmi_window,
4101 .enable_irq_window = enable_irq_window,
4102 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 4103 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
d62caabb 4104 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
ef8efd7a 4105 .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
2de9d0cc 4106 .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
c7c9c56c 4107 .load_eoi_exitmap = svm_load_eoi_exitmap,
44a95dae
SS		 4108 .hwapic_irr_update = svm_hwapic_irr_update,
4109 .hwapic_isr_update = svm_hwapic_isr_update,
fa59cc00 4110 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
be8ca170 4111 .apicv_post_state_restore = avic_post_state_restore,
cbc94022
IE		 4112
4113 .set_tss_addr = svm_set_tss_addr,
2ac52ab8 4114 .set_identity_map_addr = svm_set_identity_map_addr,
4b12f0de 4115 .get_mt_mask = svm_get_mt_mask,
229456fc 4116
586f9607 4117 .get_exit_info = svm_get_exit_info,
586f9607 4118
7c1b761b 4119 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4e47c7a6 4120
f5f48ee1 4121 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a 4122
326e7425 4123 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
1c97f0a0 4124
727a7e27 4125 .load_mmu_pgd = svm_load_mmu_pgd,
8a76d7f2
JR		 4126
4127 .check_intercept = svm_check_intercept,
95b5a48c 4128 .handle_exit_irqoff = svm_handle_exit_irqoff,
ae97a3b8 4129
d264ee0c
SC		 4130 .request_immediate_exit = __kvm_request_immediate_exit,
4131
ae97a3b8 4132 .sched_in = svm_sched_in,
25462f7f
WH		 4133
4134 .pmu_ops = &amd_pmu_ops,
33b22172
PB		 4135 .nested_ops = &svm_nested_ops,
4136
340d3bc3 4137 .deliver_posted_interrupt = svm_deliver_avic_intr,
17e433b5 4138 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
411b44ba 4139 .update_pi_irte = svm_update_pi_irte,
74f16909 4140 .setup_mce = svm_setup_mce,
0234bf88 4141
72d7b374 4142 .smi_allowed = svm_smi_allowed,
0234bf88
LP		 4143 .pre_enter_smm = svm_pre_enter_smm,
4144 .pre_leave_smm = svm_pre_leave_smm,
cc3d967f 4145 .enable_smi_window = enable_smi_window,
1654efcb
BS		 4146
4147 .mem_enc_op = svm_mem_enc_op,
1e80fdc0
BS		 4148 .mem_enc_reg_region = svm_register_enc_region,
4149 .mem_enc_unreg_region = svm_unregister_enc_region,
57b119da 4150
05d5a486 4151 .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
4b9852f4
LA		 4152
4153 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
6aa8b732
AK		 4154};
4155
d008dfdb
SC		 4156static struct kvm_x86_init_ops svm_init_ops __initdata = {
4157 .cpu_has_kvm_support = has_svm,
4158 .disabled_by_bios = is_disabled,
4159 .hardware_setup = svm_hardware_setup,
4160 .check_processor_compatibility = svm_check_processor_compat,
4161
4162 .runtime_ops = &svm_x86_ops,
6aa8b732
AK		 4163};
4164
4165static int __init svm_init(void)
4166{
d07f46f9
TL		 4167 __unused_size_checks();
4168
d008dfdb 4169 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
0ee75bea 4170 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 4171}
4172
4173static void __exit svm_exit(void)
4174{
cb498ea2 4175 kvm_exit();
6aa8b732
AK		 4176}
4177
4178module_init(svm_init)
4179module_exit(svm_exit)
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