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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
44a95dae SS |
17 | |
18 | #define pr_fmt(fmt) "SVM: " fmt | |
19 | ||
edf88417 AK |
20 | #include <linux/kvm_host.h> |
21 | ||
85f455f7 | 22 | #include "irq.h" |
1d737c8a | 23 | #include "mmu.h" |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
fe4c7b19 | 25 | #include "x86.h" |
66f7b72e | 26 | #include "cpuid.h" |
25462f7f | 27 | #include "pmu.h" |
e495606d | 28 | |
6aa8b732 | 29 | #include <linux/module.h> |
ae759544 | 30 | #include <linux/mod_devicetable.h> |
9d8f549d | 31 | #include <linux/kernel.h> |
6aa8b732 AK |
32 | #include <linux/vmalloc.h> |
33 | #include <linux/highmem.h> | |
e8edc6e0 | 34 | #include <linux/sched.h> |
af658dca | 35 | #include <linux/trace_events.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
5881f737 SS |
37 | #include <linux/amd-iommu.h> |
38 | #include <linux/hashtable.h> | |
c207aee4 | 39 | #include <linux/frame.h> |
e9df0942 | 40 | #include <linux/psp-sev.h> |
1654efcb | 41 | #include <linux/file.h> |
89c50580 BS |
42 | #include <linux/pagemap.h> |
43 | #include <linux/swap.h> | |
6aa8b732 | 44 | |
8221c137 | 45 | #include <asm/apic.h> |
1018faa6 | 46 | #include <asm/perf_event.h> |
67ec6607 | 47 | #include <asm/tlbflush.h> |
e495606d | 48 | #include <asm/desc.h> |
facb0139 | 49 | #include <asm/debugreg.h> |
631bc487 | 50 | #include <asm/kvm_para.h> |
411b44ba | 51 | #include <asm/irq_remapping.h> |
6aa8b732 | 52 | |
63d1142f | 53 | #include <asm/virtext.h> |
229456fc | 54 | #include "trace.h" |
63d1142f | 55 | |
4ecac3fd AK |
56 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
57 | ||
6aa8b732 AK |
58 | MODULE_AUTHOR("Qumranet"); |
59 | MODULE_LICENSE("GPL"); | |
60 | ||
ae759544 JT |
61 | static const struct x86_cpu_id svm_cpu_id[] = { |
62 | X86_FEATURE_MATCH(X86_FEATURE_SVM), | |
63 | {} | |
64 | }; | |
65 | MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id); | |
66 | ||
6aa8b732 AK |
67 | #define IOPM_ALLOC_ORDER 2 |
68 | #define MSRPM_ALLOC_ORDER 1 | |
69 | ||
6aa8b732 AK |
70 | #define SEG_TYPE_LDT 2 |
71 | #define SEG_TYPE_BUSY_TSS16 3 | |
72 | ||
6bc31bdc AP |
73 | #define SVM_FEATURE_NPT (1 << 0) |
74 | #define SVM_FEATURE_LBRV (1 << 1) | |
75 | #define SVM_FEATURE_SVML (1 << 2) | |
76 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
77 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
78 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
79 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
80 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 81 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 82 | |
340d3bc3 SS |
83 | #define SVM_AVIC_DOORBELL 0xc001011b |
84 | ||
410e4d57 JR |
85 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
86 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
87 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
88 | ||
24e09cbf JR |
89 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
90 | ||
fbc0db76 | 91 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
92a1f12d JR |
92 | #define TSC_RATIO_MIN 0x0000000000000001ULL |
93 | #define TSC_RATIO_MAX 0x000000ffffffffffULL | |
fbc0db76 | 94 | |
5446a979 | 95 | #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) |
44a95dae SS |
96 | |
97 | /* | |
98 | * 0xff is broadcast, so the max index allowed for physical APIC ID | |
99 | * table is 0xfe. APIC IDs above 0xff are reserved. | |
100 | */ | |
101 | #define AVIC_MAX_PHYSICAL_ID_COUNT 255 | |
102 | ||
18f40c53 SS |
103 | #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 |
104 | #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 | |
105 | #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF | |
106 | ||
5ea11f2b SS |
107 | /* AVIC GATAG is encoded using VM and VCPU IDs */ |
108 | #define AVIC_VCPU_ID_BITS 8 | |
109 | #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1) | |
110 | ||
111 | #define AVIC_VM_ID_BITS 24 | |
112 | #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS) | |
113 | #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1) | |
114 | ||
115 | #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \ | |
116 | (y & AVIC_VCPU_ID_MASK)) | |
117 | #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK) | |
118 | #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK) | |
119 | ||
67ec6607 JR |
120 | static bool erratum_383_found __read_mostly; |
121 | ||
6c8166a7 AK |
122 | static const u32 host_save_user_msrs[] = { |
123 | #ifdef CONFIG_X86_64 | |
124 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
125 | MSR_FS_BASE, | |
126 | #endif | |
127 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
46896c73 | 128 | MSR_TSC_AUX, |
6c8166a7 AK |
129 | }; |
130 | ||
131 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
132 | ||
133 | struct kvm_vcpu; | |
134 | ||
e6aa9abd JR |
135 | struct nested_state { |
136 | struct vmcb *hsave; | |
137 | u64 hsave_msr; | |
4a810181 | 138 | u64 vm_cr_msr; |
e6aa9abd JR |
139 | u64 vmcb; |
140 | ||
141 | /* These are the merged vectors */ | |
142 | u32 *msrpm; | |
143 | ||
144 | /* gpa pointers to the real vectors */ | |
145 | u64 vmcb_msrpm; | |
ce2ac085 | 146 | u64 vmcb_iopm; |
aad42c64 | 147 | |
cd3ff653 JR |
148 | /* A VMEXIT is required but not yet emulated */ |
149 | bool exit_required; | |
150 | ||
aad42c64 | 151 | /* cache for intercepts of the guest */ |
4ee546b4 | 152 | u32 intercept_cr; |
3aed041a | 153 | u32 intercept_dr; |
aad42c64 JR |
154 | u32 intercept_exceptions; |
155 | u64 intercept; | |
156 | ||
5bd2edc3 JR |
157 | /* Nested Paging related state */ |
158 | u64 nested_cr3; | |
e6aa9abd JR |
159 | }; |
160 | ||
323c3d80 JR |
161 | #define MSRPM_OFFSETS 16 |
162 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
163 | ||
2b036c6b BO |
164 | /* |
165 | * Set osvw_len to higher value when updated Revision Guides | |
166 | * are published and we know what the new status bits are | |
167 | */ | |
168 | static uint64_t osvw_len = 4, osvw_status; | |
169 | ||
6c8166a7 AK |
170 | struct vcpu_svm { |
171 | struct kvm_vcpu vcpu; | |
172 | struct vmcb *vmcb; | |
173 | unsigned long vmcb_pa; | |
174 | struct svm_cpu_data *svm_data; | |
175 | uint64_t asid_generation; | |
176 | uint64_t sysenter_esp; | |
177 | uint64_t sysenter_eip; | |
46896c73 | 178 | uint64_t tsc_aux; |
6c8166a7 AK |
179 | |
180 | u64 next_rip; | |
181 | ||
182 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 183 | struct { |
dacccfdd AK |
184 | u16 fs; |
185 | u16 gs; | |
186 | u16 ldt; | |
afe9e66f AK |
187 | u64 gs_base; |
188 | } host; | |
6c8166a7 AK |
189 | |
190 | u32 *msrpm; | |
6c8166a7 | 191 | |
bd3d1ec3 AK |
192 | ulong nmi_iret_rip; |
193 | ||
e6aa9abd | 194 | struct nested_state nested; |
6be7d306 JK |
195 | |
196 | bool nmi_singlestep; | |
ab2f4d73 | 197 | u64 nmi_singlestep_guest_rflags; |
66b7138f JK |
198 | |
199 | unsigned int3_injected; | |
200 | unsigned long int3_rip; | |
fbc0db76 | 201 | |
6092d3d3 JR |
202 | /* cached guest cpuid flags for faster access */ |
203 | bool nrips_enabled : 1; | |
44a95dae | 204 | |
18f40c53 | 205 | u32 ldr_reg; |
44a95dae SS |
206 | struct page *avic_backing_page; |
207 | u64 *avic_physical_id_cache; | |
8221c137 | 208 | bool avic_is_running; |
411b44ba SS |
209 | |
210 | /* | |
211 | * Per-vcpu list of struct amd_svm_iommu_ir: | |
212 | * This is used mainly to store interrupt remapping information used | |
213 | * when update the vcpu affinity. This avoids the need to scan for | |
214 | * IRTE and try to match ga_tag in the IOMMU driver. | |
215 | */ | |
216 | struct list_head ir_list; | |
217 | spinlock_t ir_list_lock; | |
70cd94e6 BS |
218 | |
219 | /* which host CPU was used for running this vcpu */ | |
220 | unsigned int last_cpu; | |
411b44ba SS |
221 | }; |
222 | ||
223 | /* | |
224 | * This is a wrapper of struct amd_iommu_ir_data. | |
225 | */ | |
226 | struct amd_svm_iommu_ir { | |
227 | struct list_head node; /* Used by SVM for per-vcpu ir_list */ | |
228 | void *data; /* Storing pointer to struct amd_ir_data */ | |
6c8166a7 AK |
229 | }; |
230 | ||
44a95dae SS |
231 | #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF) |
232 | #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) | |
233 | ||
234 | #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) | |
235 | #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) | |
236 | #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) | |
237 | #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) | |
238 | ||
fbc0db76 JR |
239 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
240 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
241 | ||
455716fa JR |
242 | #define MSR_INVALID 0xffffffffU |
243 | ||
09941fbb | 244 | static const struct svm_direct_access_msrs { |
ac72a9b7 JR |
245 | u32 index; /* Index of the MSR */ |
246 | bool always; /* True if intercept is always on */ | |
247 | } direct_access_msrs[] = { | |
8c06585d | 248 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
249 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
250 | #ifdef CONFIG_X86_64 | |
251 | { .index = MSR_GS_BASE, .always = true }, | |
252 | { .index = MSR_FS_BASE, .always = true }, | |
253 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
254 | { .index = MSR_LSTAR, .always = true }, | |
255 | { .index = MSR_CSTAR, .always = true }, | |
256 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
257 | #endif | |
258 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
259 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
260 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
261 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
262 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
263 | }; |
264 | ||
709ddebf JR |
265 | /* enable NPT for AMD64 and X86 with PAE */ |
266 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
267 | static bool npt_enabled = true; | |
268 | #else | |
e0231715 | 269 | static bool npt_enabled; |
709ddebf | 270 | #endif |
6c7dac72 | 271 | |
e2358851 DB |
272 | /* allow nested paging (virtualized MMU) for all guests */ |
273 | static int npt = true; | |
6c7dac72 | 274 | module_param(npt, int, S_IRUGO); |
e3da3acd | 275 | |
e2358851 DB |
276 | /* allow nested virtualization in KVM/SVM */ |
277 | static int nested = true; | |
236de055 AG |
278 | module_param(nested, int, S_IRUGO); |
279 | ||
44a95dae SS |
280 | /* enable / disable AVIC */ |
281 | static int avic; | |
5b8abf1f | 282 | #ifdef CONFIG_X86_LOCAL_APIC |
44a95dae | 283 | module_param(avic, int, S_IRUGO); |
5b8abf1f | 284 | #endif |
44a95dae | 285 | |
89c8a498 JN |
286 | /* enable/disable Virtual VMLOAD VMSAVE */ |
287 | static int vls = true; | |
288 | module_param(vls, int, 0444); | |
289 | ||
640bd6e5 JN |
290 | /* enable/disable Virtual GIF */ |
291 | static int vgif = true; | |
292 | module_param(vgif, int, 0444); | |
5ea11f2b | 293 | |
e9df0942 BS |
294 | /* enable/disable SEV support */ |
295 | static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT); | |
296 | module_param(sev, int, 0444); | |
297 | ||
79a8059d | 298 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
44874f84 | 299 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 300 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 301 | |
410e4d57 | 302 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 303 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 304 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
305 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
306 | bool has_error_code, u32 error_code); | |
307 | ||
8d28fec4 | 308 | enum { |
116a0a23 JR |
309 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
310 | pause filter count */ | |
f56838e4 | 311 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 312 | VMCB_ASID, /* ASID */ |
decdbf6a | 313 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 314 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 315 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 316 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 317 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 318 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 319 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 320 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
44a95dae SS |
321 | VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, |
322 | * AVIC PHYSICAL_TABLE pointer, | |
323 | * AVIC LOGICAL_TABLE pointer | |
324 | */ | |
8d28fec4 RJ |
325 | VMCB_DIRTY_MAX, |
326 | }; | |
327 | ||
0574dec0 JR |
328 | /* TPR and CR2 are always written before VMRUN */ |
329 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 | 330 | |
44a95dae SS |
331 | #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL |
332 | ||
ed3cd233 | 333 | static unsigned int max_sev_asid; |
1654efcb BS |
334 | static unsigned int min_sev_asid; |
335 | static unsigned long *sev_asid_bitmap; | |
89c50580 | 336 | #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT) |
1654efcb | 337 | |
1e80fdc0 BS |
338 | struct enc_region { |
339 | struct list_head list; | |
340 | unsigned long npages; | |
341 | struct page **pages; | |
342 | unsigned long uaddr; | |
343 | unsigned long size; | |
344 | }; | |
345 | ||
1654efcb BS |
346 | static inline bool svm_sev_enabled(void) |
347 | { | |
348 | return max_sev_asid; | |
349 | } | |
350 | ||
351 | static inline bool sev_guest(struct kvm *kvm) | |
352 | { | |
353 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
354 | ||
355 | return sev->active; | |
356 | } | |
ed3cd233 | 357 | |
70cd94e6 BS |
358 | static inline int sev_get_asid(struct kvm *kvm) |
359 | { | |
360 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
361 | ||
362 | return sev->asid; | |
363 | } | |
364 | ||
8d28fec4 RJ |
365 | static inline void mark_all_dirty(struct vmcb *vmcb) |
366 | { | |
367 | vmcb->control.clean = 0; | |
368 | } | |
369 | ||
370 | static inline void mark_all_clean(struct vmcb *vmcb) | |
371 | { | |
372 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
373 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
374 | } | |
375 | ||
376 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
377 | { | |
378 | vmcb->control.clean &= ~(1 << bit); | |
379 | } | |
380 | ||
a2fa3e9f GH |
381 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
382 | { | |
fb3f0f51 | 383 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
384 | } |
385 | ||
44a95dae SS |
386 | static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data) |
387 | { | |
388 | svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK; | |
389 | mark_dirty(svm->vmcb, VMCB_AVIC); | |
390 | } | |
391 | ||
340d3bc3 SS |
392 | static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) |
393 | { | |
394 | struct vcpu_svm *svm = to_svm(vcpu); | |
395 | u64 *entry = svm->avic_physical_id_cache; | |
396 | ||
397 | if (!entry) | |
398 | return false; | |
399 | ||
400 | return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
401 | } | |
402 | ||
384c6368 JR |
403 | static void recalc_intercepts(struct vcpu_svm *svm) |
404 | { | |
405 | struct vmcb_control_area *c, *h; | |
406 | struct nested_state *g; | |
407 | ||
116a0a23 JR |
408 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
409 | ||
384c6368 JR |
410 | if (!is_guest_mode(&svm->vcpu)) |
411 | return; | |
412 | ||
413 | c = &svm->vmcb->control; | |
414 | h = &svm->nested.hsave->control; | |
415 | g = &svm->nested; | |
416 | ||
4ee546b4 | 417 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 418 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
419 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
420 | c->intercept = h->intercept | g->intercept; | |
421 | } | |
422 | ||
4ee546b4 RJ |
423 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
424 | { | |
425 | if (is_guest_mode(&svm->vcpu)) | |
426 | return svm->nested.hsave; | |
427 | else | |
428 | return svm->vmcb; | |
429 | } | |
430 | ||
431 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
432 | { | |
433 | struct vmcb *vmcb = get_host_vmcb(svm); | |
434 | ||
435 | vmcb->control.intercept_cr |= (1U << bit); | |
436 | ||
437 | recalc_intercepts(svm); | |
438 | } | |
439 | ||
440 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
441 | { | |
442 | struct vmcb *vmcb = get_host_vmcb(svm); | |
443 | ||
444 | vmcb->control.intercept_cr &= ~(1U << bit); | |
445 | ||
446 | recalc_intercepts(svm); | |
447 | } | |
448 | ||
449 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
450 | { | |
451 | struct vmcb *vmcb = get_host_vmcb(svm); | |
452 | ||
453 | return vmcb->control.intercept_cr & (1U << bit); | |
454 | } | |
455 | ||
5315c716 | 456 | static inline void set_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
457 | { |
458 | struct vmcb *vmcb = get_host_vmcb(svm); | |
459 | ||
5315c716 PB |
460 | vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ) |
461 | | (1 << INTERCEPT_DR1_READ) | |
462 | | (1 << INTERCEPT_DR2_READ) | |
463 | | (1 << INTERCEPT_DR3_READ) | |
464 | | (1 << INTERCEPT_DR4_READ) | |
465 | | (1 << INTERCEPT_DR5_READ) | |
466 | | (1 << INTERCEPT_DR6_READ) | |
467 | | (1 << INTERCEPT_DR7_READ) | |
468 | | (1 << INTERCEPT_DR0_WRITE) | |
469 | | (1 << INTERCEPT_DR1_WRITE) | |
470 | | (1 << INTERCEPT_DR2_WRITE) | |
471 | | (1 << INTERCEPT_DR3_WRITE) | |
472 | | (1 << INTERCEPT_DR4_WRITE) | |
473 | | (1 << INTERCEPT_DR5_WRITE) | |
474 | | (1 << INTERCEPT_DR6_WRITE) | |
475 | | (1 << INTERCEPT_DR7_WRITE); | |
3aed041a JR |
476 | |
477 | recalc_intercepts(svm); | |
478 | } | |
479 | ||
5315c716 | 480 | static inline void clr_dr_intercepts(struct vcpu_svm *svm) |
3aed041a JR |
481 | { |
482 | struct vmcb *vmcb = get_host_vmcb(svm); | |
483 | ||
5315c716 | 484 | vmcb->control.intercept_dr = 0; |
3aed041a JR |
485 | |
486 | recalc_intercepts(svm); | |
487 | } | |
488 | ||
18c918c5 JR |
489 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
490 | { | |
491 | struct vmcb *vmcb = get_host_vmcb(svm); | |
492 | ||
493 | vmcb->control.intercept_exceptions |= (1U << bit); | |
494 | ||
495 | recalc_intercepts(svm); | |
496 | } | |
497 | ||
498 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
499 | { | |
500 | struct vmcb *vmcb = get_host_vmcb(svm); | |
501 | ||
502 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
503 | ||
504 | recalc_intercepts(svm); | |
505 | } | |
506 | ||
8a05a1b8 JR |
507 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
508 | { | |
509 | struct vmcb *vmcb = get_host_vmcb(svm); | |
510 | ||
511 | vmcb->control.intercept |= (1ULL << bit); | |
512 | ||
513 | recalc_intercepts(svm); | |
514 | } | |
515 | ||
516 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
517 | { | |
518 | struct vmcb *vmcb = get_host_vmcb(svm); | |
519 | ||
520 | vmcb->control.intercept &= ~(1ULL << bit); | |
521 | ||
522 | recalc_intercepts(svm); | |
523 | } | |
524 | ||
640bd6e5 JN |
525 | static inline bool vgif_enabled(struct vcpu_svm *svm) |
526 | { | |
527 | return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK); | |
528 | } | |
529 | ||
2af9194d JR |
530 | static inline void enable_gif(struct vcpu_svm *svm) |
531 | { | |
640bd6e5 JN |
532 | if (vgif_enabled(svm)) |
533 | svm->vmcb->control.int_ctl |= V_GIF_MASK; | |
534 | else | |
535 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
2af9194d JR |
536 | } |
537 | ||
538 | static inline void disable_gif(struct vcpu_svm *svm) | |
539 | { | |
640bd6e5 JN |
540 | if (vgif_enabled(svm)) |
541 | svm->vmcb->control.int_ctl &= ~V_GIF_MASK; | |
542 | else | |
543 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
2af9194d JR |
544 | } |
545 | ||
546 | static inline bool gif_set(struct vcpu_svm *svm) | |
547 | { | |
640bd6e5 JN |
548 | if (vgif_enabled(svm)) |
549 | return !!(svm->vmcb->control.int_ctl & V_GIF_MASK); | |
550 | else | |
551 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
2af9194d JR |
552 | } |
553 | ||
4866d5e3 | 554 | static unsigned long iopm_base; |
6aa8b732 AK |
555 | |
556 | struct kvm_ldttss_desc { | |
557 | u16 limit0; | |
558 | u16 base0; | |
e0231715 JR |
559 | unsigned base1:8, type:5, dpl:2, p:1; |
560 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
561 | u32 base3; |
562 | u32 zero1; | |
563 | } __attribute__((packed)); | |
564 | ||
565 | struct svm_cpu_data { | |
566 | int cpu; | |
567 | ||
5008fdf5 AK |
568 | u64 asid_generation; |
569 | u32 max_asid; | |
570 | u32 next_asid; | |
4faefff3 | 571 | u32 min_asid; |
6aa8b732 AK |
572 | struct kvm_ldttss_desc *tss_desc; |
573 | ||
574 | struct page *save_area; | |
70cd94e6 BS |
575 | |
576 | /* index = sev_asid, value = vmcb pointer */ | |
577 | struct vmcb **sev_vmcbs; | |
6aa8b732 AK |
578 | }; |
579 | ||
580 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
581 | ||
582 | struct svm_init_data { | |
583 | int cpu; | |
584 | int r; | |
585 | }; | |
586 | ||
09941fbb | 587 | static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; |
6aa8b732 | 588 | |
9d8f549d | 589 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
590 | #define MSRS_RANGE_SIZE 2048 |
591 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
592 | ||
455716fa JR |
593 | static u32 svm_msrpm_offset(u32 msr) |
594 | { | |
595 | u32 offset; | |
596 | int i; | |
597 | ||
598 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
599 | if (msr < msrpm_ranges[i] || | |
600 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
601 | continue; | |
602 | ||
603 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
604 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
605 | ||
606 | /* Now we have the u8 offset - but need the u32 offset */ | |
607 | return offset / 4; | |
608 | } | |
609 | ||
610 | /* MSR not in any range */ | |
611 | return MSR_INVALID; | |
612 | } | |
613 | ||
6aa8b732 AK |
614 | #define MAX_INST_SIZE 15 |
615 | ||
6aa8b732 AK |
616 | static inline void clgi(void) |
617 | { | |
4ecac3fd | 618 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
619 | } |
620 | ||
621 | static inline void stgi(void) | |
622 | { | |
4ecac3fd | 623 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
624 | } |
625 | ||
626 | static inline void invlpga(unsigned long addr, u32 asid) | |
627 | { | |
e0231715 | 628 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
629 | } |
630 | ||
855feb67 | 631 | static int get_npt_level(struct kvm_vcpu *vcpu) |
4b16184c JR |
632 | { |
633 | #ifdef CONFIG_X86_64 | |
2a7266a8 | 634 | return PT64_ROOT_4LEVEL; |
4b16184c JR |
635 | #else |
636 | return PT32E_ROOT_LEVEL; | |
637 | #endif | |
638 | } | |
639 | ||
6aa8b732 AK |
640 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
641 | { | |
6dc696d4 | 642 | vcpu->arch.efer = efer; |
709ddebf | 643 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 644 | efer &= ~EFER_LME; |
6aa8b732 | 645 | |
9962d032 | 646 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 647 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
648 | } |
649 | ||
6aa8b732 AK |
650 | static int is_external_interrupt(u32 info) |
651 | { | |
652 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
653 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
654 | } | |
655 | ||
37ccdcbe | 656 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
657 | { |
658 | struct vcpu_svm *svm = to_svm(vcpu); | |
659 | u32 ret = 0; | |
660 | ||
661 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
37ccdcbe PB |
662 | ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
663 | return ret; | |
2809f5d2 GC |
664 | } |
665 | ||
666 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
667 | { | |
668 | struct vcpu_svm *svm = to_svm(vcpu); | |
669 | ||
670 | if (mask == 0) | |
671 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
672 | else | |
673 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
674 | ||
675 | } | |
676 | ||
6aa8b732 AK |
677 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
678 | { | |
a2fa3e9f GH |
679 | struct vcpu_svm *svm = to_svm(vcpu); |
680 | ||
f104765b | 681 | if (svm->vmcb->control.next_rip != 0) { |
d2922422 | 682 | WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS)); |
6bc31bdc | 683 | svm->next_rip = svm->vmcb->control.next_rip; |
f104765b | 684 | } |
6bc31bdc | 685 | |
a2fa3e9f | 686 | if (!svm->next_rip) { |
51d8b661 | 687 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
688 | EMULATE_DONE) |
689 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
690 | return; |
691 | } | |
5fdbf976 MT |
692 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
693 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
694 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 695 | |
5fdbf976 | 696 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 697 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
698 | } |
699 | ||
cfcd20e5 | 700 | static void svm_queue_exception(struct kvm_vcpu *vcpu) |
116a4752 JK |
701 | { |
702 | struct vcpu_svm *svm = to_svm(vcpu); | |
cfcd20e5 WL |
703 | unsigned nr = vcpu->arch.exception.nr; |
704 | bool has_error_code = vcpu->arch.exception.has_error_code; | |
664f8e26 | 705 | bool reinject = vcpu->arch.exception.injected; |
cfcd20e5 | 706 | u32 error_code = vcpu->arch.exception.error_code; |
116a4752 | 707 | |
e0231715 JR |
708 | /* |
709 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
710 | * handle the exception | |
711 | */ | |
ce7ddec4 JR |
712 | if (!reinject && |
713 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
714 | return; |
715 | ||
2a6b20b8 | 716 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
717 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
718 | ||
719 | /* | |
720 | * For guest debugging where we have to reinject #BP if some | |
721 | * INT3 is guest-owned: | |
722 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
723 | * raises a fault that is not intercepted. Still better than | |
724 | * failing in all cases. | |
725 | */ | |
726 | skip_emulated_instruction(&svm->vcpu); | |
727 | rip = kvm_rip_read(&svm->vcpu); | |
728 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
729 | svm->int3_injected = rip - old_rip; | |
730 | } | |
731 | ||
116a4752 JK |
732 | svm->vmcb->control.event_inj = nr |
733 | | SVM_EVTINJ_VALID | |
734 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
735 | | SVM_EVTINJ_TYPE_EXEPT; | |
736 | svm->vmcb->control.event_inj_err = error_code; | |
737 | } | |
738 | ||
67ec6607 JR |
739 | static void svm_init_erratum_383(void) |
740 | { | |
741 | u32 low, high; | |
742 | int err; | |
743 | u64 val; | |
744 | ||
e6ee94d5 | 745 | if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH)) |
67ec6607 JR |
746 | return; |
747 | ||
748 | /* Use _safe variants to not break nested virtualization */ | |
749 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
750 | if (err) | |
751 | return; | |
752 | ||
753 | val |= (1ULL << 47); | |
754 | ||
755 | low = lower_32_bits(val); | |
756 | high = upper_32_bits(val); | |
757 | ||
758 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
759 | ||
760 | erratum_383_found = true; | |
761 | } | |
762 | ||
2b036c6b BO |
763 | static void svm_init_osvw(struct kvm_vcpu *vcpu) |
764 | { | |
765 | /* | |
766 | * Guests should see errata 400 and 415 as fixed (assuming that | |
767 | * HLT and IO instructions are intercepted). | |
768 | */ | |
769 | vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; | |
770 | vcpu->arch.osvw.status = osvw_status & ~(6ULL); | |
771 | ||
772 | /* | |
773 | * By increasing VCPU's osvw.length to 3 we are telling the guest that | |
774 | * all osvw.status bits inside that length, including bit 0 (which is | |
775 | * reserved for erratum 298), are valid. However, if host processor's | |
776 | * osvw_len is 0 then osvw_status[0] carries no information. We need to | |
777 | * be conservative here and therefore we tell the guest that erratum 298 | |
778 | * is present (because we really don't know). | |
779 | */ | |
780 | if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) | |
781 | vcpu->arch.osvw.status |= 1; | |
782 | } | |
783 | ||
6aa8b732 AK |
784 | static int has_svm(void) |
785 | { | |
63d1142f | 786 | const char *msg; |
6aa8b732 | 787 | |
63d1142f | 788 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 789 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
790 | return 0; |
791 | } | |
792 | ||
6aa8b732 AK |
793 | return 1; |
794 | } | |
795 | ||
13a34e06 | 796 | static void svm_hardware_disable(void) |
6aa8b732 | 797 | { |
fbc0db76 JR |
798 | /* Make sure we clean up behind us */ |
799 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
800 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
801 | ||
2c8dceeb | 802 | cpu_svm_disable(); |
1018faa6 JR |
803 | |
804 | amd_pmu_disable_virt(); | |
6aa8b732 AK |
805 | } |
806 | ||
13a34e06 | 807 | static int svm_hardware_enable(void) |
6aa8b732 AK |
808 | { |
809 | ||
0fe1e009 | 810 | struct svm_cpu_data *sd; |
6aa8b732 | 811 | uint64_t efer; |
6aa8b732 AK |
812 | struct desc_struct *gdt; |
813 | int me = raw_smp_processor_id(); | |
814 | ||
10474ae8 AG |
815 | rdmsrl(MSR_EFER, efer); |
816 | if (efer & EFER_SVME) | |
817 | return -EBUSY; | |
818 | ||
6aa8b732 | 819 | if (!has_svm()) { |
1f5b77f5 | 820 | pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me); |
10474ae8 | 821 | return -EINVAL; |
6aa8b732 | 822 | } |
0fe1e009 | 823 | sd = per_cpu(svm_data, me); |
0fe1e009 | 824 | if (!sd) { |
1f5b77f5 | 825 | pr_err("%s: svm_data is NULL on %d\n", __func__, me); |
10474ae8 | 826 | return -EINVAL; |
6aa8b732 AK |
827 | } |
828 | ||
0fe1e009 TH |
829 | sd->asid_generation = 1; |
830 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
831 | sd->next_asid = sd->max_asid + 1; | |
ed3cd233 | 832 | sd->min_asid = max_sev_asid + 1; |
6aa8b732 | 833 | |
45fc8757 | 834 | gdt = get_current_gdt_rw(); |
0fe1e009 | 835 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 836 | |
9962d032 | 837 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 838 | |
d0316554 | 839 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 840 | |
fbc0db76 JR |
841 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
842 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
89cbc767 | 843 | __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT); |
fbc0db76 JR |
844 | } |
845 | ||
2b036c6b BO |
846 | |
847 | /* | |
848 | * Get OSVW bits. | |
849 | * | |
850 | * Note that it is possible to have a system with mixed processor | |
851 | * revisions and therefore different OSVW bits. If bits are not the same | |
852 | * on different processors then choose the worst case (i.e. if erratum | |
853 | * is present on one processor and not on another then assume that the | |
854 | * erratum is present everywhere). | |
855 | */ | |
856 | if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { | |
857 | uint64_t len, status = 0; | |
858 | int err; | |
859 | ||
860 | len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); | |
861 | if (!err) | |
862 | status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, | |
863 | &err); | |
864 | ||
865 | if (err) | |
866 | osvw_status = osvw_len = 0; | |
867 | else { | |
868 | if (len < osvw_len) | |
869 | osvw_len = len; | |
870 | osvw_status |= status; | |
871 | osvw_status &= (1ULL << osvw_len) - 1; | |
872 | } | |
873 | } else | |
874 | osvw_status = osvw_len = 0; | |
875 | ||
67ec6607 JR |
876 | svm_init_erratum_383(); |
877 | ||
1018faa6 JR |
878 | amd_pmu_enable_virt(); |
879 | ||
10474ae8 | 880 | return 0; |
6aa8b732 AK |
881 | } |
882 | ||
0da1db75 JR |
883 | static void svm_cpu_uninit(int cpu) |
884 | { | |
0fe1e009 | 885 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 886 | |
0fe1e009 | 887 | if (!sd) |
0da1db75 JR |
888 | return; |
889 | ||
890 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
70cd94e6 | 891 | kfree(sd->sev_vmcbs); |
0fe1e009 TH |
892 | __free_page(sd->save_area); |
893 | kfree(sd); | |
0da1db75 JR |
894 | } |
895 | ||
6aa8b732 AK |
896 | static int svm_cpu_init(int cpu) |
897 | { | |
0fe1e009 | 898 | struct svm_cpu_data *sd; |
6aa8b732 AK |
899 | int r; |
900 | ||
0fe1e009 TH |
901 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
902 | if (!sd) | |
6aa8b732 | 903 | return -ENOMEM; |
0fe1e009 | 904 | sd->cpu = cpu; |
6aa8b732 | 905 | r = -ENOMEM; |
70cd94e6 | 906 | sd->save_area = alloc_page(GFP_KERNEL); |
0fe1e009 | 907 | if (!sd->save_area) |
6aa8b732 AK |
908 | goto err_1; |
909 | ||
70cd94e6 BS |
910 | if (svm_sev_enabled()) { |
911 | r = -ENOMEM; | |
912 | sd->sev_vmcbs = kmalloc((max_sev_asid + 1) * sizeof(void *), GFP_KERNEL); | |
913 | if (!sd->sev_vmcbs) | |
914 | goto err_1; | |
915 | } | |
916 | ||
0fe1e009 | 917 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
918 | |
919 | return 0; | |
920 | ||
921 | err_1: | |
0fe1e009 | 922 | kfree(sd); |
6aa8b732 AK |
923 | return r; |
924 | ||
925 | } | |
926 | ||
ac72a9b7 JR |
927 | static bool valid_msr_intercept(u32 index) |
928 | { | |
929 | int i; | |
930 | ||
931 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
932 | if (direct_access_msrs[i].index == index) | |
933 | return true; | |
934 | ||
935 | return false; | |
936 | } | |
937 | ||
bfc733a7 RR |
938 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
939 | int read, int write) | |
6aa8b732 | 940 | { |
455716fa JR |
941 | u8 bit_read, bit_write; |
942 | unsigned long tmp; | |
943 | u32 offset; | |
6aa8b732 | 944 | |
ac72a9b7 JR |
945 | /* |
946 | * If this warning triggers extend the direct_access_msrs list at the | |
947 | * beginning of the file | |
948 | */ | |
949 | WARN_ON(!valid_msr_intercept(msr)); | |
950 | ||
455716fa JR |
951 | offset = svm_msrpm_offset(msr); |
952 | bit_read = 2 * (msr & 0x0f); | |
953 | bit_write = 2 * (msr & 0x0f) + 1; | |
954 | tmp = msrpm[offset]; | |
955 | ||
956 | BUG_ON(offset == MSR_INVALID); | |
957 | ||
958 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
959 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
960 | ||
961 | msrpm[offset] = tmp; | |
6aa8b732 AK |
962 | } |
963 | ||
f65c229c | 964 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
965 | { |
966 | int i; | |
967 | ||
f65c229c JR |
968 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
969 | ||
ac72a9b7 JR |
970 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
971 | if (!direct_access_msrs[i].always) | |
972 | continue; | |
973 | ||
974 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
975 | } | |
f65c229c JR |
976 | } |
977 | ||
323c3d80 JR |
978 | static void add_msr_offset(u32 offset) |
979 | { | |
980 | int i; | |
981 | ||
982 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
983 | ||
984 | /* Offset already in list? */ | |
985 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 986 | return; |
323c3d80 JR |
987 | |
988 | /* Slot used by another offset? */ | |
989 | if (msrpm_offsets[i] != MSR_INVALID) | |
990 | continue; | |
991 | ||
992 | /* Add offset to list */ | |
993 | msrpm_offsets[i] = offset; | |
994 | ||
995 | return; | |
6aa8b732 | 996 | } |
323c3d80 JR |
997 | |
998 | /* | |
999 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
1000 | * increase MSRPM_OFFSETS in this case. | |
1001 | */ | |
bfc733a7 | 1002 | BUG(); |
6aa8b732 AK |
1003 | } |
1004 | ||
323c3d80 | 1005 | static void init_msrpm_offsets(void) |
f65c229c | 1006 | { |
323c3d80 | 1007 | int i; |
f65c229c | 1008 | |
323c3d80 JR |
1009 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
1010 | ||
1011 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
1012 | u32 offset; | |
1013 | ||
1014 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
1015 | BUG_ON(offset == MSR_INVALID); | |
1016 | ||
1017 | add_msr_offset(offset); | |
1018 | } | |
f65c229c JR |
1019 | } |
1020 | ||
24e09cbf JR |
1021 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
1022 | { | |
1023 | u32 *msrpm = svm->msrpm; | |
1024 | ||
0dc92119 | 1025 | svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK; |
24e09cbf JR |
1026 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); |
1027 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
1028 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
1029 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
1030 | } | |
1031 | ||
1032 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
1033 | { | |
1034 | u32 *msrpm = svm->msrpm; | |
1035 | ||
0dc92119 | 1036 | svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK; |
24e09cbf JR |
1037 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); |
1038 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
1039 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
1040 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
1041 | } | |
1042 | ||
4aebd0e9 LP |
1043 | static void disable_nmi_singlestep(struct vcpu_svm *svm) |
1044 | { | |
1045 | svm->nmi_singlestep = false; | |
640bd6e5 | 1046 | |
ab2f4d73 LP |
1047 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) { |
1048 | /* Clear our flags if they were not set by the guest */ | |
1049 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) | |
1050 | svm->vmcb->save.rflags &= ~X86_EFLAGS_TF; | |
1051 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) | |
1052 | svm->vmcb->save.rflags &= ~X86_EFLAGS_RF; | |
1053 | } | |
4aebd0e9 LP |
1054 | } |
1055 | ||
5881f737 SS |
1056 | /* Note: |
1057 | * This hash table is used to map VM_ID to a struct kvm_arch, | |
1058 | * when handling AMD IOMMU GALOG notification to schedule in | |
1059 | * a particular vCPU. | |
1060 | */ | |
1061 | #define SVM_VM_DATA_HASH_BITS 8 | |
681bcea8 | 1062 | static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS); |
3f0d4db7 DV |
1063 | static u32 next_vm_id = 0; |
1064 | static bool next_vm_id_wrapped = 0; | |
681bcea8 | 1065 | static DEFINE_SPINLOCK(svm_vm_data_hash_lock); |
5881f737 SS |
1066 | |
1067 | /* Note: | |
1068 | * This function is called from IOMMU driver to notify | |
1069 | * SVM to schedule in a particular vCPU of a particular VM. | |
1070 | */ | |
1071 | static int avic_ga_log_notifier(u32 ga_tag) | |
1072 | { | |
1073 | unsigned long flags; | |
1074 | struct kvm_arch *ka = NULL; | |
1075 | struct kvm_vcpu *vcpu = NULL; | |
1076 | u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag); | |
1077 | u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag); | |
1078 | ||
1079 | pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id); | |
1080 | ||
1081 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); | |
1082 | hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) { | |
1083 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
1084 | struct kvm_arch *vm_data = &kvm->arch; | |
1085 | ||
1086 | if (vm_data->avic_vm_id != vm_id) | |
1087 | continue; | |
1088 | vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id); | |
1089 | break; | |
1090 | } | |
1091 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
1092 | ||
5881f737 SS |
1093 | /* Note: |
1094 | * At this point, the IOMMU should have already set the pending | |
1095 | * bit in the vAPIC backing page. So, we just need to schedule | |
1096 | * in the vcpu. | |
1097 | */ | |
1cf53587 | 1098 | if (vcpu) |
5881f737 SS |
1099 | kvm_vcpu_wake_up(vcpu); |
1100 | ||
1101 | return 0; | |
1102 | } | |
1103 | ||
e9df0942 BS |
1104 | static __init int sev_hardware_setup(void) |
1105 | { | |
1106 | struct sev_user_data_status *status; | |
1107 | int rc; | |
1108 | ||
1109 | /* Maximum number of encrypted guests supported simultaneously */ | |
1110 | max_sev_asid = cpuid_ecx(0x8000001F); | |
1111 | ||
1112 | if (!max_sev_asid) | |
1113 | return 1; | |
1114 | ||
1654efcb BS |
1115 | /* Minimum ASID value that should be used for SEV guest */ |
1116 | min_sev_asid = cpuid_edx(0x8000001F); | |
1117 | ||
1118 | /* Initialize SEV ASID bitmap */ | |
1119 | sev_asid_bitmap = kcalloc(BITS_TO_LONGS(max_sev_asid), | |
1120 | sizeof(unsigned long), GFP_KERNEL); | |
1121 | if (!sev_asid_bitmap) | |
1122 | return 1; | |
1123 | ||
e9df0942 BS |
1124 | status = kmalloc(sizeof(*status), GFP_KERNEL); |
1125 | if (!status) | |
1126 | return 1; | |
1127 | ||
1128 | /* | |
1129 | * Check SEV platform status. | |
1130 | * | |
1131 | * PLATFORM_STATUS can be called in any state, if we failed to query | |
1132 | * the PLATFORM status then either PSP firmware does not support SEV | |
1133 | * feature or SEV firmware is dead. | |
1134 | */ | |
1135 | rc = sev_platform_status(status, NULL); | |
1136 | if (rc) | |
1137 | goto err; | |
1138 | ||
1139 | pr_info("SEV supported\n"); | |
1140 | ||
1141 | err: | |
1142 | kfree(status); | |
1143 | return rc; | |
1144 | } | |
1145 | ||
6aa8b732 AK |
1146 | static __init int svm_hardware_setup(void) |
1147 | { | |
1148 | int cpu; | |
1149 | struct page *iopm_pages; | |
f65c229c | 1150 | void *iopm_va; |
6aa8b732 AK |
1151 | int r; |
1152 | ||
6aa8b732 AK |
1153 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
1154 | ||
1155 | if (!iopm_pages) | |
1156 | return -ENOMEM; | |
c8681339 AL |
1157 | |
1158 | iopm_va = page_address(iopm_pages); | |
1159 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
1160 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
1161 | ||
323c3d80 JR |
1162 | init_msrpm_offsets(); |
1163 | ||
50a37eb4 JR |
1164 | if (boot_cpu_has(X86_FEATURE_NX)) |
1165 | kvm_enable_efer_bits(EFER_NX); | |
1166 | ||
1b2fd70c AG |
1167 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
1168 | kvm_enable_efer_bits(EFER_FFXSR); | |
1169 | ||
92a1f12d | 1170 | if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
92a1f12d | 1171 | kvm_has_tsc_control = true; |
bc9b961b HZ |
1172 | kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX; |
1173 | kvm_tsc_scaling_ratio_frac_bits = 32; | |
92a1f12d JR |
1174 | } |
1175 | ||
236de055 AG |
1176 | if (nested) { |
1177 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 1178 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
1179 | } |
1180 | ||
e9df0942 BS |
1181 | if (sev) { |
1182 | if (boot_cpu_has(X86_FEATURE_SEV) && | |
1183 | IS_ENABLED(CONFIG_KVM_AMD_SEV)) { | |
1184 | r = sev_hardware_setup(); | |
1185 | if (r) | |
1186 | sev = false; | |
1187 | } else { | |
1188 | sev = false; | |
1189 | } | |
1190 | } | |
1191 | ||
3230bb47 | 1192 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
1193 | r = svm_cpu_init(cpu); |
1194 | if (r) | |
f65c229c | 1195 | goto err; |
6aa8b732 | 1196 | } |
33bd6a0b | 1197 | |
2a6b20b8 | 1198 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
1199 | npt_enabled = false; |
1200 | ||
6c7dac72 JR |
1201 | if (npt_enabled && !npt) { |
1202 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
1203 | npt_enabled = false; | |
1204 | } | |
1205 | ||
18552672 | 1206 | if (npt_enabled) { |
e3da3acd | 1207 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 1208 | kvm_enable_tdp(); |
5f4cb662 JR |
1209 | } else |
1210 | kvm_disable_tdp(); | |
e3da3acd | 1211 | |
5b8abf1f SS |
1212 | if (avic) { |
1213 | if (!npt_enabled || | |
1214 | !boot_cpu_has(X86_FEATURE_AVIC) || | |
5881f737 | 1215 | !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) { |
5b8abf1f | 1216 | avic = false; |
5881f737 | 1217 | } else { |
5b8abf1f | 1218 | pr_info("AVIC enabled\n"); |
5881f737 | 1219 | |
5881f737 SS |
1220 | amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); |
1221 | } | |
5b8abf1f | 1222 | } |
44a95dae | 1223 | |
89c8a498 JN |
1224 | if (vls) { |
1225 | if (!npt_enabled || | |
5442c269 | 1226 | !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) || |
89c8a498 JN |
1227 | !IS_ENABLED(CONFIG_X86_64)) { |
1228 | vls = false; | |
1229 | } else { | |
1230 | pr_info("Virtual VMLOAD VMSAVE supported\n"); | |
1231 | } | |
1232 | } | |
1233 | ||
640bd6e5 JN |
1234 | if (vgif) { |
1235 | if (!boot_cpu_has(X86_FEATURE_VGIF)) | |
1236 | vgif = false; | |
1237 | else | |
1238 | pr_info("Virtual GIF supported\n"); | |
1239 | } | |
1240 | ||
6aa8b732 AK |
1241 | return 0; |
1242 | ||
f65c229c | 1243 | err: |
6aa8b732 AK |
1244 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
1245 | iopm_base = 0; | |
1246 | return r; | |
1247 | } | |
1248 | ||
1249 | static __exit void svm_hardware_unsetup(void) | |
1250 | { | |
0da1db75 JR |
1251 | int cpu; |
1252 | ||
1654efcb BS |
1253 | if (svm_sev_enabled()) |
1254 | kfree(sev_asid_bitmap); | |
1255 | ||
3230bb47 | 1256 | for_each_possible_cpu(cpu) |
0da1db75 JR |
1257 | svm_cpu_uninit(cpu); |
1258 | ||
6aa8b732 | 1259 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 1260 | iopm_base = 0; |
6aa8b732 AK |
1261 | } |
1262 | ||
1263 | static void init_seg(struct vmcb_seg *seg) | |
1264 | { | |
1265 | seg->selector = 0; | |
1266 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 1267 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
1268 | seg->limit = 0xffff; |
1269 | seg->base = 0; | |
1270 | } | |
1271 | ||
1272 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
1273 | { | |
1274 | seg->selector = 0; | |
1275 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
1276 | seg->limit = 0xffff; | |
1277 | seg->base = 0; | |
1278 | } | |
1279 | ||
f4e1b3c8 ZA |
1280 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1281 | { | |
1282 | struct vcpu_svm *svm = to_svm(vcpu); | |
1283 | u64 g_tsc_offset = 0; | |
1284 | ||
2030753d | 1285 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
1286 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
1287 | svm->nested.hsave->control.tsc_offset; | |
1288 | svm->nested.hsave->control.tsc_offset = offset; | |
489223ed YY |
1289 | } else |
1290 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, | |
1291 | svm->vmcb->control.tsc_offset, | |
1292 | offset); | |
f4e1b3c8 ZA |
1293 | |
1294 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
1295 | |
1296 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
1297 | } |
1298 | ||
44a95dae SS |
1299 | static void avic_init_vmcb(struct vcpu_svm *svm) |
1300 | { | |
1301 | struct vmcb *vmcb = svm->vmcb; | |
1302 | struct kvm_arch *vm_data = &svm->vcpu.kvm->arch; | |
d0ec49d4 TL |
1303 | phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page)); |
1304 | phys_addr_t lpa = __sme_set(page_to_phys(vm_data->avic_logical_id_table_page)); | |
1305 | phys_addr_t ppa = __sme_set(page_to_phys(vm_data->avic_physical_id_table_page)); | |
44a95dae SS |
1306 | |
1307 | vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK; | |
1308 | vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK; | |
1309 | vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK; | |
1310 | vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT; | |
1311 | vmcb->control.int_ctl |= AVIC_ENABLE_MASK; | |
44a95dae SS |
1312 | } |
1313 | ||
5690891b | 1314 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 1315 | { |
e6101a96 JR |
1316 | struct vmcb_control_area *control = &svm->vmcb->control; |
1317 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 1318 | |
4ee546b4 | 1319 | svm->vcpu.arch.hflags = 0; |
bff78274 | 1320 | |
4ee546b4 RJ |
1321 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1322 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
1323 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
1324 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
1325 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
1326 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
3bbf3565 SS |
1327 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
1328 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 1329 | |
5315c716 | 1330 | set_dr_intercepts(svm); |
6aa8b732 | 1331 | |
18c918c5 JR |
1332 | set_exception_intercept(svm, PF_VECTOR); |
1333 | set_exception_intercept(svm, UD_VECTOR); | |
1334 | set_exception_intercept(svm, MC_VECTOR); | |
54a20552 | 1335 | set_exception_intercept(svm, AC_VECTOR); |
cbdb967a | 1336 | set_exception_intercept(svm, DB_VECTOR); |
6aa8b732 | 1337 | |
8a05a1b8 JR |
1338 | set_intercept(svm, INTERCEPT_INTR); |
1339 | set_intercept(svm, INTERCEPT_NMI); | |
1340 | set_intercept(svm, INTERCEPT_SMI); | |
1341 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
332b56e4 | 1342 | set_intercept(svm, INTERCEPT_RDPMC); |
8a05a1b8 JR |
1343 | set_intercept(svm, INTERCEPT_CPUID); |
1344 | set_intercept(svm, INTERCEPT_INVD); | |
1345 | set_intercept(svm, INTERCEPT_HLT); | |
1346 | set_intercept(svm, INTERCEPT_INVLPG); | |
1347 | set_intercept(svm, INTERCEPT_INVLPGA); | |
1348 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
1349 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
1350 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
1351 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
1352 | set_intercept(svm, INTERCEPT_VMRUN); | |
1353 | set_intercept(svm, INTERCEPT_VMMCALL); | |
1354 | set_intercept(svm, INTERCEPT_VMLOAD); | |
1355 | set_intercept(svm, INTERCEPT_VMSAVE); | |
1356 | set_intercept(svm, INTERCEPT_STGI); | |
1357 | set_intercept(svm, INTERCEPT_CLGI); | |
1358 | set_intercept(svm, INTERCEPT_SKINIT); | |
1359 | set_intercept(svm, INTERCEPT_WBINVD); | |
81dd35d4 | 1360 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 | 1361 | |
668fffa3 MT |
1362 | if (!kvm_mwait_in_guest()) { |
1363 | set_intercept(svm, INTERCEPT_MONITOR); | |
1364 | set_intercept(svm, INTERCEPT_MWAIT); | |
1365 | } | |
1366 | ||
d0ec49d4 TL |
1367 | control->iopm_base_pa = __sme_set(iopm_base); |
1368 | control->msrpm_base_pa = __sme_set(__pa(svm->msrpm)); | |
6aa8b732 AK |
1369 | control->int_ctl = V_INTR_MASKING_MASK; |
1370 | ||
1371 | init_seg(&save->es); | |
1372 | init_seg(&save->ss); | |
1373 | init_seg(&save->ds); | |
1374 | init_seg(&save->fs); | |
1375 | init_seg(&save->gs); | |
1376 | ||
1377 | save->cs.selector = 0xf000; | |
04b66839 | 1378 | save->cs.base = 0xffff0000; |
6aa8b732 AK |
1379 | /* Executable/Readable Code Segment */ |
1380 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
1381 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
1382 | save->cs.limit = 0xffff; | |
6aa8b732 AK |
1383 | |
1384 | save->gdtr.limit = 0xffff; | |
1385 | save->idtr.limit = 0xffff; | |
1386 | ||
1387 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1388 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1389 | ||
5690891b | 1390 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1391 | save->dr6 = 0xffff0ff0; |
f6e78475 | 1392 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1393 | save->rip = 0x0000fff0; |
5fdbf976 | 1394 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1395 | |
e0231715 | 1396 | /* |
18fa000a | 1397 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
d28bc9dd | 1398 | * It also updates the guest-visible cr0 value. |
6aa8b732 | 1399 | */ |
79a8059d | 1400 | svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); |
ebae871a | 1401 | kvm_mmu_reset_context(&svm->vcpu); |
18fa000a | 1402 | |
66aee91a | 1403 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1404 | /* rdx = ?? */ |
709ddebf JR |
1405 | |
1406 | if (npt_enabled) { | |
1407 | /* Setup VMCB for Nested Paging */ | |
cea3a19b | 1408 | control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE; |
8a05a1b8 | 1409 | clr_intercept(svm, INTERCEPT_INVLPG); |
18c918c5 | 1410 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1411 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1412 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
74545705 | 1413 | save->g_pat = svm->vcpu.arch.pat; |
709ddebf JR |
1414 | save->cr3 = 0; |
1415 | save->cr4 = 0; | |
1416 | } | |
f40f6a45 | 1417 | svm->asid_generation = 0; |
1371d904 | 1418 | |
e6aa9abd | 1419 | svm->nested.vmcb = 0; |
2af9194d JR |
1420 | svm->vcpu.arch.hflags = 0; |
1421 | ||
2a6b20b8 | 1422 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1423 | control->pause_filter_count = 3000; |
8a05a1b8 | 1424 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1425 | } |
1426 | ||
67034bb9 | 1427 | if (kvm_vcpu_apicv_active(&svm->vcpu)) |
44a95dae SS |
1428 | avic_init_vmcb(svm); |
1429 | ||
89c8a498 JN |
1430 | /* |
1431 | * If hardware supports Virtual VMLOAD VMSAVE then enable it | |
1432 | * in VMCB and clear intercepts to avoid #VMEXIT. | |
1433 | */ | |
1434 | if (vls) { | |
1435 | clr_intercept(svm, INTERCEPT_VMLOAD); | |
1436 | clr_intercept(svm, INTERCEPT_VMSAVE); | |
1437 | svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK; | |
1438 | } | |
1439 | ||
640bd6e5 JN |
1440 | if (vgif) { |
1441 | clr_intercept(svm, INTERCEPT_STGI); | |
1442 | clr_intercept(svm, INTERCEPT_CLGI); | |
1443 | svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK; | |
1444 | } | |
1445 | ||
1654efcb BS |
1446 | if (sev_guest(svm->vcpu.kvm)) |
1447 | svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE; | |
1448 | ||
8d28fec4 RJ |
1449 | mark_all_dirty(svm->vmcb); |
1450 | ||
2af9194d | 1451 | enable_gif(svm); |
44a95dae SS |
1452 | |
1453 | } | |
1454 | ||
d3e7dec0 DC |
1455 | static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, |
1456 | unsigned int index) | |
44a95dae SS |
1457 | { |
1458 | u64 *avic_physical_id_table; | |
1459 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
1460 | ||
1461 | if (index >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1462 | return NULL; | |
1463 | ||
1464 | avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page); | |
1465 | ||
1466 | return &avic_physical_id_table[index]; | |
1467 | } | |
1468 | ||
1469 | /** | |
1470 | * Note: | |
1471 | * AVIC hardware walks the nested page table to check permissions, | |
1472 | * but does not use the SPA address specified in the leaf page | |
1473 | * table entry since it uses address in the AVIC_BACKING_PAGE pointer | |
1474 | * field of the VMCB. Therefore, we set up the | |
1475 | * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here. | |
1476 | */ | |
1477 | static int avic_init_access_page(struct kvm_vcpu *vcpu) | |
1478 | { | |
1479 | struct kvm *kvm = vcpu->kvm; | |
1480 | int ret; | |
1481 | ||
1482 | if (kvm->arch.apic_access_page_done) | |
1483 | return 0; | |
1484 | ||
1485 | ret = x86_set_memory_region(kvm, | |
1486 | APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
1487 | APIC_DEFAULT_PHYS_BASE, | |
1488 | PAGE_SIZE); | |
1489 | if (ret) | |
1490 | return ret; | |
1491 | ||
1492 | kvm->arch.apic_access_page_done = true; | |
1493 | return 0; | |
1494 | } | |
1495 | ||
1496 | static int avic_init_backing_page(struct kvm_vcpu *vcpu) | |
1497 | { | |
1498 | int ret; | |
1499 | u64 *entry, new_entry; | |
1500 | int id = vcpu->vcpu_id; | |
1501 | struct vcpu_svm *svm = to_svm(vcpu); | |
1502 | ||
1503 | ret = avic_init_access_page(vcpu); | |
1504 | if (ret) | |
1505 | return ret; | |
1506 | ||
1507 | if (id >= AVIC_MAX_PHYSICAL_ID_COUNT) | |
1508 | return -EINVAL; | |
1509 | ||
1510 | if (!svm->vcpu.arch.apic->regs) | |
1511 | return -EINVAL; | |
1512 | ||
1513 | svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs); | |
1514 | ||
1515 | /* Setting AVIC backing page address in the phy APIC ID table */ | |
1516 | entry = avic_get_physical_id_entry(vcpu, id); | |
1517 | if (!entry) | |
1518 | return -EINVAL; | |
1519 | ||
1520 | new_entry = READ_ONCE(*entry); | |
d0ec49d4 TL |
1521 | new_entry = __sme_set((page_to_phys(svm->avic_backing_page) & |
1522 | AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) | | |
1523 | AVIC_PHYSICAL_ID_ENTRY_VALID_MASK); | |
44a95dae SS |
1524 | WRITE_ONCE(*entry, new_entry); |
1525 | ||
1526 | svm->avic_physical_id_cache = entry; | |
1527 | ||
1528 | return 0; | |
1529 | } | |
1530 | ||
1654efcb BS |
1531 | static void __sev_asid_free(int asid) |
1532 | { | |
70cd94e6 BS |
1533 | struct svm_cpu_data *sd; |
1534 | int cpu, pos; | |
1654efcb BS |
1535 | |
1536 | pos = asid - 1; | |
1537 | clear_bit(pos, sev_asid_bitmap); | |
70cd94e6 BS |
1538 | |
1539 | for_each_possible_cpu(cpu) { | |
1540 | sd = per_cpu(svm_data, cpu); | |
1541 | sd->sev_vmcbs[pos] = NULL; | |
1542 | } | |
1654efcb BS |
1543 | } |
1544 | ||
1545 | static void sev_asid_free(struct kvm *kvm) | |
1546 | { | |
1547 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
1548 | ||
1549 | __sev_asid_free(sev->asid); | |
1550 | } | |
1551 | ||
59414c98 BS |
1552 | static void sev_unbind_asid(struct kvm *kvm, unsigned int handle) |
1553 | { | |
1554 | struct sev_data_decommission *decommission; | |
1555 | struct sev_data_deactivate *data; | |
1556 | ||
1557 | if (!handle) | |
1558 | return; | |
1559 | ||
1560 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
1561 | if (!data) | |
1562 | return; | |
1563 | ||
1564 | /* deactivate handle */ | |
1565 | data->handle = handle; | |
1566 | sev_guest_deactivate(data, NULL); | |
1567 | ||
1568 | wbinvd_on_all_cpus(); | |
1569 | sev_guest_df_flush(NULL); | |
1570 | kfree(data); | |
1571 | ||
1572 | decommission = kzalloc(sizeof(*decommission), GFP_KERNEL); | |
1573 | if (!decommission) | |
1574 | return; | |
1575 | ||
1576 | /* decommission handle */ | |
1577 | decommission->handle = handle; | |
1578 | sev_guest_decommission(decommission, NULL); | |
1579 | ||
1580 | kfree(decommission); | |
1581 | } | |
1582 | ||
89c50580 BS |
1583 | static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr, |
1584 | unsigned long ulen, unsigned long *n, | |
1585 | int write) | |
1586 | { | |
1587 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
1588 | unsigned long npages, npinned, size; | |
1589 | unsigned long locked, lock_limit; | |
1590 | struct page **pages; | |
1591 | int first, last; | |
1592 | ||
1593 | /* Calculate number of pages. */ | |
1594 | first = (uaddr & PAGE_MASK) >> PAGE_SHIFT; | |
1595 | last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT; | |
1596 | npages = (last - first + 1); | |
1597 | ||
1598 | locked = sev->pages_locked + npages; | |
1599 | lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT; | |
1600 | if (locked > lock_limit && !capable(CAP_IPC_LOCK)) { | |
1601 | pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit); | |
1602 | return NULL; | |
1603 | } | |
1604 | ||
1605 | /* Avoid using vmalloc for smaller buffers. */ | |
1606 | size = npages * sizeof(struct page *); | |
1607 | if (size > PAGE_SIZE) | |
1608 | pages = vmalloc(size); | |
1609 | else | |
1610 | pages = kmalloc(size, GFP_KERNEL); | |
1611 | ||
1612 | if (!pages) | |
1613 | return NULL; | |
1614 | ||
1615 | /* Pin the user virtual address. */ | |
1616 | npinned = get_user_pages_fast(uaddr, npages, write ? FOLL_WRITE : 0, pages); | |
1617 | if (npinned != npages) { | |
1618 | pr_err("SEV: Failure locking %lu pages.\n", npages); | |
1619 | goto err; | |
1620 | } | |
1621 | ||
1622 | *n = npages; | |
1623 | sev->pages_locked = locked; | |
1624 | ||
1625 | return pages; | |
1626 | ||
1627 | err: | |
1628 | if (npinned > 0) | |
1629 | release_pages(pages, npinned); | |
1630 | ||
1631 | kvfree(pages); | |
1632 | return NULL; | |
1633 | } | |
1634 | ||
1635 | static void sev_unpin_memory(struct kvm *kvm, struct page **pages, | |
1636 | unsigned long npages) | |
1637 | { | |
1638 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
1639 | ||
1640 | release_pages(pages, npages); | |
1641 | kvfree(pages); | |
1642 | sev->pages_locked -= npages; | |
1643 | } | |
1644 | ||
1645 | static void sev_clflush_pages(struct page *pages[], unsigned long npages) | |
1646 | { | |
1647 | uint8_t *page_virtual; | |
1648 | unsigned long i; | |
1649 | ||
1650 | if (npages == 0 || pages == NULL) | |
1651 | return; | |
1652 | ||
1653 | for (i = 0; i < npages; i++) { | |
1654 | page_virtual = kmap_atomic(pages[i]); | |
1655 | clflush_cache_range(page_virtual, PAGE_SIZE); | |
1656 | kunmap_atomic(page_virtual); | |
1657 | } | |
1658 | } | |
1659 | ||
1e80fdc0 BS |
1660 | static void __unregister_enc_region_locked(struct kvm *kvm, |
1661 | struct enc_region *region) | |
1662 | { | |
1663 | /* | |
1664 | * The guest may change the memory encryption attribute from C=0 -> C=1 | |
1665 | * or vice versa for this memory range. Lets make sure caches are | |
1666 | * flushed to ensure that guest data gets written into memory with | |
1667 | * correct C-bit. | |
1668 | */ | |
1669 | sev_clflush_pages(region->pages, region->npages); | |
1670 | ||
1671 | sev_unpin_memory(kvm, region->pages, region->npages); | |
1672 | list_del(®ion->list); | |
1673 | kfree(region); | |
1674 | } | |
1675 | ||
1654efcb BS |
1676 | static void sev_vm_destroy(struct kvm *kvm) |
1677 | { | |
59414c98 | 1678 | struct kvm_sev_info *sev = &kvm->arch.sev_info; |
1e80fdc0 BS |
1679 | struct list_head *head = &sev->regions_list; |
1680 | struct list_head *pos, *q; | |
59414c98 | 1681 | |
1654efcb BS |
1682 | if (!sev_guest(kvm)) |
1683 | return; | |
1684 | ||
1e80fdc0 BS |
1685 | mutex_lock(&kvm->lock); |
1686 | ||
1687 | /* | |
1688 | * if userspace was terminated before unregistering the memory regions | |
1689 | * then lets unpin all the registered memory. | |
1690 | */ | |
1691 | if (!list_empty(head)) { | |
1692 | list_for_each_safe(pos, q, head) { | |
1693 | __unregister_enc_region_locked(kvm, | |
1694 | list_entry(pos, struct enc_region, list)); | |
1695 | } | |
1696 | } | |
1697 | ||
1698 | mutex_unlock(&kvm->lock); | |
1699 | ||
59414c98 | 1700 | sev_unbind_asid(kvm, sev->handle); |
1654efcb BS |
1701 | sev_asid_free(kvm); |
1702 | } | |
1703 | ||
44a95dae SS |
1704 | static void avic_vm_destroy(struct kvm *kvm) |
1705 | { | |
5881f737 | 1706 | unsigned long flags; |
44a95dae SS |
1707 | struct kvm_arch *vm_data = &kvm->arch; |
1708 | ||
3863dff0 DV |
1709 | if (!avic) |
1710 | return; | |
1711 | ||
44a95dae SS |
1712 | if (vm_data->avic_logical_id_table_page) |
1713 | __free_page(vm_data->avic_logical_id_table_page); | |
1714 | if (vm_data->avic_physical_id_table_page) | |
1715 | __free_page(vm_data->avic_physical_id_table_page); | |
5881f737 SS |
1716 | |
1717 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); | |
1718 | hash_del(&vm_data->hnode); | |
1719 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
44a95dae SS |
1720 | } |
1721 | ||
1654efcb BS |
1722 | static void svm_vm_destroy(struct kvm *kvm) |
1723 | { | |
1724 | avic_vm_destroy(kvm); | |
1725 | sev_vm_destroy(kvm); | |
1726 | } | |
1727 | ||
44a95dae SS |
1728 | static int avic_vm_init(struct kvm *kvm) |
1729 | { | |
5881f737 | 1730 | unsigned long flags; |
3f0d4db7 | 1731 | int err = -ENOMEM; |
44a95dae SS |
1732 | struct kvm_arch *vm_data = &kvm->arch; |
1733 | struct page *p_page; | |
1734 | struct page *l_page; | |
3f0d4db7 DV |
1735 | struct kvm_arch *ka; |
1736 | u32 vm_id; | |
44a95dae SS |
1737 | |
1738 | if (!avic) | |
1739 | return 0; | |
1740 | ||
1741 | /* Allocating physical APIC ID table (4KB) */ | |
1742 | p_page = alloc_page(GFP_KERNEL); | |
1743 | if (!p_page) | |
1744 | goto free_avic; | |
1745 | ||
1746 | vm_data->avic_physical_id_table_page = p_page; | |
1747 | clear_page(page_address(p_page)); | |
1748 | ||
1749 | /* Allocating logical APIC ID table (4KB) */ | |
1750 | l_page = alloc_page(GFP_KERNEL); | |
1751 | if (!l_page) | |
1752 | goto free_avic; | |
1753 | ||
1754 | vm_data->avic_logical_id_table_page = l_page; | |
1755 | clear_page(page_address(l_page)); | |
1756 | ||
5881f737 | 1757 | spin_lock_irqsave(&svm_vm_data_hash_lock, flags); |
3f0d4db7 DV |
1758 | again: |
1759 | vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK; | |
1760 | if (vm_id == 0) { /* id is 1-based, zero is not okay */ | |
1761 | next_vm_id_wrapped = 1; | |
1762 | goto again; | |
1763 | } | |
1764 | /* Is it still in use? Only possible if wrapped at least once */ | |
1765 | if (next_vm_id_wrapped) { | |
1766 | hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) { | |
1767 | struct kvm *k2 = container_of(ka, struct kvm, arch); | |
1768 | struct kvm_arch *vd2 = &k2->arch; | |
1769 | if (vd2->avic_vm_id == vm_id) | |
1770 | goto again; | |
1771 | } | |
1772 | } | |
1773 | vm_data->avic_vm_id = vm_id; | |
5881f737 SS |
1774 | hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id); |
1775 | spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); | |
1776 | ||
44a95dae SS |
1777 | return 0; |
1778 | ||
1779 | free_avic: | |
1780 | avic_vm_destroy(kvm); | |
1781 | return err; | |
6aa8b732 AK |
1782 | } |
1783 | ||
411b44ba SS |
1784 | static inline int |
1785 | avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r) | |
8221c137 | 1786 | { |
411b44ba SS |
1787 | int ret = 0; |
1788 | unsigned long flags; | |
1789 | struct amd_svm_iommu_ir *ir; | |
8221c137 SS |
1790 | struct vcpu_svm *svm = to_svm(vcpu); |
1791 | ||
411b44ba SS |
1792 | if (!kvm_arch_has_assigned_device(vcpu->kvm)) |
1793 | return 0; | |
8221c137 | 1794 | |
411b44ba SS |
1795 | /* |
1796 | * Here, we go through the per-vcpu ir_list to update all existing | |
1797 | * interrupt remapping table entry targeting this vcpu. | |
1798 | */ | |
1799 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
8221c137 | 1800 | |
411b44ba SS |
1801 | if (list_empty(&svm->ir_list)) |
1802 | goto out; | |
8221c137 | 1803 | |
411b44ba SS |
1804 | list_for_each_entry(ir, &svm->ir_list, node) { |
1805 | ret = amd_iommu_update_ga(cpu, r, ir->data); | |
1806 | if (ret) | |
1807 | break; | |
1808 | } | |
1809 | out: | |
1810 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
1811 | return ret; | |
8221c137 SS |
1812 | } |
1813 | ||
1814 | static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |
1815 | { | |
1816 | u64 entry; | |
1817 | /* ID = 0xff (broadcast), ID > 0xff (reserved) */ | |
7d669f50 | 1818 | int h_physical_id = kvm_cpu_get_apicid(cpu); |
8221c137 SS |
1819 | struct vcpu_svm *svm = to_svm(vcpu); |
1820 | ||
1821 | if (!kvm_vcpu_apicv_active(vcpu)) | |
1822 | return; | |
1823 | ||
1824 | if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT)) | |
1825 | return; | |
1826 | ||
1827 | entry = READ_ONCE(*(svm->avic_physical_id_cache)); | |
1828 | WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); | |
1829 | ||
1830 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; | |
1831 | entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); | |
1832 | ||
1833 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; | |
1834 | if (svm->avic_is_running) | |
1835 | entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; | |
1836 | ||
1837 | WRITE_ONCE(*(svm->avic_physical_id_cache), entry); | |
411b44ba SS |
1838 | avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, |
1839 | svm->avic_is_running); | |
8221c137 SS |
1840 | } |
1841 | ||
1842 | static void avic_vcpu_put(struct kvm_vcpu *vcpu) | |
1843 | { | |
1844 | u64 entry; | |
1845 | struct vcpu_svm *svm = to_svm(vcpu); | |
1846 | ||
1847 | if (!kvm_vcpu_apicv_active(vcpu)) | |
1848 | return; | |
1849 | ||
1850 | entry = READ_ONCE(*(svm->avic_physical_id_cache)); | |
411b44ba SS |
1851 | if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) |
1852 | avic_update_iommu_vcpu_affinity(vcpu, -1, 0); | |
1853 | ||
8221c137 SS |
1854 | entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; |
1855 | WRITE_ONCE(*(svm->avic_physical_id_cache), entry); | |
6aa8b732 AK |
1856 | } |
1857 | ||
411b44ba SS |
1858 | /** |
1859 | * This function is called during VCPU halt/unhalt. | |
1860 | */ | |
1861 | static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run) | |
1862 | { | |
1863 | struct vcpu_svm *svm = to_svm(vcpu); | |
1864 | ||
1865 | svm->avic_is_running = is_run; | |
1866 | if (is_run) | |
1867 | avic_vcpu_load(vcpu, vcpu->cpu); | |
1868 | else | |
1869 | avic_vcpu_put(vcpu); | |
1870 | } | |
1871 | ||
d28bc9dd | 1872 | static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
04d2cc77 AK |
1873 | { |
1874 | struct vcpu_svm *svm = to_svm(vcpu); | |
66f7b72e JS |
1875 | u32 dummy; |
1876 | u32 eax = 1; | |
04d2cc77 | 1877 | |
d28bc9dd NA |
1878 | if (!init_event) { |
1879 | svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE | | |
1880 | MSR_IA32_APICBASE_ENABLE; | |
1881 | if (kvm_vcpu_is_reset_bsp(&svm->vcpu)) | |
1882 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; | |
1883 | } | |
5690891b | 1884 | init_vmcb(svm); |
70433389 | 1885 | |
e911eb3b | 1886 | kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true); |
66f7b72e | 1887 | kvm_register_write(vcpu, VCPU_REGS_RDX, eax); |
44a95dae SS |
1888 | |
1889 | if (kvm_vcpu_apicv_active(vcpu) && !init_event) | |
1890 | avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE); | |
04d2cc77 AK |
1891 | } |
1892 | ||
dfa20099 SS |
1893 | static int avic_init_vcpu(struct vcpu_svm *svm) |
1894 | { | |
1895 | int ret; | |
1896 | ||
67034bb9 | 1897 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
dfa20099 SS |
1898 | return 0; |
1899 | ||
1900 | ret = avic_init_backing_page(&svm->vcpu); | |
1901 | if (ret) | |
1902 | return ret; | |
1903 | ||
1904 | INIT_LIST_HEAD(&svm->ir_list); | |
1905 | spin_lock_init(&svm->ir_list_lock); | |
1906 | ||
1907 | return ret; | |
1908 | } | |
1909 | ||
fb3f0f51 | 1910 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1911 | { |
a2fa3e9f | 1912 | struct vcpu_svm *svm; |
6aa8b732 | 1913 | struct page *page; |
f65c229c | 1914 | struct page *msrpm_pages; |
b286d5d8 | 1915 | struct page *hsave_page; |
3d6368ef | 1916 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1917 | int err; |
6aa8b732 | 1918 | |
c16f862d | 1919 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1920 | if (!svm) { |
1921 | err = -ENOMEM; | |
1922 | goto out; | |
1923 | } | |
1924 | ||
1925 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
1926 | if (err) | |
1927 | goto free_svm; | |
1928 | ||
b7af4043 | 1929 | err = -ENOMEM; |
6aa8b732 | 1930 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1931 | if (!page) |
fb3f0f51 | 1932 | goto uninit; |
6aa8b732 | 1933 | |
f65c229c JR |
1934 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1935 | if (!msrpm_pages) | |
b7af4043 | 1936 | goto free_page1; |
3d6368ef AG |
1937 | |
1938 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1939 | if (!nested_msrpm_pages) | |
b7af4043 | 1940 | goto free_page2; |
f65c229c | 1941 | |
b286d5d8 AG |
1942 | hsave_page = alloc_page(GFP_KERNEL); |
1943 | if (!hsave_page) | |
b7af4043 TY |
1944 | goto free_page3; |
1945 | ||
dfa20099 SS |
1946 | err = avic_init_vcpu(svm); |
1947 | if (err) | |
1948 | goto free_page4; | |
44a95dae | 1949 | |
8221c137 SS |
1950 | /* We initialize this flag to true to make sure that the is_running |
1951 | * bit would be set the first time the vcpu is loaded. | |
1952 | */ | |
1953 | svm->avic_is_running = true; | |
1954 | ||
e6aa9abd | 1955 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1956 | |
b7af4043 TY |
1957 | svm->msrpm = page_address(msrpm_pages); |
1958 | svm_vcpu_init_msrpm(svm->msrpm); | |
1959 | ||
e6aa9abd | 1960 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1961 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1962 | |
a2fa3e9f GH |
1963 | svm->vmcb = page_address(page); |
1964 | clear_page(svm->vmcb); | |
d0ec49d4 | 1965 | svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT); |
a2fa3e9f | 1966 | svm->asid_generation = 0; |
5690891b | 1967 | init_vmcb(svm); |
6aa8b732 | 1968 | |
2b036c6b BO |
1969 | svm_init_osvw(&svm->vcpu); |
1970 | ||
fb3f0f51 | 1971 | return &svm->vcpu; |
36241b8c | 1972 | |
44a95dae SS |
1973 | free_page4: |
1974 | __free_page(hsave_page); | |
b7af4043 TY |
1975 | free_page3: |
1976 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1977 | free_page2: | |
1978 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1979 | free_page1: | |
1980 | __free_page(page); | |
fb3f0f51 RR |
1981 | uninit: |
1982 | kvm_vcpu_uninit(&svm->vcpu); | |
1983 | free_svm: | |
a4770347 | 1984 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1985 | out: |
1986 | return ERR_PTR(err); | |
6aa8b732 AK |
1987 | } |
1988 | ||
1989 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1990 | { | |
a2fa3e9f GH |
1991 | struct vcpu_svm *svm = to_svm(vcpu); |
1992 | ||
d0ec49d4 | 1993 | __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT)); |
f65c229c | 1994 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1995 | __free_page(virt_to_page(svm->nested.hsave)); |
1996 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1997 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1998 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1999 | } |
2000 | ||
15ad7146 | 2001 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 2002 | { |
a2fa3e9f | 2003 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 2004 | int i; |
0cc5064d | 2005 | |
0cc5064d | 2006 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 2007 | svm->asid_generation = 0; |
8d28fec4 | 2008 | mark_all_dirty(svm->vmcb); |
0cc5064d | 2009 | } |
94dfbdb3 | 2010 | |
82ca2d10 AK |
2011 | #ifdef CONFIG_X86_64 |
2012 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
2013 | #endif | |
dacccfdd AK |
2014 | savesegment(fs, svm->host.fs); |
2015 | savesegment(gs, svm->host.gs); | |
2016 | svm->host.ldt = kvm_read_ldt(); | |
2017 | ||
94dfbdb3 | 2018 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 2019 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 | 2020 | |
ad721883 HZ |
2021 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
2022 | u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio; | |
2023 | if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) { | |
2024 | __this_cpu_write(current_tsc_ratio, tsc_ratio); | |
2025 | wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio); | |
2026 | } | |
fbc0db76 | 2027 | } |
46896c73 PB |
2028 | /* This assumes that the kernel never uses MSR_TSC_AUX */ |
2029 | if (static_cpu_has(X86_FEATURE_RDTSCP)) | |
2030 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
8221c137 SS |
2031 | |
2032 | avic_vcpu_load(vcpu, cpu); | |
6aa8b732 AK |
2033 | } |
2034 | ||
2035 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
2036 | { | |
a2fa3e9f | 2037 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
2038 | int i; |
2039 | ||
8221c137 SS |
2040 | avic_vcpu_put(vcpu); |
2041 | ||
e1beb1d3 | 2042 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
2043 | kvm_load_ldt(svm->host.ldt); |
2044 | #ifdef CONFIG_X86_64 | |
2045 | loadsegment(fs, svm->host.fs); | |
296f781a | 2046 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase); |
893a5ab6 | 2047 | load_gs_index(svm->host.gs); |
dacccfdd | 2048 | #else |
831ca609 | 2049 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 2050 | loadsegment(gs, svm->host.gs); |
831ca609 | 2051 | #endif |
dacccfdd | 2052 | #endif |
94dfbdb3 | 2053 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 2054 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
2055 | } |
2056 | ||
8221c137 SS |
2057 | static void svm_vcpu_blocking(struct kvm_vcpu *vcpu) |
2058 | { | |
2059 | avic_set_running(vcpu, false); | |
2060 | } | |
2061 | ||
2062 | static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu) | |
2063 | { | |
2064 | avic_set_running(vcpu, true); | |
2065 | } | |
2066 | ||
6aa8b732 AK |
2067 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
2068 | { | |
9b611747 LP |
2069 | struct vcpu_svm *svm = to_svm(vcpu); |
2070 | unsigned long rflags = svm->vmcb->save.rflags; | |
2071 | ||
2072 | if (svm->nmi_singlestep) { | |
2073 | /* Hide our flags if they were not set by the guest */ | |
2074 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF)) | |
2075 | rflags &= ~X86_EFLAGS_TF; | |
2076 | if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF)) | |
2077 | rflags &= ~X86_EFLAGS_RF; | |
2078 | } | |
2079 | return rflags; | |
6aa8b732 AK |
2080 | } |
2081 | ||
2082 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
2083 | { | |
9b611747 LP |
2084 | if (to_svm(vcpu)->nmi_singlestep) |
2085 | rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); | |
2086 | ||
ae9fedc7 | 2087 | /* |
bb3541f1 | 2088 | * Any change of EFLAGS.VM is accompanied by a reload of SS |
ae9fedc7 PB |
2089 | * (caused by either a task switch or an inter-privilege IRET), |
2090 | * so we do not need to update the CPL here. | |
2091 | */ | |
a2fa3e9f | 2092 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
2093 | } |
2094 | ||
6de4f3ad AK |
2095 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
2096 | { | |
2097 | switch (reg) { | |
2098 | case VCPU_EXREG_PDPTR: | |
2099 | BUG_ON(!npt_enabled); | |
9f8fe504 | 2100 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
2101 | break; |
2102 | default: | |
2103 | BUG(); | |
2104 | } | |
2105 | } | |
2106 | ||
f0b85051 AG |
2107 | static void svm_set_vintr(struct vcpu_svm *svm) |
2108 | { | |
8a05a1b8 | 2109 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
2110 | } |
2111 | ||
2112 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
2113 | { | |
8a05a1b8 | 2114 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
2115 | } |
2116 | ||
6aa8b732 AK |
2117 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
2118 | { | |
a2fa3e9f | 2119 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
2120 | |
2121 | switch (seg) { | |
2122 | case VCPU_SREG_CS: return &save->cs; | |
2123 | case VCPU_SREG_DS: return &save->ds; | |
2124 | case VCPU_SREG_ES: return &save->es; | |
2125 | case VCPU_SREG_FS: return &save->fs; | |
2126 | case VCPU_SREG_GS: return &save->gs; | |
2127 | case VCPU_SREG_SS: return &save->ss; | |
2128 | case VCPU_SREG_TR: return &save->tr; | |
2129 | case VCPU_SREG_LDTR: return &save->ldtr; | |
2130 | } | |
2131 | BUG(); | |
8b6d44c7 | 2132 | return NULL; |
6aa8b732 AK |
2133 | } |
2134 | ||
2135 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
2136 | { | |
2137 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
2138 | ||
2139 | return s->base; | |
2140 | } | |
2141 | ||
2142 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
2143 | struct kvm_segment *var, int seg) | |
2144 | { | |
2145 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
2146 | ||
2147 | var->base = s->base; | |
2148 | var->limit = s->limit; | |
2149 | var->selector = s->selector; | |
2150 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
2151 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
2152 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
2153 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
2154 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
2155 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
2156 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
80112c89 JM |
2157 | |
2158 | /* | |
2159 | * AMD CPUs circa 2014 track the G bit for all segments except CS. | |
2160 | * However, the SVM spec states that the G bit is not observed by the | |
2161 | * CPU, and some VMware virtual CPUs drop the G bit for all segments. | |
2162 | * So let's synthesize a legal G bit for all segments, this helps | |
2163 | * running KVM nested. It also helps cross-vendor migration, because | |
2164 | * Intel's vmentry has a check on the 'G' bit. | |
2165 | */ | |
2166 | var->g = s->limit > 0xfffff; | |
25022acc | 2167 | |
e0231715 JR |
2168 | /* |
2169 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
2170 | * for cross vendor migration purposes by "not present" |
2171 | */ | |
8eae9570 | 2172 | var->unusable = !var->present; |
19bca6ab | 2173 | |
1fbdc7a5 | 2174 | switch (seg) { |
1fbdc7a5 AP |
2175 | case VCPU_SREG_TR: |
2176 | /* | |
2177 | * Work around a bug where the busy flag in the tr selector | |
2178 | * isn't exposed | |
2179 | */ | |
c0d09828 | 2180 | var->type |= 0x2; |
1fbdc7a5 AP |
2181 | break; |
2182 | case VCPU_SREG_DS: | |
2183 | case VCPU_SREG_ES: | |
2184 | case VCPU_SREG_FS: | |
2185 | case VCPU_SREG_GS: | |
2186 | /* | |
2187 | * The accessed bit must always be set in the segment | |
2188 | * descriptor cache, although it can be cleared in the | |
2189 | * descriptor, the cached bit always remains at 1. Since | |
2190 | * Intel has a check on this, set it here to support | |
2191 | * cross-vendor migration. | |
2192 | */ | |
2193 | if (!var->unusable) | |
2194 | var->type |= 0x1; | |
2195 | break; | |
b586eb02 | 2196 | case VCPU_SREG_SS: |
e0231715 JR |
2197 | /* |
2198 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
2199 | * descriptor is left as 1, although the whole segment has |
2200 | * been made unusable. Clear it here to pass an Intel VMX | |
2201 | * entry check when cross vendor migrating. | |
2202 | */ | |
2203 | if (var->unusable) | |
2204 | var->db = 0; | |
d9c1b543 | 2205 | /* This is symmetric with svm_set_segment() */ |
33b458d2 | 2206 | var->dpl = to_svm(vcpu)->vmcb->save.cpl; |
b586eb02 | 2207 | break; |
1fbdc7a5 | 2208 | } |
6aa8b732 AK |
2209 | } |
2210 | ||
2e4d2653 IE |
2211 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
2212 | { | |
2213 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
2214 | ||
2215 | return save->cpl; | |
2216 | } | |
2217 | ||
89a27f4d | 2218 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2219 | { |
a2fa3e9f GH |
2220 | struct vcpu_svm *svm = to_svm(vcpu); |
2221 | ||
89a27f4d GN |
2222 | dt->size = svm->vmcb->save.idtr.limit; |
2223 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
2224 | } |
2225 | ||
89a27f4d | 2226 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2227 | { |
a2fa3e9f GH |
2228 | struct vcpu_svm *svm = to_svm(vcpu); |
2229 | ||
89a27f4d GN |
2230 | svm->vmcb->save.idtr.limit = dt->size; |
2231 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 2232 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
2233 | } |
2234 | ||
89a27f4d | 2235 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2236 | { |
a2fa3e9f GH |
2237 | struct vcpu_svm *svm = to_svm(vcpu); |
2238 | ||
89a27f4d GN |
2239 | dt->size = svm->vmcb->save.gdtr.limit; |
2240 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
2241 | } |
2242 | ||
89a27f4d | 2243 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2244 | { |
a2fa3e9f GH |
2245 | struct vcpu_svm *svm = to_svm(vcpu); |
2246 | ||
89a27f4d GN |
2247 | svm->vmcb->save.gdtr.limit = dt->size; |
2248 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 2249 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
2250 | } |
2251 | ||
e8467fda AK |
2252 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
2253 | { | |
2254 | } | |
2255 | ||
aff48baa AK |
2256 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
2257 | { | |
2258 | } | |
2259 | ||
25c4c276 | 2260 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
2261 | { |
2262 | } | |
2263 | ||
d225157b AK |
2264 | static void update_cr0_intercept(struct vcpu_svm *svm) |
2265 | { | |
2266 | ulong gcr0 = svm->vcpu.arch.cr0; | |
2267 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
2268 | ||
bd7e5b08 PB |
2269 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) |
2270 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
d225157b | 2271 | |
dcca1a65 | 2272 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 2273 | |
bd7e5b08 | 2274 | if (gcr0 == *hcr0) { |
4ee546b4 RJ |
2275 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
2276 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 2277 | } else { |
4ee546b4 RJ |
2278 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
2279 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
2280 | } |
2281 | } | |
2282 | ||
6aa8b732 AK |
2283 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
2284 | { | |
a2fa3e9f GH |
2285 | struct vcpu_svm *svm = to_svm(vcpu); |
2286 | ||
05b3e0c2 | 2287 | #ifdef CONFIG_X86_64 |
f6801dff | 2288 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 2289 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 2290 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 2291 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
2292 | } |
2293 | ||
d77c26fc | 2294 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 2295 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 2296 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
2297 | } |
2298 | } | |
2299 | #endif | |
ad312c7c | 2300 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
2301 | |
2302 | if (!npt_enabled) | |
2303 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 | 2304 | |
bcf166a9 PB |
2305 | /* |
2306 | * re-enable caching here because the QEMU bios | |
2307 | * does not do it - this results in some delay at | |
2308 | * reboot | |
2309 | */ | |
2310 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
2311 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 2312 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 2313 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 2314 | update_cr0_intercept(svm); |
6aa8b732 AK |
2315 | } |
2316 | ||
5e1746d6 | 2317 | static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 2318 | { |
1e02ce4c | 2319 | unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE; |
e5eab0ce JR |
2320 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
2321 | ||
5e1746d6 NHE |
2322 | if (cr4 & X86_CR4_VMXE) |
2323 | return 1; | |
2324 | ||
e5eab0ce | 2325 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) |
f40f6a45 | 2326 | svm_flush_tlb(vcpu); |
6394b649 | 2327 | |
ec077263 JR |
2328 | vcpu->arch.cr4 = cr4; |
2329 | if (!npt_enabled) | |
2330 | cr4 |= X86_CR4_PAE; | |
6394b649 | 2331 | cr4 |= host_cr4_mce; |
ec077263 | 2332 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 2333 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
5e1746d6 | 2334 | return 0; |
6aa8b732 AK |
2335 | } |
2336 | ||
2337 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
2338 | struct kvm_segment *var, int seg) | |
2339 | { | |
a2fa3e9f | 2340 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
2341 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
2342 | ||
2343 | s->base = var->base; | |
2344 | s->limit = var->limit; | |
2345 | s->selector = var->selector; | |
d9c1b543 RP |
2346 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); |
2347 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
2348 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
2349 | s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT; | |
2350 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
2351 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
2352 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
2353 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
ae9fedc7 PB |
2354 | |
2355 | /* | |
2356 | * This is always accurate, except if SYSRET returned to a segment | |
2357 | * with SS.DPL != 3. Intel does not have this quirk, and always | |
2358 | * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it | |
2359 | * would entail passing the CPL to userspace and back. | |
2360 | */ | |
2361 | if (seg == VCPU_SREG_SS) | |
d9c1b543 RP |
2362 | /* This is symmetric with svm_get_segment() */ |
2363 | svm->vmcb->save.cpl = (var->dpl & 3); | |
6aa8b732 | 2364 | |
060d0c9a | 2365 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
2366 | } |
2367 | ||
cbdb967a | 2368 | static void update_bp_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 2369 | { |
d0bfb940 JK |
2370 | struct vcpu_svm *svm = to_svm(vcpu); |
2371 | ||
18c918c5 | 2372 | clr_exception_intercept(svm, BP_VECTOR); |
44c11430 | 2373 | |
d0bfb940 | 2374 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
d0bfb940 | 2375 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 2376 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
2377 | } else |
2378 | vcpu->guest_debug = 0; | |
44c11430 GN |
2379 | } |
2380 | ||
0fe1e009 | 2381 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 2382 | { |
0fe1e009 TH |
2383 | if (sd->next_asid > sd->max_asid) { |
2384 | ++sd->asid_generation; | |
4faefff3 | 2385 | sd->next_asid = sd->min_asid; |
a2fa3e9f | 2386 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
2387 | } |
2388 | ||
0fe1e009 TH |
2389 | svm->asid_generation = sd->asid_generation; |
2390 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
2391 | |
2392 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
2393 | } |
2394 | ||
73aaf249 JK |
2395 | static u64 svm_get_dr6(struct kvm_vcpu *vcpu) |
2396 | { | |
2397 | return to_svm(vcpu)->vmcb->save.dr6; | |
2398 | } | |
2399 | ||
2400 | static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value) | |
2401 | { | |
2402 | struct vcpu_svm *svm = to_svm(vcpu); | |
2403 | ||
2404 | svm->vmcb->save.dr6 = value; | |
2405 | mark_dirty(svm->vmcb, VMCB_DR); | |
2406 | } | |
2407 | ||
facb0139 PB |
2408 | static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
2409 | { | |
2410 | struct vcpu_svm *svm = to_svm(vcpu); | |
2411 | ||
2412 | get_debugreg(vcpu->arch.db[0], 0); | |
2413 | get_debugreg(vcpu->arch.db[1], 1); | |
2414 | get_debugreg(vcpu->arch.db[2], 2); | |
2415 | get_debugreg(vcpu->arch.db[3], 3); | |
2416 | vcpu->arch.dr6 = svm_get_dr6(vcpu); | |
2417 | vcpu->arch.dr7 = svm->vmcb->save.dr7; | |
2418 | ||
2419 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
2420 | set_dr_intercepts(svm); | |
2421 | } | |
2422 | ||
020df079 | 2423 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 2424 | { |
42dbaa5a | 2425 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 2426 | |
020df079 | 2427 | svm->vmcb->save.dr7 = value; |
72214b96 | 2428 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
2429 | } |
2430 | ||
851ba692 | 2431 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 2432 | { |
0ede79e1 | 2433 | u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2); |
1261bfa3 | 2434 | u64 error_code = svm->vmcb->control.exit_info_1; |
6aa8b732 | 2435 | |
1261bfa3 | 2436 | return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address, |
dc25e89e | 2437 | svm->vmcb->control.insn_bytes, |
d0006530 PB |
2438 | svm->vmcb->control.insn_len); |
2439 | } | |
2440 | ||
2441 | static int npf_interception(struct vcpu_svm *svm) | |
2442 | { | |
0ede79e1 | 2443 | u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2); |
d0006530 PB |
2444 | u64 error_code = svm->vmcb->control.exit_info_1; |
2445 | ||
2446 | trace_kvm_page_fault(fault_address, error_code); | |
2447 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, | |
2448 | svm->vmcb->control.insn_bytes, | |
2449 | svm->vmcb->control.insn_len); | |
6aa8b732 AK |
2450 | } |
2451 | ||
851ba692 | 2452 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 2453 | { |
851ba692 AK |
2454 | struct kvm_run *kvm_run = svm->vcpu.run; |
2455 | ||
d0bfb940 | 2456 | if (!(svm->vcpu.guest_debug & |
44c11430 | 2457 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 2458 | !svm->nmi_singlestep) { |
d0bfb940 JK |
2459 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
2460 | return 1; | |
2461 | } | |
44c11430 | 2462 | |
6be7d306 | 2463 | if (svm->nmi_singlestep) { |
4aebd0e9 | 2464 | disable_nmi_singlestep(svm); |
44c11430 GN |
2465 | } |
2466 | ||
2467 | if (svm->vcpu.guest_debug & | |
e0231715 | 2468 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
2469 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2470 | kvm_run->debug.arch.pc = | |
2471 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
2472 | kvm_run->debug.arch.exception = DB_VECTOR; | |
2473 | return 0; | |
2474 | } | |
2475 | ||
2476 | return 1; | |
d0bfb940 JK |
2477 | } |
2478 | ||
851ba692 | 2479 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 2480 | { |
851ba692 AK |
2481 | struct kvm_run *kvm_run = svm->vcpu.run; |
2482 | ||
d0bfb940 JK |
2483 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2484 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
2485 | kvm_run->debug.arch.exception = BP_VECTOR; | |
2486 | return 0; | |
2487 | } | |
2488 | ||
851ba692 | 2489 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
2490 | { |
2491 | int er; | |
2492 | ||
51d8b661 | 2493 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 2494 | if (er != EMULATE_DONE) |
7ee5d940 | 2495 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
2496 | return 1; |
2497 | } | |
2498 | ||
54a20552 EN |
2499 | static int ac_interception(struct vcpu_svm *svm) |
2500 | { | |
2501 | kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0); | |
2502 | return 1; | |
2503 | } | |
2504 | ||
67ec6607 JR |
2505 | static bool is_erratum_383(void) |
2506 | { | |
2507 | int err, i; | |
2508 | u64 value; | |
2509 | ||
2510 | if (!erratum_383_found) | |
2511 | return false; | |
2512 | ||
2513 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
2514 | if (err) | |
2515 | return false; | |
2516 | ||
2517 | /* Bit 62 may or may not be set for this mce */ | |
2518 | value &= ~(1ULL << 62); | |
2519 | ||
2520 | if (value != 0xb600000000010015ULL) | |
2521 | return false; | |
2522 | ||
2523 | /* Clear MCi_STATUS registers */ | |
2524 | for (i = 0; i < 6; ++i) | |
2525 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
2526 | ||
2527 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
2528 | if (!err) { | |
2529 | u32 low, high; | |
2530 | ||
2531 | value &= ~(1ULL << 2); | |
2532 | low = lower_32_bits(value); | |
2533 | high = upper_32_bits(value); | |
2534 | ||
2535 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
2536 | } | |
2537 | ||
2538 | /* Flush tlb to evict multi-match entries */ | |
2539 | __flush_tlb_all(); | |
2540 | ||
2541 | return true; | |
2542 | } | |
2543 | ||
fe5913e4 | 2544 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 2545 | { |
67ec6607 JR |
2546 | if (is_erratum_383()) { |
2547 | /* | |
2548 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
2549 | * guest. | |
2550 | */ | |
2551 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
2552 | ||
a8eeb04a | 2553 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
2554 | |
2555 | return; | |
2556 | } | |
2557 | ||
53371b50 JR |
2558 | /* |
2559 | * On an #MC intercept the MCE handler is not called automatically in | |
2560 | * the host. So do it by hand here. | |
2561 | */ | |
2562 | asm volatile ( | |
2563 | "int $0x12\n"); | |
2564 | /* not sure if we ever come back to this point */ | |
2565 | ||
fe5913e4 JR |
2566 | return; |
2567 | } | |
2568 | ||
2569 | static int mc_interception(struct vcpu_svm *svm) | |
2570 | { | |
53371b50 JR |
2571 | return 1; |
2572 | } | |
2573 | ||
851ba692 | 2574 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 2575 | { |
851ba692 AK |
2576 | struct kvm_run *kvm_run = svm->vcpu.run; |
2577 | ||
46fe4ddd JR |
2578 | /* |
2579 | * VMCB is undefined after a SHUTDOWN intercept | |
2580 | * so reinitialize it. | |
2581 | */ | |
a2fa3e9f | 2582 | clear_page(svm->vmcb); |
5690891b | 2583 | init_vmcb(svm); |
46fe4ddd JR |
2584 | |
2585 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2586 | return 0; | |
2587 | } | |
2588 | ||
851ba692 | 2589 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 2590 | { |
cf8f70bf | 2591 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 2592 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
b742c1e6 | 2593 | int size, in, string, ret; |
039576c0 | 2594 | unsigned port; |
6aa8b732 | 2595 | |
e756fc62 | 2596 | ++svm->vcpu.stat.io_exits; |
e70669ab | 2597 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 2598 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
8370c3d0 | 2599 | if (string) |
51d8b661 | 2600 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 2601 | |
039576c0 AK |
2602 | port = io_info >> 16; |
2603 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 2604 | svm->next_rip = svm->vmcb->control.exit_info_2; |
b742c1e6 | 2605 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
cf8f70bf | 2606 | |
b742c1e6 LP |
2607 | /* |
2608 | * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered | |
2609 | * KVM_EXIT_DEBUG here. | |
2610 | */ | |
2611 | if (in) | |
2612 | return kvm_fast_pio_in(vcpu, size, port) && ret; | |
2613 | else | |
2614 | return kvm_fast_pio_out(vcpu, size, port) && ret; | |
6aa8b732 AK |
2615 | } |
2616 | ||
851ba692 | 2617 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
2618 | { |
2619 | return 1; | |
2620 | } | |
2621 | ||
851ba692 | 2622 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
2623 | { |
2624 | ++svm->vcpu.stat.irq_exits; | |
2625 | return 1; | |
2626 | } | |
2627 | ||
851ba692 | 2628 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
2629 | { |
2630 | return 1; | |
2631 | } | |
2632 | ||
851ba692 | 2633 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 2634 | { |
5fdbf976 | 2635 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 | 2636 | return kvm_emulate_halt(&svm->vcpu); |
6aa8b732 AK |
2637 | } |
2638 | ||
851ba692 | 2639 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 2640 | { |
5fdbf976 | 2641 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
0d9c055e | 2642 | return kvm_emulate_hypercall(&svm->vcpu); |
02e235bc AK |
2643 | } |
2644 | ||
5bd2edc3 JR |
2645 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
2646 | { | |
2647 | struct vcpu_svm *svm = to_svm(vcpu); | |
2648 | ||
2649 | return svm->nested.nested_cr3; | |
2650 | } | |
2651 | ||
e4e517b4 AK |
2652 | static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) |
2653 | { | |
2654 | struct vcpu_svm *svm = to_svm(vcpu); | |
2655 | u64 cr3 = svm->nested.nested_cr3; | |
2656 | u64 pdpte; | |
2657 | int ret; | |
2658 | ||
d0ec49d4 | 2659 | ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte, |
54bf36aa | 2660 | offset_in_page(cr3) + index * 8, 8); |
e4e517b4 AK |
2661 | if (ret) |
2662 | return 0; | |
2663 | return pdpte; | |
2664 | } | |
2665 | ||
5bd2edc3 JR |
2666 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, |
2667 | unsigned long root) | |
2668 | { | |
2669 | struct vcpu_svm *svm = to_svm(vcpu); | |
2670 | ||
d0ec49d4 | 2671 | svm->vmcb->control.nested_cr3 = __sme_set(root); |
b2747166 | 2672 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 2673 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
2674 | } |
2675 | ||
6389ee94 AK |
2676 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
2677 | struct x86_exception *fault) | |
5bd2edc3 JR |
2678 | { |
2679 | struct vcpu_svm *svm = to_svm(vcpu); | |
2680 | ||
5e352519 PB |
2681 | if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) { |
2682 | /* | |
2683 | * TODO: track the cause of the nested page fault, and | |
2684 | * correctly fill in the high bits of exit_info_1. | |
2685 | */ | |
2686 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
2687 | svm->vmcb->control.exit_code_hi = 0; | |
2688 | svm->vmcb->control.exit_info_1 = (1ULL << 32); | |
2689 | svm->vmcb->control.exit_info_2 = fault->address; | |
2690 | } | |
2691 | ||
2692 | svm->vmcb->control.exit_info_1 &= ~0xffffffffULL; | |
2693 | svm->vmcb->control.exit_info_1 |= fault->error_code; | |
2694 | ||
2695 | /* | |
2696 | * The present bit is always zero for page structure faults on real | |
2697 | * hardware. | |
2698 | */ | |
2699 | if (svm->vmcb->control.exit_info_1 & (2ULL << 32)) | |
2700 | svm->vmcb->control.exit_info_1 &= ~1; | |
5bd2edc3 JR |
2701 | |
2702 | nested_svm_vmexit(svm); | |
2703 | } | |
2704 | ||
8a3c1a33 | 2705 | static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
4b16184c | 2706 | { |
ad896af0 PB |
2707 | WARN_ON(mmu_is_nested(vcpu)); |
2708 | kvm_init_shadow_mmu(vcpu); | |
4b16184c JR |
2709 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; |
2710 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
e4e517b4 | 2711 | vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr; |
4b16184c | 2712 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; |
855feb67 | 2713 | vcpu->arch.mmu.shadow_root_level = get_npt_level(vcpu); |
c258b62b | 2714 | reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu); |
4b16184c | 2715 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; |
4b16184c JR |
2716 | } |
2717 | ||
2718 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
2719 | { | |
2720 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
2721 | } | |
2722 | ||
c0725420 AG |
2723 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
2724 | { | |
e9196ceb DC |
2725 | if (!(svm->vcpu.arch.efer & EFER_SVME) || |
2726 | !is_paging(&svm->vcpu)) { | |
c0725420 AG |
2727 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
2728 | return 1; | |
2729 | } | |
2730 | ||
2731 | if (svm->vmcb->save.cpl) { | |
2732 | kvm_inject_gp(&svm->vcpu, 0); | |
2733 | return 1; | |
2734 | } | |
2735 | ||
e9196ceb | 2736 | return 0; |
c0725420 AG |
2737 | } |
2738 | ||
cf74a78b AG |
2739 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
2740 | bool has_error_code, u32 error_code) | |
2741 | { | |
b8e88bc8 JR |
2742 | int vmexit; |
2743 | ||
2030753d | 2744 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 2745 | return 0; |
cf74a78b | 2746 | |
adfe20fb WL |
2747 | vmexit = nested_svm_intercept(svm); |
2748 | if (vmexit != NESTED_EXIT_DONE) | |
2749 | return 0; | |
2750 | ||
0295ad7d JR |
2751 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
2752 | svm->vmcb->control.exit_code_hi = 0; | |
2753 | svm->vmcb->control.exit_info_1 = error_code; | |
b96fb439 PB |
2754 | |
2755 | /* | |
2756 | * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception. | |
2757 | * The fix is to add the ancillary datum (CR2 or DR6) to structs | |
2758 | * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be | |
2759 | * written only when inject_pending_event runs (DR6 would written here | |
2760 | * too). This should be conditional on a new capability---if the | |
2761 | * capability is disabled, kvm_multiple_exception would write the | |
2762 | * ancillary information to CR2 or DR6, for backwards ABI-compatibility. | |
2763 | */ | |
adfe20fb WL |
2764 | if (svm->vcpu.arch.exception.nested_apf) |
2765 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token; | |
2766 | else | |
2767 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
b8e88bc8 | 2768 | |
adfe20fb | 2769 | svm->nested.exit_required = true; |
b8e88bc8 | 2770 | return vmexit; |
cf74a78b AG |
2771 | } |
2772 | ||
8fe54654 JR |
2773 | /* This function returns true if it is save to enable the irq window */ |
2774 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 2775 | { |
2030753d | 2776 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 2777 | return true; |
cf74a78b | 2778 | |
26666957 | 2779 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 2780 | return true; |
cf74a78b | 2781 | |
26666957 | 2782 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 2783 | return false; |
cf74a78b | 2784 | |
a0a07cd2 GN |
2785 | /* |
2786 | * if vmexit was already requested (by intercepted exception | |
2787 | * for instance) do not overwrite it with "external interrupt" | |
2788 | * vmexit. | |
2789 | */ | |
2790 | if (svm->nested.exit_required) | |
2791 | return false; | |
2792 | ||
197717d5 JR |
2793 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
2794 | svm->vmcb->control.exit_info_1 = 0; | |
2795 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 2796 | |
cd3ff653 JR |
2797 | if (svm->nested.intercept & 1ULL) { |
2798 | /* | |
2799 | * The #vmexit can't be emulated here directly because this | |
c5ec2e56 | 2800 | * code path runs with irqs and preemption disabled. A |
cd3ff653 JR |
2801 | * #vmexit emulation might sleep. Only signal request for |
2802 | * the #vmexit here. | |
2803 | */ | |
2804 | svm->nested.exit_required = true; | |
236649de | 2805 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 2806 | return false; |
cf74a78b AG |
2807 | } |
2808 | ||
8fe54654 | 2809 | return true; |
cf74a78b AG |
2810 | } |
2811 | ||
887f500c JR |
2812 | /* This function returns true if it is save to enable the nmi window */ |
2813 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
2814 | { | |
2030753d | 2815 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
2816 | return true; |
2817 | ||
2818 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
2819 | return true; | |
2820 | ||
2821 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
2822 | svm->nested.exit_required = true; | |
2823 | ||
2824 | return false; | |
cf74a78b AG |
2825 | } |
2826 | ||
7597f129 | 2827 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
2828 | { |
2829 | struct page *page; | |
2830 | ||
6c3bd3d7 JR |
2831 | might_sleep(); |
2832 | ||
54bf36aa | 2833 | page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT); |
34f80cfa JR |
2834 | if (is_error_page(page)) |
2835 | goto error; | |
2836 | ||
7597f129 JR |
2837 | *_page = page; |
2838 | ||
2839 | return kmap(page); | |
34f80cfa JR |
2840 | |
2841 | error: | |
34f80cfa JR |
2842 | kvm_inject_gp(&svm->vcpu, 0); |
2843 | ||
2844 | return NULL; | |
2845 | } | |
2846 | ||
7597f129 | 2847 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 2848 | { |
7597f129 | 2849 | kunmap(page); |
34f80cfa JR |
2850 | kvm_release_page_dirty(page); |
2851 | } | |
34f80cfa | 2852 | |
ce2ac085 JR |
2853 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
2854 | { | |
9bf41833 JK |
2855 | unsigned port, size, iopm_len; |
2856 | u16 val, mask; | |
2857 | u8 start_bit; | |
ce2ac085 | 2858 | u64 gpa; |
34f80cfa | 2859 | |
ce2ac085 JR |
2860 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
2861 | return NESTED_EXIT_HOST; | |
34f80cfa | 2862 | |
ce2ac085 | 2863 | port = svm->vmcb->control.exit_info_1 >> 16; |
9bf41833 JK |
2864 | size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >> |
2865 | SVM_IOIO_SIZE_SHIFT; | |
ce2ac085 | 2866 | gpa = svm->nested.vmcb_iopm + (port / 8); |
9bf41833 JK |
2867 | start_bit = port % 8; |
2868 | iopm_len = (start_bit + size > 8) ? 2 : 1; | |
2869 | mask = (0xf >> (4 - size)) << start_bit; | |
2870 | val = 0; | |
ce2ac085 | 2871 | |
54bf36aa | 2872 | if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len)) |
9bf41833 | 2873 | return NESTED_EXIT_DONE; |
ce2ac085 | 2874 | |
9bf41833 | 2875 | return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
34f80cfa JR |
2876 | } |
2877 | ||
d2477826 | 2878 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 2879 | { |
0d6b3537 JR |
2880 | u32 offset, msr, value; |
2881 | int write, mask; | |
4c2161ae | 2882 | |
3d62d9aa | 2883 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 2884 | return NESTED_EXIT_HOST; |
3d62d9aa | 2885 | |
0d6b3537 JR |
2886 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
2887 | offset = svm_msrpm_offset(msr); | |
2888 | write = svm->vmcb->control.exit_info_1 & 1; | |
2889 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 2890 | |
0d6b3537 JR |
2891 | if (offset == MSR_INVALID) |
2892 | return NESTED_EXIT_DONE; | |
4c2161ae | 2893 | |
0d6b3537 JR |
2894 | /* Offset is in 32 bit units but need in 8 bit units */ |
2895 | offset *= 4; | |
4c2161ae | 2896 | |
54bf36aa | 2897 | if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4)) |
0d6b3537 | 2898 | return NESTED_EXIT_DONE; |
3d62d9aa | 2899 | |
0d6b3537 | 2900 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
2901 | } |
2902 | ||
ab2f4d73 LP |
2903 | /* DB exceptions for our internal use must not cause vmexit */ |
2904 | static int nested_svm_intercept_db(struct vcpu_svm *svm) | |
2905 | { | |
2906 | unsigned long dr6; | |
2907 | ||
2908 | /* if we're not singlestepping, it's not ours */ | |
2909 | if (!svm->nmi_singlestep) | |
2910 | return NESTED_EXIT_DONE; | |
2911 | ||
2912 | /* if it's not a singlestep exception, it's not ours */ | |
2913 | if (kvm_get_dr(&svm->vcpu, 6, &dr6)) | |
2914 | return NESTED_EXIT_DONE; | |
2915 | if (!(dr6 & DR6_BS)) | |
2916 | return NESTED_EXIT_DONE; | |
2917 | ||
2918 | /* if the guest is singlestepping, it should get the vmexit */ | |
2919 | if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) { | |
2920 | disable_nmi_singlestep(svm); | |
2921 | return NESTED_EXIT_DONE; | |
2922 | } | |
2923 | ||
2924 | /* it's ours, the nested hypervisor must not see this one */ | |
2925 | return NESTED_EXIT_HOST; | |
2926 | } | |
2927 | ||
410e4d57 | 2928 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 2929 | { |
cf74a78b | 2930 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 2931 | |
410e4d57 JR |
2932 | switch (exit_code) { |
2933 | case SVM_EXIT_INTR: | |
2934 | case SVM_EXIT_NMI: | |
ff47a49b | 2935 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 2936 | return NESTED_EXIT_HOST; |
410e4d57 | 2937 | case SVM_EXIT_NPF: |
e0231715 | 2938 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
2939 | if (npt_enabled) |
2940 | return NESTED_EXIT_HOST; | |
2941 | break; | |
410e4d57 | 2942 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 | 2943 | /* When we're shadowing, trap PFs, but not async PF */ |
1261bfa3 | 2944 | if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0) |
410e4d57 JR |
2945 | return NESTED_EXIT_HOST; |
2946 | break; | |
2947 | default: | |
2948 | break; | |
cf74a78b AG |
2949 | } |
2950 | ||
410e4d57 JR |
2951 | return NESTED_EXIT_CONTINUE; |
2952 | } | |
2953 | ||
2954 | /* | |
2955 | * If this function returns true, this #vmexit was already handled | |
2956 | */ | |
b8e88bc8 | 2957 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2958 | { |
2959 | u32 exit_code = svm->vmcb->control.exit_code; | |
2960 | int vmexit = NESTED_EXIT_HOST; | |
2961 | ||
cf74a78b | 2962 | switch (exit_code) { |
9c4e40b9 | 2963 | case SVM_EXIT_MSR: |
3d62d9aa | 2964 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2965 | break; |
ce2ac085 JR |
2966 | case SVM_EXIT_IOIO: |
2967 | vmexit = nested_svm_intercept_ioio(svm); | |
2968 | break; | |
4ee546b4 RJ |
2969 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2970 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2971 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2972 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2973 | break; |
2974 | } | |
3aed041a JR |
2975 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2976 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2977 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2978 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2979 | break; |
2980 | } | |
2981 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2982 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
ab2f4d73 LP |
2983 | if (svm->nested.intercept_exceptions & excp_bits) { |
2984 | if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR) | |
2985 | vmexit = nested_svm_intercept_db(svm); | |
2986 | else | |
2987 | vmexit = NESTED_EXIT_DONE; | |
2988 | } | |
631bc487 GN |
2989 | /* async page fault always cause vmexit */ |
2990 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
adfe20fb | 2991 | svm->vcpu.arch.exception.nested_apf != 0) |
631bc487 | 2992 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2993 | break; |
2994 | } | |
228070b1 JR |
2995 | case SVM_EXIT_ERR: { |
2996 | vmexit = NESTED_EXIT_DONE; | |
2997 | break; | |
2998 | } | |
cf74a78b AG |
2999 | default: { |
3000 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 3001 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 3002 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
3003 | } |
3004 | } | |
3005 | ||
b8e88bc8 JR |
3006 | return vmexit; |
3007 | } | |
3008 | ||
3009 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
3010 | { | |
3011 | int vmexit; | |
3012 | ||
3013 | vmexit = nested_svm_intercept(svm); | |
3014 | ||
3015 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 3016 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
3017 | |
3018 | return vmexit; | |
cf74a78b AG |
3019 | } |
3020 | ||
0460a979 JR |
3021 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
3022 | { | |
3023 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
3024 | struct vmcb_control_area *from = &from_vmcb->control; | |
3025 | ||
4ee546b4 | 3026 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 3027 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
3028 | dst->intercept_exceptions = from->intercept_exceptions; |
3029 | dst->intercept = from->intercept; | |
3030 | dst->iopm_base_pa = from->iopm_base_pa; | |
3031 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
3032 | dst->tsc_offset = from->tsc_offset; | |
3033 | dst->asid = from->asid; | |
3034 | dst->tlb_ctl = from->tlb_ctl; | |
3035 | dst->int_ctl = from->int_ctl; | |
3036 | dst->int_vector = from->int_vector; | |
3037 | dst->int_state = from->int_state; | |
3038 | dst->exit_code = from->exit_code; | |
3039 | dst->exit_code_hi = from->exit_code_hi; | |
3040 | dst->exit_info_1 = from->exit_info_1; | |
3041 | dst->exit_info_2 = from->exit_info_2; | |
3042 | dst->exit_int_info = from->exit_int_info; | |
3043 | dst->exit_int_info_err = from->exit_int_info_err; | |
3044 | dst->nested_ctl = from->nested_ctl; | |
3045 | dst->event_inj = from->event_inj; | |
3046 | dst->event_inj_err = from->event_inj_err; | |
3047 | dst->nested_cr3 = from->nested_cr3; | |
0dc92119 | 3048 | dst->virt_ext = from->virt_ext; |
0460a979 JR |
3049 | } |
3050 | ||
34f80cfa | 3051 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 3052 | { |
34f80cfa | 3053 | struct vmcb *nested_vmcb; |
e6aa9abd | 3054 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 3055 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 3056 | struct page *page; |
cf74a78b | 3057 | |
17897f36 JR |
3058 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
3059 | vmcb->control.exit_info_1, | |
3060 | vmcb->control.exit_info_2, | |
3061 | vmcb->control.exit_int_info, | |
e097e5ff SH |
3062 | vmcb->control.exit_int_info_err, |
3063 | KVM_ISA_SVM); | |
17897f36 | 3064 | |
7597f129 | 3065 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
3066 | if (!nested_vmcb) |
3067 | return 1; | |
3068 | ||
2030753d JR |
3069 | /* Exit Guest-Mode */ |
3070 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
3071 | svm->nested.vmcb = 0; |
3072 | ||
cf74a78b | 3073 | /* Give the current vmcb to the guest */ |
33740e40 JR |
3074 | disable_gif(svm); |
3075 | ||
3076 | nested_vmcb->save.es = vmcb->save.es; | |
3077 | nested_vmcb->save.cs = vmcb->save.cs; | |
3078 | nested_vmcb->save.ss = vmcb->save.ss; | |
3079 | nested_vmcb->save.ds = vmcb->save.ds; | |
3080 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
3081 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 3082 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 3083 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 3084 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 3085 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 3086 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 3087 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
3088 | nested_vmcb->save.rip = vmcb->save.rip; |
3089 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
3090 | nested_vmcb->save.rax = vmcb->save.rax; | |
3091 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
3092 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
3093 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
3094 | ||
3095 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
3096 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
3097 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
3098 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
3099 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
3100 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
3101 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
3102 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
3103 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
6092d3d3 JR |
3104 | |
3105 | if (svm->nrips_enabled) | |
3106 | nested_vmcb->control.next_rip = vmcb->control.next_rip; | |
8d23c466 AG |
3107 | |
3108 | /* | |
3109 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
3110 | * to make sure that we do not lose injected events. So check event_inj | |
3111 | * here and copy it to exit_int_info if it is valid. | |
3112 | * Exit_int_info and event_inj can't be both valid because the case | |
3113 | * below only happens on a VMRUN instruction intercept which has | |
3114 | * no valid exit_int_info set. | |
3115 | */ | |
3116 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
3117 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
3118 | ||
3119 | nc->exit_int_info = vmcb->control.event_inj; | |
3120 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
3121 | } | |
3122 | ||
33740e40 JR |
3123 | nested_vmcb->control.tlb_ctl = 0; |
3124 | nested_vmcb->control.event_inj = 0; | |
3125 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
3126 | |
3127 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
3128 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
3129 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
3130 | ||
cf74a78b | 3131 | /* Restore the original control entries */ |
0460a979 | 3132 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 3133 | |
219b65dc AG |
3134 | kvm_clear_exception_queue(&svm->vcpu); |
3135 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 3136 | |
4b16184c JR |
3137 | svm->nested.nested_cr3 = 0; |
3138 | ||
cf74a78b AG |
3139 | /* Restore selected save entries */ |
3140 | svm->vmcb->save.es = hsave->save.es; | |
3141 | svm->vmcb->save.cs = hsave->save.cs; | |
3142 | svm->vmcb->save.ss = hsave->save.ss; | |
3143 | svm->vmcb->save.ds = hsave->save.ds; | |
3144 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
3145 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 3146 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
3147 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
3148 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
3149 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
3150 | if (npt_enabled) { | |
3151 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
3152 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
3153 | } else { | |
2390218b | 3154 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
3155 | } |
3156 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
3157 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
3158 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
3159 | svm->vmcb->save.dr7 = 0; | |
3160 | svm->vmcb->save.cpl = 0; | |
3161 | svm->vmcb->control.exit_int_info = 0; | |
3162 | ||
8d28fec4 RJ |
3163 | mark_all_dirty(svm->vmcb); |
3164 | ||
7597f129 | 3165 | nested_svm_unmap(page); |
cf74a78b | 3166 | |
4b16184c | 3167 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
3168 | kvm_mmu_reset_context(&svm->vcpu); |
3169 | kvm_mmu_load(&svm->vcpu); | |
3170 | ||
3171 | return 0; | |
3172 | } | |
3d6368ef | 3173 | |
9738b2c9 | 3174 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 3175 | { |
323c3d80 JR |
3176 | /* |
3177 | * This function merges the msr permission bitmaps of kvm and the | |
c5ec2e56 | 3178 | * nested vmcb. It is optimized in that it only merges the parts where |
323c3d80 JR |
3179 | * the kvm msr permission bitmap may contain zero bits |
3180 | */ | |
3d6368ef | 3181 | int i; |
9738b2c9 | 3182 | |
323c3d80 JR |
3183 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
3184 | return true; | |
9738b2c9 | 3185 | |
323c3d80 JR |
3186 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
3187 | u32 value, p; | |
3188 | u64 offset; | |
9738b2c9 | 3189 | |
323c3d80 JR |
3190 | if (msrpm_offsets[i] == 0xffffffff) |
3191 | break; | |
3d6368ef | 3192 | |
0d6b3537 JR |
3193 | p = msrpm_offsets[i]; |
3194 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 | 3195 | |
54bf36aa | 3196 | if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4)) |
323c3d80 JR |
3197 | return false; |
3198 | ||
3199 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
3200 | } | |
3d6368ef | 3201 | |
d0ec49d4 | 3202 | svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm)); |
9738b2c9 JR |
3203 | |
3204 | return true; | |
3d6368ef AG |
3205 | } |
3206 | ||
52c65a30 JR |
3207 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
3208 | { | |
3209 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
3210 | return false; | |
3211 | ||
dbe77584 JR |
3212 | if (vmcb->control.asid == 0) |
3213 | return false; | |
3214 | ||
cea3a19b TL |
3215 | if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) && |
3216 | !npt_enabled) | |
4b16184c JR |
3217 | return false; |
3218 | ||
52c65a30 JR |
3219 | return true; |
3220 | } | |
3221 | ||
c2634065 LP |
3222 | static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa, |
3223 | struct vmcb *nested_vmcb, struct page *page) | |
3d6368ef | 3224 | { |
f6e78475 | 3225 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
3226 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
3227 | else | |
3228 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
3229 | ||
cea3a19b | 3230 | if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) { |
4b16184c JR |
3231 | kvm_mmu_unload(&svm->vcpu); |
3232 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
3233 | nested_svm_init_mmu_context(&svm->vcpu); | |
3234 | } | |
3235 | ||
3d6368ef AG |
3236 | /* Load the nested guest state */ |
3237 | svm->vmcb->save.es = nested_vmcb->save.es; | |
3238 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
3239 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
3240 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
3241 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
3242 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 3243 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
3244 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
3245 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
3246 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
3247 | if (npt_enabled) { | |
3248 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
3249 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 3250 | } else |
2390218b | 3251 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
3252 | |
3253 | /* Guest paging mode is active - reset mmu */ | |
3254 | kvm_mmu_reset_context(&svm->vcpu); | |
3255 | ||
defbba56 | 3256 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
3257 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
3258 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
3259 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 3260 | |
3d6368ef AG |
3261 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
3262 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
3263 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
3264 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
3265 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
3266 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
3267 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
3268 | ||
f7138538 | 3269 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 3270 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 3271 | |
aad42c64 | 3272 | /* cache intercepts */ |
4ee546b4 | 3273 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 3274 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
3275 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
3276 | svm->nested.intercept = nested_vmcb->control.intercept; | |
3277 | ||
f40f6a45 | 3278 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 3279 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
3280 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
3281 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
3282 | else | |
3283 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
3284 | ||
88ab24ad JR |
3285 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
3286 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
3287 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
3288 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
3289 | } |
3290 | ||
0d945bd9 | 3291 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 3292 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 3293 | |
0dc92119 | 3294 | svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext; |
3d6368ef AG |
3295 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
3296 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
3297 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
3298 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
3299 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
3300 | ||
7597f129 | 3301 | nested_svm_unmap(page); |
9738b2c9 | 3302 | |
2030753d JR |
3303 | /* Enter Guest-Mode */ |
3304 | enter_guest_mode(&svm->vcpu); | |
3305 | ||
384c6368 JR |
3306 | /* |
3307 | * Merge guest and host intercepts - must be called with vcpu in | |
3308 | * guest-mode to take affect here | |
3309 | */ | |
3310 | recalc_intercepts(svm); | |
3311 | ||
06fc7772 | 3312 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 3313 | |
2af9194d | 3314 | enable_gif(svm); |
3d6368ef | 3315 | |
8d28fec4 | 3316 | mark_all_dirty(svm->vmcb); |
c2634065 LP |
3317 | } |
3318 | ||
3319 | static bool nested_svm_vmrun(struct vcpu_svm *svm) | |
3320 | { | |
3321 | struct vmcb *nested_vmcb; | |
3322 | struct vmcb *hsave = svm->nested.hsave; | |
3323 | struct vmcb *vmcb = svm->vmcb; | |
3324 | struct page *page; | |
3325 | u64 vmcb_gpa; | |
3326 | ||
3327 | vmcb_gpa = svm->vmcb->save.rax; | |
3328 | ||
3329 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); | |
3330 | if (!nested_vmcb) | |
3331 | return false; | |
3332 | ||
3333 | if (!nested_vmcb_checks(nested_vmcb)) { | |
3334 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
3335 | nested_vmcb->control.exit_code_hi = 0; | |
3336 | nested_vmcb->control.exit_info_1 = 0; | |
3337 | nested_vmcb->control.exit_info_2 = 0; | |
3338 | ||
3339 | nested_svm_unmap(page); | |
3340 | ||
3341 | return false; | |
3342 | } | |
3343 | ||
3344 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, | |
3345 | nested_vmcb->save.rip, | |
3346 | nested_vmcb->control.int_ctl, | |
3347 | nested_vmcb->control.event_inj, | |
3348 | nested_vmcb->control.nested_ctl); | |
3349 | ||
3350 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, | |
3351 | nested_vmcb->control.intercept_cr >> 16, | |
3352 | nested_vmcb->control.intercept_exceptions, | |
3353 | nested_vmcb->control.intercept); | |
3354 | ||
3355 | /* Clear internal status */ | |
3356 | kvm_clear_exception_queue(&svm->vcpu); | |
3357 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3358 | ||
3359 | /* | |
3360 | * Save the old vmcb, so we don't need to pick what we save, but can | |
3361 | * restore everything when a VMEXIT occurs | |
3362 | */ | |
3363 | hsave->save.es = vmcb->save.es; | |
3364 | hsave->save.cs = vmcb->save.cs; | |
3365 | hsave->save.ss = vmcb->save.ss; | |
3366 | hsave->save.ds = vmcb->save.ds; | |
3367 | hsave->save.gdtr = vmcb->save.gdtr; | |
3368 | hsave->save.idtr = vmcb->save.idtr; | |
3369 | hsave->save.efer = svm->vcpu.arch.efer; | |
3370 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); | |
3371 | hsave->save.cr4 = svm->vcpu.arch.cr4; | |
3372 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); | |
3373 | hsave->save.rip = kvm_rip_read(&svm->vcpu); | |
3374 | hsave->save.rsp = vmcb->save.rsp; | |
3375 | hsave->save.rax = vmcb->save.rax; | |
3376 | if (npt_enabled) | |
3377 | hsave->save.cr3 = vmcb->save.cr3; | |
3378 | else | |
3379 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); | |
3380 | ||
3381 | copy_vmcb_control_area(hsave, vmcb); | |
3382 | ||
3383 | enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page); | |
8d28fec4 | 3384 | |
9738b2c9 | 3385 | return true; |
3d6368ef AG |
3386 | } |
3387 | ||
9966bf68 | 3388 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
3389 | { |
3390 | to_vmcb->save.fs = from_vmcb->save.fs; | |
3391 | to_vmcb->save.gs = from_vmcb->save.gs; | |
3392 | to_vmcb->save.tr = from_vmcb->save.tr; | |
3393 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
3394 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
3395 | to_vmcb->save.star = from_vmcb->save.star; | |
3396 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
3397 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
3398 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
3399 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
3400 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
3401 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
3402 | } |
3403 | ||
851ba692 | 3404 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 3405 | { |
9966bf68 | 3406 | struct vmcb *nested_vmcb; |
7597f129 | 3407 | struct page *page; |
b742c1e6 | 3408 | int ret; |
9966bf68 | 3409 | |
5542675b AG |
3410 | if (nested_svm_check_permissions(svm)) |
3411 | return 1; | |
3412 | ||
7597f129 | 3413 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
3414 | if (!nested_vmcb) |
3415 | return 1; | |
3416 | ||
e3e9ed3d | 3417 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
b742c1e6 | 3418 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
e3e9ed3d | 3419 | |
9966bf68 | 3420 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); |
7597f129 | 3421 | nested_svm_unmap(page); |
5542675b | 3422 | |
b742c1e6 | 3423 | return ret; |
5542675b AG |
3424 | } |
3425 | ||
851ba692 | 3426 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 3427 | { |
9966bf68 | 3428 | struct vmcb *nested_vmcb; |
7597f129 | 3429 | struct page *page; |
b742c1e6 | 3430 | int ret; |
9966bf68 | 3431 | |
5542675b AG |
3432 | if (nested_svm_check_permissions(svm)) |
3433 | return 1; | |
3434 | ||
7597f129 | 3435 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
3436 | if (!nested_vmcb) |
3437 | return 1; | |
3438 | ||
e3e9ed3d | 3439 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
b742c1e6 | 3440 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
e3e9ed3d | 3441 | |
9966bf68 | 3442 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); |
7597f129 | 3443 | nested_svm_unmap(page); |
5542675b | 3444 | |
b742c1e6 | 3445 | return ret; |
5542675b AG |
3446 | } |
3447 | ||
851ba692 | 3448 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 3449 | { |
3d6368ef AG |
3450 | if (nested_svm_check_permissions(svm)) |
3451 | return 1; | |
3452 | ||
b75f4eb3 RJ |
3453 | /* Save rip after vmrun instruction */ |
3454 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 3455 | |
9738b2c9 | 3456 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
3457 | return 1; |
3458 | ||
9738b2c9 | 3459 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
3460 | goto failed; |
3461 | ||
3462 | return 1; | |
3463 | ||
3464 | failed: | |
3465 | ||
3466 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
3467 | svm->vmcb->control.exit_code_hi = 0; | |
3468 | svm->vmcb->control.exit_info_1 = 0; | |
3469 | svm->vmcb->control.exit_info_2 = 0; | |
3470 | ||
3471 | nested_svm_vmexit(svm); | |
3d6368ef AG |
3472 | |
3473 | return 1; | |
3474 | } | |
3475 | ||
851ba692 | 3476 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 | 3477 | { |
b742c1e6 LP |
3478 | int ret; |
3479 | ||
1371d904 AG |
3480 | if (nested_svm_check_permissions(svm)) |
3481 | return 1; | |
3482 | ||
640bd6e5 JN |
3483 | /* |
3484 | * If VGIF is enabled, the STGI intercept is only added to | |
cc3d967f | 3485 | * detect the opening of the SMI/NMI window; remove it now. |
640bd6e5 JN |
3486 | */ |
3487 | if (vgif_enabled(svm)) | |
3488 | clr_intercept(svm, INTERCEPT_STGI); | |
3489 | ||
1371d904 | 3490 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
b742c1e6 | 3491 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
3842d135 | 3492 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 3493 | |
2af9194d | 3494 | enable_gif(svm); |
1371d904 | 3495 | |
b742c1e6 | 3496 | return ret; |
1371d904 AG |
3497 | } |
3498 | ||
851ba692 | 3499 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 | 3500 | { |
b742c1e6 LP |
3501 | int ret; |
3502 | ||
1371d904 AG |
3503 | if (nested_svm_check_permissions(svm)) |
3504 | return 1; | |
3505 | ||
3506 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
b742c1e6 | 3507 | ret = kvm_skip_emulated_instruction(&svm->vcpu); |
1371d904 | 3508 | |
2af9194d | 3509 | disable_gif(svm); |
1371d904 AG |
3510 | |
3511 | /* After a CLGI no interrupts should come */ | |
340d3bc3 SS |
3512 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) { |
3513 | svm_clear_vintr(svm); | |
3514 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
3515 | mark_dirty(svm->vmcb, VMCB_INTR); | |
3516 | } | |
decdbf6a | 3517 | |
b742c1e6 | 3518 | return ret; |
1371d904 AG |
3519 | } |
3520 | ||
851ba692 | 3521 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
3522 | { |
3523 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 3524 | |
668f198f DK |
3525 | trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX), |
3526 | kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); | |
ec1ff790 | 3527 | |
ff092385 | 3528 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
668f198f | 3529 | kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
ff092385 AG |
3530 | |
3531 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
b742c1e6 | 3532 | return kvm_skip_emulated_instruction(&svm->vcpu); |
ff092385 AG |
3533 | } |
3534 | ||
532a46b9 JR |
3535 | static int skinit_interception(struct vcpu_svm *svm) |
3536 | { | |
668f198f | 3537 | trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX)); |
532a46b9 JR |
3538 | |
3539 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3540 | return 1; | |
3541 | } | |
3542 | ||
dab429a7 DK |
3543 | static int wbinvd_interception(struct vcpu_svm *svm) |
3544 | { | |
6affcbed | 3545 | return kvm_emulate_wbinvd(&svm->vcpu); |
dab429a7 DK |
3546 | } |
3547 | ||
81dd35d4 JR |
3548 | static int xsetbv_interception(struct vcpu_svm *svm) |
3549 | { | |
3550 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
3551 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
3552 | ||
3553 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
3554 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
b742c1e6 | 3555 | return kvm_skip_emulated_instruction(&svm->vcpu); |
81dd35d4 JR |
3556 | } |
3557 | ||
3558 | return 1; | |
3559 | } | |
3560 | ||
851ba692 | 3561 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 3562 | { |
37817f29 | 3563 | u16 tss_selector; |
64a7ec06 GN |
3564 | int reason; |
3565 | int int_type = svm->vmcb->control.exit_int_info & | |
3566 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 3567 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
3568 | uint32_t type = |
3569 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
3570 | uint32_t idt_v = | |
3571 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
3572 | bool has_error_code = false; |
3573 | u32 error_code = 0; | |
37817f29 IE |
3574 | |
3575 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 3576 | |
37817f29 IE |
3577 | if (svm->vmcb->control.exit_info_2 & |
3578 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
3579 | reason = TASK_SWITCH_IRET; |
3580 | else if (svm->vmcb->control.exit_info_2 & | |
3581 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
3582 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 3583 | else if (idt_v) |
64a7ec06 GN |
3584 | reason = TASK_SWITCH_GATE; |
3585 | else | |
3586 | reason = TASK_SWITCH_CALL; | |
3587 | ||
fe8e7f83 GN |
3588 | if (reason == TASK_SWITCH_GATE) { |
3589 | switch (type) { | |
3590 | case SVM_EXITINTINFO_TYPE_NMI: | |
3591 | svm->vcpu.arch.nmi_injected = false; | |
3592 | break; | |
3593 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
3594 | if (svm->vmcb->control.exit_info_2 & |
3595 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
3596 | has_error_code = true; | |
3597 | error_code = | |
3598 | (u32)svm->vmcb->control.exit_info_2; | |
3599 | } | |
fe8e7f83 GN |
3600 | kvm_clear_exception_queue(&svm->vcpu); |
3601 | break; | |
3602 | case SVM_EXITINTINFO_TYPE_INTR: | |
3603 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3604 | break; | |
3605 | default: | |
3606 | break; | |
3607 | } | |
3608 | } | |
64a7ec06 | 3609 | |
8317c298 GN |
3610 | if (reason != TASK_SWITCH_GATE || |
3611 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
3612 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
3613 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
3614 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 3615 | |
7f3d35fd KW |
3616 | if (int_type != SVM_EXITINTINFO_TYPE_SOFT) |
3617 | int_vec = -1; | |
3618 | ||
3619 | if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason, | |
acb54517 GN |
3620 | has_error_code, error_code) == EMULATE_FAIL) { |
3621 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
3622 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
3623 | svm->vcpu.run->internal.ndata = 0; | |
3624 | return 0; | |
3625 | } | |
3626 | return 1; | |
6aa8b732 AK |
3627 | } |
3628 | ||
851ba692 | 3629 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 3630 | { |
5fdbf976 | 3631 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
6a908b62 | 3632 | return kvm_emulate_cpuid(&svm->vcpu); |
6aa8b732 AK |
3633 | } |
3634 | ||
851ba692 | 3635 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
3636 | { |
3637 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 3638 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 3639 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 3640 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
f303b4ce | 3641 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
95ba8273 GN |
3642 | return 1; |
3643 | } | |
3644 | ||
851ba692 | 3645 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 3646 | { |
df4f3108 AP |
3647 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
3648 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
3649 | ||
3650 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
b742c1e6 | 3651 | return kvm_skip_emulated_instruction(&svm->vcpu); |
a7052897 MT |
3652 | } |
3653 | ||
851ba692 | 3654 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 3655 | { |
51d8b661 | 3656 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
3657 | } |
3658 | ||
332b56e4 AK |
3659 | static int rdpmc_interception(struct vcpu_svm *svm) |
3660 | { | |
3661 | int err; | |
3662 | ||
3663 | if (!static_cpu_has(X86_FEATURE_NRIPS)) | |
3664 | return emulate_on_interception(svm); | |
3665 | ||
3666 | err = kvm_rdpmc(&svm->vcpu); | |
6affcbed | 3667 | return kvm_complete_insn_gp(&svm->vcpu, err); |
332b56e4 AK |
3668 | } |
3669 | ||
52eb5a6d XL |
3670 | static bool check_selective_cr0_intercepted(struct vcpu_svm *svm, |
3671 | unsigned long val) | |
628afd2a JR |
3672 | { |
3673 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
3674 | bool ret = false; | |
3675 | u64 intercept; | |
3676 | ||
3677 | intercept = svm->nested.intercept; | |
3678 | ||
3679 | if (!is_guest_mode(&svm->vcpu) || | |
3680 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
3681 | return false; | |
3682 | ||
3683 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
3684 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
3685 | ||
3686 | if (cr0 ^ val) { | |
3687 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
3688 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
3689 | } | |
3690 | ||
3691 | return ret; | |
3692 | } | |
3693 | ||
7ff76d58 AP |
3694 | #define CR_VALID (1ULL << 63) |
3695 | ||
3696 | static int cr_interception(struct vcpu_svm *svm) | |
3697 | { | |
3698 | int reg, cr; | |
3699 | unsigned long val; | |
3700 | int err; | |
3701 | ||
3702 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
3703 | return emulate_on_interception(svm); | |
3704 | ||
3705 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
3706 | return emulate_on_interception(svm); | |
3707 | ||
3708 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
5e57518d DK |
3709 | if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE) |
3710 | cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0; | |
3711 | else | |
3712 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
7ff76d58 AP |
3713 | |
3714 | err = 0; | |
3715 | if (cr >= 16) { /* mov to cr */ | |
3716 | cr -= 16; | |
3717 | val = kvm_register_read(&svm->vcpu, reg); | |
3718 | switch (cr) { | |
3719 | case 0: | |
628afd2a JR |
3720 | if (!check_selective_cr0_intercepted(svm, val)) |
3721 | err = kvm_set_cr0(&svm->vcpu, val); | |
977b2d03 JR |
3722 | else |
3723 | return 1; | |
3724 | ||
7ff76d58 AP |
3725 | break; |
3726 | case 3: | |
3727 | err = kvm_set_cr3(&svm->vcpu, val); | |
3728 | break; | |
3729 | case 4: | |
3730 | err = kvm_set_cr4(&svm->vcpu, val); | |
3731 | break; | |
3732 | case 8: | |
3733 | err = kvm_set_cr8(&svm->vcpu, val); | |
3734 | break; | |
3735 | default: | |
3736 | WARN(1, "unhandled write to CR%d", cr); | |
3737 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3738 | return 1; | |
3739 | } | |
3740 | } else { /* mov from cr */ | |
3741 | switch (cr) { | |
3742 | case 0: | |
3743 | val = kvm_read_cr0(&svm->vcpu); | |
3744 | break; | |
3745 | case 2: | |
3746 | val = svm->vcpu.arch.cr2; | |
3747 | break; | |
3748 | case 3: | |
9f8fe504 | 3749 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
3750 | break; |
3751 | case 4: | |
3752 | val = kvm_read_cr4(&svm->vcpu); | |
3753 | break; | |
3754 | case 8: | |
3755 | val = kvm_get_cr8(&svm->vcpu); | |
3756 | break; | |
3757 | default: | |
3758 | WARN(1, "unhandled read from CR%d", cr); | |
3759 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
3760 | return 1; | |
3761 | } | |
3762 | kvm_register_write(&svm->vcpu, reg, val); | |
3763 | } | |
6affcbed | 3764 | return kvm_complete_insn_gp(&svm->vcpu, err); |
7ff76d58 AP |
3765 | } |
3766 | ||
cae3797a AP |
3767 | static int dr_interception(struct vcpu_svm *svm) |
3768 | { | |
3769 | int reg, dr; | |
3770 | unsigned long val; | |
cae3797a | 3771 | |
facb0139 PB |
3772 | if (svm->vcpu.guest_debug == 0) { |
3773 | /* | |
3774 | * No more DR vmexits; force a reload of the debug registers | |
3775 | * and reenter on this instruction. The next vmexit will | |
3776 | * retrieve the full state of the debug registers. | |
3777 | */ | |
3778 | clr_dr_intercepts(svm); | |
3779 | svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
3780 | return 1; | |
3781 | } | |
3782 | ||
cae3797a AP |
3783 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) |
3784 | return emulate_on_interception(svm); | |
3785 | ||
3786 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
3787 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
3788 | ||
3789 | if (dr >= 16) { /* mov to DRn */ | |
16f8a6f9 NA |
3790 | if (!kvm_require_dr(&svm->vcpu, dr - 16)) |
3791 | return 1; | |
cae3797a AP |
3792 | val = kvm_register_read(&svm->vcpu, reg); |
3793 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
3794 | } else { | |
16f8a6f9 NA |
3795 | if (!kvm_require_dr(&svm->vcpu, dr)) |
3796 | return 1; | |
3797 | kvm_get_dr(&svm->vcpu, dr, &val); | |
3798 | kvm_register_write(&svm->vcpu, reg, val); | |
cae3797a AP |
3799 | } |
3800 | ||
b742c1e6 | 3801 | return kvm_skip_emulated_instruction(&svm->vcpu); |
cae3797a AP |
3802 | } |
3803 | ||
851ba692 | 3804 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 3805 | { |
851ba692 | 3806 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 3807 | int r; |
851ba692 | 3808 | |
0a5fff19 GN |
3809 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
3810 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 3811 | r = cr_interception(svm); |
35754c98 | 3812 | if (lapic_in_kernel(&svm->vcpu)) |
7ff76d58 | 3813 | return r; |
0a5fff19 | 3814 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 3815 | return r; |
1d075434 JR |
3816 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
3817 | return 0; | |
3818 | } | |
3819 | ||
609e36d3 | 3820 | static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3821 | { |
a2fa3e9f GH |
3822 | struct vcpu_svm *svm = to_svm(vcpu); |
3823 | ||
609e36d3 | 3824 | switch (msr_info->index) { |
af24a4e4 | 3825 | case MSR_IA32_TSC: { |
609e36d3 | 3826 | msr_info->data = svm->vmcb->control.tsc_offset + |
35181e86 | 3827 | kvm_scale_tsc(vcpu, rdtsc()); |
fbc0db76 | 3828 | |
6aa8b732 AK |
3829 | break; |
3830 | } | |
8c06585d | 3831 | case MSR_STAR: |
609e36d3 | 3832 | msr_info->data = svm->vmcb->save.star; |
6aa8b732 | 3833 | break; |
0e859cac | 3834 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3835 | case MSR_LSTAR: |
609e36d3 | 3836 | msr_info->data = svm->vmcb->save.lstar; |
6aa8b732 AK |
3837 | break; |
3838 | case MSR_CSTAR: | |
609e36d3 | 3839 | msr_info->data = svm->vmcb->save.cstar; |
6aa8b732 AK |
3840 | break; |
3841 | case MSR_KERNEL_GS_BASE: | |
609e36d3 | 3842 | msr_info->data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
3843 | break; |
3844 | case MSR_SYSCALL_MASK: | |
609e36d3 | 3845 | msr_info->data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
3846 | break; |
3847 | #endif | |
3848 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 3849 | msr_info->data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
3850 | break; |
3851 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3852 | msr_info->data = svm->sysenter_eip; |
6aa8b732 AK |
3853 | break; |
3854 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3855 | msr_info->data = svm->sysenter_esp; |
6aa8b732 | 3856 | break; |
46896c73 PB |
3857 | case MSR_TSC_AUX: |
3858 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
3859 | return 1; | |
3860 | msr_info->data = svm->tsc_aux; | |
3861 | break; | |
e0231715 JR |
3862 | /* |
3863 | * Nobody will change the following 5 values in the VMCB so we can | |
3864 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
3865 | * implemented. | |
3866 | */ | |
a2938c80 | 3867 | case MSR_IA32_DEBUGCTLMSR: |
609e36d3 | 3868 | msr_info->data = svm->vmcb->save.dbgctl; |
a2938c80 JR |
3869 | break; |
3870 | case MSR_IA32_LASTBRANCHFROMIP: | |
609e36d3 | 3871 | msr_info->data = svm->vmcb->save.br_from; |
a2938c80 JR |
3872 | break; |
3873 | case MSR_IA32_LASTBRANCHTOIP: | |
609e36d3 | 3874 | msr_info->data = svm->vmcb->save.br_to; |
a2938c80 JR |
3875 | break; |
3876 | case MSR_IA32_LASTINTFROMIP: | |
609e36d3 | 3877 | msr_info->data = svm->vmcb->save.last_excp_from; |
a2938c80 JR |
3878 | break; |
3879 | case MSR_IA32_LASTINTTOIP: | |
609e36d3 | 3880 | msr_info->data = svm->vmcb->save.last_excp_to; |
a2938c80 | 3881 | break; |
b286d5d8 | 3882 | case MSR_VM_HSAVE_PA: |
609e36d3 | 3883 | msr_info->data = svm->nested.hsave_msr; |
b286d5d8 | 3884 | break; |
eb6f302e | 3885 | case MSR_VM_CR: |
609e36d3 | 3886 | msr_info->data = svm->nested.vm_cr_msr; |
eb6f302e | 3887 | break; |
c8a73f18 | 3888 | case MSR_IA32_UCODE_REV: |
609e36d3 | 3889 | msr_info->data = 0x01000065; |
c8a73f18 | 3890 | break; |
ae8b7875 BP |
3891 | case MSR_F15H_IC_CFG: { |
3892 | ||
3893 | int family, model; | |
3894 | ||
3895 | family = guest_cpuid_family(vcpu); | |
3896 | model = guest_cpuid_model(vcpu); | |
3897 | ||
3898 | if (family < 0 || model < 0) | |
3899 | return kvm_get_msr_common(vcpu, msr_info); | |
3900 | ||
3901 | msr_info->data = 0; | |
3902 | ||
3903 | if (family == 0x15 && | |
3904 | (model >= 0x2 && model < 0x20)) | |
3905 | msr_info->data = 0x1E; | |
3906 | } | |
3907 | break; | |
6aa8b732 | 3908 | default: |
609e36d3 | 3909 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3910 | } |
3911 | return 0; | |
3912 | } | |
3913 | ||
851ba692 | 3914 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3915 | { |
668f198f | 3916 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
609e36d3 | 3917 | struct msr_data msr_info; |
6aa8b732 | 3918 | |
609e36d3 PB |
3919 | msr_info.index = ecx; |
3920 | msr_info.host_initiated = false; | |
3921 | if (svm_get_msr(&svm->vcpu, &msr_info)) { | |
59200273 | 3922 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 3923 | kvm_inject_gp(&svm->vcpu, 0); |
b742c1e6 | 3924 | return 1; |
59200273 | 3925 | } else { |
609e36d3 | 3926 | trace_kvm_msr_read(ecx, msr_info.data); |
af9ca2d7 | 3927 | |
609e36d3 PB |
3928 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, |
3929 | msr_info.data & 0xffffffff); | |
3930 | kvm_register_write(&svm->vcpu, VCPU_REGS_RDX, | |
3931 | msr_info.data >> 32); | |
5fdbf976 | 3932 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
b742c1e6 | 3933 | return kvm_skip_emulated_instruction(&svm->vcpu); |
6aa8b732 | 3934 | } |
6aa8b732 AK |
3935 | } |
3936 | ||
4a810181 JR |
3937 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
3938 | { | |
3939 | struct vcpu_svm *svm = to_svm(vcpu); | |
3940 | int svm_dis, chg_mask; | |
3941 | ||
3942 | if (data & ~SVM_VM_CR_VALID_MASK) | |
3943 | return 1; | |
3944 | ||
3945 | chg_mask = SVM_VM_CR_VALID_MASK; | |
3946 | ||
3947 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
3948 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
3949 | ||
3950 | svm->nested.vm_cr_msr &= ~chg_mask; | |
3951 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
3952 | ||
3953 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
3954 | ||
3955 | /* check for svm_disable while efer.svme is set */ | |
3956 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
3957 | return 1; | |
3958 | ||
3959 | return 0; | |
3960 | } | |
3961 | ||
8fe8ab46 | 3962 | static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
6aa8b732 | 3963 | { |
a2fa3e9f GH |
3964 | struct vcpu_svm *svm = to_svm(vcpu); |
3965 | ||
8fe8ab46 WA |
3966 | u32 ecx = msr->index; |
3967 | u64 data = msr->data; | |
6aa8b732 | 3968 | switch (ecx) { |
15038e14 PB |
3969 | case MSR_IA32_CR_PAT: |
3970 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) | |
3971 | return 1; | |
3972 | vcpu->arch.pat = data; | |
3973 | svm->vmcb->save.g_pat = data; | |
3974 | mark_dirty(svm->vmcb, VMCB_NPT); | |
3975 | break; | |
f4e1b3c8 | 3976 | case MSR_IA32_TSC: |
8fe8ab46 | 3977 | kvm_write_tsc(vcpu, msr); |
6aa8b732 | 3978 | break; |
8c06585d | 3979 | case MSR_STAR: |
a2fa3e9f | 3980 | svm->vmcb->save.star = data; |
6aa8b732 | 3981 | break; |
49b14f24 | 3982 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3983 | case MSR_LSTAR: |
a2fa3e9f | 3984 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
3985 | break; |
3986 | case MSR_CSTAR: | |
a2fa3e9f | 3987 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
3988 | break; |
3989 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3990 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
3991 | break; |
3992 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3993 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
3994 | break; |
3995 | #endif | |
3996 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3997 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
3998 | break; |
3999 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 4000 | svm->sysenter_eip = data; |
a2fa3e9f | 4001 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
4002 | break; |
4003 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 4004 | svm->sysenter_esp = data; |
a2fa3e9f | 4005 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 4006 | break; |
46896c73 PB |
4007 | case MSR_TSC_AUX: |
4008 | if (!boot_cpu_has(X86_FEATURE_RDTSCP)) | |
4009 | return 1; | |
4010 | ||
4011 | /* | |
4012 | * This is rare, so we update the MSR here instead of using | |
4013 | * direct_access_msrs. Doing that would require a rdmsr in | |
4014 | * svm_vcpu_put. | |
4015 | */ | |
4016 | svm->tsc_aux = data; | |
4017 | wrmsrl(MSR_TSC_AUX, svm->tsc_aux); | |
4018 | break; | |
a2938c80 | 4019 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 4020 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
a737f256 CD |
4021 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
4022 | __func__, data); | |
24e09cbf JR |
4023 | break; |
4024 | } | |
4025 | if (data & DEBUGCTL_RESERVED_BITS) | |
4026 | return 1; | |
4027 | ||
4028 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 4029 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
4030 | if (data & (1ULL<<0)) |
4031 | svm_enable_lbrv(svm); | |
4032 | else | |
4033 | svm_disable_lbrv(svm); | |
a2938c80 | 4034 | break; |
b286d5d8 | 4035 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 4036 | svm->nested.hsave_msr = data; |
62b9abaa | 4037 | break; |
3c5d0a44 | 4038 | case MSR_VM_CR: |
4a810181 | 4039 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 4040 | case MSR_VM_IGNNE: |
a737f256 | 4041 | vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3c5d0a44 | 4042 | break; |
44a95dae SS |
4043 | case MSR_IA32_APICBASE: |
4044 | if (kvm_vcpu_apicv_active(vcpu)) | |
4045 | avic_update_vapic_bar(to_svm(vcpu), data); | |
4046 | /* Follow through */ | |
6aa8b732 | 4047 | default: |
8fe8ab46 | 4048 | return kvm_set_msr_common(vcpu, msr); |
6aa8b732 AK |
4049 | } |
4050 | return 0; | |
4051 | } | |
4052 | ||
851ba692 | 4053 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 4054 | { |
8fe8ab46 | 4055 | struct msr_data msr; |
668f198f DK |
4056 | u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); |
4057 | u64 data = kvm_read_edx_eax(&svm->vcpu); | |
af9ca2d7 | 4058 | |
8fe8ab46 WA |
4059 | msr.data = data; |
4060 | msr.index = ecx; | |
4061 | msr.host_initiated = false; | |
af9ca2d7 | 4062 | |
5fdbf976 | 4063 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
854e8bb1 | 4064 | if (kvm_set_msr(&svm->vcpu, &msr)) { |
59200273 | 4065 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 4066 | kvm_inject_gp(&svm->vcpu, 0); |
b742c1e6 | 4067 | return 1; |
59200273 AK |
4068 | } else { |
4069 | trace_kvm_msr_write(ecx, data); | |
b742c1e6 | 4070 | return kvm_skip_emulated_instruction(&svm->vcpu); |
59200273 | 4071 | } |
6aa8b732 AK |
4072 | } |
4073 | ||
851ba692 | 4074 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 4075 | { |
e756fc62 | 4076 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 4077 | return wrmsr_interception(svm); |
6aa8b732 | 4078 | else |
851ba692 | 4079 | return rdmsr_interception(svm); |
6aa8b732 AK |
4080 | } |
4081 | ||
851ba692 | 4082 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 4083 | { |
3842d135 | 4084 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 4085 | svm_clear_vintr(svm); |
85f455f7 | 4086 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 4087 | mark_dirty(svm->vmcb, VMCB_INTR); |
675acb75 | 4088 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
4089 | return 1; |
4090 | } | |
4091 | ||
565d0998 ML |
4092 | static int pause_interception(struct vcpu_svm *svm) |
4093 | { | |
de63ad4c LM |
4094 | struct kvm_vcpu *vcpu = &svm->vcpu; |
4095 | bool in_kernel = (svm_get_cpl(vcpu) == 0); | |
4096 | ||
4097 | kvm_vcpu_on_spin(vcpu, in_kernel); | |
565d0998 ML |
4098 | return 1; |
4099 | } | |
4100 | ||
87c00572 GS |
4101 | static int nop_interception(struct vcpu_svm *svm) |
4102 | { | |
b742c1e6 | 4103 | return kvm_skip_emulated_instruction(&(svm->vcpu)); |
87c00572 GS |
4104 | } |
4105 | ||
4106 | static int monitor_interception(struct vcpu_svm *svm) | |
4107 | { | |
4108 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
4109 | return nop_interception(svm); | |
4110 | } | |
4111 | ||
4112 | static int mwait_interception(struct vcpu_svm *svm) | |
4113 | { | |
4114 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
4115 | return nop_interception(svm); | |
4116 | } | |
4117 | ||
18f40c53 SS |
4118 | enum avic_ipi_failure_cause { |
4119 | AVIC_IPI_FAILURE_INVALID_INT_TYPE, | |
4120 | AVIC_IPI_FAILURE_TARGET_NOT_RUNNING, | |
4121 | AVIC_IPI_FAILURE_INVALID_TARGET, | |
4122 | AVIC_IPI_FAILURE_INVALID_BACKING_PAGE, | |
4123 | }; | |
4124 | ||
4125 | static int avic_incomplete_ipi_interception(struct vcpu_svm *svm) | |
4126 | { | |
4127 | u32 icrh = svm->vmcb->control.exit_info_1 >> 32; | |
4128 | u32 icrl = svm->vmcb->control.exit_info_1; | |
4129 | u32 id = svm->vmcb->control.exit_info_2 >> 32; | |
5446a979 | 4130 | u32 index = svm->vmcb->control.exit_info_2 & 0xFF; |
18f40c53 SS |
4131 | struct kvm_lapic *apic = svm->vcpu.arch.apic; |
4132 | ||
4133 | trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index); | |
4134 | ||
4135 | switch (id) { | |
4136 | case AVIC_IPI_FAILURE_INVALID_INT_TYPE: | |
4137 | /* | |
4138 | * AVIC hardware handles the generation of | |
4139 | * IPIs when the specified Message Type is Fixed | |
4140 | * (also known as fixed delivery mode) and | |
4141 | * the Trigger Mode is edge-triggered. The hardware | |
4142 | * also supports self and broadcast delivery modes | |
4143 | * specified via the Destination Shorthand(DSH) | |
4144 | * field of the ICRL. Logical and physical APIC ID | |
4145 | * formats are supported. All other IPI types cause | |
4146 | * a #VMEXIT, which needs to emulated. | |
4147 | */ | |
4148 | kvm_lapic_reg_write(apic, APIC_ICR2, icrh); | |
4149 | kvm_lapic_reg_write(apic, APIC_ICR, icrl); | |
4150 | break; | |
4151 | case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: { | |
4152 | int i; | |
4153 | struct kvm_vcpu *vcpu; | |
4154 | struct kvm *kvm = svm->vcpu.kvm; | |
4155 | struct kvm_lapic *apic = svm->vcpu.arch.apic; | |
4156 | ||
4157 | /* | |
4158 | * At this point, we expect that the AVIC HW has already | |
4159 | * set the appropriate IRR bits on the valid target | |
4160 | * vcpus. So, we just need to kick the appropriate vcpu. | |
4161 | */ | |
4162 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
4163 | bool m = kvm_apic_match_dest(vcpu, apic, | |
4164 | icrl & KVM_APIC_SHORT_MASK, | |
4165 | GET_APIC_DEST_FIELD(icrh), | |
4166 | icrl & KVM_APIC_DEST_MASK); | |
4167 | ||
4168 | if (m && !avic_vcpu_is_running(vcpu)) | |
4169 | kvm_vcpu_wake_up(vcpu); | |
4170 | } | |
4171 | break; | |
4172 | } | |
4173 | case AVIC_IPI_FAILURE_INVALID_TARGET: | |
4174 | break; | |
4175 | case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE: | |
4176 | WARN_ONCE(1, "Invalid backing page\n"); | |
4177 | break; | |
4178 | default: | |
4179 | pr_err("Unknown IPI interception\n"); | |
4180 | } | |
4181 | ||
4182 | return 1; | |
4183 | } | |
4184 | ||
4185 | static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat) | |
4186 | { | |
4187 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
4188 | int index; | |
4189 | u32 *logical_apic_id_table; | |
4190 | int dlid = GET_APIC_LOGICAL_ID(ldr); | |
4191 | ||
4192 | if (!dlid) | |
4193 | return NULL; | |
4194 | ||
4195 | if (flat) { /* flat */ | |
4196 | index = ffs(dlid) - 1; | |
4197 | if (index > 7) | |
4198 | return NULL; | |
4199 | } else { /* cluster */ | |
4200 | int cluster = (dlid & 0xf0) >> 4; | |
4201 | int apic = ffs(dlid & 0x0f) - 1; | |
4202 | ||
4203 | if ((apic < 0) || (apic > 7) || | |
4204 | (cluster >= 0xf)) | |
4205 | return NULL; | |
4206 | index = (cluster << 2) + apic; | |
4207 | } | |
4208 | ||
4209 | logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page); | |
4210 | ||
4211 | return &logical_apic_id_table[index]; | |
4212 | } | |
4213 | ||
4214 | static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr, | |
4215 | bool valid) | |
4216 | { | |
4217 | bool flat; | |
4218 | u32 *entry, new_entry; | |
4219 | ||
4220 | flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT; | |
4221 | entry = avic_get_logical_id_entry(vcpu, ldr, flat); | |
4222 | if (!entry) | |
4223 | return -EINVAL; | |
4224 | ||
4225 | new_entry = READ_ONCE(*entry); | |
4226 | new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK; | |
4227 | new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK); | |
4228 | if (valid) | |
4229 | new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK; | |
4230 | else | |
4231 | new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK; | |
4232 | WRITE_ONCE(*entry, new_entry); | |
4233 | ||
4234 | return 0; | |
4235 | } | |
4236 | ||
4237 | static int avic_handle_ldr_update(struct kvm_vcpu *vcpu) | |
4238 | { | |
4239 | int ret; | |
4240 | struct vcpu_svm *svm = to_svm(vcpu); | |
4241 | u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR); | |
4242 | ||
4243 | if (!ldr) | |
4244 | return 1; | |
4245 | ||
4246 | ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true); | |
4247 | if (ret && svm->ldr_reg) { | |
4248 | avic_ldr_write(vcpu, 0, svm->ldr_reg, false); | |
4249 | svm->ldr_reg = 0; | |
4250 | } else { | |
4251 | svm->ldr_reg = ldr; | |
4252 | } | |
4253 | return ret; | |
4254 | } | |
4255 | ||
4256 | static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu) | |
4257 | { | |
4258 | u64 *old, *new; | |
4259 | struct vcpu_svm *svm = to_svm(vcpu); | |
4260 | u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID); | |
4261 | u32 id = (apic_id_reg >> 24) & 0xff; | |
4262 | ||
4263 | if (vcpu->vcpu_id == id) | |
4264 | return 0; | |
4265 | ||
4266 | old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id); | |
4267 | new = avic_get_physical_id_entry(vcpu, id); | |
4268 | if (!new || !old) | |
4269 | return 1; | |
4270 | ||
4271 | /* We need to move physical_id_entry to new offset */ | |
4272 | *new = *old; | |
4273 | *old = 0ULL; | |
4274 | to_svm(vcpu)->avic_physical_id_cache = new; | |
4275 | ||
4276 | /* | |
4277 | * Also update the guest physical APIC ID in the logical | |
4278 | * APIC ID table entry if already setup the LDR. | |
4279 | */ | |
4280 | if (svm->ldr_reg) | |
4281 | avic_handle_ldr_update(vcpu); | |
4282 | ||
4283 | return 0; | |
4284 | } | |
4285 | ||
4286 | static int avic_handle_dfr_update(struct kvm_vcpu *vcpu) | |
4287 | { | |
4288 | struct vcpu_svm *svm = to_svm(vcpu); | |
4289 | struct kvm_arch *vm_data = &vcpu->kvm->arch; | |
4290 | u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR); | |
4291 | u32 mod = (dfr >> 28) & 0xf; | |
4292 | ||
4293 | /* | |
4294 | * We assume that all local APICs are using the same type. | |
4295 | * If this changes, we need to flush the AVIC logical | |
4296 | * APID id table. | |
4297 | */ | |
4298 | if (vm_data->ldr_mode == mod) | |
4299 | return 0; | |
4300 | ||
4301 | clear_page(page_address(vm_data->avic_logical_id_table_page)); | |
4302 | vm_data->ldr_mode = mod; | |
4303 | ||
4304 | if (svm->ldr_reg) | |
4305 | avic_handle_ldr_update(vcpu); | |
4306 | return 0; | |
4307 | } | |
4308 | ||
4309 | static int avic_unaccel_trap_write(struct vcpu_svm *svm) | |
4310 | { | |
4311 | struct kvm_lapic *apic = svm->vcpu.arch.apic; | |
4312 | u32 offset = svm->vmcb->control.exit_info_1 & | |
4313 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
4314 | ||
4315 | switch (offset) { | |
4316 | case APIC_ID: | |
4317 | if (avic_handle_apic_id_update(&svm->vcpu)) | |
4318 | return 0; | |
4319 | break; | |
4320 | case APIC_LDR: | |
4321 | if (avic_handle_ldr_update(&svm->vcpu)) | |
4322 | return 0; | |
4323 | break; | |
4324 | case APIC_DFR: | |
4325 | avic_handle_dfr_update(&svm->vcpu); | |
4326 | break; | |
4327 | default: | |
4328 | break; | |
4329 | } | |
4330 | ||
4331 | kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset)); | |
4332 | ||
4333 | return 1; | |
4334 | } | |
4335 | ||
4336 | static bool is_avic_unaccelerated_access_trap(u32 offset) | |
4337 | { | |
4338 | bool ret = false; | |
4339 | ||
4340 | switch (offset) { | |
4341 | case APIC_ID: | |
4342 | case APIC_EOI: | |
4343 | case APIC_RRR: | |
4344 | case APIC_LDR: | |
4345 | case APIC_DFR: | |
4346 | case APIC_SPIV: | |
4347 | case APIC_ESR: | |
4348 | case APIC_ICR: | |
4349 | case APIC_LVTT: | |
4350 | case APIC_LVTTHMR: | |
4351 | case APIC_LVTPC: | |
4352 | case APIC_LVT0: | |
4353 | case APIC_LVT1: | |
4354 | case APIC_LVTERR: | |
4355 | case APIC_TMICT: | |
4356 | case APIC_TDCR: | |
4357 | ret = true; | |
4358 | break; | |
4359 | default: | |
4360 | break; | |
4361 | } | |
4362 | return ret; | |
4363 | } | |
4364 | ||
4365 | static int avic_unaccelerated_access_interception(struct vcpu_svm *svm) | |
4366 | { | |
4367 | int ret = 0; | |
4368 | u32 offset = svm->vmcb->control.exit_info_1 & | |
4369 | AVIC_UNACCEL_ACCESS_OFFSET_MASK; | |
4370 | u32 vector = svm->vmcb->control.exit_info_2 & | |
4371 | AVIC_UNACCEL_ACCESS_VECTOR_MASK; | |
4372 | bool write = (svm->vmcb->control.exit_info_1 >> 32) & | |
4373 | AVIC_UNACCEL_ACCESS_WRITE_MASK; | |
4374 | bool trap = is_avic_unaccelerated_access_trap(offset); | |
4375 | ||
4376 | trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset, | |
4377 | trap, write, vector); | |
4378 | if (trap) { | |
4379 | /* Handling Trap */ | |
4380 | WARN_ONCE(!write, "svm: Handling trap read.\n"); | |
4381 | ret = avic_unaccel_trap_write(svm); | |
4382 | } else { | |
4383 | /* Handling Fault */ | |
4384 | ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE); | |
4385 | } | |
4386 | ||
4387 | return ret; | |
4388 | } | |
4389 | ||
09941fbb | 4390 | static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
4391 | [SVM_EXIT_READ_CR0] = cr_interception, |
4392 | [SVM_EXIT_READ_CR3] = cr_interception, | |
4393 | [SVM_EXIT_READ_CR4] = cr_interception, | |
4394 | [SVM_EXIT_READ_CR8] = cr_interception, | |
5e57518d | 4395 | [SVM_EXIT_CR0_SEL_WRITE] = cr_interception, |
628afd2a | 4396 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
4397 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
4398 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 4399 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
4400 | [SVM_EXIT_READ_DR0] = dr_interception, |
4401 | [SVM_EXIT_READ_DR1] = dr_interception, | |
4402 | [SVM_EXIT_READ_DR2] = dr_interception, | |
4403 | [SVM_EXIT_READ_DR3] = dr_interception, | |
4404 | [SVM_EXIT_READ_DR4] = dr_interception, | |
4405 | [SVM_EXIT_READ_DR5] = dr_interception, | |
4406 | [SVM_EXIT_READ_DR6] = dr_interception, | |
4407 | [SVM_EXIT_READ_DR7] = dr_interception, | |
4408 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
4409 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
4410 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
4411 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
4412 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
4413 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
4414 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
4415 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
4416 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
4417 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 4418 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 | 4419 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
e0231715 | 4420 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
54a20552 | 4421 | [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception, |
e0231715 | 4422 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 4423 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
4424 | [SVM_EXIT_SMI] = nop_on_interception, |
4425 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 4426 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
332b56e4 | 4427 | [SVM_EXIT_RDPMC] = rdpmc_interception, |
6aa8b732 | 4428 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 4429 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 4430 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 4431 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 4432 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 4433 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 4434 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 4435 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
4436 | [SVM_EXIT_MSR] = msr_interception, |
4437 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 4438 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 4439 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 4440 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
4441 | [SVM_EXIT_VMLOAD] = vmload_interception, |
4442 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
4443 | [SVM_EXIT_STGI] = stgi_interception, |
4444 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 4445 | [SVM_EXIT_SKINIT] = skinit_interception, |
dab429a7 | 4446 | [SVM_EXIT_WBINVD] = wbinvd_interception, |
87c00572 GS |
4447 | [SVM_EXIT_MONITOR] = monitor_interception, |
4448 | [SVM_EXIT_MWAIT] = mwait_interception, | |
81dd35d4 | 4449 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
d0006530 | 4450 | [SVM_EXIT_NPF] = npf_interception, |
64d60670 | 4451 | [SVM_EXIT_RSM] = emulate_on_interception, |
18f40c53 SS |
4452 | [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception, |
4453 | [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception, | |
6aa8b732 AK |
4454 | }; |
4455 | ||
ae8cc059 | 4456 | static void dump_vmcb(struct kvm_vcpu *vcpu) |
3f10c846 JR |
4457 | { |
4458 | struct vcpu_svm *svm = to_svm(vcpu); | |
4459 | struct vmcb_control_area *control = &svm->vmcb->control; | |
4460 | struct vmcb_save_area *save = &svm->vmcb->save; | |
4461 | ||
4462 | pr_err("VMCB Control Area:\n"); | |
ae8cc059 JP |
4463 | pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); |
4464 | pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); | |
4465 | pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); | |
4466 | pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); | |
4467 | pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); | |
4468 | pr_err("%-20s%016llx\n", "intercepts:", control->intercept); | |
4469 | pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); | |
4470 | pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); | |
4471 | pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); | |
4472 | pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); | |
4473 | pr_err("%-20s%d\n", "asid:", control->asid); | |
4474 | pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); | |
4475 | pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); | |
4476 | pr_err("%-20s%08x\n", "int_vector:", control->int_vector); | |
4477 | pr_err("%-20s%08x\n", "int_state:", control->int_state); | |
4478 | pr_err("%-20s%08x\n", "exit_code:", control->exit_code); | |
4479 | pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); | |
4480 | pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); | |
4481 | pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); | |
4482 | pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); | |
4483 | pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); | |
4484 | pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); | |
44a95dae | 4485 | pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar); |
ae8cc059 JP |
4486 | pr_err("%-20s%08x\n", "event_inj:", control->event_inj); |
4487 | pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); | |
0dc92119 | 4488 | pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext); |
ae8cc059 | 4489 | pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); |
44a95dae SS |
4490 | pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page); |
4491 | pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id); | |
4492 | pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id); | |
3f10c846 | 4493 | pr_err("VMCB State Save Area:\n"); |
ae8cc059 JP |
4494 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", |
4495 | "es:", | |
4496 | save->es.selector, save->es.attrib, | |
4497 | save->es.limit, save->es.base); | |
4498 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4499 | "cs:", | |
4500 | save->cs.selector, save->cs.attrib, | |
4501 | save->cs.limit, save->cs.base); | |
4502 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4503 | "ss:", | |
4504 | save->ss.selector, save->ss.attrib, | |
4505 | save->ss.limit, save->ss.base); | |
4506 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4507 | "ds:", | |
4508 | save->ds.selector, save->ds.attrib, | |
4509 | save->ds.limit, save->ds.base); | |
4510 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4511 | "fs:", | |
4512 | save->fs.selector, save->fs.attrib, | |
4513 | save->fs.limit, save->fs.base); | |
4514 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4515 | "gs:", | |
4516 | save->gs.selector, save->gs.attrib, | |
4517 | save->gs.limit, save->gs.base); | |
4518 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4519 | "gdtr:", | |
4520 | save->gdtr.selector, save->gdtr.attrib, | |
4521 | save->gdtr.limit, save->gdtr.base); | |
4522 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4523 | "ldtr:", | |
4524 | save->ldtr.selector, save->ldtr.attrib, | |
4525 | save->ldtr.limit, save->ldtr.base); | |
4526 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4527 | "idtr:", | |
4528 | save->idtr.selector, save->idtr.attrib, | |
4529 | save->idtr.limit, save->idtr.base); | |
4530 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
4531 | "tr:", | |
4532 | save->tr.selector, save->tr.attrib, | |
4533 | save->tr.limit, save->tr.base); | |
3f10c846 JR |
4534 | pr_err("cpl: %d efer: %016llx\n", |
4535 | save->cpl, save->efer); | |
ae8cc059 JP |
4536 | pr_err("%-15s %016llx %-13s %016llx\n", |
4537 | "cr0:", save->cr0, "cr2:", save->cr2); | |
4538 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4539 | "cr3:", save->cr3, "cr4:", save->cr4); | |
4540 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4541 | "dr6:", save->dr6, "dr7:", save->dr7); | |
4542 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4543 | "rip:", save->rip, "rflags:", save->rflags); | |
4544 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4545 | "rsp:", save->rsp, "rax:", save->rax); | |
4546 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4547 | "star:", save->star, "lstar:", save->lstar); | |
4548 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4549 | "cstar:", save->cstar, "sfmask:", save->sfmask); | |
4550 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4551 | "kernel_gs_base:", save->kernel_gs_base, | |
4552 | "sysenter_cs:", save->sysenter_cs); | |
4553 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4554 | "sysenter_esp:", save->sysenter_esp, | |
4555 | "sysenter_eip:", save->sysenter_eip); | |
4556 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4557 | "gpat:", save->g_pat, "dbgctl:", save->dbgctl); | |
4558 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4559 | "br_from:", save->br_from, "br_to:", save->br_to); | |
4560 | pr_err("%-15s %016llx %-13s %016llx\n", | |
4561 | "excp_from:", save->last_excp_from, | |
4562 | "excp_to:", save->last_excp_to); | |
3f10c846 JR |
4563 | } |
4564 | ||
586f9607 AK |
4565 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
4566 | { | |
4567 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
4568 | ||
4569 | *info1 = control->exit_info_1; | |
4570 | *info2 = control->exit_info_2; | |
4571 | } | |
4572 | ||
851ba692 | 4573 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 4574 | { |
04d2cc77 | 4575 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 4576 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 4577 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 4578 | |
8b89fe1f PB |
4579 | trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM); |
4580 | ||
4ee546b4 | 4581 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
4582 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
4583 | if (npt_enabled) | |
4584 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 4585 | |
cd3ff653 JR |
4586 | if (unlikely(svm->nested.exit_required)) { |
4587 | nested_svm_vmexit(svm); | |
4588 | svm->nested.exit_required = false; | |
4589 | ||
4590 | return 1; | |
4591 | } | |
4592 | ||
2030753d | 4593 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
4594 | int vmexit; |
4595 | ||
d8cabddf JR |
4596 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
4597 | svm->vmcb->control.exit_info_1, | |
4598 | svm->vmcb->control.exit_info_2, | |
4599 | svm->vmcb->control.exit_int_info, | |
e097e5ff SH |
4600 | svm->vmcb->control.exit_int_info_err, |
4601 | KVM_ISA_SVM); | |
d8cabddf | 4602 | |
410e4d57 JR |
4603 | vmexit = nested_svm_exit_special(svm); |
4604 | ||
4605 | if (vmexit == NESTED_EXIT_CONTINUE) | |
4606 | vmexit = nested_svm_exit_handled(svm); | |
4607 | ||
4608 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 4609 | return 1; |
cf74a78b AG |
4610 | } |
4611 | ||
a5c3832d JR |
4612 | svm_complete_interrupts(svm); |
4613 | ||
04d2cc77 AK |
4614 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
4615 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
4616 | kvm_run->fail_entry.hardware_entry_failure_reason | |
4617 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
4618 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
4619 | dump_vmcb(vcpu); | |
04d2cc77 AK |
4620 | return 0; |
4621 | } | |
4622 | ||
a2fa3e9f | 4623 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 4624 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
4625 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
4626 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6614c7d0 | 4627 | printk(KERN_ERR "%s: unexpected exit_int_info 0x%x " |
6aa8b732 | 4628 | "exit_code 0x%x\n", |
b8688d51 | 4629 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
4630 | exit_code); |
4631 | ||
9d8f549d | 4632 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 4633 | || !svm_exit_handlers[exit_code]) { |
faac2458 | 4634 | WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code); |
2bc19dc3 MT |
4635 | kvm_queue_exception(vcpu, UD_VECTOR); |
4636 | return 1; | |
6aa8b732 AK |
4637 | } |
4638 | ||
851ba692 | 4639 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
4640 | } |
4641 | ||
4642 | static void reload_tss(struct kvm_vcpu *vcpu) | |
4643 | { | |
4644 | int cpu = raw_smp_processor_id(); | |
4645 | ||
0fe1e009 TH |
4646 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
4647 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
4648 | load_TR_desc(); |
4649 | } | |
4650 | ||
70cd94e6 BS |
4651 | static void pre_sev_run(struct vcpu_svm *svm, int cpu) |
4652 | { | |
4653 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); | |
4654 | int asid = sev_get_asid(svm->vcpu.kvm); | |
4655 | ||
4656 | /* Assign the asid allocated with this SEV guest */ | |
4657 | svm->vmcb->control.asid = asid; | |
4658 | ||
4659 | /* | |
4660 | * Flush guest TLB: | |
4661 | * | |
4662 | * 1) when different VMCB for the same ASID is to be run on the same host CPU. | |
4663 | * 2) or this VMCB was executed on different host CPU in previous VMRUNs. | |
4664 | */ | |
4665 | if (sd->sev_vmcbs[asid] == svm->vmcb && | |
4666 | svm->last_cpu == cpu) | |
4667 | return; | |
4668 | ||
4669 | svm->last_cpu = cpu; | |
4670 | sd->sev_vmcbs[asid] = svm->vmcb; | |
4671 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
4672 | mark_dirty(svm->vmcb, VMCB_ASID); | |
4673 | } | |
4674 | ||
e756fc62 | 4675 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
4676 | { |
4677 | int cpu = raw_smp_processor_id(); | |
4678 | ||
0fe1e009 | 4679 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 4680 | |
70cd94e6 BS |
4681 | if (sev_guest(svm->vcpu.kvm)) |
4682 | return pre_sev_run(svm, cpu); | |
4683 | ||
4b656b12 | 4684 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
4685 | if (svm->asid_generation != sd->asid_generation) |
4686 | new_asid(svm, sd); | |
6aa8b732 AK |
4687 | } |
4688 | ||
95ba8273 GN |
4689 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
4690 | { | |
4691 | struct vcpu_svm *svm = to_svm(vcpu); | |
4692 | ||
4693 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
4694 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 4695 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
4696 | ++vcpu->stat.nmi_injections; |
4697 | } | |
6aa8b732 | 4698 | |
85f455f7 | 4699 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
4700 | { |
4701 | struct vmcb_control_area *control; | |
4702 | ||
340d3bc3 | 4703 | /* The following fields are ignored when AVIC is enabled */ |
e756fc62 | 4704 | control = &svm->vmcb->control; |
85f455f7 | 4705 | control->int_vector = irq; |
6aa8b732 AK |
4706 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
4707 | control->int_ctl |= V_IRQ_MASK | | |
4708 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 4709 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
4710 | } |
4711 | ||
66fd3f7f | 4712 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
4713 | { |
4714 | struct vcpu_svm *svm = to_svm(vcpu); | |
4715 | ||
2af9194d | 4716 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 4717 | |
9fb2d2b4 GN |
4718 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
4719 | ++vcpu->stat.irq_injections; | |
4720 | ||
219b65dc AG |
4721 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
4722 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
4723 | } |
4724 | ||
3bbf3565 SS |
4725 | static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu) |
4726 | { | |
4727 | return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK); | |
4728 | } | |
4729 | ||
95ba8273 | 4730 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
4731 | { |
4732 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 4733 | |
3bbf3565 SS |
4734 | if (svm_nested_virtualize_tpr(vcpu) || |
4735 | kvm_vcpu_apicv_active(vcpu)) | |
88ab24ad JR |
4736 | return; |
4737 | ||
596f3142 RK |
4738 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
4739 | ||
95ba8273 | 4740 | if (irr == -1) |
aaacfc9a JR |
4741 | return; |
4742 | ||
95ba8273 | 4743 | if (tpr >= irr) |
4ee546b4 | 4744 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 4745 | } |
aaacfc9a | 4746 | |
8d14695f YZ |
4747 | static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
4748 | { | |
4749 | return; | |
4750 | } | |
4751 | ||
b2a05fef | 4752 | static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu) |
d62caabb | 4753 | { |
67034bb9 | 4754 | return avic && irqchip_split(vcpu->kvm); |
44a95dae SS |
4755 | } |
4756 | ||
4757 | static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
4758 | { | |
d62caabb AS |
4759 | } |
4760 | ||
67c9dddc | 4761 | static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
44a95dae | 4762 | { |
d62caabb AS |
4763 | } |
4764 | ||
44a95dae | 4765 | /* Note: Currently only used by Hyper-V. */ |
d62caabb | 4766 | static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
c7c9c56c | 4767 | { |
44a95dae SS |
4768 | struct vcpu_svm *svm = to_svm(vcpu); |
4769 | struct vmcb *vmcb = svm->vmcb; | |
4770 | ||
67034bb9 | 4771 | if (!kvm_vcpu_apicv_active(&svm->vcpu)) |
44a95dae SS |
4772 | return; |
4773 | ||
4774 | vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK; | |
4775 | mark_dirty(vmcb, VMCB_INTR); | |
c7c9c56c YZ |
4776 | } |
4777 | ||
6308630b | 4778 | static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c YZ |
4779 | { |
4780 | return; | |
4781 | } | |
4782 | ||
340d3bc3 SS |
4783 | static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec) |
4784 | { | |
4785 | kvm_lapic_set_irr(vec, vcpu->arch.apic); | |
4786 | smp_mb__after_atomic(); | |
4787 | ||
4788 | if (avic_vcpu_is_running(vcpu)) | |
4789 | wrmsrl(SVM_AVIC_DOORBELL, | |
7d669f50 | 4790 | kvm_cpu_get_apicid(vcpu->cpu)); |
340d3bc3 SS |
4791 | else |
4792 | kvm_vcpu_wake_up(vcpu); | |
4793 | } | |
4794 | ||
411b44ba SS |
4795 | static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) |
4796 | { | |
4797 | unsigned long flags; | |
4798 | struct amd_svm_iommu_ir *cur; | |
4799 | ||
4800 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
4801 | list_for_each_entry(cur, &svm->ir_list, node) { | |
4802 | if (cur->data != pi->ir_data) | |
4803 | continue; | |
4804 | list_del(&cur->node); | |
4805 | kfree(cur); | |
4806 | break; | |
4807 | } | |
4808 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
4809 | } | |
4810 | ||
4811 | static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) | |
4812 | { | |
4813 | int ret = 0; | |
4814 | unsigned long flags; | |
4815 | struct amd_svm_iommu_ir *ir; | |
4816 | ||
4817 | /** | |
4818 | * In some cases, the existing irte is updaed and re-set, | |
4819 | * so we need to check here if it's already been * added | |
4820 | * to the ir_list. | |
4821 | */ | |
4822 | if (pi->ir_data && (pi->prev_ga_tag != 0)) { | |
4823 | struct kvm *kvm = svm->vcpu.kvm; | |
4824 | u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag); | |
4825 | struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id); | |
4826 | struct vcpu_svm *prev_svm; | |
4827 | ||
4828 | if (!prev_vcpu) { | |
4829 | ret = -EINVAL; | |
4830 | goto out; | |
4831 | } | |
4832 | ||
4833 | prev_svm = to_svm(prev_vcpu); | |
4834 | svm_ir_list_del(prev_svm, pi); | |
4835 | } | |
4836 | ||
4837 | /** | |
4838 | * Allocating new amd_iommu_pi_data, which will get | |
4839 | * add to the per-vcpu ir_list. | |
4840 | */ | |
4841 | ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL); | |
4842 | if (!ir) { | |
4843 | ret = -ENOMEM; | |
4844 | goto out; | |
4845 | } | |
4846 | ir->data = pi->ir_data; | |
4847 | ||
4848 | spin_lock_irqsave(&svm->ir_list_lock, flags); | |
4849 | list_add(&ir->node, &svm->ir_list); | |
4850 | spin_unlock_irqrestore(&svm->ir_list_lock, flags); | |
4851 | out: | |
4852 | return ret; | |
4853 | } | |
4854 | ||
4855 | /** | |
4856 | * Note: | |
4857 | * The HW cannot support posting multicast/broadcast | |
4858 | * interrupts to a vCPU. So, we still use legacy interrupt | |
4859 | * remapping for these kind of interrupts. | |
4860 | * | |
4861 | * For lowest-priority interrupts, we only support | |
4862 | * those with single CPU as the destination, e.g. user | |
4863 | * configures the interrupts via /proc/irq or uses | |
4864 | * irqbalance to make the interrupts single-CPU. | |
4865 | */ | |
4866 | static int | |
4867 | get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, | |
4868 | struct vcpu_data *vcpu_info, struct vcpu_svm **svm) | |
4869 | { | |
4870 | struct kvm_lapic_irq irq; | |
4871 | struct kvm_vcpu *vcpu = NULL; | |
4872 | ||
4873 | kvm_set_msi_irq(kvm, e, &irq); | |
4874 | ||
4875 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { | |
4876 | pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n", | |
4877 | __func__, irq.vector); | |
4878 | return -1; | |
4879 | } | |
4880 | ||
4881 | pr_debug("SVM: %s: use GA mode for irq %u\n", __func__, | |
4882 | irq.vector); | |
4883 | *svm = to_svm(vcpu); | |
d0ec49d4 | 4884 | vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page)); |
411b44ba SS |
4885 | vcpu_info->vector = irq.vector; |
4886 | ||
4887 | return 0; | |
4888 | } | |
4889 | ||
4890 | /* | |
4891 | * svm_update_pi_irte - set IRTE for Posted-Interrupts | |
4892 | * | |
4893 | * @kvm: kvm | |
4894 | * @host_irq: host irq of the interrupt | |
4895 | * @guest_irq: gsi of the interrupt | |
4896 | * @set: set or unset PI | |
4897 | * returns 0 on success, < 0 on failure | |
4898 | */ | |
4899 | static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
4900 | uint32_t guest_irq, bool set) | |
4901 | { | |
4902 | struct kvm_kernel_irq_routing_entry *e; | |
4903 | struct kvm_irq_routing_table *irq_rt; | |
4904 | int idx, ret = -EINVAL; | |
4905 | ||
4906 | if (!kvm_arch_has_assigned_device(kvm) || | |
4907 | !irq_remapping_cap(IRQ_POSTING_CAP)) | |
4908 | return 0; | |
4909 | ||
4910 | pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n", | |
4911 | __func__, host_irq, guest_irq, set); | |
4912 | ||
4913 | idx = srcu_read_lock(&kvm->irq_srcu); | |
4914 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
4915 | WARN_ON(guest_irq >= irq_rt->nr_rt_entries); | |
4916 | ||
4917 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
4918 | struct vcpu_data vcpu_info; | |
4919 | struct vcpu_svm *svm = NULL; | |
4920 | ||
4921 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
4922 | continue; | |
4923 | ||
4924 | /** | |
4925 | * Here, we setup with legacy mode in the following cases: | |
4926 | * 1. When cannot target interrupt to a specific vcpu. | |
4927 | * 2. Unsetting posted interrupt. | |
4928 | * 3. APIC virtialization is disabled for the vcpu. | |
4929 | */ | |
4930 | if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set && | |
4931 | kvm_vcpu_apicv_active(&svm->vcpu)) { | |
4932 | struct amd_iommu_pi_data pi; | |
4933 | ||
4934 | /* Try to enable guest_mode in IRTE */ | |
d0ec49d4 TL |
4935 | pi.base = __sme_set(page_to_phys(svm->avic_backing_page) & |
4936 | AVIC_HPA_MASK); | |
411b44ba SS |
4937 | pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id, |
4938 | svm->vcpu.vcpu_id); | |
4939 | pi.is_guest_mode = true; | |
4940 | pi.vcpu_data = &vcpu_info; | |
4941 | ret = irq_set_vcpu_affinity(host_irq, &pi); | |
4942 | ||
4943 | /** | |
4944 | * Here, we successfully setting up vcpu affinity in | |
4945 | * IOMMU guest mode. Now, we need to store the posted | |
4946 | * interrupt information in a per-vcpu ir_list so that | |
4947 | * we can reference to them directly when we update vcpu | |
4948 | * scheduling information in IOMMU irte. | |
4949 | */ | |
4950 | if (!ret && pi.is_guest_mode) | |
4951 | svm_ir_list_add(svm, &pi); | |
4952 | } else { | |
4953 | /* Use legacy mode in IRTE */ | |
4954 | struct amd_iommu_pi_data pi; | |
4955 | ||
4956 | /** | |
4957 | * Here, pi is used to: | |
4958 | * - Tell IOMMU to use legacy mode for this interrupt. | |
4959 | * - Retrieve ga_tag of prior interrupt remapping data. | |
4960 | */ | |
4961 | pi.is_guest_mode = false; | |
4962 | ret = irq_set_vcpu_affinity(host_irq, &pi); | |
4963 | ||
4964 | /** | |
4965 | * Check if the posted interrupt was previously | |
4966 | * setup with the guest_mode by checking if the ga_tag | |
4967 | * was cached. If so, we need to clean up the per-vcpu | |
4968 | * ir_list. | |
4969 | */ | |
4970 | if (!ret && pi.prev_ga_tag) { | |
4971 | int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag); | |
4972 | struct kvm_vcpu *vcpu; | |
4973 | ||
4974 | vcpu = kvm_get_vcpu_by_id(kvm, id); | |
4975 | if (vcpu) | |
4976 | svm_ir_list_del(to_svm(vcpu), &pi); | |
4977 | } | |
4978 | } | |
4979 | ||
4980 | if (!ret && svm) { | |
4981 | trace_kvm_pi_irte_update(svm->vcpu.vcpu_id, | |
4982 | host_irq, e->gsi, | |
4983 | vcpu_info.vector, | |
4984 | vcpu_info.pi_desc_addr, set); | |
4985 | } | |
4986 | ||
4987 | if (ret < 0) { | |
4988 | pr_err("%s: failed to update PI IRTE\n", __func__); | |
4989 | goto out; | |
4990 | } | |
4991 | } | |
4992 | ||
4993 | ret = 0; | |
4994 | out: | |
4995 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
4996 | return ret; | |
4997 | } | |
4998 | ||
95ba8273 GN |
4999 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
5000 | { | |
5001 | struct vcpu_svm *svm = to_svm(vcpu); | |
5002 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
5003 | int ret; |
5004 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
5005 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
5006 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
5007 | ||
5008 | return ret; | |
aaacfc9a JR |
5009 | } |
5010 | ||
3cfc3092 JK |
5011 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
5012 | { | |
5013 | struct vcpu_svm *svm = to_svm(vcpu); | |
5014 | ||
5015 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
5016 | } | |
5017 | ||
5018 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
5019 | { | |
5020 | struct vcpu_svm *svm = to_svm(vcpu); | |
5021 | ||
5022 | if (masked) { | |
5023 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 5024 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
5025 | } else { |
5026 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 5027 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
5028 | } |
5029 | } | |
5030 | ||
78646121 GN |
5031 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
5032 | { | |
5033 | struct vcpu_svm *svm = to_svm(vcpu); | |
5034 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
5035 | int ret; |
5036 | ||
5037 | if (!gif_set(svm) || | |
5038 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
5039 | return 0; | |
5040 | ||
f6e78475 | 5041 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 5042 | |
2030753d | 5043 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
5044 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
5045 | ||
5046 | return ret; | |
78646121 GN |
5047 | } |
5048 | ||
c9a7953f | 5049 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 5050 | { |
219b65dc | 5051 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 5052 | |
340d3bc3 SS |
5053 | if (kvm_vcpu_apicv_active(vcpu)) |
5054 | return; | |
5055 | ||
e0231715 JR |
5056 | /* |
5057 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
5058 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
5059 | * get that intercept, this function will be called again though and | |
640bd6e5 JN |
5060 | * we'll get the vintr intercept. However, if the vGIF feature is |
5061 | * enabled, the STGI interception will not occur. Enable the irq | |
5062 | * window under the assumption that the hardware will set the GIF. | |
e0231715 | 5063 | */ |
640bd6e5 | 5064 | if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) { |
219b65dc AG |
5065 | svm_set_vintr(svm); |
5066 | svm_inject_irq(svm, 0x0); | |
5067 | } | |
85f455f7 ED |
5068 | } |
5069 | ||
c9a7953f | 5070 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 5071 | { |
04d2cc77 | 5072 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 5073 | |
44c11430 GN |
5074 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
5075 | == HF_NMI_MASK) | |
c9a7953f | 5076 | return; /* IRET will cause a vm exit */ |
44c11430 | 5077 | |
640bd6e5 JN |
5078 | if (!gif_set(svm)) { |
5079 | if (vgif_enabled(svm)) | |
5080 | set_intercept(svm, INTERCEPT_STGI); | |
1a5e1852 | 5081 | return; /* STGI will cause a vm exit */ |
640bd6e5 | 5082 | } |
1a5e1852 LP |
5083 | |
5084 | if (svm->nested.exit_required) | |
5085 | return; /* we're not going to run the guest yet */ | |
5086 | ||
e0231715 JR |
5087 | /* |
5088 | * Something prevents NMI from been injected. Single step over possible | |
5089 | * problem (IRET or exception injection or interrupt shadow) | |
5090 | */ | |
ab2f4d73 | 5091 | svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu); |
6be7d306 | 5092 | svm->nmi_singlestep = true; |
44c11430 | 5093 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
c1150d8c DL |
5094 | } |
5095 | ||
cbc94022 IE |
5096 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
5097 | { | |
5098 | return 0; | |
5099 | } | |
5100 | ||
d9e368d6 AK |
5101 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
5102 | { | |
38e5e92f JR |
5103 | struct vcpu_svm *svm = to_svm(vcpu); |
5104 | ||
5105 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
5106 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
5107 | else | |
5108 | svm->asid_generation--; | |
d9e368d6 AK |
5109 | } |
5110 | ||
04d2cc77 AK |
5111 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
5112 | { | |
5113 | } | |
5114 | ||
d7bf8221 JR |
5115 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
5116 | { | |
5117 | struct vcpu_svm *svm = to_svm(vcpu); | |
5118 | ||
3bbf3565 | 5119 | if (svm_nested_virtualize_tpr(vcpu)) |
88ab24ad JR |
5120 | return; |
5121 | ||
4ee546b4 | 5122 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 5123 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 5124 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
5125 | } |
5126 | } | |
5127 | ||
649d6864 JR |
5128 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
5129 | { | |
5130 | struct vcpu_svm *svm = to_svm(vcpu); | |
5131 | u64 cr8; | |
5132 | ||
3bbf3565 SS |
5133 | if (svm_nested_virtualize_tpr(vcpu) || |
5134 | kvm_vcpu_apicv_active(vcpu)) | |
88ab24ad JR |
5135 | return; |
5136 | ||
649d6864 JR |
5137 | cr8 = kvm_get_cr8(vcpu); |
5138 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
5139 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
5140 | } | |
5141 | ||
9222be18 GN |
5142 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
5143 | { | |
5144 | u8 vector; | |
5145 | int type; | |
5146 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
5147 | unsigned int3_injected = svm->int3_injected; |
5148 | ||
5149 | svm->int3_injected = 0; | |
9222be18 | 5150 | |
bd3d1ec3 AK |
5151 | /* |
5152 | * If we've made progress since setting HF_IRET_MASK, we've | |
5153 | * executed an IRET and can allow NMI injection. | |
5154 | */ | |
5155 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
5156 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 5157 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
5158 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
5159 | } | |
44c11430 | 5160 | |
9222be18 GN |
5161 | svm->vcpu.arch.nmi_injected = false; |
5162 | kvm_clear_exception_queue(&svm->vcpu); | |
5163 | kvm_clear_interrupt_queue(&svm->vcpu); | |
5164 | ||
5165 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
5166 | return; | |
5167 | ||
3842d135 AK |
5168 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
5169 | ||
9222be18 GN |
5170 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
5171 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
5172 | ||
5173 | switch (type) { | |
5174 | case SVM_EXITINTINFO_TYPE_NMI: | |
5175 | svm->vcpu.arch.nmi_injected = true; | |
5176 | break; | |
5177 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
5178 | /* |
5179 | * In case of software exceptions, do not reinject the vector, | |
5180 | * but re-execute the instruction instead. Rewind RIP first | |
5181 | * if we emulated INT3 before. | |
5182 | */ | |
5183 | if (kvm_exception_is_soft(vector)) { | |
5184 | if (vector == BP_VECTOR && int3_injected && | |
5185 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
5186 | kvm_rip_write(&svm->vcpu, | |
5187 | kvm_rip_read(&svm->vcpu) - | |
5188 | int3_injected); | |
9222be18 | 5189 | break; |
66b7138f | 5190 | } |
9222be18 GN |
5191 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
5192 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 5193 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
5194 | |
5195 | } else | |
ce7ddec4 | 5196 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
5197 | break; |
5198 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 5199 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
5200 | break; |
5201 | default: | |
5202 | break; | |
5203 | } | |
5204 | } | |
5205 | ||
b463a6f7 AK |
5206 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
5207 | { | |
5208 | struct vcpu_svm *svm = to_svm(vcpu); | |
5209 | struct vmcb_control_area *control = &svm->vmcb->control; | |
5210 | ||
5211 | control->exit_int_info = control->event_inj; | |
5212 | control->exit_int_info_err = control->event_inj_err; | |
5213 | control->event_inj = 0; | |
5214 | svm_complete_interrupts(svm); | |
5215 | } | |
5216 | ||
851ba692 | 5217 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 5218 | { |
a2fa3e9f | 5219 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 5220 | |
2041a06a JR |
5221 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
5222 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
5223 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
5224 | ||
cd3ff653 JR |
5225 | /* |
5226 | * A vmexit emulation is required before the vcpu can be executed | |
5227 | * again. | |
5228 | */ | |
5229 | if (unlikely(svm->nested.exit_required)) | |
5230 | return; | |
5231 | ||
a12713c2 LP |
5232 | /* |
5233 | * Disable singlestep if we're injecting an interrupt/exception. | |
5234 | * We don't want our modified rflags to be pushed on the stack where | |
5235 | * we might not be able to easily reset them if we disabled NMI | |
5236 | * singlestep later. | |
5237 | */ | |
5238 | if (svm->nmi_singlestep && svm->vmcb->control.event_inj) { | |
5239 | /* | |
5240 | * Event injection happens before external interrupts cause a | |
5241 | * vmexit and interrupts are disabled here, so smp_send_reschedule | |
5242 | * is enough to force an immediate vmexit. | |
5243 | */ | |
5244 | disable_nmi_singlestep(svm); | |
5245 | smp_send_reschedule(vcpu->cpu); | |
5246 | } | |
5247 | ||
e756fc62 | 5248 | pre_svm_run(svm); |
6aa8b732 | 5249 | |
649d6864 JR |
5250 | sync_lapic_to_cr8(vcpu); |
5251 | ||
cda0ffdd | 5252 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 5253 | |
04d2cc77 AK |
5254 | clgi(); |
5255 | ||
5256 | local_irq_enable(); | |
36241b8c | 5257 | |
6aa8b732 | 5258 | asm volatile ( |
7454766f AK |
5259 | "push %%" _ASM_BP "; \n\t" |
5260 | "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t" | |
5261 | "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t" | |
5262 | "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t" | |
5263 | "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t" | |
5264 | "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t" | |
5265 | "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 5266 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
5267 | "mov %c[r8](%[svm]), %%r8 \n\t" |
5268 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
5269 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
5270 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
5271 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
5272 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
5273 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
5274 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
5275 | #endif |
5276 | ||
6aa8b732 | 5277 | /* Enter guest mode */ |
7454766f AK |
5278 | "push %%" _ASM_AX " \n\t" |
5279 | "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t" | |
4ecac3fd AK |
5280 | __ex(SVM_VMLOAD) "\n\t" |
5281 | __ex(SVM_VMRUN) "\n\t" | |
5282 | __ex(SVM_VMSAVE) "\n\t" | |
7454766f | 5283 | "pop %%" _ASM_AX " \n\t" |
6aa8b732 AK |
5284 | |
5285 | /* Save guest registers, load host registers */ | |
7454766f AK |
5286 | "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t" |
5287 | "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t" | |
5288 | "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t" | |
5289 | "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t" | |
5290 | "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t" | |
5291 | "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 5292 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
5293 | "mov %%r8, %c[r8](%[svm]) \n\t" |
5294 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
5295 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
5296 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
5297 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
5298 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
5299 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
5300 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 5301 | #endif |
7454766f | 5302 | "pop %%" _ASM_BP |
6aa8b732 | 5303 | : |
fb3f0f51 | 5304 | : [svm]"a"(svm), |
6aa8b732 | 5305 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
5306 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
5307 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
5308 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
5309 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
5310 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
5311 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 5312 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
5313 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
5314 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
5315 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
5316 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
5317 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
5318 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
5319 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
5320 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 5321 | #endif |
54a08c04 LV |
5322 | : "cc", "memory" |
5323 | #ifdef CONFIG_X86_64 | |
7454766f | 5324 | , "rbx", "rcx", "rdx", "rsi", "rdi" |
54a08c04 | 5325 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
7454766f AK |
5326 | #else |
5327 | , "ebx", "ecx", "edx", "esi", "edi" | |
54a08c04 LV |
5328 | #endif |
5329 | ); | |
6aa8b732 | 5330 | |
82ca2d10 AK |
5331 | #ifdef CONFIG_X86_64 |
5332 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
5333 | #else | |
dacccfdd | 5334 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
5335 | #ifndef CONFIG_X86_32_LAZY_GS |
5336 | loadsegment(gs, svm->host.gs); | |
5337 | #endif | |
9581d442 | 5338 | #endif |
6aa8b732 AK |
5339 | |
5340 | reload_tss(vcpu); | |
5341 | ||
56ba47dd AK |
5342 | local_irq_disable(); |
5343 | ||
13c34e07 AK |
5344 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
5345 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
5346 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
5347 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
5348 | ||
3781c01c JR |
5349 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
5350 | kvm_before_handle_nmi(&svm->vcpu); | |
5351 | ||
5352 | stgi(); | |
5353 | ||
5354 | /* Any pending NMI will happen here */ | |
5355 | ||
5356 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
5357 | kvm_after_handle_nmi(&svm->vcpu); | |
5358 | ||
d7bf8221 JR |
5359 | sync_cr8_to_lapic(vcpu); |
5360 | ||
a2fa3e9f | 5361 | svm->next_rip = 0; |
9222be18 | 5362 | |
38e5e92f JR |
5363 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
5364 | ||
631bc487 GN |
5365 | /* if exit due to PF check for async PF */ |
5366 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
1261bfa3 | 5367 | svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); |
631bc487 | 5368 | |
6de4f3ad AK |
5369 | if (npt_enabled) { |
5370 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
5371 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
5372 | } | |
fe5913e4 JR |
5373 | |
5374 | /* | |
5375 | * We need to handle MC intercepts here before the vcpu has a chance to | |
5376 | * change the physical cpu | |
5377 | */ | |
5378 | if (unlikely(svm->vmcb->control.exit_code == | |
5379 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
5380 | svm_handle_mce(svm); | |
8d28fec4 RJ |
5381 | |
5382 | mark_all_clean(svm->vmcb); | |
6aa8b732 | 5383 | } |
c207aee4 | 5384 | STACK_FRAME_NON_STANDARD(svm_vcpu_run); |
6aa8b732 | 5385 | |
6aa8b732 AK |
5386 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
5387 | { | |
a2fa3e9f GH |
5388 | struct vcpu_svm *svm = to_svm(vcpu); |
5389 | ||
d0ec49d4 | 5390 | svm->vmcb->save.cr3 = __sme_set(root); |
dcca1a65 | 5391 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 5392 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
5393 | } |
5394 | ||
1c97f0a0 JR |
5395 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
5396 | { | |
5397 | struct vcpu_svm *svm = to_svm(vcpu); | |
5398 | ||
d0ec49d4 | 5399 | svm->vmcb->control.nested_cr3 = __sme_set(root); |
b2747166 | 5400 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
5401 | |
5402 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 5403 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 5404 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 5405 | |
f40f6a45 | 5406 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
5407 | } |
5408 | ||
6aa8b732 AK |
5409 | static int is_disabled(void) |
5410 | { | |
6031a61c JR |
5411 | u64 vm_cr; |
5412 | ||
5413 | rdmsrl(MSR_VM_CR, vm_cr); | |
5414 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
5415 | return 1; | |
5416 | ||
6aa8b732 AK |
5417 | return 0; |
5418 | } | |
5419 | ||
102d8325 IM |
5420 | static void |
5421 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
5422 | { | |
5423 | /* | |
5424 | * Patch in the VMMCALL instruction: | |
5425 | */ | |
5426 | hypercall[0] = 0x0f; | |
5427 | hypercall[1] = 0x01; | |
5428 | hypercall[2] = 0xd9; | |
102d8325 IM |
5429 | } |
5430 | ||
002c7f7c YS |
5431 | static void svm_check_processor_compat(void *rtn) |
5432 | { | |
5433 | *(int *)rtn = 0; | |
5434 | } | |
5435 | ||
774ead3a AK |
5436 | static bool svm_cpu_has_accelerated_tpr(void) |
5437 | { | |
5438 | return false; | |
5439 | } | |
5440 | ||
6d396b55 PB |
5441 | static bool svm_has_high_real_mode_segbase(void) |
5442 | { | |
5443 | return true; | |
5444 | } | |
5445 | ||
fc07e76a PB |
5446 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
5447 | { | |
5448 | return 0; | |
5449 | } | |
5450 | ||
0e851880 SY |
5451 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
5452 | { | |
6092d3d3 JR |
5453 | struct vcpu_svm *svm = to_svm(vcpu); |
5454 | ||
5455 | /* Update nrips enabled cache */ | |
d6321d49 | 5456 | svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS); |
46781eae SS |
5457 | |
5458 | if (!kvm_vcpu_apicv_active(vcpu)) | |
5459 | return; | |
5460 | ||
1b4d56b8 | 5461 | guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC); |
0e851880 SY |
5462 | } |
5463 | ||
d4330ef2 JR |
5464 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
5465 | { | |
c2c63a49 | 5466 | switch (func) { |
46781eae SS |
5467 | case 0x1: |
5468 | if (avic) | |
5469 | entry->ecx &= ~bit(X86_FEATURE_X2APIC); | |
5470 | break; | |
4c62a2dc JR |
5471 | case 0x80000001: |
5472 | if (nested) | |
5473 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
5474 | break; | |
c2c63a49 JR |
5475 | case 0x8000000A: |
5476 | entry->eax = 1; /* SVM revision 1 */ | |
5477 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
5478 | ASID emulation to nested SVM */ | |
5479 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
5480 | entry->edx = 0; /* Per default do not support any |
5481 | additional features */ | |
5482 | ||
5483 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 5484 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 5485 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 5486 | |
3d4aeaad JR |
5487 | /* Support NPT for the guest if enabled */ |
5488 | if (npt_enabled) | |
5489 | entry->edx |= SVM_FEATURE_NPT; | |
5490 | ||
c2c63a49 | 5491 | break; |
8765d753 BS |
5492 | case 0x8000001F: |
5493 | /* Support memory encryption cpuid if host supports it */ | |
5494 | if (boot_cpu_has(X86_FEATURE_SEV)) | |
5495 | cpuid(0x8000001f, &entry->eax, &entry->ebx, | |
5496 | &entry->ecx, &entry->edx); | |
5497 | ||
c2c63a49 | 5498 | } |
d4330ef2 JR |
5499 | } |
5500 | ||
17cc3935 | 5501 | static int svm_get_lpage_level(void) |
344f414f | 5502 | { |
17cc3935 | 5503 | return PT_PDPE_LEVEL; |
344f414f JR |
5504 | } |
5505 | ||
4e47c7a6 SY |
5506 | static bool svm_rdtscp_supported(void) |
5507 | { | |
46896c73 | 5508 | return boot_cpu_has(X86_FEATURE_RDTSCP); |
4e47c7a6 SY |
5509 | } |
5510 | ||
ad756a16 MJ |
5511 | static bool svm_invpcid_supported(void) |
5512 | { | |
5513 | return false; | |
5514 | } | |
5515 | ||
93c4adc7 PB |
5516 | static bool svm_mpx_supported(void) |
5517 | { | |
5518 | return false; | |
5519 | } | |
5520 | ||
55412b2e WL |
5521 | static bool svm_xsaves_supported(void) |
5522 | { | |
5523 | return false; | |
5524 | } | |
5525 | ||
f5f48ee1 SY |
5526 | static bool svm_has_wbinvd_exit(void) |
5527 | { | |
5528 | return true; | |
5529 | } | |
5530 | ||
8061252e | 5531 | #define PRE_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 5532 | .stage = X86_ICPT_PRE_EXCEPT, } |
cfec82cb | 5533 | #define POST_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 5534 | .stage = X86_ICPT_POST_EXCEPT, } |
d7eb8203 | 5535 | #define POST_MEM(exit) { .exit_code = (exit), \ |
40e19b51 | 5536 | .stage = X86_ICPT_POST_MEMACCESS, } |
cfec82cb | 5537 | |
09941fbb | 5538 | static const struct __x86_intercept { |
cfec82cb JR |
5539 | u32 exit_code; |
5540 | enum x86_intercept_stage stage; | |
cfec82cb JR |
5541 | } x86_intercept_map[] = { |
5542 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
5543 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
5544 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
5545 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
5546 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
5547 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
5548 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
5549 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
5550 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
5551 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
5552 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
5553 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
5554 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
5555 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
5556 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
5557 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
5558 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
5559 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
5560 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
5561 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
5562 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
5563 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
5564 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
5565 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
5566 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
5567 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
5568 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
5569 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
5570 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
5571 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
5572 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
5573 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
5574 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
5575 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
5576 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
5577 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
5578 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
5579 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
5580 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
5581 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
5582 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
5583 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
5584 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
5585 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
5586 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
5587 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
cfec82cb JR |
5588 | }; |
5589 | ||
8061252e | 5590 | #undef PRE_EX |
cfec82cb | 5591 | #undef POST_EX |
d7eb8203 | 5592 | #undef POST_MEM |
cfec82cb | 5593 | |
8a76d7f2 JR |
5594 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
5595 | struct x86_instruction_info *info, | |
5596 | enum x86_intercept_stage stage) | |
5597 | { | |
cfec82cb JR |
5598 | struct vcpu_svm *svm = to_svm(vcpu); |
5599 | int vmexit, ret = X86EMUL_CONTINUE; | |
5600 | struct __x86_intercept icpt_info; | |
5601 | struct vmcb *vmcb = svm->vmcb; | |
5602 | ||
5603 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
5604 | goto out; | |
5605 | ||
5606 | icpt_info = x86_intercept_map[info->intercept]; | |
5607 | ||
40e19b51 | 5608 | if (stage != icpt_info.stage) |
cfec82cb JR |
5609 | goto out; |
5610 | ||
5611 | switch (icpt_info.exit_code) { | |
5612 | case SVM_EXIT_READ_CR0: | |
5613 | if (info->intercept == x86_intercept_cr_read) | |
5614 | icpt_info.exit_code += info->modrm_reg; | |
5615 | break; | |
5616 | case SVM_EXIT_WRITE_CR0: { | |
5617 | unsigned long cr0, val; | |
5618 | u64 intercept; | |
5619 | ||
5620 | if (info->intercept == x86_intercept_cr_write) | |
5621 | icpt_info.exit_code += info->modrm_reg; | |
5622 | ||
62baf44c JK |
5623 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 || |
5624 | info->intercept == x86_intercept_clts) | |
cfec82cb JR |
5625 | break; |
5626 | ||
5627 | intercept = svm->nested.intercept; | |
5628 | ||
5629 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
5630 | break; | |
5631 | ||
5632 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
5633 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
5634 | ||
5635 | if (info->intercept == x86_intercept_lmsw) { | |
5636 | cr0 &= 0xfUL; | |
5637 | val &= 0xfUL; | |
5638 | /* lmsw can't clear PE - catch this here */ | |
5639 | if (cr0 & X86_CR0_PE) | |
5640 | val |= X86_CR0_PE; | |
5641 | } | |
5642 | ||
5643 | if (cr0 ^ val) | |
5644 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
5645 | ||
5646 | break; | |
5647 | } | |
3b88e41a JR |
5648 | case SVM_EXIT_READ_DR0: |
5649 | case SVM_EXIT_WRITE_DR0: | |
5650 | icpt_info.exit_code += info->modrm_reg; | |
5651 | break; | |
8061252e JR |
5652 | case SVM_EXIT_MSR: |
5653 | if (info->intercept == x86_intercept_wrmsr) | |
5654 | vmcb->control.exit_info_1 = 1; | |
5655 | else | |
5656 | vmcb->control.exit_info_1 = 0; | |
5657 | break; | |
bf608f88 JR |
5658 | case SVM_EXIT_PAUSE: |
5659 | /* | |
5660 | * We get this for NOP only, but pause | |
5661 | * is rep not, check this here | |
5662 | */ | |
5663 | if (info->rep_prefix != REPE_PREFIX) | |
5664 | goto out; | |
49a8afca | 5665 | break; |
f6511935 JR |
5666 | case SVM_EXIT_IOIO: { |
5667 | u64 exit_info; | |
5668 | u32 bytes; | |
5669 | ||
f6511935 JR |
5670 | if (info->intercept == x86_intercept_in || |
5671 | info->intercept == x86_intercept_ins) { | |
6cbc5f5a JK |
5672 | exit_info = ((info->src_val & 0xffff) << 16) | |
5673 | SVM_IOIO_TYPE_MASK; | |
f6511935 | 5674 | bytes = info->dst_bytes; |
6493f157 | 5675 | } else { |
6cbc5f5a | 5676 | exit_info = (info->dst_val & 0xffff) << 16; |
6493f157 | 5677 | bytes = info->src_bytes; |
f6511935 JR |
5678 | } |
5679 | ||
5680 | if (info->intercept == x86_intercept_outs || | |
5681 | info->intercept == x86_intercept_ins) | |
5682 | exit_info |= SVM_IOIO_STR_MASK; | |
5683 | ||
5684 | if (info->rep_prefix) | |
5685 | exit_info |= SVM_IOIO_REP_MASK; | |
5686 | ||
5687 | bytes = min(bytes, 4u); | |
5688 | ||
5689 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
5690 | ||
5691 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
5692 | ||
5693 | vmcb->control.exit_info_1 = exit_info; | |
5694 | vmcb->control.exit_info_2 = info->next_rip; | |
5695 | ||
5696 | break; | |
5697 | } | |
cfec82cb JR |
5698 | default: |
5699 | break; | |
5700 | } | |
5701 | ||
f104765b BD |
5702 | /* TODO: Advertise NRIPS to guest hypervisor unconditionally */ |
5703 | if (static_cpu_has(X86_FEATURE_NRIPS)) | |
5704 | vmcb->control.next_rip = info->next_rip; | |
cfec82cb JR |
5705 | vmcb->control.exit_code = icpt_info.exit_code; |
5706 | vmexit = nested_svm_exit_handled(svm); | |
5707 | ||
5708 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
5709 | : X86EMUL_CONTINUE; | |
5710 | ||
5711 | out: | |
5712 | return ret; | |
8a76d7f2 JR |
5713 | } |
5714 | ||
a547c6db YZ |
5715 | static void svm_handle_external_intr(struct kvm_vcpu *vcpu) |
5716 | { | |
5717 | local_irq_enable(); | |
f2485b3e PB |
5718 | /* |
5719 | * We must have an instruction with interrupts enabled, so | |
5720 | * the timer interrupt isn't delayed by the interrupt shadow. | |
5721 | */ | |
5722 | asm("nop"); | |
5723 | local_irq_disable(); | |
a547c6db YZ |
5724 | } |
5725 | ||
ae97a3b8 RK |
5726 | static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu) |
5727 | { | |
5728 | } | |
5729 | ||
be8ca170 SS |
5730 | static inline void avic_post_state_restore(struct kvm_vcpu *vcpu) |
5731 | { | |
5732 | if (avic_handle_apic_id_update(vcpu) != 0) | |
5733 | return; | |
5734 | if (avic_handle_dfr_update(vcpu) != 0) | |
5735 | return; | |
5736 | avic_handle_ldr_update(vcpu); | |
5737 | } | |
5738 | ||
74f16909 BP |
5739 | static void svm_setup_mce(struct kvm_vcpu *vcpu) |
5740 | { | |
5741 | /* [63:9] are reserved. */ | |
5742 | vcpu->arch.mcg_cap &= 0x1ff; | |
5743 | } | |
5744 | ||
72d7b374 LP |
5745 | static int svm_smi_allowed(struct kvm_vcpu *vcpu) |
5746 | { | |
05cade71 LP |
5747 | struct vcpu_svm *svm = to_svm(vcpu); |
5748 | ||
5749 | /* Per APM Vol.2 15.22.2 "Response to SMI" */ | |
5750 | if (!gif_set(svm)) | |
5751 | return 0; | |
5752 | ||
5753 | if (is_guest_mode(&svm->vcpu) && | |
5754 | svm->nested.intercept & (1ULL << INTERCEPT_SMI)) { | |
5755 | /* TODO: Might need to set exit_info_1 and exit_info_2 here */ | |
5756 | svm->vmcb->control.exit_code = SVM_EXIT_SMI; | |
5757 | svm->nested.exit_required = true; | |
5758 | return 0; | |
5759 | } | |
5760 | ||
72d7b374 LP |
5761 | return 1; |
5762 | } | |
5763 | ||
0234bf88 LP |
5764 | static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) |
5765 | { | |
05cade71 LP |
5766 | struct vcpu_svm *svm = to_svm(vcpu); |
5767 | int ret; | |
5768 | ||
5769 | if (is_guest_mode(vcpu)) { | |
5770 | /* FED8h - SVM Guest */ | |
5771 | put_smstate(u64, smstate, 0x7ed8, 1); | |
5772 | /* FEE0h - SVM Guest VMCB Physical Address */ | |
5773 | put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb); | |
5774 | ||
5775 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; | |
5776 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
5777 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
5778 | ||
5779 | ret = nested_svm_vmexit(svm); | |
5780 | if (ret) | |
5781 | return ret; | |
5782 | } | |
0234bf88 LP |
5783 | return 0; |
5784 | } | |
5785 | ||
5786 | static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase) | |
5787 | { | |
05cade71 LP |
5788 | struct vcpu_svm *svm = to_svm(vcpu); |
5789 | struct vmcb *nested_vmcb; | |
5790 | struct page *page; | |
5791 | struct { | |
5792 | u64 guest; | |
5793 | u64 vmcb; | |
5794 | } svm_state_save; | |
5795 | int ret; | |
5796 | ||
5797 | ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save, | |
5798 | sizeof(svm_state_save)); | |
5799 | if (ret) | |
5800 | return ret; | |
5801 | ||
5802 | if (svm_state_save.guest) { | |
5803 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
5804 | nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page); | |
5805 | if (nested_vmcb) | |
5806 | enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page); | |
5807 | else | |
5808 | ret = 1; | |
5809 | vcpu->arch.hflags |= HF_SMM_MASK; | |
5810 | } | |
5811 | return ret; | |
0234bf88 LP |
5812 | } |
5813 | ||
cc3d967f LP |
5814 | static int enable_smi_window(struct kvm_vcpu *vcpu) |
5815 | { | |
5816 | struct vcpu_svm *svm = to_svm(vcpu); | |
5817 | ||
5818 | if (!gif_set(svm)) { | |
5819 | if (vgif_enabled(svm)) | |
5820 | set_intercept(svm, INTERCEPT_STGI); | |
5821 | /* STGI will cause a vm exit */ | |
5822 | return 1; | |
5823 | } | |
5824 | return 0; | |
5825 | } | |
5826 | ||
1654efcb BS |
5827 | static int sev_asid_new(void) |
5828 | { | |
5829 | int pos; | |
5830 | ||
5831 | /* | |
5832 | * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid. | |
5833 | */ | |
5834 | pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1); | |
5835 | if (pos >= max_sev_asid) | |
5836 | return -EBUSY; | |
5837 | ||
5838 | set_bit(pos, sev_asid_bitmap); | |
5839 | return pos + 1; | |
5840 | } | |
5841 | ||
5842 | static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp) | |
5843 | { | |
5844 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
5845 | int asid, ret; | |
5846 | ||
5847 | ret = -EBUSY; | |
5848 | asid = sev_asid_new(); | |
5849 | if (asid < 0) | |
5850 | return ret; | |
5851 | ||
5852 | ret = sev_platform_init(&argp->error); | |
5853 | if (ret) | |
5854 | goto e_free; | |
5855 | ||
5856 | sev->active = true; | |
5857 | sev->asid = asid; | |
1e80fdc0 | 5858 | INIT_LIST_HEAD(&sev->regions_list); |
1654efcb BS |
5859 | |
5860 | return 0; | |
5861 | ||
5862 | e_free: | |
5863 | __sev_asid_free(asid); | |
5864 | return ret; | |
5865 | } | |
5866 | ||
59414c98 BS |
5867 | static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error) |
5868 | { | |
5869 | struct sev_data_activate *data; | |
5870 | int asid = sev_get_asid(kvm); | |
5871 | int ret; | |
5872 | ||
5873 | wbinvd_on_all_cpus(); | |
5874 | ||
5875 | ret = sev_guest_df_flush(error); | |
5876 | if (ret) | |
5877 | return ret; | |
5878 | ||
5879 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
5880 | if (!data) | |
5881 | return -ENOMEM; | |
5882 | ||
5883 | /* activate ASID on the given handle */ | |
5884 | data->handle = handle; | |
5885 | data->asid = asid; | |
5886 | ret = sev_guest_activate(data, error); | |
5887 | kfree(data); | |
5888 | ||
5889 | return ret; | |
5890 | } | |
5891 | ||
89c50580 | 5892 | static int __sev_issue_cmd(int fd, int id, void *data, int *error) |
59414c98 BS |
5893 | { |
5894 | struct fd f; | |
5895 | int ret; | |
5896 | ||
5897 | f = fdget(fd); | |
5898 | if (!f.file) | |
5899 | return -EBADF; | |
5900 | ||
5901 | ret = sev_issue_cmd_external_user(f.file, id, data, error); | |
5902 | ||
5903 | fdput(f); | |
5904 | return ret; | |
5905 | } | |
5906 | ||
89c50580 BS |
5907 | static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error) |
5908 | { | |
5909 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
5910 | ||
5911 | return __sev_issue_cmd(sev->fd, id, data, error); | |
5912 | } | |
5913 | ||
59414c98 BS |
5914 | static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp) |
5915 | { | |
5916 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
5917 | struct sev_data_launch_start *start; | |
5918 | struct kvm_sev_launch_start params; | |
5919 | void *dh_blob, *session_blob; | |
5920 | int *error = &argp->error; | |
5921 | int ret; | |
5922 | ||
5923 | if (!sev_guest(kvm)) | |
5924 | return -ENOTTY; | |
5925 | ||
5926 | if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params))) | |
5927 | return -EFAULT; | |
5928 | ||
5929 | start = kzalloc(sizeof(*start), GFP_KERNEL); | |
5930 | if (!start) | |
5931 | return -ENOMEM; | |
5932 | ||
5933 | dh_blob = NULL; | |
5934 | if (params.dh_uaddr) { | |
5935 | dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len); | |
5936 | if (IS_ERR(dh_blob)) { | |
5937 | ret = PTR_ERR(dh_blob); | |
5938 | goto e_free; | |
5939 | } | |
5940 | ||
5941 | start->dh_cert_address = __sme_set(__pa(dh_blob)); | |
5942 | start->dh_cert_len = params.dh_len; | |
5943 | } | |
5944 | ||
5945 | session_blob = NULL; | |
5946 | if (params.session_uaddr) { | |
5947 | session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len); | |
5948 | if (IS_ERR(session_blob)) { | |
5949 | ret = PTR_ERR(session_blob); | |
5950 | goto e_free_dh; | |
5951 | } | |
5952 | ||
5953 | start->session_address = __sme_set(__pa(session_blob)); | |
5954 | start->session_len = params.session_len; | |
5955 | } | |
5956 | ||
5957 | start->handle = params.handle; | |
5958 | start->policy = params.policy; | |
5959 | ||
5960 | /* create memory encryption context */ | |
89c50580 | 5961 | ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error); |
59414c98 BS |
5962 | if (ret) |
5963 | goto e_free_session; | |
5964 | ||
5965 | /* Bind ASID to this guest */ | |
5966 | ret = sev_bind_asid(kvm, start->handle, error); | |
5967 | if (ret) | |
5968 | goto e_free_session; | |
5969 | ||
5970 | /* return handle to userspace */ | |
5971 | params.handle = start->handle; | |
5972 | if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) { | |
5973 | sev_unbind_asid(kvm, start->handle); | |
5974 | ret = -EFAULT; | |
5975 | goto e_free_session; | |
5976 | } | |
5977 | ||
5978 | sev->handle = start->handle; | |
5979 | sev->fd = argp->sev_fd; | |
5980 | ||
5981 | e_free_session: | |
5982 | kfree(session_blob); | |
5983 | e_free_dh: | |
5984 | kfree(dh_blob); | |
5985 | e_free: | |
5986 | kfree(start); | |
5987 | return ret; | |
5988 | } | |
5989 | ||
89c50580 BS |
5990 | static int get_num_contig_pages(int idx, struct page **inpages, |
5991 | unsigned long npages) | |
5992 | { | |
5993 | unsigned long paddr, next_paddr; | |
5994 | int i = idx + 1, pages = 1; | |
5995 | ||
5996 | /* find the number of contiguous pages starting from idx */ | |
5997 | paddr = __sme_page_pa(inpages[idx]); | |
5998 | while (i < npages) { | |
5999 | next_paddr = __sme_page_pa(inpages[i++]); | |
6000 | if ((paddr + PAGE_SIZE) == next_paddr) { | |
6001 | pages++; | |
6002 | paddr = next_paddr; | |
6003 | continue; | |
6004 | } | |
6005 | break; | |
6006 | } | |
6007 | ||
6008 | return pages; | |
6009 | } | |
6010 | ||
6011 | static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp) | |
6012 | { | |
6013 | unsigned long vaddr, vaddr_end, next_vaddr, npages, size; | |
6014 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
6015 | struct kvm_sev_launch_update_data params; | |
6016 | struct sev_data_launch_update_data *data; | |
6017 | struct page **inpages; | |
6018 | int i, ret, pages; | |
6019 | ||
6020 | if (!sev_guest(kvm)) | |
6021 | return -ENOTTY; | |
6022 | ||
6023 | if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params))) | |
6024 | return -EFAULT; | |
6025 | ||
6026 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
6027 | if (!data) | |
6028 | return -ENOMEM; | |
6029 | ||
6030 | vaddr = params.uaddr; | |
6031 | size = params.len; | |
6032 | vaddr_end = vaddr + size; | |
6033 | ||
6034 | /* Lock the user memory. */ | |
6035 | inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1); | |
6036 | if (!inpages) { | |
6037 | ret = -ENOMEM; | |
6038 | goto e_free; | |
6039 | } | |
6040 | ||
6041 | /* | |
6042 | * The LAUNCH_UPDATE command will perform in-place encryption of the | |
6043 | * memory content (i.e it will write the same memory region with C=1). | |
6044 | * It's possible that the cache may contain the data with C=0, i.e., | |
6045 | * unencrypted so invalidate it first. | |
6046 | */ | |
6047 | sev_clflush_pages(inpages, npages); | |
6048 | ||
6049 | for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) { | |
6050 | int offset, len; | |
6051 | ||
6052 | /* | |
6053 | * If the user buffer is not page-aligned, calculate the offset | |
6054 | * within the page. | |
6055 | */ | |
6056 | offset = vaddr & (PAGE_SIZE - 1); | |
6057 | ||
6058 | /* Calculate the number of pages that can be encrypted in one go. */ | |
6059 | pages = get_num_contig_pages(i, inpages, npages); | |
6060 | ||
6061 | len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size); | |
6062 | ||
6063 | data->handle = sev->handle; | |
6064 | data->len = len; | |
6065 | data->address = __sme_page_pa(inpages[i]) + offset; | |
6066 | ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error); | |
6067 | if (ret) | |
6068 | goto e_unpin; | |
6069 | ||
6070 | size -= len; | |
6071 | next_vaddr = vaddr + len; | |
6072 | } | |
6073 | ||
6074 | e_unpin: | |
6075 | /* content of memory is updated, mark pages dirty */ | |
6076 | for (i = 0; i < npages; i++) { | |
6077 | set_page_dirty_lock(inpages[i]); | |
6078 | mark_page_accessed(inpages[i]); | |
6079 | } | |
6080 | /* unlock the user pages */ | |
6081 | sev_unpin_memory(kvm, inpages, npages); | |
6082 | e_free: | |
6083 | kfree(data); | |
6084 | return ret; | |
6085 | } | |
6086 | ||
0d0736f7 BS |
6087 | static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp) |
6088 | { | |
6089 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
6090 | struct sev_data_launch_measure *data; | |
6091 | struct kvm_sev_launch_measure params; | |
6092 | void *blob = NULL; | |
6093 | int ret; | |
6094 | ||
6095 | if (!sev_guest(kvm)) | |
6096 | return -ENOTTY; | |
6097 | ||
6098 | if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params))) | |
6099 | return -EFAULT; | |
6100 | ||
6101 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
6102 | if (!data) | |
6103 | return -ENOMEM; | |
6104 | ||
6105 | /* User wants to query the blob length */ | |
6106 | if (!params.len) | |
6107 | goto cmd; | |
6108 | ||
6109 | if (params.uaddr) { | |
6110 | if (params.len > SEV_FW_BLOB_MAX_SIZE) { | |
6111 | ret = -EINVAL; | |
6112 | goto e_free; | |
6113 | } | |
6114 | ||
6115 | if (!access_ok(VERIFY_WRITE, params.uaddr, params.len)) { | |
6116 | ret = -EFAULT; | |
6117 | goto e_free; | |
6118 | } | |
6119 | ||
6120 | ret = -ENOMEM; | |
6121 | blob = kmalloc(params.len, GFP_KERNEL); | |
6122 | if (!blob) | |
6123 | goto e_free; | |
6124 | ||
6125 | data->address = __psp_pa(blob); | |
6126 | data->len = params.len; | |
6127 | } | |
6128 | ||
6129 | cmd: | |
6130 | data->handle = sev->handle; | |
6131 | ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error); | |
6132 | ||
6133 | /* | |
6134 | * If we query the session length, FW responded with expected data. | |
6135 | */ | |
6136 | if (!params.len) | |
6137 | goto done; | |
6138 | ||
6139 | if (ret) | |
6140 | goto e_free_blob; | |
6141 | ||
6142 | if (blob) { | |
6143 | if (copy_to_user((void __user *)(uintptr_t)params.uaddr, blob, params.len)) | |
6144 | ret = -EFAULT; | |
6145 | } | |
6146 | ||
6147 | done: | |
6148 | params.len = data->len; | |
6149 | if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) | |
6150 | ret = -EFAULT; | |
6151 | e_free_blob: | |
6152 | kfree(blob); | |
6153 | e_free: | |
6154 | kfree(data); | |
6155 | return ret; | |
6156 | } | |
6157 | ||
5bdb0e2f BS |
6158 | static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp) |
6159 | { | |
6160 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
6161 | struct sev_data_launch_finish *data; | |
6162 | int ret; | |
6163 | ||
6164 | if (!sev_guest(kvm)) | |
6165 | return -ENOTTY; | |
6166 | ||
6167 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
6168 | if (!data) | |
6169 | return -ENOMEM; | |
6170 | ||
6171 | data->handle = sev->handle; | |
6172 | ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error); | |
6173 | ||
6174 | kfree(data); | |
6175 | return ret; | |
6176 | } | |
6177 | ||
255d9e75 BS |
6178 | static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp) |
6179 | { | |
6180 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
6181 | struct kvm_sev_guest_status params; | |
6182 | struct sev_data_guest_status *data; | |
6183 | int ret; | |
6184 | ||
6185 | if (!sev_guest(kvm)) | |
6186 | return -ENOTTY; | |
6187 | ||
6188 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
6189 | if (!data) | |
6190 | return -ENOMEM; | |
6191 | ||
6192 | data->handle = sev->handle; | |
6193 | ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error); | |
6194 | if (ret) | |
6195 | goto e_free; | |
6196 | ||
6197 | params.policy = data->policy; | |
6198 | params.state = data->state; | |
6199 | params.handle = data->handle; | |
6200 | ||
6201 | if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) | |
6202 | ret = -EFAULT; | |
6203 | e_free: | |
6204 | kfree(data); | |
6205 | return ret; | |
6206 | } | |
6207 | ||
24f41fb2 BS |
6208 | static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src, |
6209 | unsigned long dst, int size, | |
6210 | int *error, bool enc) | |
6211 | { | |
6212 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
6213 | struct sev_data_dbg *data; | |
6214 | int ret; | |
6215 | ||
6216 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
6217 | if (!data) | |
6218 | return -ENOMEM; | |
6219 | ||
6220 | data->handle = sev->handle; | |
6221 | data->dst_addr = dst; | |
6222 | data->src_addr = src; | |
6223 | data->len = size; | |
6224 | ||
6225 | ret = sev_issue_cmd(kvm, | |
6226 | enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT, | |
6227 | data, error); | |
6228 | kfree(data); | |
6229 | return ret; | |
6230 | } | |
6231 | ||
6232 | static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr, | |
6233 | unsigned long dst_paddr, int sz, int *err) | |
6234 | { | |
6235 | int offset; | |
6236 | ||
6237 | /* | |
6238 | * Its safe to read more than we are asked, caller should ensure that | |
6239 | * destination has enough space. | |
6240 | */ | |
6241 | src_paddr = round_down(src_paddr, 16); | |
6242 | offset = src_paddr & 15; | |
6243 | sz = round_up(sz + offset, 16); | |
6244 | ||
6245 | return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false); | |
6246 | } | |
6247 | ||
6248 | static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr, | |
6249 | unsigned long __user dst_uaddr, | |
6250 | unsigned long dst_paddr, | |
6251 | int size, int *err) | |
6252 | { | |
6253 | struct page *tpage = NULL; | |
6254 | int ret, offset; | |
6255 | ||
6256 | /* if inputs are not 16-byte then use intermediate buffer */ | |
6257 | if (!IS_ALIGNED(dst_paddr, 16) || | |
6258 | !IS_ALIGNED(paddr, 16) || | |
6259 | !IS_ALIGNED(size, 16)) { | |
6260 | tpage = (void *)alloc_page(GFP_KERNEL); | |
6261 | if (!tpage) | |
6262 | return -ENOMEM; | |
6263 | ||
6264 | dst_paddr = __sme_page_pa(tpage); | |
6265 | } | |
6266 | ||
6267 | ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err); | |
6268 | if (ret) | |
6269 | goto e_free; | |
6270 | ||
6271 | if (tpage) { | |
6272 | offset = paddr & 15; | |
6273 | if (copy_to_user((void __user *)(uintptr_t)dst_uaddr, | |
6274 | page_address(tpage) + offset, size)) | |
6275 | ret = -EFAULT; | |
6276 | } | |
6277 | ||
6278 | e_free: | |
6279 | if (tpage) | |
6280 | __free_page(tpage); | |
6281 | ||
6282 | return ret; | |
6283 | } | |
6284 | ||
7d1594f5 BS |
6285 | static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr, |
6286 | unsigned long __user vaddr, | |
6287 | unsigned long dst_paddr, | |
6288 | unsigned long __user dst_vaddr, | |
6289 | int size, int *error) | |
6290 | { | |
6291 | struct page *src_tpage = NULL; | |
6292 | struct page *dst_tpage = NULL; | |
6293 | int ret, len = size; | |
6294 | ||
6295 | /* If source buffer is not aligned then use an intermediate buffer */ | |
6296 | if (!IS_ALIGNED(vaddr, 16)) { | |
6297 | src_tpage = alloc_page(GFP_KERNEL); | |
6298 | if (!src_tpage) | |
6299 | return -ENOMEM; | |
6300 | ||
6301 | if (copy_from_user(page_address(src_tpage), | |
6302 | (void __user *)(uintptr_t)vaddr, size)) { | |
6303 | __free_page(src_tpage); | |
6304 | return -EFAULT; | |
6305 | } | |
6306 | ||
6307 | paddr = __sme_page_pa(src_tpage); | |
6308 | } | |
6309 | ||
6310 | /* | |
6311 | * If destination buffer or length is not aligned then do read-modify-write: | |
6312 | * - decrypt destination in an intermediate buffer | |
6313 | * - copy the source buffer in an intermediate buffer | |
6314 | * - use the intermediate buffer as source buffer | |
6315 | */ | |
6316 | if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) { | |
6317 | int dst_offset; | |
6318 | ||
6319 | dst_tpage = alloc_page(GFP_KERNEL); | |
6320 | if (!dst_tpage) { | |
6321 | ret = -ENOMEM; | |
6322 | goto e_free; | |
6323 | } | |
6324 | ||
6325 | ret = __sev_dbg_decrypt(kvm, dst_paddr, | |
6326 | __sme_page_pa(dst_tpage), size, error); | |
6327 | if (ret) | |
6328 | goto e_free; | |
6329 | ||
6330 | /* | |
6331 | * If source is kernel buffer then use memcpy() otherwise | |
6332 | * copy_from_user(). | |
6333 | */ | |
6334 | dst_offset = dst_paddr & 15; | |
6335 | ||
6336 | if (src_tpage) | |
6337 | memcpy(page_address(dst_tpage) + dst_offset, | |
6338 | page_address(src_tpage), size); | |
6339 | else { | |
6340 | if (copy_from_user(page_address(dst_tpage) + dst_offset, | |
6341 | (void __user *)(uintptr_t)vaddr, size)) { | |
6342 | ret = -EFAULT; | |
6343 | goto e_free; | |
6344 | } | |
6345 | } | |
6346 | ||
6347 | paddr = __sme_page_pa(dst_tpage); | |
6348 | dst_paddr = round_down(dst_paddr, 16); | |
6349 | len = round_up(size, 16); | |
6350 | } | |
6351 | ||
6352 | ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true); | |
6353 | ||
6354 | e_free: | |
6355 | if (src_tpage) | |
6356 | __free_page(src_tpage); | |
6357 | if (dst_tpage) | |
6358 | __free_page(dst_tpage); | |
6359 | return ret; | |
6360 | } | |
6361 | ||
24f41fb2 BS |
6362 | static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec) |
6363 | { | |
6364 | unsigned long vaddr, vaddr_end, next_vaddr; | |
6365 | unsigned long dst_vaddr, dst_vaddr_end; | |
6366 | struct page **src_p, **dst_p; | |
6367 | struct kvm_sev_dbg debug; | |
6368 | unsigned long n; | |
6369 | int ret, size; | |
6370 | ||
6371 | if (!sev_guest(kvm)) | |
6372 | return -ENOTTY; | |
6373 | ||
6374 | if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug))) | |
6375 | return -EFAULT; | |
6376 | ||
6377 | vaddr = debug.src_uaddr; | |
6378 | size = debug.len; | |
6379 | vaddr_end = vaddr + size; | |
6380 | dst_vaddr = debug.dst_uaddr; | |
6381 | dst_vaddr_end = dst_vaddr + size; | |
6382 | ||
6383 | for (; vaddr < vaddr_end; vaddr = next_vaddr) { | |
6384 | int len, s_off, d_off; | |
6385 | ||
6386 | /* lock userspace source and destination page */ | |
6387 | src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0); | |
6388 | if (!src_p) | |
6389 | return -EFAULT; | |
6390 | ||
6391 | dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1); | |
6392 | if (!dst_p) { | |
6393 | sev_unpin_memory(kvm, src_p, n); | |
6394 | return -EFAULT; | |
6395 | } | |
6396 | ||
6397 | /* | |
6398 | * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the | |
6399 | * memory content (i.e it will write the same memory region with C=1). | |
6400 | * It's possible that the cache may contain the data with C=0, i.e., | |
6401 | * unencrypted so invalidate it first. | |
6402 | */ | |
6403 | sev_clflush_pages(src_p, 1); | |
6404 | sev_clflush_pages(dst_p, 1); | |
6405 | ||
6406 | /* | |
6407 | * Since user buffer may not be page aligned, calculate the | |
6408 | * offset within the page. | |
6409 | */ | |
6410 | s_off = vaddr & ~PAGE_MASK; | |
6411 | d_off = dst_vaddr & ~PAGE_MASK; | |
6412 | len = min_t(size_t, (PAGE_SIZE - s_off), size); | |
6413 | ||
7d1594f5 BS |
6414 | if (dec) |
6415 | ret = __sev_dbg_decrypt_user(kvm, | |
6416 | __sme_page_pa(src_p[0]) + s_off, | |
6417 | dst_vaddr, | |
6418 | __sme_page_pa(dst_p[0]) + d_off, | |
6419 | len, &argp->error); | |
6420 | else | |
6421 | ret = __sev_dbg_encrypt_user(kvm, | |
6422 | __sme_page_pa(src_p[0]) + s_off, | |
6423 | vaddr, | |
6424 | __sme_page_pa(dst_p[0]) + d_off, | |
6425 | dst_vaddr, | |
6426 | len, &argp->error); | |
24f41fb2 BS |
6427 | |
6428 | sev_unpin_memory(kvm, src_p, 1); | |
6429 | sev_unpin_memory(kvm, dst_p, 1); | |
6430 | ||
6431 | if (ret) | |
6432 | goto err; | |
6433 | ||
6434 | next_vaddr = vaddr + len; | |
6435 | dst_vaddr = dst_vaddr + len; | |
6436 | size -= len; | |
6437 | } | |
6438 | err: | |
6439 | return ret; | |
6440 | } | |
6441 | ||
9f5b5b95 BS |
6442 | static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp) |
6443 | { | |
6444 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
6445 | struct sev_data_launch_secret *data; | |
6446 | struct kvm_sev_launch_secret params; | |
6447 | struct page **pages; | |
6448 | void *blob, *hdr; | |
6449 | unsigned long n; | |
6450 | int ret; | |
6451 | ||
6452 | if (!sev_guest(kvm)) | |
6453 | return -ENOTTY; | |
6454 | ||
6455 | if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params))) | |
6456 | return -EFAULT; | |
6457 | ||
6458 | pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1); | |
6459 | if (!pages) | |
6460 | return -ENOMEM; | |
6461 | ||
6462 | /* | |
6463 | * The secret must be copied into contiguous memory region, lets verify | |
6464 | * that userspace memory pages are contiguous before we issue command. | |
6465 | */ | |
6466 | if (get_num_contig_pages(0, pages, n) != n) { | |
6467 | ret = -EINVAL; | |
6468 | goto e_unpin_memory; | |
6469 | } | |
6470 | ||
6471 | ret = -ENOMEM; | |
6472 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
6473 | if (!data) | |
6474 | goto e_unpin_memory; | |
6475 | ||
6476 | blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len); | |
6477 | if (IS_ERR(blob)) { | |
6478 | ret = PTR_ERR(blob); | |
6479 | goto e_free; | |
6480 | } | |
6481 | ||
6482 | data->trans_address = __psp_pa(blob); | |
6483 | data->trans_len = params.trans_len; | |
6484 | ||
6485 | hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len); | |
6486 | if (IS_ERR(hdr)) { | |
6487 | ret = PTR_ERR(hdr); | |
6488 | goto e_free_blob; | |
6489 | } | |
6490 | data->trans_address = __psp_pa(blob); | |
6491 | data->trans_len = params.trans_len; | |
6492 | ||
6493 | data->handle = sev->handle; | |
6494 | ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error); | |
6495 | ||
6496 | kfree(hdr); | |
6497 | ||
6498 | e_free_blob: | |
6499 | kfree(blob); | |
6500 | e_free: | |
6501 | kfree(data); | |
6502 | e_unpin_memory: | |
6503 | sev_unpin_memory(kvm, pages, n); | |
6504 | return ret; | |
6505 | } | |
6506 | ||
1654efcb BS |
6507 | static int svm_mem_enc_op(struct kvm *kvm, void __user *argp) |
6508 | { | |
6509 | struct kvm_sev_cmd sev_cmd; | |
6510 | int r; | |
6511 | ||
6512 | if (!svm_sev_enabled()) | |
6513 | return -ENOTTY; | |
6514 | ||
6515 | if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd))) | |
6516 | return -EFAULT; | |
6517 | ||
6518 | mutex_lock(&kvm->lock); | |
6519 | ||
6520 | switch (sev_cmd.id) { | |
6521 | case KVM_SEV_INIT: | |
6522 | r = sev_guest_init(kvm, &sev_cmd); | |
6523 | break; | |
59414c98 BS |
6524 | case KVM_SEV_LAUNCH_START: |
6525 | r = sev_launch_start(kvm, &sev_cmd); | |
6526 | break; | |
89c50580 BS |
6527 | case KVM_SEV_LAUNCH_UPDATE_DATA: |
6528 | r = sev_launch_update_data(kvm, &sev_cmd); | |
6529 | break; | |
0d0736f7 BS |
6530 | case KVM_SEV_LAUNCH_MEASURE: |
6531 | r = sev_launch_measure(kvm, &sev_cmd); | |
6532 | break; | |
5bdb0e2f BS |
6533 | case KVM_SEV_LAUNCH_FINISH: |
6534 | r = sev_launch_finish(kvm, &sev_cmd); | |
6535 | break; | |
255d9e75 BS |
6536 | case KVM_SEV_GUEST_STATUS: |
6537 | r = sev_guest_status(kvm, &sev_cmd); | |
6538 | break; | |
24f41fb2 BS |
6539 | case KVM_SEV_DBG_DECRYPT: |
6540 | r = sev_dbg_crypt(kvm, &sev_cmd, true); | |
6541 | break; | |
7d1594f5 BS |
6542 | case KVM_SEV_DBG_ENCRYPT: |
6543 | r = sev_dbg_crypt(kvm, &sev_cmd, false); | |
6544 | break; | |
9f5b5b95 BS |
6545 | case KVM_SEV_LAUNCH_SECRET: |
6546 | r = sev_launch_secret(kvm, &sev_cmd); | |
6547 | break; | |
1654efcb BS |
6548 | default: |
6549 | r = -EINVAL; | |
6550 | goto out; | |
6551 | } | |
6552 | ||
6553 | if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd))) | |
6554 | r = -EFAULT; | |
6555 | ||
6556 | out: | |
6557 | mutex_unlock(&kvm->lock); | |
6558 | return r; | |
6559 | } | |
6560 | ||
1e80fdc0 BS |
6561 | static int svm_register_enc_region(struct kvm *kvm, |
6562 | struct kvm_enc_region *range) | |
6563 | { | |
6564 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
6565 | struct enc_region *region; | |
6566 | int ret = 0; | |
6567 | ||
6568 | if (!sev_guest(kvm)) | |
6569 | return -ENOTTY; | |
6570 | ||
6571 | region = kzalloc(sizeof(*region), GFP_KERNEL); | |
6572 | if (!region) | |
6573 | return -ENOMEM; | |
6574 | ||
6575 | region->pages = sev_pin_memory(kvm, range->addr, range->size, ®ion->npages, 1); | |
6576 | if (!region->pages) { | |
6577 | ret = -ENOMEM; | |
6578 | goto e_free; | |
6579 | } | |
6580 | ||
6581 | /* | |
6582 | * The guest may change the memory encryption attribute from C=0 -> C=1 | |
6583 | * or vice versa for this memory range. Lets make sure caches are | |
6584 | * flushed to ensure that guest data gets written into memory with | |
6585 | * correct C-bit. | |
6586 | */ | |
6587 | sev_clflush_pages(region->pages, region->npages); | |
6588 | ||
6589 | region->uaddr = range->addr; | |
6590 | region->size = range->size; | |
6591 | ||
6592 | mutex_lock(&kvm->lock); | |
6593 | list_add_tail(®ion->list, &sev->regions_list); | |
6594 | mutex_unlock(&kvm->lock); | |
6595 | ||
6596 | return ret; | |
6597 | ||
6598 | e_free: | |
6599 | kfree(region); | |
6600 | return ret; | |
6601 | } | |
6602 | ||
6603 | static struct enc_region * | |
6604 | find_enc_region(struct kvm *kvm, struct kvm_enc_region *range) | |
6605 | { | |
6606 | struct kvm_sev_info *sev = &kvm->arch.sev_info; | |
6607 | struct list_head *head = &sev->regions_list; | |
6608 | struct enc_region *i; | |
6609 | ||
6610 | list_for_each_entry(i, head, list) { | |
6611 | if (i->uaddr == range->addr && | |
6612 | i->size == range->size) | |
6613 | return i; | |
6614 | } | |
6615 | ||
6616 | return NULL; | |
6617 | } | |
6618 | ||
6619 | ||
6620 | static int svm_unregister_enc_region(struct kvm *kvm, | |
6621 | struct kvm_enc_region *range) | |
6622 | { | |
6623 | struct enc_region *region; | |
6624 | int ret; | |
6625 | ||
6626 | mutex_lock(&kvm->lock); | |
6627 | ||
6628 | if (!sev_guest(kvm)) { | |
6629 | ret = -ENOTTY; | |
6630 | goto failed; | |
6631 | } | |
6632 | ||
6633 | region = find_enc_region(kvm, range); | |
6634 | if (!region) { | |
6635 | ret = -EINVAL; | |
6636 | goto failed; | |
6637 | } | |
6638 | ||
6639 | __unregister_enc_region_locked(kvm, region); | |
6640 | ||
6641 | mutex_unlock(&kvm->lock); | |
6642 | return 0; | |
6643 | ||
6644 | failed: | |
6645 | mutex_unlock(&kvm->lock); | |
6646 | return ret; | |
6647 | } | |
6648 | ||
404f6aac | 6649 | static struct kvm_x86_ops svm_x86_ops __ro_after_init = { |
6aa8b732 AK |
6650 | .cpu_has_kvm_support = has_svm, |
6651 | .disabled_by_bios = is_disabled, | |
6652 | .hardware_setup = svm_hardware_setup, | |
6653 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 6654 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
6655 | .hardware_enable = svm_hardware_enable, |
6656 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 6657 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6d396b55 | 6658 | .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase, |
6aa8b732 AK |
6659 | |
6660 | .vcpu_create = svm_create_vcpu, | |
6661 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 6662 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 6663 | |
44a95dae | 6664 | .vm_init = avic_vm_init, |
1654efcb | 6665 | .vm_destroy = svm_vm_destroy, |
44a95dae | 6666 | |
04d2cc77 | 6667 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
6668 | .vcpu_load = svm_vcpu_load, |
6669 | .vcpu_put = svm_vcpu_put, | |
8221c137 SS |
6670 | .vcpu_blocking = svm_vcpu_blocking, |
6671 | .vcpu_unblocking = svm_vcpu_unblocking, | |
6aa8b732 | 6672 | |
a96036b8 | 6673 | .update_bp_intercept = update_bp_intercept, |
6aa8b732 AK |
6674 | .get_msr = svm_get_msr, |
6675 | .set_msr = svm_set_msr, | |
6676 | .get_segment_base = svm_get_segment_base, | |
6677 | .get_segment = svm_get_segment, | |
6678 | .set_segment = svm_set_segment, | |
2e4d2653 | 6679 | .get_cpl = svm_get_cpl, |
1747fb71 | 6680 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 6681 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 6682 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 6683 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 6684 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
6685 | .set_cr3 = svm_set_cr3, |
6686 | .set_cr4 = svm_set_cr4, | |
6687 | .set_efer = svm_set_efer, | |
6688 | .get_idt = svm_get_idt, | |
6689 | .set_idt = svm_set_idt, | |
6690 | .get_gdt = svm_get_gdt, | |
6691 | .set_gdt = svm_set_gdt, | |
73aaf249 JK |
6692 | .get_dr6 = svm_get_dr6, |
6693 | .set_dr6 = svm_set_dr6, | |
020df079 | 6694 | .set_dr7 = svm_set_dr7, |
facb0139 | 6695 | .sync_dirty_debug_regs = svm_sync_dirty_debug_regs, |
6de4f3ad | 6696 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
6697 | .get_rflags = svm_get_rflags, |
6698 | .set_rflags = svm_set_rflags, | |
be94f6b7 | 6699 | |
6aa8b732 | 6700 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 6701 | |
6aa8b732 | 6702 | .run = svm_vcpu_run, |
04d2cc77 | 6703 | .handle_exit = handle_exit, |
6aa8b732 | 6704 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
6705 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
6706 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 6707 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 6708 | .set_irq = svm_set_irq, |
95ba8273 | 6709 | .set_nmi = svm_inject_nmi, |
298101da | 6710 | .queue_exception = svm_queue_exception, |
b463a6f7 | 6711 | .cancel_injection = svm_cancel_injection, |
78646121 | 6712 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 6713 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
6714 | .get_nmi_mask = svm_get_nmi_mask, |
6715 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
6716 | .enable_nmi_window = enable_nmi_window, |
6717 | .enable_irq_window = enable_irq_window, | |
6718 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 6719 | .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode, |
d62caabb AS |
6720 | .get_enable_apicv = svm_get_enable_apicv, |
6721 | .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl, | |
c7c9c56c | 6722 | .load_eoi_exitmap = svm_load_eoi_exitmap, |
44a95dae SS |
6723 | .hwapic_irr_update = svm_hwapic_irr_update, |
6724 | .hwapic_isr_update = svm_hwapic_isr_update, | |
be8ca170 | 6725 | .apicv_post_state_restore = avic_post_state_restore, |
cbc94022 IE |
6726 | |
6727 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 6728 | .get_tdp_level = get_npt_level, |
4b12f0de | 6729 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 6730 | |
586f9607 | 6731 | .get_exit_info = svm_get_exit_info, |
586f9607 | 6732 | |
17cc3935 | 6733 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
6734 | |
6735 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
6736 | |
6737 | .rdtscp_supported = svm_rdtscp_supported, | |
ad756a16 | 6738 | .invpcid_supported = svm_invpcid_supported, |
93c4adc7 | 6739 | .mpx_supported = svm_mpx_supported, |
55412b2e | 6740 | .xsaves_supported = svm_xsaves_supported, |
d4330ef2 JR |
6741 | |
6742 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
6743 | |
6744 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a ZA |
6745 | |
6746 | .write_tsc_offset = svm_write_tsc_offset, | |
1c97f0a0 JR |
6747 | |
6748 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
6749 | |
6750 | .check_intercept = svm_check_intercept, | |
a547c6db | 6751 | .handle_external_intr = svm_handle_external_intr, |
ae97a3b8 RK |
6752 | |
6753 | .sched_in = svm_sched_in, | |
25462f7f WH |
6754 | |
6755 | .pmu_ops = &amd_pmu_ops, | |
340d3bc3 | 6756 | .deliver_posted_interrupt = svm_deliver_avic_intr, |
411b44ba | 6757 | .update_pi_irte = svm_update_pi_irte, |
74f16909 | 6758 | .setup_mce = svm_setup_mce, |
0234bf88 | 6759 | |
72d7b374 | 6760 | .smi_allowed = svm_smi_allowed, |
0234bf88 LP |
6761 | .pre_enter_smm = svm_pre_enter_smm, |
6762 | .pre_leave_smm = svm_pre_leave_smm, | |
cc3d967f | 6763 | .enable_smi_window = enable_smi_window, |
1654efcb BS |
6764 | |
6765 | .mem_enc_op = svm_mem_enc_op, | |
1e80fdc0 BS |
6766 | .mem_enc_reg_region = svm_register_enc_region, |
6767 | .mem_enc_unreg_region = svm_unregister_enc_region, | |
6aa8b732 AK |
6768 | }; |
6769 | ||
6770 | static int __init svm_init(void) | |
6771 | { | |
cb498ea2 | 6772 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 6773 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
6774 | } |
6775 | ||
6776 | static void __exit svm_exit(void) | |
6777 | { | |
cb498ea2 | 6778 | kvm_exit(); |
6aa8b732 AK |
6779 | } |
6780 | ||
6781 | module_init(svm_init) | |
6782 | module_exit(svm_exit) |