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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
edf88417 AK |
16 | #include <linux/kvm_host.h> |
17 | ||
e495606d | 18 | #include "kvm_svm.h" |
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
6aa8b732 | 22 | #include <linux/module.h> |
9d8f549d | 23 | #include <linux/kernel.h> |
6aa8b732 AK |
24 | #include <linux/vmalloc.h> |
25 | #include <linux/highmem.h> | |
e8edc6e0 | 26 | #include <linux/sched.h> |
6aa8b732 | 27 | |
e495606d | 28 | #include <asm/desc.h> |
6aa8b732 | 29 | |
4ecac3fd AK |
30 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
31 | ||
6aa8b732 AK |
32 | MODULE_AUTHOR("Qumranet"); |
33 | MODULE_LICENSE("GPL"); | |
34 | ||
35 | #define IOPM_ALLOC_ORDER 2 | |
36 | #define MSRPM_ALLOC_ORDER 1 | |
37 | ||
38 | #define DB_VECTOR 1 | |
39 | #define UD_VECTOR 6 | |
40 | #define GP_VECTOR 13 | |
41 | ||
42 | #define DR7_GD_MASK (1 << 13) | |
43 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
44 | |
45 | #define SEG_TYPE_LDT 2 | |
46 | #define SEG_TYPE_BUSY_TSS16 3 | |
47 | ||
80b7706e JR |
48 | #define SVM_FEATURE_NPT (1 << 0) |
49 | #define SVM_FEATURE_LBRV (1 << 1) | |
50 | #define SVM_DEATURE_SVML (1 << 2) | |
51 | ||
24e09cbf JR |
52 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
53 | ||
709ddebf JR |
54 | /* enable NPT for AMD64 and X86 with PAE */ |
55 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
56 | static bool npt_enabled = true; | |
57 | #else | |
e3da3acd | 58 | static bool npt_enabled = false; |
709ddebf | 59 | #endif |
6c7dac72 JR |
60 | static int npt = 1; |
61 | ||
62 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 63 | |
04d2cc77 AK |
64 | static void kvm_reput_irq(struct vcpu_svm *svm); |
65 | ||
a2fa3e9f GH |
66 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
67 | { | |
fb3f0f51 | 68 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
69 | } |
70 | ||
4866d5e3 | 71 | static unsigned long iopm_base; |
6aa8b732 AK |
72 | |
73 | struct kvm_ldttss_desc { | |
74 | u16 limit0; | |
75 | u16 base0; | |
76 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
77 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
78 | u32 base3; | |
79 | u32 zero1; | |
80 | } __attribute__((packed)); | |
81 | ||
82 | struct svm_cpu_data { | |
83 | int cpu; | |
84 | ||
5008fdf5 AK |
85 | u64 asid_generation; |
86 | u32 max_asid; | |
87 | u32 next_asid; | |
6aa8b732 AK |
88 | struct kvm_ldttss_desc *tss_desc; |
89 | ||
90 | struct page *save_area; | |
91 | }; | |
92 | ||
93 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 94 | static uint32_t svm_features; |
6aa8b732 AK |
95 | |
96 | struct svm_init_data { | |
97 | int cpu; | |
98 | int r; | |
99 | }; | |
100 | ||
101 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
102 | ||
9d8f549d | 103 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
104 | #define MSRS_RANGE_SIZE 2048 |
105 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
106 | ||
107 | #define MAX_INST_SIZE 15 | |
108 | ||
80b7706e JR |
109 | static inline u32 svm_has(u32 feat) |
110 | { | |
111 | return svm_features & feat; | |
112 | } | |
113 | ||
6aa8b732 AK |
114 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) |
115 | { | |
ad312c7c ZX |
116 | int word_index = __ffs(vcpu->arch.irq_summary); |
117 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
118 | int irq = word_index * BITS_PER_LONG + bit_index; |
119 | ||
ad312c7c ZX |
120 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
121 | if (!vcpu->arch.irq_pending[word_index]) | |
122 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
123 | return irq; |
124 | } | |
125 | ||
126 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
127 | { | |
ad312c7c ZX |
128 | set_bit(irq, vcpu->arch.irq_pending); |
129 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
130 | } |
131 | ||
132 | static inline void clgi(void) | |
133 | { | |
4ecac3fd | 134 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
135 | } |
136 | ||
137 | static inline void stgi(void) | |
138 | { | |
4ecac3fd | 139 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
140 | } |
141 | ||
142 | static inline void invlpga(unsigned long addr, u32 asid) | |
143 | { | |
4ecac3fd | 144 | asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid)); |
6aa8b732 AK |
145 | } |
146 | ||
147 | static inline unsigned long kvm_read_cr2(void) | |
148 | { | |
149 | unsigned long cr2; | |
150 | ||
151 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
152 | return cr2; | |
153 | } | |
154 | ||
155 | static inline void kvm_write_cr2(unsigned long val) | |
156 | { | |
157 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
158 | } | |
159 | ||
160 | static inline unsigned long read_dr6(void) | |
161 | { | |
162 | unsigned long dr6; | |
163 | ||
164 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
165 | return dr6; | |
166 | } | |
167 | ||
168 | static inline void write_dr6(unsigned long val) | |
169 | { | |
170 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
171 | } | |
172 | ||
173 | static inline unsigned long read_dr7(void) | |
174 | { | |
175 | unsigned long dr7; | |
176 | ||
177 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
178 | return dr7; | |
179 | } | |
180 | ||
181 | static inline void write_dr7(unsigned long val) | |
182 | { | |
183 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
184 | } | |
185 | ||
6aa8b732 AK |
186 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
187 | { | |
a2fa3e9f | 188 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
189 | } |
190 | ||
191 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
192 | { | |
193 | force_new_asid(vcpu); | |
194 | } | |
195 | ||
196 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
197 | { | |
709ddebf | 198 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 199 | efer &= ~EFER_LME; |
6aa8b732 | 200 | |
a2fa3e9f | 201 | to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; |
ad312c7c | 202 | vcpu->arch.shadow_efer = efer; |
6aa8b732 AK |
203 | } |
204 | ||
298101da AK |
205 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
206 | bool has_error_code, u32 error_code) | |
207 | { | |
208 | struct vcpu_svm *svm = to_svm(vcpu); | |
209 | ||
210 | svm->vmcb->control.event_inj = nr | |
211 | | SVM_EVTINJ_VALID | |
212 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
213 | | SVM_EVTINJ_TYPE_EXEPT; | |
214 | svm->vmcb->control.event_inj_err = error_code; | |
215 | } | |
216 | ||
217 | static bool svm_exception_injected(struct kvm_vcpu *vcpu) | |
218 | { | |
219 | struct vcpu_svm *svm = to_svm(vcpu); | |
220 | ||
221 | return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID); | |
222 | } | |
223 | ||
6aa8b732 AK |
224 | static int is_external_interrupt(u32 info) |
225 | { | |
226 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
227 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
228 | } | |
229 | ||
230 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
231 | { | |
a2fa3e9f GH |
232 | struct vcpu_svm *svm = to_svm(vcpu); |
233 | ||
234 | if (!svm->next_rip) { | |
b8688d51 | 235 | printk(KERN_DEBUG "%s: NOP\n", __func__); |
6aa8b732 AK |
236 | return; |
237 | } | |
d77c26fc | 238 | if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) |
6aa8b732 | 239 | printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n", |
b8688d51 | 240 | __func__, |
a2fa3e9f GH |
241 | svm->vmcb->save.rip, |
242 | svm->next_rip); | |
6aa8b732 | 243 | |
ad312c7c | 244 | vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip; |
a2fa3e9f | 245 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; |
c1150d8c | 246 | |
ad312c7c | 247 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
248 | } |
249 | ||
250 | static int has_svm(void) | |
251 | { | |
252 | uint32_t eax, ebx, ecx, edx; | |
253 | ||
1e885461 | 254 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
255 | printk(KERN_INFO "has_svm: not amd\n"); |
256 | return 0; | |
257 | } | |
258 | ||
259 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
260 | if (eax < SVM_CPUID_FUNC) { | |
261 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
262 | return 0; | |
263 | } | |
264 | ||
265 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
266 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
267 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
268 | return 0; | |
269 | } | |
270 | return 1; | |
271 | } | |
272 | ||
273 | static void svm_hardware_disable(void *garbage) | |
274 | { | |
275 | struct svm_cpu_data *svm_data | |
276 | = per_cpu(svm_data, raw_smp_processor_id()); | |
277 | ||
278 | if (svm_data) { | |
279 | uint64_t efer; | |
280 | ||
281 | wrmsrl(MSR_VM_HSAVE_PA, 0); | |
282 | rdmsrl(MSR_EFER, efer); | |
283 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
8b6d44c7 | 284 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; |
6aa8b732 AK |
285 | __free_page(svm_data->save_area); |
286 | kfree(svm_data); | |
287 | } | |
288 | } | |
289 | ||
290 | static void svm_hardware_enable(void *garbage) | |
291 | { | |
292 | ||
293 | struct svm_cpu_data *svm_data; | |
294 | uint64_t efer; | |
6aa8b732 | 295 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
296 | struct desc_struct *gdt; |
297 | int me = raw_smp_processor_id(); | |
298 | ||
299 | if (!has_svm()) { | |
300 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
301 | return; | |
302 | } | |
303 | svm_data = per_cpu(svm_data, me); | |
304 | ||
305 | if (!svm_data) { | |
306 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
307 | me); | |
308 | return; | |
309 | } | |
310 | ||
311 | svm_data->asid_generation = 1; | |
312 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
313 | svm_data->next_asid = svm_data->max_asid + 1; | |
314 | ||
d77c26fc | 315 | asm volatile ("sgdt %0" : "=m"(gdt_descr)); |
6aa8b732 AK |
316 | gdt = (struct desc_struct *)gdt_descr.address; |
317 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
318 | ||
319 | rdmsrl(MSR_EFER, efer); | |
320 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
321 | ||
322 | wrmsrl(MSR_VM_HSAVE_PA, | |
323 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
324 | } | |
325 | ||
326 | static int svm_cpu_init(int cpu) | |
327 | { | |
328 | struct svm_cpu_data *svm_data; | |
329 | int r; | |
330 | ||
331 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
332 | if (!svm_data) | |
333 | return -ENOMEM; | |
334 | svm_data->cpu = cpu; | |
335 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
336 | r = -ENOMEM; | |
337 | if (!svm_data->save_area) | |
338 | goto err_1; | |
339 | ||
340 | per_cpu(svm_data, cpu) = svm_data; | |
341 | ||
342 | return 0; | |
343 | ||
344 | err_1: | |
345 | kfree(svm_data); | |
346 | return r; | |
347 | ||
348 | } | |
349 | ||
bfc733a7 RR |
350 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
351 | int read, int write) | |
6aa8b732 AK |
352 | { |
353 | int i; | |
354 | ||
355 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
356 | if (msr >= msrpm_ranges[i] && | |
357 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
358 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
359 | msrpm_ranges[i]) * 2; | |
360 | ||
361 | u32 *base = msrpm + (msr_offset / 32); | |
362 | u32 msr_shift = msr_offset % 32; | |
363 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
364 | *base = (*base & ~(0x3 << msr_shift)) | | |
365 | (mask << msr_shift); | |
bfc733a7 | 366 | return; |
6aa8b732 AK |
367 | } |
368 | } | |
bfc733a7 | 369 | BUG(); |
6aa8b732 AK |
370 | } |
371 | ||
f65c229c JR |
372 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
373 | { | |
374 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
375 | ||
376 | #ifdef CONFIG_X86_64 | |
377 | set_msr_interception(msrpm, MSR_GS_BASE, 1, 1); | |
378 | set_msr_interception(msrpm, MSR_FS_BASE, 1, 1); | |
379 | set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1); | |
380 | set_msr_interception(msrpm, MSR_LSTAR, 1, 1); | |
381 | set_msr_interception(msrpm, MSR_CSTAR, 1, 1); | |
382 | set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1); | |
383 | #endif | |
384 | set_msr_interception(msrpm, MSR_K6_STAR, 1, 1); | |
385 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1); | |
386 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1); | |
387 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1); | |
388 | } | |
389 | ||
24e09cbf JR |
390 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
391 | { | |
392 | u32 *msrpm = svm->msrpm; | |
393 | ||
394 | svm->vmcb->control.lbr_ctl = 1; | |
395 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
396 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
397 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
398 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
399 | } | |
400 | ||
401 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
402 | { | |
403 | u32 *msrpm = svm->msrpm; | |
404 | ||
405 | svm->vmcb->control.lbr_ctl = 0; | |
406 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
407 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
408 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
409 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
410 | } | |
411 | ||
6aa8b732 AK |
412 | static __init int svm_hardware_setup(void) |
413 | { | |
414 | int cpu; | |
415 | struct page *iopm_pages; | |
f65c229c | 416 | void *iopm_va; |
6aa8b732 AK |
417 | int r; |
418 | ||
6aa8b732 AK |
419 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
420 | ||
421 | if (!iopm_pages) | |
422 | return -ENOMEM; | |
c8681339 AL |
423 | |
424 | iopm_va = page_address(iopm_pages); | |
425 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
426 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
427 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
428 | ||
50a37eb4 JR |
429 | if (boot_cpu_has(X86_FEATURE_NX)) |
430 | kvm_enable_efer_bits(EFER_NX); | |
431 | ||
6aa8b732 AK |
432 | for_each_online_cpu(cpu) { |
433 | r = svm_cpu_init(cpu); | |
434 | if (r) | |
f65c229c | 435 | goto err; |
6aa8b732 | 436 | } |
33bd6a0b JR |
437 | |
438 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
439 | ||
e3da3acd JR |
440 | if (!svm_has(SVM_FEATURE_NPT)) |
441 | npt_enabled = false; | |
442 | ||
6c7dac72 JR |
443 | if (npt_enabled && !npt) { |
444 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
445 | npt_enabled = false; | |
446 | } | |
447 | ||
18552672 | 448 | if (npt_enabled) { |
e3da3acd | 449 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 JR |
450 | kvm_enable_tdp(); |
451 | } | |
e3da3acd | 452 | |
6aa8b732 AK |
453 | return 0; |
454 | ||
f65c229c | 455 | err: |
6aa8b732 AK |
456 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
457 | iopm_base = 0; | |
458 | return r; | |
459 | } | |
460 | ||
461 | static __exit void svm_hardware_unsetup(void) | |
462 | { | |
6aa8b732 | 463 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 464 | iopm_base = 0; |
6aa8b732 AK |
465 | } |
466 | ||
467 | static void init_seg(struct vmcb_seg *seg) | |
468 | { | |
469 | seg->selector = 0; | |
470 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
471 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
472 | seg->limit = 0xffff; | |
473 | seg->base = 0; | |
474 | } | |
475 | ||
476 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
477 | { | |
478 | seg->selector = 0; | |
479 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
480 | seg->limit = 0xffff; | |
481 | seg->base = 0; | |
482 | } | |
483 | ||
e6101a96 | 484 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 485 | { |
e6101a96 JR |
486 | struct vmcb_control_area *control = &svm->vmcb->control; |
487 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 AK |
488 | |
489 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
490 | INTERCEPT_CR3_MASK | | |
649d6864 | 491 | INTERCEPT_CR4_MASK; |
6aa8b732 AK |
492 | |
493 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
494 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
495 | INTERCEPT_CR4_MASK | |
496 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
497 | |
498 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
499 | INTERCEPT_DR1_MASK | | |
500 | INTERCEPT_DR2_MASK | | |
501 | INTERCEPT_DR3_MASK; | |
502 | ||
503 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
504 | INTERCEPT_DR1_MASK | | |
505 | INTERCEPT_DR2_MASK | | |
506 | INTERCEPT_DR3_MASK | | |
507 | INTERCEPT_DR5_MASK | | |
508 | INTERCEPT_DR7_MASK; | |
509 | ||
7aa81cc0 | 510 | control->intercept_exceptions = (1 << PF_VECTOR) | |
53371b50 JR |
511 | (1 << UD_VECTOR) | |
512 | (1 << MC_VECTOR); | |
6aa8b732 AK |
513 | |
514 | ||
515 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
516 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 517 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 | 518 | (1ULL << INTERCEPT_CPUID) | |
cf5a94d1 | 519 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 520 | (1ULL << INTERCEPT_HLT) | |
6aa8b732 AK |
521 | (1ULL << INTERCEPT_INVLPGA) | |
522 | (1ULL << INTERCEPT_IOIO_PROT) | | |
523 | (1ULL << INTERCEPT_MSR_PROT) | | |
524 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 525 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
526 | (1ULL << INTERCEPT_VMRUN) | |
527 | (1ULL << INTERCEPT_VMMCALL) | | |
528 | (1ULL << INTERCEPT_VMLOAD) | | |
529 | (1ULL << INTERCEPT_VMSAVE) | | |
530 | (1ULL << INTERCEPT_STGI) | | |
531 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 532 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 533 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
534 | (1ULL << INTERCEPT_MONITOR) | |
535 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
536 | |
537 | control->iopm_base_pa = iopm_base; | |
f65c229c | 538 | control->msrpm_base_pa = __pa(svm->msrpm); |
0cc5064d | 539 | control->tsc_offset = 0; |
6aa8b732 AK |
540 | control->int_ctl = V_INTR_MASKING_MASK; |
541 | ||
542 | init_seg(&save->es); | |
543 | init_seg(&save->ss); | |
544 | init_seg(&save->ds); | |
545 | init_seg(&save->fs); | |
546 | init_seg(&save->gs); | |
547 | ||
548 | save->cs.selector = 0xf000; | |
549 | /* Executable/Readable Code Segment */ | |
550 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
551 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
552 | save->cs.limit = 0xffff; | |
d92899a0 AK |
553 | /* |
554 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
555 | * be consistent with it. | |
556 | * | |
557 | * Replace when we have real mode working for vmx. | |
558 | */ | |
559 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
560 | |
561 | save->gdtr.limit = 0xffff; | |
562 | save->idtr.limit = 0xffff; | |
563 | ||
564 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
565 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
566 | ||
567 | save->efer = MSR_EFER_SVME_MASK; | |
d77c26fc | 568 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
569 | save->dr7 = 0x400; |
570 | save->rflags = 2; | |
571 | save->rip = 0x0000fff0; | |
572 | ||
573 | /* | |
574 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
575 | * cache by default. the orderly way is to enable cache in bios. | |
576 | */ | |
707d92fa | 577 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 578 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 579 | /* rdx = ?? */ |
709ddebf JR |
580 | |
581 | if (npt_enabled) { | |
582 | /* Setup VMCB for Nested Paging */ | |
583 | control->nested_ctl = 1; | |
3564990a | 584 | control->intercept &= ~(1ULL << INTERCEPT_TASK_SWITCH); |
709ddebf JR |
585 | control->intercept_exceptions &= ~(1 << PF_VECTOR); |
586 | control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK| | |
587 | INTERCEPT_CR3_MASK); | |
588 | control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK| | |
589 | INTERCEPT_CR3_MASK); | |
590 | save->g_pat = 0x0007040600070406ULL; | |
591 | /* enable caching because the QEMU Bios doesn't enable it */ | |
592 | save->cr0 = X86_CR0_ET; | |
593 | save->cr3 = 0; | |
594 | save->cr4 = 0; | |
595 | } | |
a79d2f18 | 596 | force_new_asid(&svm->vcpu); |
6aa8b732 AK |
597 | } |
598 | ||
e00c8cf2 | 599 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
600 | { |
601 | struct vcpu_svm *svm = to_svm(vcpu); | |
602 | ||
e6101a96 | 603 | init_vmcb(svm); |
70433389 AK |
604 | |
605 | if (vcpu->vcpu_id != 0) { | |
606 | svm->vmcb->save.rip = 0; | |
ad312c7c ZX |
607 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
608 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 609 | } |
e00c8cf2 AK |
610 | |
611 | return 0; | |
04d2cc77 AK |
612 | } |
613 | ||
fb3f0f51 | 614 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 615 | { |
a2fa3e9f | 616 | struct vcpu_svm *svm; |
6aa8b732 | 617 | struct page *page; |
f65c229c | 618 | struct page *msrpm_pages; |
fb3f0f51 | 619 | int err; |
6aa8b732 | 620 | |
c16f862d | 621 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
622 | if (!svm) { |
623 | err = -ENOMEM; | |
624 | goto out; | |
625 | } | |
626 | ||
627 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
628 | if (err) | |
629 | goto free_svm; | |
630 | ||
6aa8b732 | 631 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
632 | if (!page) { |
633 | err = -ENOMEM; | |
634 | goto uninit; | |
635 | } | |
6aa8b732 | 636 | |
f65c229c JR |
637 | err = -ENOMEM; |
638 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
639 | if (!msrpm_pages) | |
640 | goto uninit; | |
641 | svm->msrpm = page_address(msrpm_pages); | |
642 | svm_vcpu_init_msrpm(svm->msrpm); | |
643 | ||
a2fa3e9f GH |
644 | svm->vmcb = page_address(page); |
645 | clear_page(svm->vmcb); | |
646 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
647 | svm->asid_generation = 0; | |
648 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
e6101a96 | 649 | init_vmcb(svm); |
a2fa3e9f | 650 | |
fb3f0f51 RR |
651 | fx_init(&svm->vcpu); |
652 | svm->vcpu.fpu_active = 1; | |
ad312c7c | 653 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
fb3f0f51 | 654 | if (svm->vcpu.vcpu_id == 0) |
ad312c7c | 655 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 656 | |
fb3f0f51 | 657 | return &svm->vcpu; |
36241b8c | 658 | |
fb3f0f51 RR |
659 | uninit: |
660 | kvm_vcpu_uninit(&svm->vcpu); | |
661 | free_svm: | |
a4770347 | 662 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
663 | out: |
664 | return ERR_PTR(err); | |
6aa8b732 AK |
665 | } |
666 | ||
667 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
668 | { | |
a2fa3e9f GH |
669 | struct vcpu_svm *svm = to_svm(vcpu); |
670 | ||
fb3f0f51 | 671 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 672 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
fb3f0f51 | 673 | kvm_vcpu_uninit(vcpu); |
a4770347 | 674 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
675 | } |
676 | ||
15ad7146 | 677 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 678 | { |
a2fa3e9f | 679 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 680 | int i; |
0cc5064d | 681 | |
0cc5064d AK |
682 | if (unlikely(cpu != vcpu->cpu)) { |
683 | u64 tsc_this, delta; | |
684 | ||
685 | /* | |
686 | * Make sure that the guest sees a monotonically | |
687 | * increasing TSC. | |
688 | */ | |
689 | rdtscll(tsc_this); | |
ad312c7c | 690 | delta = vcpu->arch.host_tsc - tsc_this; |
a2fa3e9f | 691 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d | 692 | vcpu->cpu = cpu; |
2f599714 | 693 | kvm_migrate_timers(vcpu); |
0cc5064d | 694 | } |
94dfbdb3 AL |
695 | |
696 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 697 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
698 | } |
699 | ||
700 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
701 | { | |
a2fa3e9f | 702 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
703 | int i; |
704 | ||
e1beb1d3 | 705 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 706 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 707 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 708 | |
ad312c7c | 709 | rdtscll(vcpu->arch.host_tsc); |
6aa8b732 AK |
710 | } |
711 | ||
712 | static void svm_cache_regs(struct kvm_vcpu *vcpu) | |
713 | { | |
a2fa3e9f GH |
714 | struct vcpu_svm *svm = to_svm(vcpu); |
715 | ||
ad312c7c ZX |
716 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; |
717 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
718 | vcpu->arch.rip = svm->vmcb->save.rip; | |
6aa8b732 AK |
719 | } |
720 | ||
721 | static void svm_decache_regs(struct kvm_vcpu *vcpu) | |
722 | { | |
a2fa3e9f | 723 | struct vcpu_svm *svm = to_svm(vcpu); |
ad312c7c ZX |
724 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
725 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
726 | svm->vmcb->save.rip = vcpu->arch.rip; | |
6aa8b732 AK |
727 | } |
728 | ||
729 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
730 | { | |
a2fa3e9f | 731 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
732 | } |
733 | ||
734 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
735 | { | |
a2fa3e9f | 736 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
737 | } |
738 | ||
739 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
740 | { | |
a2fa3e9f | 741 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
742 | |
743 | switch (seg) { | |
744 | case VCPU_SREG_CS: return &save->cs; | |
745 | case VCPU_SREG_DS: return &save->ds; | |
746 | case VCPU_SREG_ES: return &save->es; | |
747 | case VCPU_SREG_FS: return &save->fs; | |
748 | case VCPU_SREG_GS: return &save->gs; | |
749 | case VCPU_SREG_SS: return &save->ss; | |
750 | case VCPU_SREG_TR: return &save->tr; | |
751 | case VCPU_SREG_LDTR: return &save->ldtr; | |
752 | } | |
753 | BUG(); | |
8b6d44c7 | 754 | return NULL; |
6aa8b732 AK |
755 | } |
756 | ||
757 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
758 | { | |
759 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
760 | ||
761 | return s->base; | |
762 | } | |
763 | ||
764 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
765 | struct kvm_segment *var, int seg) | |
766 | { | |
767 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
768 | ||
769 | var->base = s->base; | |
770 | var->limit = s->limit; | |
771 | var->selector = s->selector; | |
772 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
773 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
774 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
775 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
776 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
777 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
778 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
779 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
780 | var->unusable = !var->present; | |
781 | } | |
782 | ||
2e4d2653 IE |
783 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
784 | { | |
785 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
786 | ||
787 | return save->cpl; | |
788 | } | |
789 | ||
6aa8b732 AK |
790 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
791 | { | |
a2fa3e9f GH |
792 | struct vcpu_svm *svm = to_svm(vcpu); |
793 | ||
794 | dt->limit = svm->vmcb->save.idtr.limit; | |
795 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
796 | } |
797 | ||
798 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
799 | { | |
a2fa3e9f GH |
800 | struct vcpu_svm *svm = to_svm(vcpu); |
801 | ||
802 | svm->vmcb->save.idtr.limit = dt->limit; | |
803 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
804 | } |
805 | ||
806 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
807 | { | |
a2fa3e9f GH |
808 | struct vcpu_svm *svm = to_svm(vcpu); |
809 | ||
810 | dt->limit = svm->vmcb->save.gdtr.limit; | |
811 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
812 | } |
813 | ||
814 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
815 | { | |
a2fa3e9f GH |
816 | struct vcpu_svm *svm = to_svm(vcpu); |
817 | ||
818 | svm->vmcb->save.gdtr.limit = dt->limit; | |
819 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
820 | } |
821 | ||
25c4c276 | 822 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
823 | { |
824 | } | |
825 | ||
6aa8b732 AK |
826 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
827 | { | |
a2fa3e9f GH |
828 | struct vcpu_svm *svm = to_svm(vcpu); |
829 | ||
05b3e0c2 | 830 | #ifdef CONFIG_X86_64 |
ad312c7c | 831 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 832 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
ad312c7c | 833 | vcpu->arch.shadow_efer |= EFER_LMA; |
2b5203ee | 834 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
835 | } |
836 | ||
d77c26fc | 837 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
ad312c7c | 838 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
2b5203ee | 839 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
840 | } |
841 | } | |
842 | #endif | |
709ddebf JR |
843 | if (npt_enabled) |
844 | goto set; | |
845 | ||
ad312c7c | 846 | if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 847 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
848 | vcpu->fpu_active = 1; |
849 | } | |
850 | ||
ad312c7c | 851 | vcpu->arch.cr0 = cr0; |
707d92fa | 852 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
6b390b63 JR |
853 | if (!vcpu->fpu_active) { |
854 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); | |
334df50a | 855 | cr0 |= X86_CR0_TS; |
6b390b63 | 856 | } |
709ddebf JR |
857 | set: |
858 | /* | |
859 | * re-enable caching here because the QEMU bios | |
860 | * does not do it - this results in some delay at | |
861 | * reboot | |
862 | */ | |
863 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 864 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
865 | } |
866 | ||
867 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
868 | { | |
6394b649 JR |
869 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
870 | ||
ec077263 JR |
871 | vcpu->arch.cr4 = cr4; |
872 | if (!npt_enabled) | |
873 | cr4 |= X86_CR4_PAE; | |
6394b649 | 874 | cr4 |= host_cr4_mce; |
ec077263 | 875 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
6aa8b732 AK |
876 | } |
877 | ||
878 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
879 | struct kvm_segment *var, int seg) | |
880 | { | |
a2fa3e9f | 881 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
882 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
883 | ||
884 | s->base = var->base; | |
885 | s->limit = var->limit; | |
886 | s->selector = var->selector; | |
887 | if (var->unusable) | |
888 | s->attrib = 0; | |
889 | else { | |
890 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
891 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
892 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
893 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
894 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
895 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
896 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
897 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
898 | } | |
899 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
900 | svm->vmcb->save.cpl |
901 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
902 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
903 | ||
904 | } | |
905 | ||
6aa8b732 AK |
906 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) |
907 | { | |
908 | return -EOPNOTSUPP; | |
909 | } | |
910 | ||
2a8067f1 ED |
911 | static int svm_get_irq(struct kvm_vcpu *vcpu) |
912 | { | |
913 | struct vcpu_svm *svm = to_svm(vcpu); | |
914 | u32 exit_int_info = svm->vmcb->control.exit_int_info; | |
915 | ||
916 | if (is_external_interrupt(exit_int_info)) | |
917 | return exit_int_info & SVM_EVTINJ_VEC_MASK; | |
918 | return -1; | |
919 | } | |
920 | ||
6aa8b732 AK |
921 | static void load_host_msrs(struct kvm_vcpu *vcpu) |
922 | { | |
94dfbdb3 | 923 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 924 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 925 | #endif |
6aa8b732 AK |
926 | } |
927 | ||
928 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
929 | { | |
94dfbdb3 | 930 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 931 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 932 | #endif |
6aa8b732 AK |
933 | } |
934 | ||
e756fc62 | 935 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
936 | { |
937 | if (svm_data->next_asid > svm_data->max_asid) { | |
938 | ++svm_data->asid_generation; | |
939 | svm_data->next_asid = 1; | |
a2fa3e9f | 940 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
941 | } |
942 | ||
e756fc62 | 943 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
944 | svm->asid_generation = svm_data->asid_generation; |
945 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
946 | } |
947 | ||
6aa8b732 AK |
948 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
949 | { | |
af9ca2d7 JR |
950 | unsigned long val = to_svm(vcpu)->db_regs[dr]; |
951 | KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler); | |
952 | return val; | |
6aa8b732 AK |
953 | } |
954 | ||
955 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
956 | int *exception) | |
957 | { | |
a2fa3e9f GH |
958 | struct vcpu_svm *svm = to_svm(vcpu); |
959 | ||
6aa8b732 AK |
960 | *exception = 0; |
961 | ||
a2fa3e9f GH |
962 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
963 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
964 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
965 | *exception = DB_VECTOR; |
966 | return; | |
967 | } | |
968 | ||
969 | switch (dr) { | |
970 | case 0 ... 3: | |
a2fa3e9f | 971 | svm->db_regs[dr] = value; |
6aa8b732 AK |
972 | return; |
973 | case 4 ... 5: | |
ad312c7c | 974 | if (vcpu->arch.cr4 & X86_CR4_DE) { |
6aa8b732 AK |
975 | *exception = UD_VECTOR; |
976 | return; | |
977 | } | |
978 | case 7: { | |
979 | if (value & ~((1ULL << 32) - 1)) { | |
980 | *exception = GP_VECTOR; | |
981 | return; | |
982 | } | |
a2fa3e9f | 983 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
984 | return; |
985 | } | |
986 | default: | |
987 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
b8688d51 | 988 | __func__, dr); |
6aa8b732 AK |
989 | *exception = UD_VECTOR; |
990 | return; | |
991 | } | |
992 | } | |
993 | ||
e756fc62 | 994 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 995 | { |
a2fa3e9f | 996 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 997 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
998 | u64 fault_address; |
999 | u32 error_code; | |
6aa8b732 | 1000 | |
85f455f7 ED |
1001 | if (!irqchip_in_kernel(kvm) && |
1002 | is_external_interrupt(exit_int_info)) | |
e756fc62 | 1003 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
6aa8b732 | 1004 | |
a2fa3e9f GH |
1005 | fault_address = svm->vmcb->control.exit_info_2; |
1006 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 JR |
1007 | |
1008 | if (!npt_enabled) | |
1009 | KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code, | |
1010 | (u32)fault_address, (u32)(fault_address >> 32), | |
1011 | handler); | |
d2ebb410 JR |
1012 | else |
1013 | KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code, | |
1014 | (u32)fault_address, (u32)(fault_address >> 32), | |
1015 | handler); | |
af9ca2d7 | 1016 | |
3067714c | 1017 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
1018 | } |
1019 | ||
7aa81cc0 AL |
1020 | static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1021 | { | |
1022 | int er; | |
1023 | ||
571008da | 1024 | er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1025 | if (er != EMULATE_DONE) |
7ee5d940 | 1026 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1027 | return 1; |
1028 | } | |
1029 | ||
e756fc62 | 1030 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 1031 | { |
a2fa3e9f | 1032 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
ad312c7c | 1033 | if (!(svm->vcpu.arch.cr0 & X86_CR0_TS)) |
a2fa3e9f | 1034 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 1035 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
1036 | |
1037 | return 1; | |
7807fa6c AL |
1038 | } |
1039 | ||
53371b50 JR |
1040 | static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1041 | { | |
1042 | /* | |
1043 | * On an #MC intercept the MCE handler is not called automatically in | |
1044 | * the host. So do it by hand here. | |
1045 | */ | |
1046 | asm volatile ( | |
1047 | "int $0x12\n"); | |
1048 | /* not sure if we ever come back to this point */ | |
1049 | ||
1050 | return 1; | |
1051 | } | |
1052 | ||
e756fc62 | 1053 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
1054 | { |
1055 | /* | |
1056 | * VMCB is undefined after a SHUTDOWN intercept | |
1057 | * so reinitialize it. | |
1058 | */ | |
a2fa3e9f | 1059 | clear_page(svm->vmcb); |
e6101a96 | 1060 | init_vmcb(svm); |
46fe4ddd JR |
1061 | |
1062 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1063 | return 0; | |
1064 | } | |
1065 | ||
e756fc62 | 1066 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1067 | { |
d77c26fc | 1068 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
039576c0 AK |
1069 | int size, down, in, string, rep; |
1070 | unsigned port; | |
6aa8b732 | 1071 | |
e756fc62 | 1072 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1073 | |
a2fa3e9f | 1074 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1075 | |
e70669ab LV |
1076 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
1077 | ||
1078 | if (string) { | |
3427318f LV |
1079 | if (emulate_instruction(&svm->vcpu, |
1080 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
1081 | return 0; |
1082 | return 1; | |
1083 | } | |
1084 | ||
039576c0 AK |
1085 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1086 | port = io_info >> 16; | |
1087 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
039576c0 | 1088 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; |
a2fa3e9f | 1089 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1090 | |
3090dd73 | 1091 | return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1092 | } |
1093 | ||
c47f098d JR |
1094 | static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1095 | { | |
af9ca2d7 | 1096 | KVMTRACE_0D(NMI, &svm->vcpu, handler); |
c47f098d JR |
1097 | return 1; |
1098 | } | |
1099 | ||
a0698055 JR |
1100 | static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1101 | { | |
1102 | ++svm->vcpu.stat.irq_exits; | |
af9ca2d7 | 1103 | KVMTRACE_0D(INTR, &svm->vcpu, handler); |
a0698055 JR |
1104 | return 1; |
1105 | } | |
1106 | ||
e756fc62 | 1107 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1108 | { |
1109 | return 1; | |
1110 | } | |
1111 | ||
e756fc62 | 1112 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1113 | { |
a2fa3e9f | 1114 | svm->next_rip = svm->vmcb->save.rip + 1; |
e756fc62 RR |
1115 | skip_emulated_instruction(&svm->vcpu); |
1116 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1117 | } |
1118 | ||
e756fc62 | 1119 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1120 | { |
a2fa3e9f | 1121 | svm->next_rip = svm->vmcb->save.rip + 3; |
e756fc62 | 1122 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1123 | kvm_emulate_hypercall(&svm->vcpu); |
1124 | return 1; | |
02e235bc AK |
1125 | } |
1126 | ||
e756fc62 RR |
1127 | static int invalid_op_interception(struct vcpu_svm *svm, |
1128 | struct kvm_run *kvm_run) | |
6aa8b732 | 1129 | { |
7ee5d940 | 1130 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
1131 | return 1; |
1132 | } | |
1133 | ||
e756fc62 RR |
1134 | static int task_switch_interception(struct vcpu_svm *svm, |
1135 | struct kvm_run *kvm_run) | |
6aa8b732 | 1136 | { |
37817f29 IE |
1137 | u16 tss_selector; |
1138 | ||
1139 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
1140 | if (svm->vmcb->control.exit_info_2 & | |
1141 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
1142 | return kvm_task_switch(&svm->vcpu, tss_selector, | |
1143 | TASK_SWITCH_IRET); | |
1144 | if (svm->vmcb->control.exit_info_2 & | |
1145 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
1146 | return kvm_task_switch(&svm->vcpu, tss_selector, | |
1147 | TASK_SWITCH_JMP); | |
1148 | return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL); | |
6aa8b732 AK |
1149 | } |
1150 | ||
e756fc62 | 1151 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1152 | { |
a2fa3e9f | 1153 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1154 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1155 | return 1; |
6aa8b732 AK |
1156 | } |
1157 | ||
e756fc62 RR |
1158 | static int emulate_on_interception(struct vcpu_svm *svm, |
1159 | struct kvm_run *kvm_run) | |
6aa8b732 | 1160 | { |
3427318f | 1161 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE) |
b8688d51 | 1162 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); |
6aa8b732 AK |
1163 | return 1; |
1164 | } | |
1165 | ||
1d075434 JR |
1166 | static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1167 | { | |
1168 | emulate_instruction(&svm->vcpu, NULL, 0, 0, 0); | |
1169 | if (irqchip_in_kernel(svm->vcpu.kvm)) | |
1170 | return 1; | |
1171 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; | |
1172 | return 0; | |
1173 | } | |
1174 | ||
6aa8b732 AK |
1175 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
1176 | { | |
a2fa3e9f GH |
1177 | struct vcpu_svm *svm = to_svm(vcpu); |
1178 | ||
6aa8b732 | 1179 | switch (ecx) { |
6aa8b732 AK |
1180 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1181 | u64 tsc; | |
1182 | ||
1183 | rdtscll(tsc); | |
a2fa3e9f | 1184 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1185 | break; |
1186 | } | |
0e859cac | 1187 | case MSR_K6_STAR: |
a2fa3e9f | 1188 | *data = svm->vmcb->save.star; |
6aa8b732 | 1189 | break; |
0e859cac | 1190 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1191 | case MSR_LSTAR: |
a2fa3e9f | 1192 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1193 | break; |
1194 | case MSR_CSTAR: | |
a2fa3e9f | 1195 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1196 | break; |
1197 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1198 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1199 | break; |
1200 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1201 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1202 | break; |
1203 | #endif | |
1204 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1205 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1206 | break; |
1207 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1208 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1209 | break; |
1210 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1211 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 | 1212 | break; |
a2938c80 JR |
1213 | /* Nobody will change the following 5 values in the VMCB so |
1214 | we can safely return them on rdmsr. They will always be 0 | |
1215 | until LBRV is implemented. */ | |
1216 | case MSR_IA32_DEBUGCTLMSR: | |
1217 | *data = svm->vmcb->save.dbgctl; | |
1218 | break; | |
1219 | case MSR_IA32_LASTBRANCHFROMIP: | |
1220 | *data = svm->vmcb->save.br_from; | |
1221 | break; | |
1222 | case MSR_IA32_LASTBRANCHTOIP: | |
1223 | *data = svm->vmcb->save.br_to; | |
1224 | break; | |
1225 | case MSR_IA32_LASTINTFROMIP: | |
1226 | *data = svm->vmcb->save.last_excp_from; | |
1227 | break; | |
1228 | case MSR_IA32_LASTINTTOIP: | |
1229 | *data = svm->vmcb->save.last_excp_to; | |
1230 | break; | |
6aa8b732 | 1231 | default: |
3bab1f5d | 1232 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1233 | } |
1234 | return 0; | |
1235 | } | |
1236 | ||
e756fc62 | 1237 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1238 | { |
ad312c7c | 1239 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1240 | u64 data; |
1241 | ||
e756fc62 | 1242 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
c1a5d4f9 | 1243 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1244 | else { |
af9ca2d7 JR |
1245 | KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data, |
1246 | (u32)(data >> 32), handler); | |
1247 | ||
a2fa3e9f | 1248 | svm->vmcb->save.rax = data & 0xffffffff; |
ad312c7c | 1249 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
a2fa3e9f | 1250 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1251 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1252 | } |
1253 | return 1; | |
1254 | } | |
1255 | ||
1256 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1257 | { | |
a2fa3e9f GH |
1258 | struct vcpu_svm *svm = to_svm(vcpu); |
1259 | ||
6aa8b732 | 1260 | switch (ecx) { |
6aa8b732 AK |
1261 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1262 | u64 tsc; | |
1263 | ||
1264 | rdtscll(tsc); | |
a2fa3e9f | 1265 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1266 | break; |
1267 | } | |
0e859cac | 1268 | case MSR_K6_STAR: |
a2fa3e9f | 1269 | svm->vmcb->save.star = data; |
6aa8b732 | 1270 | break; |
49b14f24 | 1271 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1272 | case MSR_LSTAR: |
a2fa3e9f | 1273 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1274 | break; |
1275 | case MSR_CSTAR: | |
a2fa3e9f | 1276 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1277 | break; |
1278 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1279 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1280 | break; |
1281 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1282 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1283 | break; |
1284 | #endif | |
1285 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1286 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1287 | break; |
1288 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1289 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1290 | break; |
1291 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1292 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 1293 | break; |
a2938c80 | 1294 | case MSR_IA32_DEBUGCTLMSR: |
24e09cbf JR |
1295 | if (!svm_has(SVM_FEATURE_LBRV)) { |
1296 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", | |
b8688d51 | 1297 | __func__, data); |
24e09cbf JR |
1298 | break; |
1299 | } | |
1300 | if (data & DEBUGCTL_RESERVED_BITS) | |
1301 | return 1; | |
1302 | ||
1303 | svm->vmcb->save.dbgctl = data; | |
1304 | if (data & (1ULL<<0)) | |
1305 | svm_enable_lbrv(svm); | |
1306 | else | |
1307 | svm_disable_lbrv(svm); | |
a2938c80 | 1308 | break; |
62b9abaa JR |
1309 | case MSR_K7_EVNTSEL0: |
1310 | case MSR_K7_EVNTSEL1: | |
1311 | case MSR_K7_EVNTSEL2: | |
1312 | case MSR_K7_EVNTSEL3: | |
14ae51b6 CL |
1313 | case MSR_K7_PERFCTR0: |
1314 | case MSR_K7_PERFCTR1: | |
1315 | case MSR_K7_PERFCTR2: | |
1316 | case MSR_K7_PERFCTR3: | |
62b9abaa | 1317 | /* |
14ae51b6 CL |
1318 | * Just discard all writes to the performance counters; this |
1319 | * should keep both older linux and windows 64-bit guests | |
1320 | * happy | |
62b9abaa | 1321 | */ |
14ae51b6 CL |
1322 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data); |
1323 | ||
62b9abaa | 1324 | break; |
6aa8b732 | 1325 | default: |
3bab1f5d | 1326 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1327 | } |
1328 | return 0; | |
1329 | } | |
1330 | ||
e756fc62 | 1331 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1332 | { |
ad312c7c | 1333 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
a2fa3e9f | 1334 | u64 data = (svm->vmcb->save.rax & -1u) |
ad312c7c | 1335 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 JR |
1336 | |
1337 | KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32), | |
1338 | handler); | |
1339 | ||
a2fa3e9f | 1340 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1341 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
c1a5d4f9 | 1342 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1343 | else |
e756fc62 | 1344 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1345 | return 1; |
1346 | } | |
1347 | ||
e756fc62 | 1348 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1349 | { |
e756fc62 RR |
1350 | if (svm->vmcb->control.exit_info_1) |
1351 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1352 | else |
e756fc62 | 1353 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1354 | } |
1355 | ||
e756fc62 | 1356 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1357 | struct kvm_run *kvm_run) |
1358 | { | |
af9ca2d7 JR |
1359 | KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler); |
1360 | ||
85f455f7 ED |
1361 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); |
1362 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
c1150d8c DL |
1363 | /* |
1364 | * If the user space waits to inject interrupts, exit as soon as | |
1365 | * possible | |
1366 | */ | |
1367 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 1368 | !svm->vcpu.arch.irq_summary) { |
e756fc62 | 1369 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
1370 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1371 | return 0; | |
1372 | } | |
1373 | ||
1374 | return 1; | |
1375 | } | |
1376 | ||
e756fc62 | 1377 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1378 | struct kvm_run *kvm_run) = { |
1379 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1380 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1381 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
80a8119c | 1382 | [SVM_EXIT_READ_CR8] = emulate_on_interception, |
6aa8b732 AK |
1383 | /* for now: */ |
1384 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1385 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1386 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1d075434 | 1387 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
6aa8b732 AK |
1388 | [SVM_EXIT_READ_DR0] = emulate_on_interception, |
1389 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1390 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1391 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1392 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1393 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1394 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1395 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1396 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1397 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
7aa81cc0 | 1398 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 1399 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 1400 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
53371b50 | 1401 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
a0698055 | 1402 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 1403 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
1404 | [SVM_EXIT_SMI] = nop_on_interception, |
1405 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1406 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1407 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1408 | [SVM_EXIT_CPUID] = cpuid_interception, | |
cf5a94d1 | 1409 | [SVM_EXIT_INVD] = emulate_on_interception, |
6aa8b732 AK |
1410 | [SVM_EXIT_HLT] = halt_interception, |
1411 | [SVM_EXIT_INVLPG] = emulate_on_interception, | |
1412 | [SVM_EXIT_INVLPGA] = invalid_op_interception, | |
1413 | [SVM_EXIT_IOIO] = io_interception, | |
1414 | [SVM_EXIT_MSR] = msr_interception, | |
1415 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1416 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1417 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1418 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1419 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1420 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1421 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1422 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1423 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
cf5a94d1 | 1424 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
1425 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1426 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 1427 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
1428 | }; |
1429 | ||
04d2cc77 | 1430 | static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
6aa8b732 | 1431 | { |
04d2cc77 | 1432 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1433 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1434 | |
af9ca2d7 JR |
1435 | KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip, |
1436 | (u32)((u64)svm->vmcb->save.rip >> 32), entryexit); | |
1437 | ||
709ddebf JR |
1438 | if (npt_enabled) { |
1439 | int mmu_reload = 0; | |
1440 | if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) { | |
1441 | svm_set_cr0(vcpu, svm->vmcb->save.cr0); | |
1442 | mmu_reload = 1; | |
1443 | } | |
1444 | vcpu->arch.cr0 = svm->vmcb->save.cr0; | |
1445 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
1446 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
1447 | if (!load_pdptrs(vcpu, vcpu->arch.cr3)) { | |
1448 | kvm_inject_gp(vcpu, 0); | |
1449 | return 1; | |
1450 | } | |
1451 | } | |
1452 | if (mmu_reload) { | |
1453 | kvm_mmu_reset_context(vcpu); | |
1454 | kvm_mmu_load(vcpu); | |
1455 | } | |
1456 | } | |
1457 | ||
04d2cc77 AK |
1458 | kvm_reput_irq(svm); |
1459 | ||
1460 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
1461 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
1462 | kvm_run->fail_entry.hardware_entry_failure_reason | |
1463 | = svm->vmcb->control.exit_code; | |
1464 | return 0; | |
1465 | } | |
1466 | ||
a2fa3e9f | 1467 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf JR |
1468 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
1469 | exit_code != SVM_EXIT_NPF) | |
6aa8b732 AK |
1470 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
1471 | "exit_code 0x%x\n", | |
b8688d51 | 1472 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1473 | exit_code); |
1474 | ||
9d8f549d | 1475 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 1476 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 1477 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 1478 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1479 | return 0; |
1480 | } | |
1481 | ||
e756fc62 | 1482 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1483 | } |
1484 | ||
1485 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1486 | { | |
1487 | int cpu = raw_smp_processor_id(); | |
1488 | ||
1489 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
d77c26fc | 1490 | svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */ |
6aa8b732 AK |
1491 | load_TR_desc(); |
1492 | } | |
1493 | ||
e756fc62 | 1494 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1495 | { |
1496 | int cpu = raw_smp_processor_id(); | |
1497 | ||
1498 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1499 | ||
a2fa3e9f | 1500 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1501 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1502 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1503 | new_asid(svm, svm_data); |
6aa8b732 AK |
1504 | } |
1505 | ||
1506 | ||
85f455f7 | 1507 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
1508 | { |
1509 | struct vmcb_control_area *control; | |
1510 | ||
af9ca2d7 JR |
1511 | KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler); |
1512 | ||
e756fc62 | 1513 | control = &svm->vmcb->control; |
85f455f7 | 1514 | control->int_vector = irq; |
6aa8b732 AK |
1515 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1516 | control->int_ctl |= V_IRQ_MASK | | |
1517 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1518 | } | |
1519 | ||
2a8067f1 ED |
1520 | static void svm_set_irq(struct kvm_vcpu *vcpu, int irq) |
1521 | { | |
1522 | struct vcpu_svm *svm = to_svm(vcpu); | |
1523 | ||
1524 | svm_inject_irq(svm, irq); | |
1525 | } | |
1526 | ||
aaacfc9a JR |
1527 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
1528 | { | |
1529 | struct vcpu_svm *svm = to_svm(vcpu); | |
1530 | struct vmcb *vmcb = svm->vmcb; | |
1531 | int max_irr, tpr; | |
1532 | ||
1533 | if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr) | |
1534 | return; | |
1535 | ||
1536 | vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
1537 | ||
1538 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
1539 | if (max_irr == -1) | |
1540 | return; | |
1541 | ||
1542 | tpr = kvm_lapic_get_cr8(vcpu) << 4; | |
1543 | ||
1544 | if (tpr >= (max_irr & 0xf0)) | |
1545 | vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK; | |
1546 | } | |
1547 | ||
04d2cc77 | 1548 | static void svm_intr_assist(struct kvm_vcpu *vcpu) |
6aa8b732 | 1549 | { |
04d2cc77 | 1550 | struct vcpu_svm *svm = to_svm(vcpu); |
85f455f7 ED |
1551 | struct vmcb *vmcb = svm->vmcb; |
1552 | int intr_vector = -1; | |
1553 | ||
1554 | if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) && | |
1555 | ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) { | |
1556 | intr_vector = vmcb->control.exit_int_info & | |
1557 | SVM_EVTINJ_VEC_MASK; | |
1558 | vmcb->control.exit_int_info = 0; | |
1559 | svm_inject_irq(svm, intr_vector); | |
aaacfc9a | 1560 | goto out; |
85f455f7 ED |
1561 | } |
1562 | ||
1563 | if (vmcb->control.int_ctl & V_IRQ_MASK) | |
aaacfc9a | 1564 | goto out; |
85f455f7 | 1565 | |
1b9778da | 1566 | if (!kvm_cpu_has_interrupt(vcpu)) |
aaacfc9a | 1567 | goto out; |
85f455f7 ED |
1568 | |
1569 | if (!(vmcb->save.rflags & X86_EFLAGS_IF) || | |
1570 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) || | |
1571 | (vmcb->control.event_inj & SVM_EVTINJ_VALID)) { | |
1572 | /* unable to deliver irq, set pending irq */ | |
1573 | vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR); | |
1574 | svm_inject_irq(svm, 0x0); | |
aaacfc9a | 1575 | goto out; |
85f455f7 ED |
1576 | } |
1577 | /* Okay, we can deliver the interrupt: grab it and update PIC state. */ | |
1b9778da | 1578 | intr_vector = kvm_cpu_get_interrupt(vcpu); |
85f455f7 | 1579 | svm_inject_irq(svm, intr_vector); |
1b9778da | 1580 | kvm_timer_intr_post(vcpu, intr_vector); |
aaacfc9a JR |
1581 | out: |
1582 | update_cr8_intercept(vcpu); | |
85f455f7 ED |
1583 | } |
1584 | ||
1585 | static void kvm_reput_irq(struct vcpu_svm *svm) | |
1586 | { | |
e756fc62 | 1587 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 | 1588 | |
7017fc3d ED |
1589 | if ((control->int_ctl & V_IRQ_MASK) |
1590 | && !irqchip_in_kernel(svm->vcpu.kvm)) { | |
6aa8b732 | 1591 | control->int_ctl &= ~V_IRQ_MASK; |
e756fc62 | 1592 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1593 | } |
c1150d8c | 1594 | |
ad312c7c | 1595 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c DL |
1596 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1597 | } | |
1598 | ||
85f455f7 ED |
1599 | static void svm_do_inject_vector(struct vcpu_svm *svm) |
1600 | { | |
1601 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ad312c7c ZX |
1602 | int word_index = __ffs(vcpu->arch.irq_summary); |
1603 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
85f455f7 ED |
1604 | int irq = word_index * BITS_PER_LONG + bit_index; |
1605 | ||
ad312c7c ZX |
1606 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
1607 | if (!vcpu->arch.irq_pending[word_index]) | |
1608 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
85f455f7 ED |
1609 | svm_inject_irq(svm, irq); |
1610 | } | |
1611 | ||
04d2cc77 | 1612 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
c1150d8c DL |
1613 | struct kvm_run *kvm_run) |
1614 | { | |
04d2cc77 | 1615 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1616 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1617 | |
ad312c7c | 1618 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c | 1619 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1620 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1621 | |
ad312c7c | 1622 | if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary) |
c1150d8c DL |
1623 | /* |
1624 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1625 | */ | |
85f455f7 | 1626 | svm_do_inject_vector(svm); |
c1150d8c DL |
1627 | |
1628 | /* | |
1629 | * Interrupts blocked. Wait for unblock. | |
1630 | */ | |
ad312c7c ZX |
1631 | if (!svm->vcpu.arch.interrupt_window_open && |
1632 | (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window)) | |
c1150d8c | 1633 | control->intercept |= 1ULL << INTERCEPT_VINTR; |
d77c26fc | 1634 | else |
c1150d8c DL |
1635 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); |
1636 | } | |
1637 | ||
cbc94022 IE |
1638 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
1639 | { | |
1640 | return 0; | |
1641 | } | |
1642 | ||
6aa8b732 AK |
1643 | static void save_db_regs(unsigned long *db_regs) |
1644 | { | |
5aff458e AK |
1645 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1646 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1647 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1648 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1649 | } |
1650 | ||
1651 | static void load_db_regs(unsigned long *db_regs) | |
1652 | { | |
5aff458e AK |
1653 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1654 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1655 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1656 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1657 | } |
1658 | ||
d9e368d6 AK |
1659 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1660 | { | |
1661 | force_new_asid(vcpu); | |
1662 | } | |
1663 | ||
04d2cc77 AK |
1664 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
1665 | { | |
1666 | } | |
1667 | ||
d7bf8221 JR |
1668 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
1669 | { | |
1670 | struct vcpu_svm *svm = to_svm(vcpu); | |
1671 | ||
1672 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) { | |
1673 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; | |
1674 | kvm_lapic_set_tpr(vcpu, cr8); | |
1675 | } | |
1676 | } | |
1677 | ||
649d6864 JR |
1678 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
1679 | { | |
1680 | struct vcpu_svm *svm = to_svm(vcpu); | |
1681 | u64 cr8; | |
1682 | ||
1683 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1684 | return; | |
1685 | ||
1686 | cr8 = kvm_get_cr8(vcpu); | |
1687 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
1688 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
1689 | } | |
1690 | ||
04d2cc77 | 1691 | static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6aa8b732 | 1692 | { |
a2fa3e9f | 1693 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1694 | u16 fs_selector; |
1695 | u16 gs_selector; | |
1696 | u16 ldt_selector; | |
d9e368d6 | 1697 | |
e756fc62 | 1698 | pre_svm_run(svm); |
6aa8b732 | 1699 | |
649d6864 JR |
1700 | sync_lapic_to_cr8(vcpu); |
1701 | ||
6aa8b732 AK |
1702 | save_host_msrs(vcpu); |
1703 | fs_selector = read_fs(); | |
1704 | gs_selector = read_gs(); | |
1705 | ldt_selector = read_ldt(); | |
a2fa3e9f GH |
1706 | svm->host_cr2 = kvm_read_cr2(); |
1707 | svm->host_dr6 = read_dr6(); | |
1708 | svm->host_dr7 = read_dr7(); | |
ad312c7c | 1709 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
709ddebf JR |
1710 | /* required for live migration with NPT */ |
1711 | if (npt_enabled) | |
1712 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
6aa8b732 | 1713 | |
a2fa3e9f | 1714 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1715 | write_dr7(0); |
a2fa3e9f GH |
1716 | save_db_regs(svm->host_db_regs); |
1717 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1718 | } |
36241b8c | 1719 | |
04d2cc77 AK |
1720 | clgi(); |
1721 | ||
1722 | local_irq_enable(); | |
36241b8c | 1723 | |
6aa8b732 | 1724 | asm volatile ( |
05b3e0c2 | 1725 | #ifdef CONFIG_X86_64 |
54a08c04 | 1726 | "push %%rbp; \n\t" |
6aa8b732 | 1727 | #else |
fe7935d4 | 1728 | "push %%ebp; \n\t" |
6aa8b732 AK |
1729 | #endif |
1730 | ||
05b3e0c2 | 1731 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1732 | "mov %c[rbx](%[svm]), %%rbx \n\t" |
1733 | "mov %c[rcx](%[svm]), %%rcx \n\t" | |
1734 | "mov %c[rdx](%[svm]), %%rdx \n\t" | |
1735 | "mov %c[rsi](%[svm]), %%rsi \n\t" | |
1736 | "mov %c[rdi](%[svm]), %%rdi \n\t" | |
1737 | "mov %c[rbp](%[svm]), %%rbp \n\t" | |
1738 | "mov %c[r8](%[svm]), %%r8 \n\t" | |
1739 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1740 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1741 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1742 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1743 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1744 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1745 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 | 1746 | #else |
fb3f0f51 RR |
1747 | "mov %c[rbx](%[svm]), %%ebx \n\t" |
1748 | "mov %c[rcx](%[svm]), %%ecx \n\t" | |
1749 | "mov %c[rdx](%[svm]), %%edx \n\t" | |
1750 | "mov %c[rsi](%[svm]), %%esi \n\t" | |
1751 | "mov %c[rdi](%[svm]), %%edi \n\t" | |
1752 | "mov %c[rbp](%[svm]), %%ebp \n\t" | |
6aa8b732 AK |
1753 | #endif |
1754 | ||
05b3e0c2 | 1755 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1756 | /* Enter guest mode */ |
1757 | "push %%rax \n\t" | |
fb3f0f51 | 1758 | "mov %c[vmcb](%[svm]), %%rax \n\t" |
4ecac3fd AK |
1759 | __ex(SVM_VMLOAD) "\n\t" |
1760 | __ex(SVM_VMRUN) "\n\t" | |
1761 | __ex(SVM_VMSAVE) "\n\t" | |
6aa8b732 AK |
1762 | "pop %%rax \n\t" |
1763 | #else | |
1764 | /* Enter guest mode */ | |
1765 | "push %%eax \n\t" | |
fb3f0f51 | 1766 | "mov %c[vmcb](%[svm]), %%eax \n\t" |
4ecac3fd AK |
1767 | __ex(SVM_VMLOAD) "\n\t" |
1768 | __ex(SVM_VMRUN) "\n\t" | |
1769 | __ex(SVM_VMSAVE) "\n\t" | |
6aa8b732 AK |
1770 | "pop %%eax \n\t" |
1771 | #endif | |
1772 | ||
1773 | /* Save guest registers, load host registers */ | |
05b3e0c2 | 1774 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1775 | "mov %%rbx, %c[rbx](%[svm]) \n\t" |
1776 | "mov %%rcx, %c[rcx](%[svm]) \n\t" | |
1777 | "mov %%rdx, %c[rdx](%[svm]) \n\t" | |
1778 | "mov %%rsi, %c[rsi](%[svm]) \n\t" | |
1779 | "mov %%rdi, %c[rdi](%[svm]) \n\t" | |
1780 | "mov %%rbp, %c[rbp](%[svm]) \n\t" | |
1781 | "mov %%r8, %c[r8](%[svm]) \n\t" | |
1782 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1783 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1784 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1785 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1786 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1787 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1788 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 1789 | |
54a08c04 | 1790 | "pop %%rbp; \n\t" |
6aa8b732 | 1791 | #else |
fb3f0f51 RR |
1792 | "mov %%ebx, %c[rbx](%[svm]) \n\t" |
1793 | "mov %%ecx, %c[rcx](%[svm]) \n\t" | |
1794 | "mov %%edx, %c[rdx](%[svm]) \n\t" | |
1795 | "mov %%esi, %c[rsi](%[svm]) \n\t" | |
1796 | "mov %%edi, %c[rdi](%[svm]) \n\t" | |
1797 | "mov %%ebp, %c[rbp](%[svm]) \n\t" | |
6aa8b732 | 1798 | |
fe7935d4 | 1799 | "pop %%ebp; \n\t" |
6aa8b732 AK |
1800 | #endif |
1801 | : | |
fb3f0f51 | 1802 | : [svm]"a"(svm), |
6aa8b732 | 1803 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
1804 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
1805 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
1806 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
1807 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
1808 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
1809 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1810 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
1811 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
1812 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
1813 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
1814 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
1815 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
1816 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
1817 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
1818 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 1819 | #endif |
54a08c04 LV |
1820 | : "cc", "memory" |
1821 | #ifdef CONFIG_X86_64 | |
1822 | , "rbx", "rcx", "rdx", "rsi", "rdi" | |
1823 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" | |
fe7935d4 LV |
1824 | #else |
1825 | , "ebx", "ecx", "edx" , "esi", "edi" | |
54a08c04 LV |
1826 | #endif |
1827 | ); | |
6aa8b732 | 1828 | |
a2fa3e9f GH |
1829 | if ((svm->vmcb->save.dr7 & 0xff)) |
1830 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1831 | |
ad312c7c | 1832 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
6aa8b732 | 1833 | |
a2fa3e9f GH |
1834 | write_dr6(svm->host_dr6); |
1835 | write_dr7(svm->host_dr7); | |
1836 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 AK |
1837 | |
1838 | load_fs(fs_selector); | |
1839 | load_gs(gs_selector); | |
1840 | load_ldt(ldt_selector); | |
1841 | load_host_msrs(vcpu); | |
1842 | ||
1843 | reload_tss(vcpu); | |
1844 | ||
56ba47dd AK |
1845 | local_irq_disable(); |
1846 | ||
1847 | stgi(); | |
1848 | ||
d7bf8221 JR |
1849 | sync_cr8_to_lapic(vcpu); |
1850 | ||
a2fa3e9f | 1851 | svm->next_rip = 0; |
6aa8b732 AK |
1852 | } |
1853 | ||
6aa8b732 AK |
1854 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1855 | { | |
a2fa3e9f GH |
1856 | struct vcpu_svm *svm = to_svm(vcpu); |
1857 | ||
709ddebf JR |
1858 | if (npt_enabled) { |
1859 | svm->vmcb->control.nested_cr3 = root; | |
1860 | force_new_asid(vcpu); | |
1861 | return; | |
1862 | } | |
1863 | ||
a2fa3e9f | 1864 | svm->vmcb->save.cr3 = root; |
6aa8b732 | 1865 | force_new_asid(vcpu); |
7807fa6c AL |
1866 | |
1867 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1868 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1869 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1870 | vcpu->fpu_active = 0; |
1871 | } | |
6aa8b732 AK |
1872 | } |
1873 | ||
6aa8b732 AK |
1874 | static int is_disabled(void) |
1875 | { | |
6031a61c JR |
1876 | u64 vm_cr; |
1877 | ||
1878 | rdmsrl(MSR_VM_CR, vm_cr); | |
1879 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1880 | return 1; | |
1881 | ||
6aa8b732 AK |
1882 | return 0; |
1883 | } | |
1884 | ||
102d8325 IM |
1885 | static void |
1886 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1887 | { | |
1888 | /* | |
1889 | * Patch in the VMMCALL instruction: | |
1890 | */ | |
1891 | hypercall[0] = 0x0f; | |
1892 | hypercall[1] = 0x01; | |
1893 | hypercall[2] = 0xd9; | |
102d8325 IM |
1894 | } |
1895 | ||
002c7f7c YS |
1896 | static void svm_check_processor_compat(void *rtn) |
1897 | { | |
1898 | *(int *)rtn = 0; | |
1899 | } | |
1900 | ||
774ead3a AK |
1901 | static bool svm_cpu_has_accelerated_tpr(void) |
1902 | { | |
1903 | return false; | |
1904 | } | |
1905 | ||
67253af5 SY |
1906 | static int get_npt_level(void) |
1907 | { | |
1908 | #ifdef CONFIG_X86_64 | |
1909 | return PT64_ROOT_LEVEL; | |
1910 | #else | |
1911 | return PT32E_ROOT_LEVEL; | |
1912 | #endif | |
1913 | } | |
1914 | ||
cbdd1bea | 1915 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
1916 | .cpu_has_kvm_support = has_svm, |
1917 | .disabled_by_bios = is_disabled, | |
1918 | .hardware_setup = svm_hardware_setup, | |
1919 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 1920 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
1921 | .hardware_enable = svm_hardware_enable, |
1922 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 1923 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
1924 | |
1925 | .vcpu_create = svm_create_vcpu, | |
1926 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 1927 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 1928 | |
04d2cc77 | 1929 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
1930 | .vcpu_load = svm_vcpu_load, |
1931 | .vcpu_put = svm_vcpu_put, | |
1932 | ||
1933 | .set_guest_debug = svm_guest_debug, | |
1934 | .get_msr = svm_get_msr, | |
1935 | .set_msr = svm_set_msr, | |
1936 | .get_segment_base = svm_get_segment_base, | |
1937 | .get_segment = svm_get_segment, | |
1938 | .set_segment = svm_set_segment, | |
2e4d2653 | 1939 | .get_cpl = svm_get_cpl, |
1747fb71 | 1940 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 1941 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1942 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1943 | .set_cr3 = svm_set_cr3, |
1944 | .set_cr4 = svm_set_cr4, | |
1945 | .set_efer = svm_set_efer, | |
1946 | .get_idt = svm_get_idt, | |
1947 | .set_idt = svm_set_idt, | |
1948 | .get_gdt = svm_get_gdt, | |
1949 | .set_gdt = svm_set_gdt, | |
1950 | .get_dr = svm_get_dr, | |
1951 | .set_dr = svm_set_dr, | |
1952 | .cache_regs = svm_cache_regs, | |
1953 | .decache_regs = svm_decache_regs, | |
1954 | .get_rflags = svm_get_rflags, | |
1955 | .set_rflags = svm_set_rflags, | |
1956 | ||
6aa8b732 | 1957 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 1958 | |
6aa8b732 | 1959 | .run = svm_vcpu_run, |
04d2cc77 | 1960 | .handle_exit = handle_exit, |
6aa8b732 | 1961 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 1962 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 ED |
1963 | .get_irq = svm_get_irq, |
1964 | .set_irq = svm_set_irq, | |
298101da AK |
1965 | .queue_exception = svm_queue_exception, |
1966 | .exception_injected = svm_exception_injected, | |
04d2cc77 AK |
1967 | .inject_pending_irq = svm_intr_assist, |
1968 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
1969 | |
1970 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 1971 | .get_tdp_level = get_npt_level, |
6aa8b732 AK |
1972 | }; |
1973 | ||
1974 | static int __init svm_init(void) | |
1975 | { | |
cb498ea2 | 1976 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 1977 | THIS_MODULE); |
6aa8b732 AK |
1978 | } |
1979 | ||
1980 | static void __exit svm_exit(void) | |
1981 | { | |
cb498ea2 | 1982 | kvm_exit(); |
6aa8b732 AK |
1983 | } |
1984 | ||
1985 | module_init(svm_init) | |
1986 | module_exit(svm_exit) |