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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
edf88417 AK |
16 | #include <linux/kvm_host.h> |
17 | ||
e495606d | 18 | #include "kvm_svm.h" |
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
6aa8b732 | 22 | #include <linux/module.h> |
9d8f549d | 23 | #include <linux/kernel.h> |
6aa8b732 AK |
24 | #include <linux/vmalloc.h> |
25 | #include <linux/highmem.h> | |
e8edc6e0 | 26 | #include <linux/sched.h> |
6aa8b732 | 27 | |
e495606d | 28 | #include <asm/desc.h> |
6aa8b732 AK |
29 | |
30 | MODULE_AUTHOR("Qumranet"); | |
31 | MODULE_LICENSE("GPL"); | |
32 | ||
33 | #define IOPM_ALLOC_ORDER 2 | |
34 | #define MSRPM_ALLOC_ORDER 1 | |
35 | ||
36 | #define DB_VECTOR 1 | |
37 | #define UD_VECTOR 6 | |
38 | #define GP_VECTOR 13 | |
39 | ||
40 | #define DR7_GD_MASK (1 << 13) | |
41 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
42 | |
43 | #define SEG_TYPE_LDT 2 | |
44 | #define SEG_TYPE_BUSY_TSS16 3 | |
45 | ||
80b7706e JR |
46 | #define SVM_FEATURE_NPT (1 << 0) |
47 | #define SVM_FEATURE_LBRV (1 << 1) | |
48 | #define SVM_DEATURE_SVML (1 << 2) | |
49 | ||
709ddebf JR |
50 | /* enable NPT for AMD64 and X86 with PAE */ |
51 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
52 | static bool npt_enabled = true; | |
53 | #else | |
e3da3acd | 54 | static bool npt_enabled = false; |
709ddebf | 55 | #endif |
6c7dac72 JR |
56 | static int npt = 1; |
57 | ||
58 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 59 | |
04d2cc77 AK |
60 | static void kvm_reput_irq(struct vcpu_svm *svm); |
61 | ||
a2fa3e9f GH |
62 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
63 | { | |
fb3f0f51 | 64 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
65 | } |
66 | ||
6aa8b732 AK |
67 | unsigned long iopm_base; |
68 | unsigned long msrpm_base; | |
69 | ||
70 | struct kvm_ldttss_desc { | |
71 | u16 limit0; | |
72 | u16 base0; | |
73 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
74 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
75 | u32 base3; | |
76 | u32 zero1; | |
77 | } __attribute__((packed)); | |
78 | ||
79 | struct svm_cpu_data { | |
80 | int cpu; | |
81 | ||
5008fdf5 AK |
82 | u64 asid_generation; |
83 | u32 max_asid; | |
84 | u32 next_asid; | |
6aa8b732 AK |
85 | struct kvm_ldttss_desc *tss_desc; |
86 | ||
87 | struct page *save_area; | |
88 | }; | |
89 | ||
90 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 91 | static uint32_t svm_features; |
6aa8b732 AK |
92 | |
93 | struct svm_init_data { | |
94 | int cpu; | |
95 | int r; | |
96 | }; | |
97 | ||
98 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
99 | ||
9d8f549d | 100 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
101 | #define MSRS_RANGE_SIZE 2048 |
102 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
103 | ||
104 | #define MAX_INST_SIZE 15 | |
105 | ||
80b7706e JR |
106 | static inline u32 svm_has(u32 feat) |
107 | { | |
108 | return svm_features & feat; | |
109 | } | |
110 | ||
6aa8b732 AK |
111 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) |
112 | { | |
ad312c7c ZX |
113 | int word_index = __ffs(vcpu->arch.irq_summary); |
114 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
115 | int irq = word_index * BITS_PER_LONG + bit_index; |
116 | ||
ad312c7c ZX |
117 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
118 | if (!vcpu->arch.irq_pending[word_index]) | |
119 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
120 | return irq; |
121 | } | |
122 | ||
123 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
124 | { | |
ad312c7c ZX |
125 | set_bit(irq, vcpu->arch.irq_pending); |
126 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
127 | } |
128 | ||
129 | static inline void clgi(void) | |
130 | { | |
131 | asm volatile (SVM_CLGI); | |
132 | } | |
133 | ||
134 | static inline void stgi(void) | |
135 | { | |
136 | asm volatile (SVM_STGI); | |
137 | } | |
138 | ||
139 | static inline void invlpga(unsigned long addr, u32 asid) | |
140 | { | |
141 | asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid)); | |
142 | } | |
143 | ||
144 | static inline unsigned long kvm_read_cr2(void) | |
145 | { | |
146 | unsigned long cr2; | |
147 | ||
148 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
149 | return cr2; | |
150 | } | |
151 | ||
152 | static inline void kvm_write_cr2(unsigned long val) | |
153 | { | |
154 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
155 | } | |
156 | ||
157 | static inline unsigned long read_dr6(void) | |
158 | { | |
159 | unsigned long dr6; | |
160 | ||
161 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
162 | return dr6; | |
163 | } | |
164 | ||
165 | static inline void write_dr6(unsigned long val) | |
166 | { | |
167 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
168 | } | |
169 | ||
170 | static inline unsigned long read_dr7(void) | |
171 | { | |
172 | unsigned long dr7; | |
173 | ||
174 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
175 | return dr7; | |
176 | } | |
177 | ||
178 | static inline void write_dr7(unsigned long val) | |
179 | { | |
180 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
181 | } | |
182 | ||
6aa8b732 AK |
183 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
184 | { | |
a2fa3e9f | 185 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
186 | } |
187 | ||
188 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
189 | { | |
190 | force_new_asid(vcpu); | |
191 | } | |
192 | ||
193 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
194 | { | |
709ddebf | 195 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 196 | efer &= ~EFER_LME; |
6aa8b732 | 197 | |
a2fa3e9f | 198 | to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; |
ad312c7c | 199 | vcpu->arch.shadow_efer = efer; |
6aa8b732 AK |
200 | } |
201 | ||
298101da AK |
202 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
203 | bool has_error_code, u32 error_code) | |
204 | { | |
205 | struct vcpu_svm *svm = to_svm(vcpu); | |
206 | ||
207 | svm->vmcb->control.event_inj = nr | |
208 | | SVM_EVTINJ_VALID | |
209 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
210 | | SVM_EVTINJ_TYPE_EXEPT; | |
211 | svm->vmcb->control.event_inj_err = error_code; | |
212 | } | |
213 | ||
214 | static bool svm_exception_injected(struct kvm_vcpu *vcpu) | |
215 | { | |
216 | struct vcpu_svm *svm = to_svm(vcpu); | |
217 | ||
218 | return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID); | |
219 | } | |
220 | ||
6aa8b732 AK |
221 | static int is_external_interrupt(u32 info) |
222 | { | |
223 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
224 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
225 | } | |
226 | ||
227 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
228 | { | |
a2fa3e9f GH |
229 | struct vcpu_svm *svm = to_svm(vcpu); |
230 | ||
231 | if (!svm->next_rip) { | |
6aa8b732 AK |
232 | printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__); |
233 | return; | |
234 | } | |
d77c26fc | 235 | if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) |
6aa8b732 AK |
236 | printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n", |
237 | __FUNCTION__, | |
a2fa3e9f GH |
238 | svm->vmcb->save.rip, |
239 | svm->next_rip); | |
6aa8b732 | 240 | |
ad312c7c | 241 | vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip; |
a2fa3e9f | 242 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; |
c1150d8c | 243 | |
ad312c7c | 244 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
245 | } |
246 | ||
247 | static int has_svm(void) | |
248 | { | |
249 | uint32_t eax, ebx, ecx, edx; | |
250 | ||
1e885461 | 251 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
252 | printk(KERN_INFO "has_svm: not amd\n"); |
253 | return 0; | |
254 | } | |
255 | ||
256 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
257 | if (eax < SVM_CPUID_FUNC) { | |
258 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
259 | return 0; | |
260 | } | |
261 | ||
262 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
263 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
264 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
265 | return 0; | |
266 | } | |
267 | return 1; | |
268 | } | |
269 | ||
270 | static void svm_hardware_disable(void *garbage) | |
271 | { | |
272 | struct svm_cpu_data *svm_data | |
273 | = per_cpu(svm_data, raw_smp_processor_id()); | |
274 | ||
275 | if (svm_data) { | |
276 | uint64_t efer; | |
277 | ||
278 | wrmsrl(MSR_VM_HSAVE_PA, 0); | |
279 | rdmsrl(MSR_EFER, efer); | |
280 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
8b6d44c7 | 281 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; |
6aa8b732 AK |
282 | __free_page(svm_data->save_area); |
283 | kfree(svm_data); | |
284 | } | |
285 | } | |
286 | ||
287 | static void svm_hardware_enable(void *garbage) | |
288 | { | |
289 | ||
290 | struct svm_cpu_data *svm_data; | |
291 | uint64_t efer; | |
05b3e0c2 | 292 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
293 | struct desc_ptr gdt_descr; |
294 | #else | |
6b68f01b | 295 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
296 | #endif |
297 | struct desc_struct *gdt; | |
298 | int me = raw_smp_processor_id(); | |
299 | ||
300 | if (!has_svm()) { | |
301 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
302 | return; | |
303 | } | |
304 | svm_data = per_cpu(svm_data, me); | |
305 | ||
306 | if (!svm_data) { | |
307 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
308 | me); | |
309 | return; | |
310 | } | |
311 | ||
312 | svm_data->asid_generation = 1; | |
313 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
314 | svm_data->next_asid = svm_data->max_asid + 1; | |
315 | ||
d77c26fc | 316 | asm volatile ("sgdt %0" : "=m"(gdt_descr)); |
6aa8b732 AK |
317 | gdt = (struct desc_struct *)gdt_descr.address; |
318 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
319 | ||
320 | rdmsrl(MSR_EFER, efer); | |
321 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
322 | ||
323 | wrmsrl(MSR_VM_HSAVE_PA, | |
324 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
325 | } | |
326 | ||
327 | static int svm_cpu_init(int cpu) | |
328 | { | |
329 | struct svm_cpu_data *svm_data; | |
330 | int r; | |
331 | ||
332 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
333 | if (!svm_data) | |
334 | return -ENOMEM; | |
335 | svm_data->cpu = cpu; | |
336 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
337 | r = -ENOMEM; | |
338 | if (!svm_data->save_area) | |
339 | goto err_1; | |
340 | ||
341 | per_cpu(svm_data, cpu) = svm_data; | |
342 | ||
343 | return 0; | |
344 | ||
345 | err_1: | |
346 | kfree(svm_data); | |
347 | return r; | |
348 | ||
349 | } | |
350 | ||
bfc733a7 RR |
351 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
352 | int read, int write) | |
6aa8b732 AK |
353 | { |
354 | int i; | |
355 | ||
356 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
357 | if (msr >= msrpm_ranges[i] && | |
358 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
359 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
360 | msrpm_ranges[i]) * 2; | |
361 | ||
362 | u32 *base = msrpm + (msr_offset / 32); | |
363 | u32 msr_shift = msr_offset % 32; | |
364 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
365 | *base = (*base & ~(0x3 << msr_shift)) | | |
366 | (mask << msr_shift); | |
bfc733a7 | 367 | return; |
6aa8b732 AK |
368 | } |
369 | } | |
bfc733a7 | 370 | BUG(); |
6aa8b732 AK |
371 | } |
372 | ||
373 | static __init int svm_hardware_setup(void) | |
374 | { | |
375 | int cpu; | |
376 | struct page *iopm_pages; | |
377 | struct page *msrpm_pages; | |
c8681339 | 378 | void *iopm_va, *msrpm_va; |
6aa8b732 AK |
379 | int r; |
380 | ||
6aa8b732 AK |
381 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
382 | ||
383 | if (!iopm_pages) | |
384 | return -ENOMEM; | |
c8681339 AL |
385 | |
386 | iopm_va = page_address(iopm_pages); | |
387 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
388 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
389 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
390 | ||
391 | ||
392 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
393 | ||
394 | r = -ENOMEM; | |
395 | if (!msrpm_pages) | |
396 | goto err_1; | |
397 | ||
398 | msrpm_va = page_address(msrpm_pages); | |
399 | memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
400 | msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT; | |
401 | ||
05b3e0c2 | 402 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
403 | set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1); |
404 | set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1); | |
405 | set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1); | |
6aa8b732 AK |
406 | set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1); |
407 | set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1); | |
408 | set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1); | |
409 | #endif | |
0e859cac | 410 | set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1); |
6aa8b732 AK |
411 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1); |
412 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1); | |
413 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1); | |
414 | ||
50a37eb4 JR |
415 | if (boot_cpu_has(X86_FEATURE_NX)) |
416 | kvm_enable_efer_bits(EFER_NX); | |
417 | ||
6aa8b732 AK |
418 | for_each_online_cpu(cpu) { |
419 | r = svm_cpu_init(cpu); | |
420 | if (r) | |
421 | goto err_2; | |
422 | } | |
33bd6a0b JR |
423 | |
424 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
425 | ||
e3da3acd JR |
426 | if (!svm_has(SVM_FEATURE_NPT)) |
427 | npt_enabled = false; | |
428 | ||
6c7dac72 JR |
429 | if (npt_enabled && !npt) { |
430 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
431 | npt_enabled = false; | |
432 | } | |
433 | ||
18552672 | 434 | if (npt_enabled) { |
e3da3acd | 435 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 JR |
436 | kvm_enable_tdp(); |
437 | } | |
e3da3acd | 438 | |
6aa8b732 AK |
439 | return 0; |
440 | ||
441 | err_2: | |
442 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
443 | msrpm_base = 0; | |
444 | err_1: | |
445 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); | |
446 | iopm_base = 0; | |
447 | return r; | |
448 | } | |
449 | ||
450 | static __exit void svm_hardware_unsetup(void) | |
451 | { | |
452 | __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER); | |
453 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); | |
454 | iopm_base = msrpm_base = 0; | |
455 | } | |
456 | ||
457 | static void init_seg(struct vmcb_seg *seg) | |
458 | { | |
459 | seg->selector = 0; | |
460 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
461 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
462 | seg->limit = 0xffff; | |
463 | seg->base = 0; | |
464 | } | |
465 | ||
466 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
467 | { | |
468 | seg->selector = 0; | |
469 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
470 | seg->limit = 0xffff; | |
471 | seg->base = 0; | |
472 | } | |
473 | ||
e6101a96 | 474 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 475 | { |
e6101a96 JR |
476 | struct vmcb_control_area *control = &svm->vmcb->control; |
477 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 AK |
478 | |
479 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
480 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
481 | INTERCEPT_CR4_MASK | |
482 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
483 | |
484 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
485 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
486 | INTERCEPT_CR4_MASK | |
487 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
488 | |
489 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
490 | INTERCEPT_DR1_MASK | | |
491 | INTERCEPT_DR2_MASK | | |
492 | INTERCEPT_DR3_MASK; | |
493 | ||
494 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
495 | INTERCEPT_DR1_MASK | | |
496 | INTERCEPT_DR2_MASK | | |
497 | INTERCEPT_DR3_MASK | | |
498 | INTERCEPT_DR5_MASK | | |
499 | INTERCEPT_DR7_MASK; | |
500 | ||
7aa81cc0 AL |
501 | control->intercept_exceptions = (1 << PF_VECTOR) | |
502 | (1 << UD_VECTOR); | |
6aa8b732 AK |
503 | |
504 | ||
505 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
506 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 507 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 AK |
508 | /* |
509 | * selective cr0 intercept bug? | |
510 | * 0: 0f 22 d8 mov %eax,%cr3 | |
511 | * 3: 0f 20 c0 mov %cr0,%eax | |
512 | * 6: 0d 00 00 00 80 or $0x80000000,%eax | |
513 | * b: 0f 22 c0 mov %eax,%cr0 | |
514 | * set cr3 ->interception | |
515 | * get cr0 ->interception | |
516 | * set cr0 -> no interception | |
517 | */ | |
518 | /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */ | |
519 | (1ULL << INTERCEPT_CPUID) | | |
cf5a94d1 | 520 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 521 | (1ULL << INTERCEPT_HLT) | |
6aa8b732 AK |
522 | (1ULL << INTERCEPT_INVLPGA) | |
523 | (1ULL << INTERCEPT_IOIO_PROT) | | |
524 | (1ULL << INTERCEPT_MSR_PROT) | | |
525 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 526 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
527 | (1ULL << INTERCEPT_VMRUN) | |
528 | (1ULL << INTERCEPT_VMMCALL) | | |
529 | (1ULL << INTERCEPT_VMLOAD) | | |
530 | (1ULL << INTERCEPT_VMSAVE) | | |
531 | (1ULL << INTERCEPT_STGI) | | |
532 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 533 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 534 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
535 | (1ULL << INTERCEPT_MONITOR) | |
536 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
537 | |
538 | control->iopm_base_pa = iopm_base; | |
539 | control->msrpm_base_pa = msrpm_base; | |
0cc5064d | 540 | control->tsc_offset = 0; |
6aa8b732 AK |
541 | control->int_ctl = V_INTR_MASKING_MASK; |
542 | ||
543 | init_seg(&save->es); | |
544 | init_seg(&save->ss); | |
545 | init_seg(&save->ds); | |
546 | init_seg(&save->fs); | |
547 | init_seg(&save->gs); | |
548 | ||
549 | save->cs.selector = 0xf000; | |
550 | /* Executable/Readable Code Segment */ | |
551 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
552 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
553 | save->cs.limit = 0xffff; | |
d92899a0 AK |
554 | /* |
555 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
556 | * be consistent with it. | |
557 | * | |
558 | * Replace when we have real mode working for vmx. | |
559 | */ | |
560 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
561 | |
562 | save->gdtr.limit = 0xffff; | |
563 | save->idtr.limit = 0xffff; | |
564 | ||
565 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
566 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
567 | ||
568 | save->efer = MSR_EFER_SVME_MASK; | |
d77c26fc | 569 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
570 | save->dr7 = 0x400; |
571 | save->rflags = 2; | |
572 | save->rip = 0x0000fff0; | |
573 | ||
574 | /* | |
575 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
576 | * cache by default. the orderly way is to enable cache in bios. | |
577 | */ | |
707d92fa | 578 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 579 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 580 | /* rdx = ?? */ |
709ddebf JR |
581 | |
582 | if (npt_enabled) { | |
583 | /* Setup VMCB for Nested Paging */ | |
584 | control->nested_ctl = 1; | |
585 | control->intercept_exceptions &= ~(1 << PF_VECTOR); | |
586 | control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK| | |
587 | INTERCEPT_CR3_MASK); | |
588 | control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK| | |
589 | INTERCEPT_CR3_MASK); | |
590 | save->g_pat = 0x0007040600070406ULL; | |
591 | /* enable caching because the QEMU Bios doesn't enable it */ | |
592 | save->cr0 = X86_CR0_ET; | |
593 | save->cr3 = 0; | |
594 | save->cr4 = 0; | |
595 | } | |
596 | ||
6aa8b732 AK |
597 | } |
598 | ||
e00c8cf2 | 599 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
600 | { |
601 | struct vcpu_svm *svm = to_svm(vcpu); | |
602 | ||
e6101a96 | 603 | init_vmcb(svm); |
70433389 AK |
604 | |
605 | if (vcpu->vcpu_id != 0) { | |
606 | svm->vmcb->save.rip = 0; | |
ad312c7c ZX |
607 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
608 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 609 | } |
e00c8cf2 AK |
610 | |
611 | return 0; | |
04d2cc77 AK |
612 | } |
613 | ||
fb3f0f51 | 614 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 615 | { |
a2fa3e9f | 616 | struct vcpu_svm *svm; |
6aa8b732 | 617 | struct page *page; |
fb3f0f51 | 618 | int err; |
6aa8b732 | 619 | |
c16f862d | 620 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
621 | if (!svm) { |
622 | err = -ENOMEM; | |
623 | goto out; | |
624 | } | |
625 | ||
626 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
627 | if (err) | |
628 | goto free_svm; | |
629 | ||
6aa8b732 | 630 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
631 | if (!page) { |
632 | err = -ENOMEM; | |
633 | goto uninit; | |
634 | } | |
6aa8b732 | 635 | |
a2fa3e9f GH |
636 | svm->vmcb = page_address(page); |
637 | clear_page(svm->vmcb); | |
638 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
639 | svm->asid_generation = 0; | |
640 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
e6101a96 | 641 | init_vmcb(svm); |
a2fa3e9f | 642 | |
fb3f0f51 RR |
643 | fx_init(&svm->vcpu); |
644 | svm->vcpu.fpu_active = 1; | |
ad312c7c | 645 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
fb3f0f51 | 646 | if (svm->vcpu.vcpu_id == 0) |
ad312c7c | 647 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 648 | |
fb3f0f51 | 649 | return &svm->vcpu; |
36241b8c | 650 | |
fb3f0f51 RR |
651 | uninit: |
652 | kvm_vcpu_uninit(&svm->vcpu); | |
653 | free_svm: | |
a4770347 | 654 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
655 | out: |
656 | return ERR_PTR(err); | |
6aa8b732 AK |
657 | } |
658 | ||
659 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
660 | { | |
a2fa3e9f GH |
661 | struct vcpu_svm *svm = to_svm(vcpu); |
662 | ||
fb3f0f51 RR |
663 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
664 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 665 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
666 | } |
667 | ||
15ad7146 | 668 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 669 | { |
a2fa3e9f | 670 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 671 | int i; |
0cc5064d | 672 | |
0cc5064d AK |
673 | if (unlikely(cpu != vcpu->cpu)) { |
674 | u64 tsc_this, delta; | |
675 | ||
676 | /* | |
677 | * Make sure that the guest sees a monotonically | |
678 | * increasing TSC. | |
679 | */ | |
680 | rdtscll(tsc_this); | |
ad312c7c | 681 | delta = vcpu->arch.host_tsc - tsc_this; |
a2fa3e9f | 682 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d | 683 | vcpu->cpu = cpu; |
a3d7f85f | 684 | kvm_migrate_apic_timer(vcpu); |
0cc5064d | 685 | } |
94dfbdb3 AL |
686 | |
687 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 688 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
689 | } |
690 | ||
691 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
692 | { | |
a2fa3e9f | 693 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
694 | int i; |
695 | ||
e1beb1d3 | 696 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 697 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 698 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 699 | |
ad312c7c | 700 | rdtscll(vcpu->arch.host_tsc); |
6aa8b732 AK |
701 | } |
702 | ||
774c47f1 AK |
703 | static void svm_vcpu_decache(struct kvm_vcpu *vcpu) |
704 | { | |
705 | } | |
706 | ||
6aa8b732 AK |
707 | static void svm_cache_regs(struct kvm_vcpu *vcpu) |
708 | { | |
a2fa3e9f GH |
709 | struct vcpu_svm *svm = to_svm(vcpu); |
710 | ||
ad312c7c ZX |
711 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; |
712 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
713 | vcpu->arch.rip = svm->vmcb->save.rip; | |
6aa8b732 AK |
714 | } |
715 | ||
716 | static void svm_decache_regs(struct kvm_vcpu *vcpu) | |
717 | { | |
a2fa3e9f | 718 | struct vcpu_svm *svm = to_svm(vcpu); |
ad312c7c ZX |
719 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
720 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
721 | svm->vmcb->save.rip = vcpu->arch.rip; | |
6aa8b732 AK |
722 | } |
723 | ||
724 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
725 | { | |
a2fa3e9f | 726 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
727 | } |
728 | ||
729 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
730 | { | |
a2fa3e9f | 731 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
732 | } |
733 | ||
734 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
735 | { | |
a2fa3e9f | 736 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
737 | |
738 | switch (seg) { | |
739 | case VCPU_SREG_CS: return &save->cs; | |
740 | case VCPU_SREG_DS: return &save->ds; | |
741 | case VCPU_SREG_ES: return &save->es; | |
742 | case VCPU_SREG_FS: return &save->fs; | |
743 | case VCPU_SREG_GS: return &save->gs; | |
744 | case VCPU_SREG_SS: return &save->ss; | |
745 | case VCPU_SREG_TR: return &save->tr; | |
746 | case VCPU_SREG_LDTR: return &save->ldtr; | |
747 | } | |
748 | BUG(); | |
8b6d44c7 | 749 | return NULL; |
6aa8b732 AK |
750 | } |
751 | ||
752 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
753 | { | |
754 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
755 | ||
756 | return s->base; | |
757 | } | |
758 | ||
759 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
760 | struct kvm_segment *var, int seg) | |
761 | { | |
762 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
763 | ||
764 | var->base = s->base; | |
765 | var->limit = s->limit; | |
766 | var->selector = s->selector; | |
767 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
768 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
769 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
770 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
771 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
772 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
773 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
774 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
775 | var->unusable = !var->present; | |
776 | } | |
777 | ||
6aa8b732 AK |
778 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
779 | { | |
a2fa3e9f GH |
780 | struct vcpu_svm *svm = to_svm(vcpu); |
781 | ||
782 | dt->limit = svm->vmcb->save.idtr.limit; | |
783 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
784 | } |
785 | ||
786 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
787 | { | |
a2fa3e9f GH |
788 | struct vcpu_svm *svm = to_svm(vcpu); |
789 | ||
790 | svm->vmcb->save.idtr.limit = dt->limit; | |
791 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
792 | } |
793 | ||
794 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
795 | { | |
a2fa3e9f GH |
796 | struct vcpu_svm *svm = to_svm(vcpu); |
797 | ||
798 | dt->limit = svm->vmcb->save.gdtr.limit; | |
799 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
800 | } |
801 | ||
802 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
803 | { | |
a2fa3e9f GH |
804 | struct vcpu_svm *svm = to_svm(vcpu); |
805 | ||
806 | svm->vmcb->save.gdtr.limit = dt->limit; | |
807 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
808 | } |
809 | ||
25c4c276 | 810 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
811 | { |
812 | } | |
813 | ||
6aa8b732 AK |
814 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
815 | { | |
a2fa3e9f GH |
816 | struct vcpu_svm *svm = to_svm(vcpu); |
817 | ||
05b3e0c2 | 818 | #ifdef CONFIG_X86_64 |
ad312c7c | 819 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 820 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
ad312c7c | 821 | vcpu->arch.shadow_efer |= EFER_LMA; |
2b5203ee | 822 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
823 | } |
824 | ||
d77c26fc | 825 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
ad312c7c | 826 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
2b5203ee | 827 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
828 | } |
829 | } | |
830 | #endif | |
709ddebf JR |
831 | if (npt_enabled) |
832 | goto set; | |
833 | ||
ad312c7c | 834 | if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 835 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
836 | vcpu->fpu_active = 1; |
837 | } | |
838 | ||
ad312c7c | 839 | vcpu->arch.cr0 = cr0; |
707d92fa | 840 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
6b390b63 JR |
841 | if (!vcpu->fpu_active) { |
842 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); | |
334df50a | 843 | cr0 |= X86_CR0_TS; |
6b390b63 | 844 | } |
709ddebf JR |
845 | set: |
846 | /* | |
847 | * re-enable caching here because the QEMU bios | |
848 | * does not do it - this results in some delay at | |
849 | * reboot | |
850 | */ | |
851 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 852 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
853 | } |
854 | ||
855 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
856 | { | |
ad312c7c | 857 | vcpu->arch.cr4 = cr4; |
709ddebf JR |
858 | if (!npt_enabled) |
859 | cr4 |= X86_CR4_PAE; | |
860 | to_svm(vcpu)->vmcb->save.cr4 = cr4; | |
6aa8b732 AK |
861 | } |
862 | ||
863 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
864 | struct kvm_segment *var, int seg) | |
865 | { | |
a2fa3e9f | 866 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
867 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
868 | ||
869 | s->base = var->base; | |
870 | s->limit = var->limit; | |
871 | s->selector = var->selector; | |
872 | if (var->unusable) | |
873 | s->attrib = 0; | |
874 | else { | |
875 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
876 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
877 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
878 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
879 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
880 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
881 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
882 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
883 | } | |
884 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
885 | svm->vmcb->save.cpl |
886 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
887 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
888 | ||
889 | } | |
890 | ||
891 | /* FIXME: | |
892 | ||
a2fa3e9f GH |
893 | svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK; |
894 | svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK); | |
6aa8b732 AK |
895 | |
896 | */ | |
897 | ||
898 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
899 | { | |
900 | return -EOPNOTSUPP; | |
901 | } | |
902 | ||
2a8067f1 ED |
903 | static int svm_get_irq(struct kvm_vcpu *vcpu) |
904 | { | |
905 | struct vcpu_svm *svm = to_svm(vcpu); | |
906 | u32 exit_int_info = svm->vmcb->control.exit_int_info; | |
907 | ||
908 | if (is_external_interrupt(exit_int_info)) | |
909 | return exit_int_info & SVM_EVTINJ_VEC_MASK; | |
910 | return -1; | |
911 | } | |
912 | ||
6aa8b732 AK |
913 | static void load_host_msrs(struct kvm_vcpu *vcpu) |
914 | { | |
94dfbdb3 | 915 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 916 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 917 | #endif |
6aa8b732 AK |
918 | } |
919 | ||
920 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
921 | { | |
94dfbdb3 | 922 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 923 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 924 | #endif |
6aa8b732 AK |
925 | } |
926 | ||
e756fc62 | 927 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
928 | { |
929 | if (svm_data->next_asid > svm_data->max_asid) { | |
930 | ++svm_data->asid_generation; | |
931 | svm_data->next_asid = 1; | |
a2fa3e9f | 932 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
933 | } |
934 | ||
e756fc62 | 935 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
936 | svm->asid_generation = svm_data->asid_generation; |
937 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
938 | } |
939 | ||
6aa8b732 AK |
940 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
941 | { | |
a2fa3e9f | 942 | return to_svm(vcpu)->db_regs[dr]; |
6aa8b732 AK |
943 | } |
944 | ||
945 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
946 | int *exception) | |
947 | { | |
a2fa3e9f GH |
948 | struct vcpu_svm *svm = to_svm(vcpu); |
949 | ||
6aa8b732 AK |
950 | *exception = 0; |
951 | ||
a2fa3e9f GH |
952 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
953 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
954 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
955 | *exception = DB_VECTOR; |
956 | return; | |
957 | } | |
958 | ||
959 | switch (dr) { | |
960 | case 0 ... 3: | |
a2fa3e9f | 961 | svm->db_regs[dr] = value; |
6aa8b732 AK |
962 | return; |
963 | case 4 ... 5: | |
ad312c7c | 964 | if (vcpu->arch.cr4 & X86_CR4_DE) { |
6aa8b732 AK |
965 | *exception = UD_VECTOR; |
966 | return; | |
967 | } | |
968 | case 7: { | |
969 | if (value & ~((1ULL << 32) - 1)) { | |
970 | *exception = GP_VECTOR; | |
971 | return; | |
972 | } | |
a2fa3e9f | 973 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
974 | return; |
975 | } | |
976 | default: | |
977 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
978 | __FUNCTION__, dr); | |
979 | *exception = UD_VECTOR; | |
980 | return; | |
981 | } | |
982 | } | |
983 | ||
e756fc62 | 984 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 985 | { |
a2fa3e9f | 986 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 987 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
988 | u64 fault_address; |
989 | u32 error_code; | |
6aa8b732 | 990 | |
85f455f7 ED |
991 | if (!irqchip_in_kernel(kvm) && |
992 | is_external_interrupt(exit_int_info)) | |
e756fc62 | 993 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
6aa8b732 | 994 | |
a2fa3e9f GH |
995 | fault_address = svm->vmcb->control.exit_info_2; |
996 | error_code = svm->vmcb->control.exit_info_1; | |
3067714c | 997 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
998 | } |
999 | ||
7aa81cc0 AL |
1000 | static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1001 | { | |
1002 | int er; | |
1003 | ||
571008da | 1004 | er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1005 | if (er != EMULATE_DONE) |
7ee5d940 | 1006 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1007 | return 1; |
1008 | } | |
1009 | ||
e756fc62 | 1010 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 1011 | { |
a2fa3e9f | 1012 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
ad312c7c | 1013 | if (!(svm->vcpu.arch.cr0 & X86_CR0_TS)) |
a2fa3e9f | 1014 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 1015 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
1016 | |
1017 | return 1; | |
7807fa6c AL |
1018 | } |
1019 | ||
e756fc62 | 1020 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
1021 | { |
1022 | /* | |
1023 | * VMCB is undefined after a SHUTDOWN intercept | |
1024 | * so reinitialize it. | |
1025 | */ | |
a2fa3e9f | 1026 | clear_page(svm->vmcb); |
e6101a96 | 1027 | init_vmcb(svm); |
46fe4ddd JR |
1028 | |
1029 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1030 | return 0; | |
1031 | } | |
1032 | ||
e756fc62 | 1033 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1034 | { |
d77c26fc | 1035 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
039576c0 AK |
1036 | int size, down, in, string, rep; |
1037 | unsigned port; | |
6aa8b732 | 1038 | |
e756fc62 | 1039 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1040 | |
a2fa3e9f | 1041 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1042 | |
e70669ab LV |
1043 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
1044 | ||
1045 | if (string) { | |
3427318f LV |
1046 | if (emulate_instruction(&svm->vcpu, |
1047 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
1048 | return 0; |
1049 | return 1; | |
1050 | } | |
1051 | ||
039576c0 AK |
1052 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1053 | port = io_info >> 16; | |
1054 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
039576c0 | 1055 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; |
a2fa3e9f | 1056 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1057 | |
3090dd73 | 1058 | return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1059 | } |
1060 | ||
e756fc62 | 1061 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1062 | { |
1063 | return 1; | |
1064 | } | |
1065 | ||
e756fc62 | 1066 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1067 | { |
a2fa3e9f | 1068 | svm->next_rip = svm->vmcb->save.rip + 1; |
e756fc62 RR |
1069 | skip_emulated_instruction(&svm->vcpu); |
1070 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1071 | } |
1072 | ||
e756fc62 | 1073 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1074 | { |
a2fa3e9f | 1075 | svm->next_rip = svm->vmcb->save.rip + 3; |
e756fc62 | 1076 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1077 | kvm_emulate_hypercall(&svm->vcpu); |
1078 | return 1; | |
02e235bc AK |
1079 | } |
1080 | ||
e756fc62 RR |
1081 | static int invalid_op_interception(struct vcpu_svm *svm, |
1082 | struct kvm_run *kvm_run) | |
6aa8b732 | 1083 | { |
7ee5d940 | 1084 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
1085 | return 1; |
1086 | } | |
1087 | ||
e756fc62 RR |
1088 | static int task_switch_interception(struct vcpu_svm *svm, |
1089 | struct kvm_run *kvm_run) | |
6aa8b732 | 1090 | { |
f0242478 | 1091 | pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__); |
6aa8b732 AK |
1092 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
1093 | return 0; | |
1094 | } | |
1095 | ||
e756fc62 | 1096 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1097 | { |
a2fa3e9f | 1098 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1099 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1100 | return 1; |
6aa8b732 AK |
1101 | } |
1102 | ||
e756fc62 RR |
1103 | static int emulate_on_interception(struct vcpu_svm *svm, |
1104 | struct kvm_run *kvm_run) | |
6aa8b732 | 1105 | { |
3427318f | 1106 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE) |
f0242478 | 1107 | pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__); |
6aa8b732 AK |
1108 | return 1; |
1109 | } | |
1110 | ||
1d075434 JR |
1111 | static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1112 | { | |
1113 | emulate_instruction(&svm->vcpu, NULL, 0, 0, 0); | |
1114 | if (irqchip_in_kernel(svm->vcpu.kvm)) | |
1115 | return 1; | |
1116 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; | |
1117 | return 0; | |
1118 | } | |
1119 | ||
6aa8b732 AK |
1120 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
1121 | { | |
a2fa3e9f GH |
1122 | struct vcpu_svm *svm = to_svm(vcpu); |
1123 | ||
6aa8b732 | 1124 | switch (ecx) { |
6aa8b732 AK |
1125 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1126 | u64 tsc; | |
1127 | ||
1128 | rdtscll(tsc); | |
a2fa3e9f | 1129 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1130 | break; |
1131 | } | |
0e859cac | 1132 | case MSR_K6_STAR: |
a2fa3e9f | 1133 | *data = svm->vmcb->save.star; |
6aa8b732 | 1134 | break; |
0e859cac | 1135 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1136 | case MSR_LSTAR: |
a2fa3e9f | 1137 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1138 | break; |
1139 | case MSR_CSTAR: | |
a2fa3e9f | 1140 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1141 | break; |
1142 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1143 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1144 | break; |
1145 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1146 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1147 | break; |
1148 | #endif | |
1149 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1150 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1151 | break; |
1152 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1153 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1154 | break; |
1155 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1156 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 | 1157 | break; |
a2938c80 JR |
1158 | /* Nobody will change the following 5 values in the VMCB so |
1159 | we can safely return them on rdmsr. They will always be 0 | |
1160 | until LBRV is implemented. */ | |
1161 | case MSR_IA32_DEBUGCTLMSR: | |
1162 | *data = svm->vmcb->save.dbgctl; | |
1163 | break; | |
1164 | case MSR_IA32_LASTBRANCHFROMIP: | |
1165 | *data = svm->vmcb->save.br_from; | |
1166 | break; | |
1167 | case MSR_IA32_LASTBRANCHTOIP: | |
1168 | *data = svm->vmcb->save.br_to; | |
1169 | break; | |
1170 | case MSR_IA32_LASTINTFROMIP: | |
1171 | *data = svm->vmcb->save.last_excp_from; | |
1172 | break; | |
1173 | case MSR_IA32_LASTINTTOIP: | |
1174 | *data = svm->vmcb->save.last_excp_to; | |
1175 | break; | |
6aa8b732 | 1176 | default: |
3bab1f5d | 1177 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1178 | } |
1179 | return 0; | |
1180 | } | |
1181 | ||
e756fc62 | 1182 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1183 | { |
ad312c7c | 1184 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1185 | u64 data; |
1186 | ||
e756fc62 | 1187 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
c1a5d4f9 | 1188 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1189 | else { |
a2fa3e9f | 1190 | svm->vmcb->save.rax = data & 0xffffffff; |
ad312c7c | 1191 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
a2fa3e9f | 1192 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1193 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1194 | } |
1195 | return 1; | |
1196 | } | |
1197 | ||
1198 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1199 | { | |
a2fa3e9f GH |
1200 | struct vcpu_svm *svm = to_svm(vcpu); |
1201 | ||
6aa8b732 | 1202 | switch (ecx) { |
6aa8b732 AK |
1203 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1204 | u64 tsc; | |
1205 | ||
1206 | rdtscll(tsc); | |
a2fa3e9f | 1207 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1208 | break; |
1209 | } | |
0e859cac | 1210 | case MSR_K6_STAR: |
a2fa3e9f | 1211 | svm->vmcb->save.star = data; |
6aa8b732 | 1212 | break; |
49b14f24 | 1213 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1214 | case MSR_LSTAR: |
a2fa3e9f | 1215 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1216 | break; |
1217 | case MSR_CSTAR: | |
a2fa3e9f | 1218 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1219 | break; |
1220 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1221 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1222 | break; |
1223 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1224 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1225 | break; |
1226 | #endif | |
1227 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1228 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1229 | break; |
1230 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1231 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1232 | break; |
1233 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1234 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 1235 | break; |
a2938c80 JR |
1236 | case MSR_IA32_DEBUGCTLMSR: |
1237 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
1238 | __FUNCTION__, data); | |
1239 | break; | |
62b9abaa JR |
1240 | case MSR_K7_EVNTSEL0: |
1241 | case MSR_K7_EVNTSEL1: | |
1242 | case MSR_K7_EVNTSEL2: | |
1243 | case MSR_K7_EVNTSEL3: | |
1244 | /* | |
1245 | * only support writing 0 to the performance counters for now | |
1246 | * to make Windows happy. Should be replaced by a real | |
1247 | * performance counter emulation later. | |
1248 | */ | |
1249 | if (data != 0) | |
1250 | goto unhandled; | |
1251 | break; | |
6aa8b732 | 1252 | default: |
62b9abaa | 1253 | unhandled: |
3bab1f5d | 1254 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1255 | } |
1256 | return 0; | |
1257 | } | |
1258 | ||
e756fc62 | 1259 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1260 | { |
ad312c7c | 1261 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
a2fa3e9f | 1262 | u64 data = (svm->vmcb->save.rax & -1u) |
ad312c7c | 1263 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
a2fa3e9f | 1264 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1265 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
c1a5d4f9 | 1266 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1267 | else |
e756fc62 | 1268 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1269 | return 1; |
1270 | } | |
1271 | ||
e756fc62 | 1272 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1273 | { |
e756fc62 RR |
1274 | if (svm->vmcb->control.exit_info_1) |
1275 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1276 | else |
e756fc62 | 1277 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1278 | } |
1279 | ||
e756fc62 | 1280 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1281 | struct kvm_run *kvm_run) |
1282 | { | |
85f455f7 ED |
1283 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); |
1284 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
c1150d8c DL |
1285 | /* |
1286 | * If the user space waits to inject interrupts, exit as soon as | |
1287 | * possible | |
1288 | */ | |
1289 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 1290 | !svm->vcpu.arch.irq_summary) { |
e756fc62 | 1291 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
1292 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | return 1; | |
1297 | } | |
1298 | ||
e756fc62 | 1299 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1300 | struct kvm_run *kvm_run) = { |
1301 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1302 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1303 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
80a8119c | 1304 | [SVM_EXIT_READ_CR8] = emulate_on_interception, |
6aa8b732 AK |
1305 | /* for now: */ |
1306 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1307 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1308 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1d075434 | 1309 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
6aa8b732 AK |
1310 | [SVM_EXIT_READ_DR0] = emulate_on_interception, |
1311 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1312 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1313 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1314 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1315 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1316 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1317 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1318 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1319 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
7aa81cc0 | 1320 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 1321 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 1322 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
6aa8b732 AK |
1323 | [SVM_EXIT_INTR] = nop_on_interception, |
1324 | [SVM_EXIT_NMI] = nop_on_interception, | |
1325 | [SVM_EXIT_SMI] = nop_on_interception, | |
1326 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1327 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1328 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1329 | [SVM_EXIT_CPUID] = cpuid_interception, | |
cf5a94d1 | 1330 | [SVM_EXIT_INVD] = emulate_on_interception, |
6aa8b732 AK |
1331 | [SVM_EXIT_HLT] = halt_interception, |
1332 | [SVM_EXIT_INVLPG] = emulate_on_interception, | |
1333 | [SVM_EXIT_INVLPGA] = invalid_op_interception, | |
1334 | [SVM_EXIT_IOIO] = io_interception, | |
1335 | [SVM_EXIT_MSR] = msr_interception, | |
1336 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1337 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1338 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1339 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1340 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1341 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1342 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1343 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1344 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
cf5a94d1 | 1345 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
1346 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1347 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 1348 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
1349 | }; |
1350 | ||
04d2cc77 | 1351 | static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
6aa8b732 | 1352 | { |
04d2cc77 | 1353 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1354 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1355 | |
709ddebf JR |
1356 | if (npt_enabled) { |
1357 | int mmu_reload = 0; | |
1358 | if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) { | |
1359 | svm_set_cr0(vcpu, svm->vmcb->save.cr0); | |
1360 | mmu_reload = 1; | |
1361 | } | |
1362 | vcpu->arch.cr0 = svm->vmcb->save.cr0; | |
1363 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
1364 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
1365 | if (!load_pdptrs(vcpu, vcpu->arch.cr3)) { | |
1366 | kvm_inject_gp(vcpu, 0); | |
1367 | return 1; | |
1368 | } | |
1369 | } | |
1370 | if (mmu_reload) { | |
1371 | kvm_mmu_reset_context(vcpu); | |
1372 | kvm_mmu_load(vcpu); | |
1373 | } | |
1374 | } | |
1375 | ||
04d2cc77 AK |
1376 | kvm_reput_irq(svm); |
1377 | ||
1378 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
1379 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
1380 | kvm_run->fail_entry.hardware_entry_failure_reason | |
1381 | = svm->vmcb->control.exit_code; | |
1382 | return 0; | |
1383 | } | |
1384 | ||
a2fa3e9f | 1385 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf JR |
1386 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
1387 | exit_code != SVM_EXIT_NPF) | |
6aa8b732 AK |
1388 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
1389 | "exit_code 0x%x\n", | |
a2fa3e9f | 1390 | __FUNCTION__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1391 | exit_code); |
1392 | ||
9d8f549d | 1393 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 1394 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 1395 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 1396 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1397 | return 0; |
1398 | } | |
1399 | ||
e756fc62 | 1400 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1401 | } |
1402 | ||
1403 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1404 | { | |
1405 | int cpu = raw_smp_processor_id(); | |
1406 | ||
1407 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
d77c26fc | 1408 | svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */ |
6aa8b732 AK |
1409 | load_TR_desc(); |
1410 | } | |
1411 | ||
e756fc62 | 1412 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1413 | { |
1414 | int cpu = raw_smp_processor_id(); | |
1415 | ||
1416 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1417 | ||
a2fa3e9f | 1418 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1419 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1420 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1421 | new_asid(svm, svm_data); |
6aa8b732 AK |
1422 | } |
1423 | ||
1424 | ||
85f455f7 | 1425 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
1426 | { |
1427 | struct vmcb_control_area *control; | |
1428 | ||
e756fc62 | 1429 | control = &svm->vmcb->control; |
85f455f7 | 1430 | control->int_vector = irq; |
6aa8b732 AK |
1431 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1432 | control->int_ctl |= V_IRQ_MASK | | |
1433 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1434 | } | |
1435 | ||
2a8067f1 ED |
1436 | static void svm_set_irq(struct kvm_vcpu *vcpu, int irq) |
1437 | { | |
1438 | struct vcpu_svm *svm = to_svm(vcpu); | |
1439 | ||
1440 | svm_inject_irq(svm, irq); | |
1441 | } | |
1442 | ||
04d2cc77 | 1443 | static void svm_intr_assist(struct kvm_vcpu *vcpu) |
6aa8b732 | 1444 | { |
04d2cc77 | 1445 | struct vcpu_svm *svm = to_svm(vcpu); |
85f455f7 ED |
1446 | struct vmcb *vmcb = svm->vmcb; |
1447 | int intr_vector = -1; | |
1448 | ||
1449 | if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) && | |
1450 | ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) { | |
1451 | intr_vector = vmcb->control.exit_int_info & | |
1452 | SVM_EVTINJ_VEC_MASK; | |
1453 | vmcb->control.exit_int_info = 0; | |
1454 | svm_inject_irq(svm, intr_vector); | |
1455 | return; | |
1456 | } | |
1457 | ||
1458 | if (vmcb->control.int_ctl & V_IRQ_MASK) | |
1459 | return; | |
1460 | ||
1b9778da | 1461 | if (!kvm_cpu_has_interrupt(vcpu)) |
85f455f7 ED |
1462 | return; |
1463 | ||
1464 | if (!(vmcb->save.rflags & X86_EFLAGS_IF) || | |
1465 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) || | |
1466 | (vmcb->control.event_inj & SVM_EVTINJ_VALID)) { | |
1467 | /* unable to deliver irq, set pending irq */ | |
1468 | vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR); | |
1469 | svm_inject_irq(svm, 0x0); | |
1470 | return; | |
1471 | } | |
1472 | /* Okay, we can deliver the interrupt: grab it and update PIC state. */ | |
1b9778da | 1473 | intr_vector = kvm_cpu_get_interrupt(vcpu); |
85f455f7 | 1474 | svm_inject_irq(svm, intr_vector); |
1b9778da | 1475 | kvm_timer_intr_post(vcpu, intr_vector); |
85f455f7 ED |
1476 | } |
1477 | ||
1478 | static void kvm_reput_irq(struct vcpu_svm *svm) | |
1479 | { | |
e756fc62 | 1480 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 | 1481 | |
7017fc3d ED |
1482 | if ((control->int_ctl & V_IRQ_MASK) |
1483 | && !irqchip_in_kernel(svm->vcpu.kvm)) { | |
6aa8b732 | 1484 | control->int_ctl &= ~V_IRQ_MASK; |
e756fc62 | 1485 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1486 | } |
c1150d8c | 1487 | |
ad312c7c | 1488 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c DL |
1489 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1490 | } | |
1491 | ||
85f455f7 ED |
1492 | static void svm_do_inject_vector(struct vcpu_svm *svm) |
1493 | { | |
1494 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ad312c7c ZX |
1495 | int word_index = __ffs(vcpu->arch.irq_summary); |
1496 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
85f455f7 ED |
1497 | int irq = word_index * BITS_PER_LONG + bit_index; |
1498 | ||
ad312c7c ZX |
1499 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
1500 | if (!vcpu->arch.irq_pending[word_index]) | |
1501 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
85f455f7 ED |
1502 | svm_inject_irq(svm, irq); |
1503 | } | |
1504 | ||
04d2cc77 | 1505 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
c1150d8c DL |
1506 | struct kvm_run *kvm_run) |
1507 | { | |
04d2cc77 | 1508 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1509 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1510 | |
ad312c7c | 1511 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c | 1512 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1513 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1514 | |
ad312c7c | 1515 | if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary) |
c1150d8c DL |
1516 | /* |
1517 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1518 | */ | |
85f455f7 | 1519 | svm_do_inject_vector(svm); |
c1150d8c DL |
1520 | |
1521 | /* | |
1522 | * Interrupts blocked. Wait for unblock. | |
1523 | */ | |
ad312c7c ZX |
1524 | if (!svm->vcpu.arch.interrupt_window_open && |
1525 | (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window)) | |
c1150d8c | 1526 | control->intercept |= 1ULL << INTERCEPT_VINTR; |
d77c26fc | 1527 | else |
c1150d8c DL |
1528 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); |
1529 | } | |
1530 | ||
cbc94022 IE |
1531 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
1532 | { | |
1533 | return 0; | |
1534 | } | |
1535 | ||
6aa8b732 AK |
1536 | static void save_db_regs(unsigned long *db_regs) |
1537 | { | |
5aff458e AK |
1538 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1539 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1540 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1541 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1542 | } |
1543 | ||
1544 | static void load_db_regs(unsigned long *db_regs) | |
1545 | { | |
5aff458e AK |
1546 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1547 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1548 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1549 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1550 | } |
1551 | ||
d9e368d6 AK |
1552 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1553 | { | |
1554 | force_new_asid(vcpu); | |
1555 | } | |
1556 | ||
04d2cc77 AK |
1557 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
1558 | { | |
1559 | } | |
1560 | ||
1561 | static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
6aa8b732 | 1562 | { |
a2fa3e9f | 1563 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1564 | u16 fs_selector; |
1565 | u16 gs_selector; | |
1566 | u16 ldt_selector; | |
d9e368d6 | 1567 | |
e756fc62 | 1568 | pre_svm_run(svm); |
6aa8b732 AK |
1569 | |
1570 | save_host_msrs(vcpu); | |
1571 | fs_selector = read_fs(); | |
1572 | gs_selector = read_gs(); | |
1573 | ldt_selector = read_ldt(); | |
a2fa3e9f GH |
1574 | svm->host_cr2 = kvm_read_cr2(); |
1575 | svm->host_dr6 = read_dr6(); | |
1576 | svm->host_dr7 = read_dr7(); | |
ad312c7c | 1577 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
709ddebf JR |
1578 | /* required for live migration with NPT */ |
1579 | if (npt_enabled) | |
1580 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
6aa8b732 | 1581 | |
a2fa3e9f | 1582 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1583 | write_dr7(0); |
a2fa3e9f GH |
1584 | save_db_regs(svm->host_db_regs); |
1585 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1586 | } |
36241b8c | 1587 | |
04d2cc77 AK |
1588 | clgi(); |
1589 | ||
1590 | local_irq_enable(); | |
36241b8c | 1591 | |
6aa8b732 | 1592 | asm volatile ( |
05b3e0c2 | 1593 | #ifdef CONFIG_X86_64 |
54a08c04 | 1594 | "push %%rbp; \n\t" |
6aa8b732 | 1595 | #else |
fe7935d4 | 1596 | "push %%ebp; \n\t" |
6aa8b732 AK |
1597 | #endif |
1598 | ||
05b3e0c2 | 1599 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1600 | "mov %c[rbx](%[svm]), %%rbx \n\t" |
1601 | "mov %c[rcx](%[svm]), %%rcx \n\t" | |
1602 | "mov %c[rdx](%[svm]), %%rdx \n\t" | |
1603 | "mov %c[rsi](%[svm]), %%rsi \n\t" | |
1604 | "mov %c[rdi](%[svm]), %%rdi \n\t" | |
1605 | "mov %c[rbp](%[svm]), %%rbp \n\t" | |
1606 | "mov %c[r8](%[svm]), %%r8 \n\t" | |
1607 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1608 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1609 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1610 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1611 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1612 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1613 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 | 1614 | #else |
fb3f0f51 RR |
1615 | "mov %c[rbx](%[svm]), %%ebx \n\t" |
1616 | "mov %c[rcx](%[svm]), %%ecx \n\t" | |
1617 | "mov %c[rdx](%[svm]), %%edx \n\t" | |
1618 | "mov %c[rsi](%[svm]), %%esi \n\t" | |
1619 | "mov %c[rdi](%[svm]), %%edi \n\t" | |
1620 | "mov %c[rbp](%[svm]), %%ebp \n\t" | |
6aa8b732 AK |
1621 | #endif |
1622 | ||
05b3e0c2 | 1623 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1624 | /* Enter guest mode */ |
1625 | "push %%rax \n\t" | |
fb3f0f51 | 1626 | "mov %c[vmcb](%[svm]), %%rax \n\t" |
6aa8b732 AK |
1627 | SVM_VMLOAD "\n\t" |
1628 | SVM_VMRUN "\n\t" | |
1629 | SVM_VMSAVE "\n\t" | |
1630 | "pop %%rax \n\t" | |
1631 | #else | |
1632 | /* Enter guest mode */ | |
1633 | "push %%eax \n\t" | |
fb3f0f51 | 1634 | "mov %c[vmcb](%[svm]), %%eax \n\t" |
6aa8b732 AK |
1635 | SVM_VMLOAD "\n\t" |
1636 | SVM_VMRUN "\n\t" | |
1637 | SVM_VMSAVE "\n\t" | |
1638 | "pop %%eax \n\t" | |
1639 | #endif | |
1640 | ||
1641 | /* Save guest registers, load host registers */ | |
05b3e0c2 | 1642 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1643 | "mov %%rbx, %c[rbx](%[svm]) \n\t" |
1644 | "mov %%rcx, %c[rcx](%[svm]) \n\t" | |
1645 | "mov %%rdx, %c[rdx](%[svm]) \n\t" | |
1646 | "mov %%rsi, %c[rsi](%[svm]) \n\t" | |
1647 | "mov %%rdi, %c[rdi](%[svm]) \n\t" | |
1648 | "mov %%rbp, %c[rbp](%[svm]) \n\t" | |
1649 | "mov %%r8, %c[r8](%[svm]) \n\t" | |
1650 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1651 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1652 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1653 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1654 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1655 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1656 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 1657 | |
54a08c04 | 1658 | "pop %%rbp; \n\t" |
6aa8b732 | 1659 | #else |
fb3f0f51 RR |
1660 | "mov %%ebx, %c[rbx](%[svm]) \n\t" |
1661 | "mov %%ecx, %c[rcx](%[svm]) \n\t" | |
1662 | "mov %%edx, %c[rdx](%[svm]) \n\t" | |
1663 | "mov %%esi, %c[rsi](%[svm]) \n\t" | |
1664 | "mov %%edi, %c[rdi](%[svm]) \n\t" | |
1665 | "mov %%ebp, %c[rbp](%[svm]) \n\t" | |
6aa8b732 | 1666 | |
fe7935d4 | 1667 | "pop %%ebp; \n\t" |
6aa8b732 AK |
1668 | #endif |
1669 | : | |
fb3f0f51 | 1670 | : [svm]"a"(svm), |
6aa8b732 | 1671 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
1672 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
1673 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
1674 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
1675 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
1676 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
1677 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1678 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
1679 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
1680 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
1681 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
1682 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
1683 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
1684 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
1685 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
1686 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 1687 | #endif |
54a08c04 LV |
1688 | : "cc", "memory" |
1689 | #ifdef CONFIG_X86_64 | |
1690 | , "rbx", "rcx", "rdx", "rsi", "rdi" | |
1691 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" | |
fe7935d4 LV |
1692 | #else |
1693 | , "ebx", "ecx", "edx" , "esi", "edi" | |
54a08c04 LV |
1694 | #endif |
1695 | ); | |
6aa8b732 | 1696 | |
a2fa3e9f GH |
1697 | if ((svm->vmcb->save.dr7 & 0xff)) |
1698 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1699 | |
ad312c7c | 1700 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
6aa8b732 | 1701 | |
a2fa3e9f GH |
1702 | write_dr6(svm->host_dr6); |
1703 | write_dr7(svm->host_dr7); | |
1704 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 AK |
1705 | |
1706 | load_fs(fs_selector); | |
1707 | load_gs(gs_selector); | |
1708 | load_ldt(ldt_selector); | |
1709 | load_host_msrs(vcpu); | |
1710 | ||
1711 | reload_tss(vcpu); | |
1712 | ||
56ba47dd AK |
1713 | local_irq_disable(); |
1714 | ||
1715 | stgi(); | |
1716 | ||
a2fa3e9f | 1717 | svm->next_rip = 0; |
6aa8b732 AK |
1718 | } |
1719 | ||
6aa8b732 AK |
1720 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1721 | { | |
a2fa3e9f GH |
1722 | struct vcpu_svm *svm = to_svm(vcpu); |
1723 | ||
709ddebf JR |
1724 | if (npt_enabled) { |
1725 | svm->vmcb->control.nested_cr3 = root; | |
1726 | force_new_asid(vcpu); | |
1727 | return; | |
1728 | } | |
1729 | ||
a2fa3e9f | 1730 | svm->vmcb->save.cr3 = root; |
6aa8b732 | 1731 | force_new_asid(vcpu); |
7807fa6c AL |
1732 | |
1733 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1734 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1735 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1736 | vcpu->fpu_active = 0; |
1737 | } | |
6aa8b732 AK |
1738 | } |
1739 | ||
6aa8b732 AK |
1740 | static int is_disabled(void) |
1741 | { | |
6031a61c JR |
1742 | u64 vm_cr; |
1743 | ||
1744 | rdmsrl(MSR_VM_CR, vm_cr); | |
1745 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1746 | return 1; | |
1747 | ||
6aa8b732 AK |
1748 | return 0; |
1749 | } | |
1750 | ||
102d8325 IM |
1751 | static void |
1752 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1753 | { | |
1754 | /* | |
1755 | * Patch in the VMMCALL instruction: | |
1756 | */ | |
1757 | hypercall[0] = 0x0f; | |
1758 | hypercall[1] = 0x01; | |
1759 | hypercall[2] = 0xd9; | |
102d8325 IM |
1760 | } |
1761 | ||
002c7f7c YS |
1762 | static void svm_check_processor_compat(void *rtn) |
1763 | { | |
1764 | *(int *)rtn = 0; | |
1765 | } | |
1766 | ||
774ead3a AK |
1767 | static bool svm_cpu_has_accelerated_tpr(void) |
1768 | { | |
1769 | return false; | |
1770 | } | |
1771 | ||
cbdd1bea | 1772 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
1773 | .cpu_has_kvm_support = has_svm, |
1774 | .disabled_by_bios = is_disabled, | |
1775 | .hardware_setup = svm_hardware_setup, | |
1776 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 1777 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
1778 | .hardware_enable = svm_hardware_enable, |
1779 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 1780 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
1781 | |
1782 | .vcpu_create = svm_create_vcpu, | |
1783 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 1784 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 1785 | |
04d2cc77 | 1786 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
1787 | .vcpu_load = svm_vcpu_load, |
1788 | .vcpu_put = svm_vcpu_put, | |
774c47f1 | 1789 | .vcpu_decache = svm_vcpu_decache, |
6aa8b732 AK |
1790 | |
1791 | .set_guest_debug = svm_guest_debug, | |
1792 | .get_msr = svm_get_msr, | |
1793 | .set_msr = svm_set_msr, | |
1794 | .get_segment_base = svm_get_segment_base, | |
1795 | .get_segment = svm_get_segment, | |
1796 | .set_segment = svm_set_segment, | |
1747fb71 | 1797 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 1798 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1799 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1800 | .set_cr3 = svm_set_cr3, |
1801 | .set_cr4 = svm_set_cr4, | |
1802 | .set_efer = svm_set_efer, | |
1803 | .get_idt = svm_get_idt, | |
1804 | .set_idt = svm_set_idt, | |
1805 | .get_gdt = svm_get_gdt, | |
1806 | .set_gdt = svm_set_gdt, | |
1807 | .get_dr = svm_get_dr, | |
1808 | .set_dr = svm_set_dr, | |
1809 | .cache_regs = svm_cache_regs, | |
1810 | .decache_regs = svm_decache_regs, | |
1811 | .get_rflags = svm_get_rflags, | |
1812 | .set_rflags = svm_set_rflags, | |
1813 | ||
6aa8b732 | 1814 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 1815 | |
6aa8b732 | 1816 | .run = svm_vcpu_run, |
04d2cc77 | 1817 | .handle_exit = handle_exit, |
6aa8b732 | 1818 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 1819 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 ED |
1820 | .get_irq = svm_get_irq, |
1821 | .set_irq = svm_set_irq, | |
298101da AK |
1822 | .queue_exception = svm_queue_exception, |
1823 | .exception_injected = svm_exception_injected, | |
04d2cc77 AK |
1824 | .inject_pending_irq = svm_intr_assist, |
1825 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
1826 | |
1827 | .set_tss_addr = svm_set_tss_addr, | |
6aa8b732 AK |
1828 | }; |
1829 | ||
1830 | static int __init svm_init(void) | |
1831 | { | |
cb498ea2 | 1832 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 1833 | THIS_MODULE); |
6aa8b732 AK |
1834 | } |
1835 | ||
1836 | static void __exit svm_exit(void) | |
1837 | { | |
cb498ea2 | 1838 | kvm_exit(); |
6aa8b732 AK |
1839 | } |
1840 | ||
1841 | module_init(svm_init) | |
1842 | module_exit(svm_exit) |