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KVM: x86: get_msr support for HV_X64_MSR_APIC_ASSIST_PAGE
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
890ca9ae 63#define KVM_MAX_MCE_BANKS 32
5854dbca 64#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 65
0f65dd70
AK		 66#define emul_to_vcpu(ctxt) \
67 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
68
50a37eb4
JR		 69/* EFER defaults:
70 * - enable syscall per default because its emulated by KVM
71 * - enable LME and LMA per default on 64 bit KVM
72 */
73#ifdef CONFIG_X86_64
1260edbe
LJ		 74static
75u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 76#else
1260edbe 77static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 78#endif
313a3dc7 79
ba1389b7
AK		 80#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
81#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 82
cb142eb7 83static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 84static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
85 struct kvm_cpuid_entry2 __user *entries);
86
97896d04 87struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 88EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 89
ed85c068
AP		 90int ignore_msrs = 0;
91module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
92
92a1f12d
JR		 93bool kvm_has_tsc_control;
94EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
95u32 kvm_max_guest_tsc_khz;
96EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
97
18863bdd
AK		 98#define KVM_NR_SHARED_MSRS 16
99
100struct kvm_shared_msrs_global {
101 int nr;
2bf78fa7 102 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 103};
104
105struct kvm_shared_msrs {
106 struct user_return_notifier urn;
107 bool registered;
2bf78fa7
SY		 108 struct kvm_shared_msr_values {
109 u64 host;
110 u64 curr;
111 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 112};
113
114static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
115static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
116
417bc304 117struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 118 { "pf_fixed", VCPU_STAT(pf_fixed) },
119 { "pf_guest", VCPU_STAT(pf_guest) },
120 { "tlb_flush", VCPU_STAT(tlb_flush) },
121 { "invlpg", VCPU_STAT(invlpg) },
122 { "exits", VCPU_STAT(exits) },
123 { "io_exits", VCPU_STAT(io_exits) },
124 { "mmio_exits", VCPU_STAT(mmio_exits) },
125 { "signal_exits", VCPU_STAT(signal_exits) },
126 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 127 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 128 { "halt_exits", VCPU_STAT(halt_exits) },
129 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 130 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 131 { "request_irq", VCPU_STAT(request_irq_exits) },
132 { "irq_exits", VCPU_STAT(irq_exits) },
133 { "host_state_reload", VCPU_STAT(host_state_reload) },
134 { "efer_reload", VCPU_STAT(efer_reload) },
135 { "fpu_reload", VCPU_STAT(fpu_reload) },
136 { "insn_emulation", VCPU_STAT(insn_emulation) },
137 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 138 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 139 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 140 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
141 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
142 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
143 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
144 { "mmu_flooded", VM_STAT(mmu_flooded) },
145 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 146 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 147 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 148 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 149 { "largepages", VM_STAT(lpages) },
417bc304
HB		 150 { NULL }
151};
152
2acf923e
DC		 153u64 __read_mostly host_xcr0;
154
d6aa1000
AK		 155int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
156
af585b92
GN		 157static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
158{
159 int i;
160 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
161 vcpu->arch.apf.gfns[i] = ~0;
162}
163
18863bdd
AK		 164static void kvm_on_user_return(struct user_return_notifier *urn)
165{
166 unsigned slot;
18863bdd
AK		 167 struct kvm_shared_msrs *locals
168 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 169 struct kvm_shared_msr_values *values;
18863bdd
AK		 170
171 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 172 values = &locals->values[slot];
173 if (values->host != values->curr) {
174 wrmsrl(shared_msrs_global.msrs[slot], values->host);
175 values->curr = values->host;
18863bdd
AK		 176 }
177 }
178 locals->registered = false;
179 user_return_notifier_unregister(urn);
180}
181
2bf78fa7 182static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 183{
2bf78fa7 184 struct kvm_shared_msrs *smsr;
18863bdd
AK		 185 u64 value;
186
2bf78fa7
SY		 187 smsr = &__get_cpu_var(shared_msrs);
188 /* only read, and nobody should modify it at this time,
189 * so don't need lock */
190 if (slot >= shared_msrs_global.nr) {
191 printk(KERN_ERR "kvm: invalid MSR slot!");
192 return;
193 }
194 rdmsrl_safe(msr, &value);
195 smsr->values[slot].host = value;
196 smsr->values[slot].curr = value;
197}
198
199void kvm_define_shared_msr(unsigned slot, u32 msr)
200{
18863bdd
AK		 201 if (slot >= shared_msrs_global.nr)
202 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 203 shared_msrs_global.msrs[slot] = msr;
204 /* we need ensured the shared_msr_global have been updated */
205 smp_wmb();
18863bdd
AK		 206}
207EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
208
209static void kvm_shared_msr_cpu_online(void)
210{
211 unsigned i;
18863bdd
AK		 212
213 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 214 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 215}
216
d5696725 217void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 218{
219 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
220
2bf78fa7 221 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 222 return;
2bf78fa7
SY		 223 smsr->values[slot].curr = value;
224 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 225 if (!smsr->registered) {
226 smsr->urn.on_user_return = kvm_on_user_return;
227 user_return_notifier_register(&smsr->urn);
228 smsr->registered = true;
229 }
230}
231EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
232
3548bab5
AK		 233static void drop_user_return_notifiers(void *ignore)
234{
235 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
236
237 if (smsr->registered)
238 kvm_on_user_return(&smsr->urn);
239}
240
6866b83e
CO		 241u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
242{
243 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 244 return vcpu->arch.apic_base;
6866b83e 245 else
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e
CO		 247}
248EXPORT_SYMBOL_GPL(kvm_get_apic_base);
249
250void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
251{
252 /* TODO: reserve bits check */
253 if (irqchip_in_kernel(vcpu->kvm))
254 kvm_lapic_set_base(vcpu, data);
255 else
ad312c7c 256 vcpu->arch.apic_base = data;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259
3fd28fce
ED		 260#define EXCPT_BENIGN 0
261#define EXCPT_CONTRIBUTORY 1
262#define EXCPT_PF 2
263
264static int exception_class(int vector)
265{
266 switch (vector) {
267 case PF_VECTOR:
268 return EXCPT_PF;
269 case DE_VECTOR:
270 case TS_VECTOR:
271 case NP_VECTOR:
272 case SS_VECTOR:
273 case GP_VECTOR:
274 return EXCPT_CONTRIBUTORY;
275 default:
276 break;
277 }
278 return EXCPT_BENIGN;
279}
280
281static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 282 unsigned nr, bool has_error, u32 error_code,
283 bool reinject)
3fd28fce
ED		 284{
285 u32 prev_nr;
286 int class1, class2;
287
3842d135
AK		 288 kvm_make_request(KVM_REQ_EVENT, vcpu);
289
3fd28fce
ED		 290 if (!vcpu->arch.exception.pending) {
291 queue:
292 vcpu->arch.exception.pending = true;
293 vcpu->arch.exception.has_error_code = has_error;
294 vcpu->arch.exception.nr = nr;
295 vcpu->arch.exception.error_code = error_code;
3f0fd292 296 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 297 return;
298 }
299
300 /* to check exception */
301 prev_nr = vcpu->arch.exception.nr;
302 if (prev_nr == DF_VECTOR) {
303 /* triple fault -> shutdown */
a8eeb04a 304 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 305 return;
306 }
307 class1 = exception_class(prev_nr);
308 class2 = exception_class(nr);
309 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
310 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
311 /* generate double fault per SDM Table 5-5 */
312 vcpu->arch.exception.pending = true;
313 vcpu->arch.exception.has_error_code = true;
314 vcpu->arch.exception.nr = DF_VECTOR;
315 vcpu->arch.exception.error_code = 0;
316 } else
317 /* replace previous exception with a new one in a hope
318 that instruction re-execution will regenerate lost
319 exception */
320 goto queue;
321}
322
298101da
AK		 323void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
324{
ce7ddec4 325 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 326}
327EXPORT_SYMBOL_GPL(kvm_queue_exception);
328
ce7ddec4
JR		 329void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
331 kvm_multiple_exception(vcpu, nr, false, 0, true);
332}
333EXPORT_SYMBOL_GPL(kvm_requeue_exception);
334
db8fcefa 335void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 336{
db8fcefa
AP		 337 if (err)
338 kvm_inject_gp(vcpu, 0);
339 else
340 kvm_x86_ops->skip_emulated_instruction(vcpu);
341}
342EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 343
6389ee94 344void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 345{
346 ++vcpu->stat.pf_guest;
6389ee94
AK		 347 vcpu->arch.cr2 = fault->address;
348 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 349}
27d6c865 350EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 351
6389ee94 352void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 353{
6389ee94
AK		 354 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
355 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 356 else
6389ee94 357 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 358}
359
3419ffc8
SY		 360void kvm_inject_nmi(struct kvm_vcpu *vcpu)
361{
3842d135 362 kvm_make_request(KVM_REQ_EVENT, vcpu);
c761e586 363 vcpu->arch.nmi_pending = 1;
3419ffc8
SY		 364}
365EXPORT_SYMBOL_GPL(kvm_inject_nmi);
366
298101da
AK		 367void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
368{
ce7ddec4 369 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 370}
371EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
372
ce7ddec4
JR		 373void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374{
375 kvm_multiple_exception(vcpu, nr, true, error_code, true);
376}
377EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
378
0a79b009
AK		 379/*
380 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
381 * a #GP and return false.
382 */
383bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 384{
0a79b009
AK		 385 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
386 return true;
387 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
388 return false;
298101da 389}
0a79b009 390EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 391
ec92fe44
JR		 392/*
393 * This function will be used to read from the physical memory of the currently
394 * running guest. The difference to kvm_read_guest_page is that this function
395 * can read from guest physical or from the guest's guest physical memory.
396 */
397int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
398 gfn_t ngfn, void *data, int offset, int len,
399 u32 access)
400{
401 gfn_t real_gfn;
402 gpa_t ngpa;
403
404 ngpa = gfn_to_gpa(ngfn);
405 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
406 if (real_gfn == UNMAPPED_GVA)
407 return -EFAULT;
408
409 real_gfn = gpa_to_gfn(real_gfn);
410
411 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
412}
413EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
414
3d06b8bf
JR		 415int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
416 void *data, int offset, int len, u32 access)
417{
418 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
419 data, offset, len, access);
420}
421
a03490ed
CO		 422/*
423 * Load the pae pdptrs. Return true is they are all valid.
424 */
ff03a073 425int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 426{
427 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
428 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
429 int i;
430 int ret;
ff03a073 431 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 432
ff03a073
JR		 433 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
434 offset * sizeof(u64), sizeof(pdpte),
435 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 436 if (ret < 0) {
437 ret = 0;
438 goto out;
439 }
440 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 441 if (is_present_gpte(pdpte[i]) &&
20c466b5 442 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 443 ret = 0;
444 goto out;
445 }
446 }
447 ret = 1;
448
ff03a073 449 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 450 __set_bit(VCPU_EXREG_PDPTR,
451 (unsigned long *)&vcpu->arch.regs_avail);
452 __set_bit(VCPU_EXREG_PDPTR,
453 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 454out:
a03490ed
CO		 455
456 return ret;
457}
cc4b6871 458EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 459
d835dfec
AK		 460static bool pdptrs_changed(struct kvm_vcpu *vcpu)
461{
ff03a073 462 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 463 bool changed = true;
3d06b8bf
JR		 464 int offset;
465 gfn_t gfn;
d835dfec
AK		 466 int r;
467
468 if (is_long_mode(vcpu) || !is_pae(vcpu))
469 return false;
470
6de4f3ad
AK		 471 if (!test_bit(VCPU_EXREG_PDPTR,
472 (unsigned long *)&vcpu->arch.regs_avail))
473 return true;
474
9f8fe504
AK		 475 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
476 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 477 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
478 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 479 if (r < 0)
480 goto out;
ff03a073 481 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 482out:
d835dfec
AK		 483
484 return changed;
485}
486
49a9b07e 487int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 488{
aad82703
SY		 489 unsigned long old_cr0 = kvm_read_cr0(vcpu);
490 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
491 X86_CR0_CD | X86_CR0_NW;
492
f9a48e6a
AK		 493 cr0 |= X86_CR0_ET;
494
ab344828 495#ifdef CONFIG_X86_64
0f12244f
GN		 496 if (cr0 & 0xffffffff00000000UL)
497 return 1;
ab344828
GN		 498#endif
499
500 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 501
0f12244f
GN		 502 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
503 return 1;
a03490ed 504
0f12244f
GN		 505 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
506 return 1;
a03490ed
CO		 507
508 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
509#ifdef CONFIG_X86_64
f6801dff 510 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 511 int cs_db, cs_l;
512
0f12244f
GN		 513 if (!is_pae(vcpu))
514 return 1;
a03490ed 515 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 516 if (cs_l)
517 return 1;
a03490ed
CO		 518 } else
519#endif
ff03a073 520 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 521 kvm_read_cr3(vcpu)))
0f12244f 522 return 1;
a03490ed
CO		 523 }
524
525 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 526
d170c419 527 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 528 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 529 kvm_async_pf_hash_reset(vcpu);
530 }
e5f3f027 531
aad82703
SY		 532 if ((cr0 ^ old_cr0) & update_bits)
533 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 534 return 0;
535}
2d3ad1f4 536EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 537
2d3ad1f4 538void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 539{
49a9b07e 540 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 541}
2d3ad1f4 542EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 543
2acf923e
DC		 544int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
545{
546 u64 xcr0;
547
548 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
549 if (index != XCR_XFEATURE_ENABLED_MASK)
550 return 1;
551 xcr0 = xcr;
552 if (kvm_x86_ops->get_cpl(vcpu) != 0)
553 return 1;
554 if (!(xcr0 & XSTATE_FP))
555 return 1;
556 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
557 return 1;
558 if (xcr0 & ~host_xcr0)
559 return 1;
560 vcpu->arch.xcr0 = xcr0;
561 vcpu->guest_xcr0_loaded = 0;
562 return 0;
563}
564
565int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
566{
567 if (__kvm_set_xcr(vcpu, index, xcr)) {
568 kvm_inject_gp(vcpu, 0);
569 return 1;
570 }
571 return 0;
572}
573EXPORT_SYMBOL_GPL(kvm_set_xcr);
574
575static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
576{
577 struct kvm_cpuid_entry2 *best;
578
579 best = kvm_find_cpuid_entry(vcpu, 1, 0);
580 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
581}
582
c68b734f
YW		 583static bool guest_cpuid_has_smep(struct kvm_vcpu *vcpu)
584{
585 struct kvm_cpuid_entry2 *best;
586
587 best = kvm_find_cpuid_entry(vcpu, 7, 0);
588 return best && (best->ebx & bit(X86_FEATURE_SMEP));
589}
590
74dc2b4f
YW		 591static bool guest_cpuid_has_fsgsbase(struct kvm_vcpu *vcpu)
592{
593 struct kvm_cpuid_entry2 *best;
594
595 best = kvm_find_cpuid_entry(vcpu, 7, 0);
596 return best && (best->ebx & bit(X86_FEATURE_FSGSBASE));
597}
598
2acf923e
DC		 599static void update_cpuid(struct kvm_vcpu *vcpu)
600{
601 struct kvm_cpuid_entry2 *best;
602
603 best = kvm_find_cpuid_entry(vcpu, 1, 0);
604 if (!best)
605 return;
606
607 /* Update OSXSAVE bit */
608 if (cpu_has_xsave && best->function == 0x1) {
609 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
610 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
611 best->ecx |= bit(X86_FEATURE_OSXSAVE);
612 }
613}
614
a83b29c6 615int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 616{
fc78f519 617 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 618 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
619 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 620 if (cr4 & CR4_RESERVED_BITS)
621 return 1;
a03490ed 622
2acf923e
DC		 623 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
624 return 1;
625
c68b734f
YW		 626 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
627 return 1;
628
74dc2b4f
YW		 629 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
630 return 1;
631
a03490ed 632 if (is_long_mode(vcpu)) {
0f12244f
GN		 633 if (!(cr4 & X86_CR4_PAE))
634 return 1;
a2edf57f
AK		 635 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
636 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 637 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
638 kvm_read_cr3(vcpu)))
0f12244f
GN		 639 return 1;
640
5e1746d6 641 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 642 return 1;
a03490ed 643
aad82703
SY		 644 if ((cr4 ^ old_cr4) & pdptr_bits)
645 kvm_mmu_reset_context(vcpu);
0f12244f 646
2acf923e
DC		 647 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
648 update_cpuid(vcpu);
649
0f12244f
GN		 650 return 0;
651}
2d3ad1f4 652EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 653
2390218b 654int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 655{
9f8fe504 656 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 657 kvm_mmu_sync_roots(vcpu);
d835dfec 658 kvm_mmu_flush_tlb(vcpu);
0f12244f 659 return 0;
d835dfec
AK		 660 }
661
a03490ed 662 if (is_long_mode(vcpu)) {
0f12244f
GN		 663 if (cr3 & CR3_L_MODE_RESERVED_BITS)
664 return 1;
a03490ed
CO		 665 } else {
666 if (is_pae(vcpu)) {
0f12244f
GN		 667 if (cr3 & CR3_PAE_RESERVED_BITS)
668 return 1;
ff03a073
JR		 669 if (is_paging(vcpu) &&
670 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 671 return 1;
a03490ed
CO		 672 }
673 /*
674 * We don't check reserved bits in nonpae mode, because
675 * this isn't enforced, and VMware depends on this.
676 */
677 }
678
a03490ed
CO		 679 /*
680 * Does the new cr3 value map to physical memory? (Note, we
681 * catch an invalid cr3 even in real-mode, because it would
682 * cause trouble later on when we turn on paging anyway.)
683 *
684 * A real CPU would silently accept an invalid cr3 and would
685 * attempt to use it - with largely undefined (and often hard
686 * to debug) behavior on the guest side.
687 */
688 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 689 return 1;
690 vcpu->arch.cr3 = cr3;
aff48baa 691 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 692 vcpu->arch.mmu.new_cr3(vcpu);
693 return 0;
694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 696
eea1cff9 697int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 698{
0f12244f
GN		 699 if (cr8 & CR8_RESERVED_BITS)
700 return 1;
a03490ed
CO		 701 if (irqchip_in_kernel(vcpu->kvm))
702 kvm_lapic_set_tpr(vcpu, cr8);
703 else
ad312c7c 704 vcpu->arch.cr8 = cr8;
0f12244f
GN		 705 return 0;
706}
2d3ad1f4 707EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 708
2d3ad1f4 709unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 710{
711 if (irqchip_in_kernel(vcpu->kvm))
712 return kvm_lapic_get_cr8(vcpu);
713 else
ad312c7c 714 return vcpu->arch.cr8;
a03490ed 715}
2d3ad1f4 716EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 717
338dbc97 718static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 719{
720 switch (dr) {
721 case 0 ... 3:
722 vcpu->arch.db[dr] = val;
723 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
724 vcpu->arch.eff_db[dr] = val;
725 break;
726 case 4:
338dbc97
GN		 727 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
728 return 1; /* #UD */
020df079
GN		 729 /* fall through */
730 case 6:
338dbc97
GN		 731 if (val & 0xffffffff00000000ULL)
732 return -1; /* #GP */
020df079
GN		 733 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
734 break;
735 case 5:
338dbc97
GN		 736 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
737 return 1; /* #UD */
020df079
GN		 738 /* fall through */
739 default: /* 7 */
338dbc97
GN		 740 if (val & 0xffffffff00000000ULL)
741 return -1; /* #GP */
020df079
GN		 742 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
743 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
744 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
745 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
746 }
747 break;
748 }
749
750 return 0;
751}
338dbc97
GN		 752
753int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
754{
755 int res;
756
757 res = __kvm_set_dr(vcpu, dr, val);
758 if (res > 0)
759 kvm_queue_exception(vcpu, UD_VECTOR);
760 else if (res < 0)
761 kvm_inject_gp(vcpu, 0);
762
763 return res;
764}
020df079
GN		 765EXPORT_SYMBOL_GPL(kvm_set_dr);
766
338dbc97 767static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 768{
769 switch (dr) {
770 case 0 ... 3:
771 *val = vcpu->arch.db[dr];
772 break;
773 case 4:
338dbc97 774 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 775 return 1;
020df079
GN		 776 /* fall through */
777 case 6:
778 *val = vcpu->arch.dr6;
779 break;
780 case 5:
338dbc97 781 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 782 return 1;
020df079
GN		 783 /* fall through */
784 default: /* 7 */
785 *val = vcpu->arch.dr7;
786 break;
787 }
788
789 return 0;
790}
338dbc97
GN		 791
792int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
793{
794 if (_kvm_get_dr(vcpu, dr, val)) {
795 kvm_queue_exception(vcpu, UD_VECTOR);
796 return 1;
797 }
798 return 0;
799}
020df079
GN		 800EXPORT_SYMBOL_GPL(kvm_get_dr);
801
043405e1
CO		 802/*
803 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
804 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
805 *
806 * This list is modified at module load time to reflect the
e3267cbb
GC		 807 * capabilities of the host cpu. This capabilities test skips MSRs that are
808 * kvm-specific. Those are put in the beginning of the list.
043405e1 809 */
e3267cbb 810
c9aaa895 811#define KVM_SAVE_MSRS_BEGIN 9
043405e1 812static u32 msrs_to_save[] = {
e3267cbb 813 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 814 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 815 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 816 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
043405e1 817 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 818 MSR_STAR,
043405e1
CO		 819#ifdef CONFIG_X86_64
820 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
821#endif
e90aa41e 822 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 823};
824
825static unsigned num_msrs_to_save;
826
827static u32 emulated_msrs[] = {
828 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 829 MSR_IA32_MCG_STATUS,
830 MSR_IA32_MCG_CTL,
043405e1
CO		 831};
832
b69e8cae 833static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 834{
aad82703
SY		 835 u64 old_efer = vcpu->arch.efer;
836
b69e8cae
RJ		 837 if (efer & efer_reserved_bits)
838 return 1;
15c4a640
CO		 839
840 if (is_paging(vcpu)
b69e8cae
RJ		 841 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
842 return 1;
15c4a640 843
1b2fd70c
AG		 844 if (efer & EFER_FFXSR) {
845 struct kvm_cpuid_entry2 *feat;
846
847 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 848 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
849 return 1;
1b2fd70c
AG		 850 }
851
d8017474
AG		 852 if (efer & EFER_SVME) {
853 struct kvm_cpuid_entry2 *feat;
854
855 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 856 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
857 return 1;
d8017474
AG		 858 }
859
15c4a640 860 efer &= ~EFER_LMA;
f6801dff 861 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 862
a3d204e2
SY		 863 kvm_x86_ops->set_efer(vcpu, efer);
864
9645bb56 865 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 866
aad82703
SY		 867 /* Update reserved bits */
868 if ((efer ^ old_efer) & EFER_NX)
869 kvm_mmu_reset_context(vcpu);
870
b69e8cae 871 return 0;
15c4a640
CO		 872}
873
f2b4b7dd
JR		 874void kvm_enable_efer_bits(u64 mask)
875{
876 efer_reserved_bits &= ~mask;
877}
878EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
879
880
15c4a640
CO		 881/*
882 * Writes msr value into into the appropriate "register".
883 * Returns 0 on success, non-0 otherwise.
884 * Assumes vcpu_load() was already called.
885 */
886int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
887{
888 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
889}
890
313a3dc7
CO		 891/*
892 * Adapt set_msr() to msr_io()'s calling convention
893 */
894static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
895{
896 return kvm_set_msr(vcpu, index, *data);
897}
898
18068523
GOC		 899static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
900{
9ed3c444
AK		 901 int version;
902 int r;
50d0a0f9 903 struct pvclock_wall_clock wc;
923de3cf 904 struct timespec boot;
18068523
GOC		 905
906 if (!wall_clock)
907 return;
908
9ed3c444
AK		 909 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
910 if (r)
911 return;
912
913 if (version & 1)
914 ++version; /* first time write, random junk */
915
916 ++version;
18068523 917
18068523
GOC		 918 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
919
50d0a0f9
GH		 920 /*
921 * The guest calculates current wall clock time by adding
34c238a1 922 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 923 * wall clock specified here. guest system time equals host
924 * system time for us, thus we must fill in host boot time here.
925 */
923de3cf 926 getboottime(&boot);
50d0a0f9
GH		 927
928 wc.sec = boot.tv_sec;
929 wc.nsec = boot.tv_nsec;
930 wc.version = version;
18068523
GOC		 931
932 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
933
934 version++;
935 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 936}
937
50d0a0f9
GH		 938static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
939{
940 uint32_t quotient, remainder;
941
942 /* Don't try to replace with do_div(), this one calculates
943 * "(dividend << 32) / divisor" */
944 __asm__ ( "divl %4"
945 : "=a" (quotient), "=d" (remainder)
946 : "0" (0), "1" (dividend), "r" (divisor) );
947 return quotient;
948}
949
5f4e3f88
ZA		 950static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
951 s8 *pshift, u32 *pmultiplier)
50d0a0f9 952{
5f4e3f88 953 uint64_t scaled64;
50d0a0f9
GH		 954 int32_t shift = 0;
955 uint64_t tps64;
956 uint32_t tps32;
957
5f4e3f88
ZA		 958 tps64 = base_khz * 1000LL;
959 scaled64 = scaled_khz * 1000LL;
50933623 960 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 961 tps64 >>= 1;
962 shift--;
963 }
964
965 tps32 = (uint32_t)tps64;
50933623
JK		 966 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
967 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 968 scaled64 >>= 1;
969 else
970 tps32 <<= 1;
50d0a0f9
GH		 971 shift++;
972 }
973
5f4e3f88
ZA		 974 *pshift = shift;
975 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 976
5f4e3f88
ZA		 977 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
978 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 979}
980
759379dd
ZA		 981static inline u64 get_kernel_ns(void)
982{
983 struct timespec ts;
984
985 WARN_ON(preemptible());
986 ktime_get_ts(&ts);
987 monotonic_to_bootbased(&ts);
988 return timespec_to_ns(&ts);
50d0a0f9
GH		 989}
990
c8076604 991static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 992unsigned long max_tsc_khz;
c8076604 993
8cfdc000
ZA		 994static inline int kvm_tsc_changes_freq(void)
995{
996 int cpu = get_cpu();
997 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
998 cpufreq_quick_get(cpu) != 0;
999 put_cpu();
1000 return ret;
1001}
1002
1e993611
JR		 1003static u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
1004{
1005 if (vcpu->arch.virtual_tsc_khz)
1006 return vcpu->arch.virtual_tsc_khz;
1007 else
1008 return __this_cpu_read(cpu_tsc_khz);
1009}
1010
857e4099 1011static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 1012{
217fc9cf
AK		 1013 u64 ret;
1014
759379dd
ZA		 1015 WARN_ON(preemptible());
1016 if (kvm_tsc_changes_freq())
1017 printk_once(KERN_WARNING
1018 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 1019 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 1020 do_div(ret, USEC_PER_SEC);
1021 return ret;
759379dd
ZA		 1022}
1023
1e993611 1024static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 1025{
1026 /* Compute a scale to convert nanoseconds in TSC cycles */
1027 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 1028 &vcpu->arch.tsc_catchup_shift,
1029 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 1030}
1031
1032static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1033{
1034 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1035 vcpu->arch.tsc_catchup_mult,
1036 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1037 tsc += vcpu->arch.last_tsc_write;
1038 return tsc;
1039}
1040
99e3e30a
ZA		 1041void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1042{
1043 struct kvm *kvm = vcpu->kvm;
f38e098f 1044 u64 offset, ns, elapsed;
99e3e30a 1045 unsigned long flags;
46543ba4 1046 s64 sdiff;
99e3e30a 1047
038f8c11 1048 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1049 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1050 ns = get_kernel_ns();
f38e098f 1051 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1052 sdiff = data - kvm->arch.last_tsc_write;
1053 if (sdiff < 0)
1054 sdiff = -sdiff;
f38e098f
ZA		 1055
1056 /*
46543ba4 1057 * Special case: close write to TSC within 5 seconds of
f38e098f 1058 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1059 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1060 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1061 *
1062 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1063 * or make a best guest using elapsed value.
f38e098f 1064 */
857e4099 1065 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1066 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1067 if (!check_tsc_unstable()) {
1068 offset = kvm->arch.last_tsc_offset;
1069 pr_debug("kvm: matched tsc offset for %llu\n", data);
1070 } else {
857e4099 1071 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1072 offset += delta;
1073 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1074 }
1075 ns = kvm->arch.last_tsc_nsec;
1076 }
1077 kvm->arch.last_tsc_nsec = ns;
1078 kvm->arch.last_tsc_write = data;
1079 kvm->arch.last_tsc_offset = offset;
99e3e30a 1080 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1081 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1082
1083 /* Reset of TSC must disable overshoot protection below */
1084 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1085 vcpu->arch.last_tsc_write = data;
1086 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1087}
1088EXPORT_SYMBOL_GPL(kvm_write_tsc);
1089
34c238a1 1090static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1091{
18068523
GOC		 1092 unsigned long flags;
1093 struct kvm_vcpu_arch *vcpu = &v->arch;
1094 void *shared_kaddr;
463656c0 1095 unsigned long this_tsc_khz;
1d5f066e
ZA		 1096 s64 kernel_ns, max_kernel_ns;
1097 u64 tsc_timestamp;
18068523 1098
18068523
GOC		 1099 /* Keep irq disabled to prevent changes to the clock */
1100 local_irq_save(flags);
1d5f066e 1101 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1102 kernel_ns = get_kernel_ns();
1e993611 1103 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1104 if (unlikely(this_tsc_khz == 0)) {
c285545f 1105 local_irq_restore(flags);
34c238a1 1106 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1107 return 1;
1108 }
18068523 1109
c285545f
ZA		 1110 /*
1111 * We may have to catch up the TSC to match elapsed wall clock
1112 * time for two reasons, even if kvmclock is used.
1113 * 1) CPU could have been running below the maximum TSC rate
1114 * 2) Broken TSC compensation resets the base at each VCPU
1115 * entry to avoid unknown leaps of TSC even when running
1116 * again on the same CPU. This may cause apparent elapsed
1117 * time to disappear, and the guest to stand still or run
1118 * very slowly.
1119 */
1120 if (vcpu->tsc_catchup) {
1121 u64 tsc = compute_guest_tsc(v, kernel_ns);
1122 if (tsc > tsc_timestamp) {
1123 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1124 tsc_timestamp = tsc;
1125 }
50d0a0f9
GH		 1126 }
1127
18068523
GOC		 1128 local_irq_restore(flags);
1129
c285545f
ZA		 1130 if (!vcpu->time_page)
1131 return 0;
18068523 1132
1d5f066e
ZA		 1133 /*
1134 * Time as measured by the TSC may go backwards when resetting the base
1135 * tsc_timestamp. The reason for this is that the TSC resolution is
1136 * higher than the resolution of the other clock scales. Thus, many
1137 * possible measurments of the TSC correspond to one measurement of any
1138 * other clock, and so a spread of values is possible. This is not a
1139 * problem for the computation of the nanosecond clock; with TSC rates
1140 * around 1GHZ, there can only be a few cycles which correspond to one
1141 * nanosecond value, and any path through this code will inevitably
1142 * take longer than that. However, with the kernel_ns value itself,
1143 * the precision may be much lower, down to HZ granularity. If the
1144 * first sampling of TSC against kernel_ns ends in the low part of the
1145 * range, and the second in the high end of the range, we can get:
1146 *
1147 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1148 *
1149 * As the sampling errors potentially range in the thousands of cycles,
1150 * it is possible such a time value has already been observed by the
1151 * guest. To protect against this, we must compute the system time as
1152 * observed by the guest and ensure the new system time is greater.
1153 */
1154 max_kernel_ns = 0;
1155 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1156 max_kernel_ns = vcpu->last_guest_tsc -
1157 vcpu->hv_clock.tsc_timestamp;
1158 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1159 vcpu->hv_clock.tsc_to_system_mul,
1160 vcpu->hv_clock.tsc_shift);
1161 max_kernel_ns += vcpu->last_kernel_ns;
1162 }
afbcf7ab 1163
e48672fa 1164 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1165 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1166 &vcpu->hv_clock.tsc_shift,
1167 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1168 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1169 }
1170
1d5f066e
ZA		 1171 if (max_kernel_ns > kernel_ns)
1172 kernel_ns = max_kernel_ns;
1173
8cfdc000 1174 /* With all the info we got, fill in the values */
1d5f066e 1175 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1176 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1177 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1178 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1179 vcpu->hv_clock.flags = 0;
1180
18068523
GOC		 1181 /*
1182 * The interface expects us to write an even number signaling that the
1183 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1184 * state, we just increase by 2 at the end.
18068523 1185 */
50d0a0f9 1186 vcpu->hv_clock.version += 2;
18068523
GOC		 1187
1188 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1189
1190 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1191 sizeof(vcpu->hv_clock));
18068523
GOC		 1192
1193 kunmap_atomic(shared_kaddr, KM_USER0);
1194
1195 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1196 return 0;
c8076604
GH		 1197}
1198
9ba075a6
AK		 1199static bool msr_mtrr_valid(unsigned msr)
1200{
1201 switch (msr) {
1202 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1203 case MSR_MTRRfix64K_00000:
1204 case MSR_MTRRfix16K_80000:
1205 case MSR_MTRRfix16K_A0000:
1206 case MSR_MTRRfix4K_C0000:
1207 case MSR_MTRRfix4K_C8000:
1208 case MSR_MTRRfix4K_D0000:
1209 case MSR_MTRRfix4K_D8000:
1210 case MSR_MTRRfix4K_E0000:
1211 case MSR_MTRRfix4K_E8000:
1212 case MSR_MTRRfix4K_F0000:
1213 case MSR_MTRRfix4K_F8000:
1214 case MSR_MTRRdefType:
1215 case MSR_IA32_CR_PAT:
1216 return true;
1217 case 0x2f8:
1218 return true;
1219 }
1220 return false;
1221}
1222
d6289b93
MT		 1223static bool valid_pat_type(unsigned t)
1224{
1225 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1226}
1227
1228static bool valid_mtrr_type(unsigned t)
1229{
1230 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1231}
1232
1233static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1234{
1235 int i;
1236
1237 if (!msr_mtrr_valid(msr))
1238 return false;
1239
1240 if (msr == MSR_IA32_CR_PAT) {
1241 for (i = 0; i < 8; i++)
1242 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1243 return false;
1244 return true;
1245 } else if (msr == MSR_MTRRdefType) {
1246 if (data & ~0xcff)
1247 return false;
1248 return valid_mtrr_type(data & 0xff);
1249 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1250 for (i = 0; i < 8 ; i++)
1251 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1252 return false;
1253 return true;
1254 }
1255
1256 /* variable MTRRs */
1257 return valid_mtrr_type(data & 0xff);
1258}
1259
9ba075a6
AK		 1260static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1261{
0bed3b56
SY		 1262 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1263
d6289b93 1264 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1265 return 1;
1266
0bed3b56
SY		 1267 if (msr == MSR_MTRRdefType) {
1268 vcpu->arch.mtrr_state.def_type = data;
1269 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1270 } else if (msr == MSR_MTRRfix64K_00000)
1271 p[0] = data;
1272 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1273 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1274 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1275 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1276 else if (msr == MSR_IA32_CR_PAT)
1277 vcpu->arch.pat = data;
1278 else { /* Variable MTRRs */
1279 int idx, is_mtrr_mask;
1280 u64 *pt;
1281
1282 idx = (msr - 0x200) / 2;
1283 is_mtrr_mask = msr - 0x200 - 2 * idx;
1284 if (!is_mtrr_mask)
1285 pt =
1286 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1287 else
1288 pt =
1289 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1290 *pt = data;
1291 }
1292
1293 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1294 return 0;
1295}
15c4a640 1296
890ca9ae 1297static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1298{
890ca9ae
HY		 1299 u64 mcg_cap = vcpu->arch.mcg_cap;
1300 unsigned bank_num = mcg_cap & 0xff;
1301
15c4a640 1302 switch (msr) {
15c4a640 1303 case MSR_IA32_MCG_STATUS:
890ca9ae 1304 vcpu->arch.mcg_status = data;
15c4a640 1305 break;
c7ac679c 1306 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1307 if (!(mcg_cap & MCG_CTL_P))
1308 return 1;
1309 if (data != 0 && data != ~(u64)0)
1310 return -1;
1311 vcpu->arch.mcg_ctl = data;
1312 break;
1313 default:
1314 if (msr >= MSR_IA32_MC0_CTL &&
1315 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1316 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1317 /* only 0 or all 1s can be written to IA32_MCi_CTL
1318 * some Linux kernels though clear bit 10 in bank 4 to
1319 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1320 * this to avoid an uncatched #GP in the guest
1321 */
890ca9ae 1322 if ((offset & 0x3) == 0 &&
114be429 1323 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1324 return -1;
1325 vcpu->arch.mce_banks[offset] = data;
1326 break;
1327 }
1328 return 1;
1329 }
1330 return 0;
1331}
1332
ffde22ac
ES		 1333static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1334{
1335 struct kvm *kvm = vcpu->kvm;
1336 int lm = is_long_mode(vcpu);
1337 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1338 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1339 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1340 : kvm->arch.xen_hvm_config.blob_size_32;
1341 u32 page_num = data & ~PAGE_MASK;
1342 u64 page_addr = data & PAGE_MASK;
1343 u8 *page;
1344 int r;
1345
1346 r = -E2BIG;
1347 if (page_num >= blob_size)
1348 goto out;
1349 r = -ENOMEM;
1350 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1351 if (!page)
1352 goto out;
1353 r = -EFAULT;
1354 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1355 goto out_free;
1356 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1357 goto out_free;
1358 r = 0;
1359out_free:
1360 kfree(page);
1361out:
1362 return r;
1363}
1364
55cd8e5a
GN		 1365static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1366{
1367 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1368}
1369
1370static bool kvm_hv_msr_partition_wide(u32 msr)
1371{
1372 bool r = false;
1373 switch (msr) {
1374 case HV_X64_MSR_GUEST_OS_ID:
1375 case HV_X64_MSR_HYPERCALL:
1376 r = true;
1377 break;
1378 }
1379
1380 return r;
1381}
1382
1383static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1384{
1385 struct kvm *kvm = vcpu->kvm;
1386
1387 switch (msr) {
1388 case HV_X64_MSR_GUEST_OS_ID:
1389 kvm->arch.hv_guest_os_id = data;
1390 /* setting guest os id to zero disables hypercall page */
1391 if (!kvm->arch.hv_guest_os_id)
1392 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1393 break;
1394 case HV_X64_MSR_HYPERCALL: {
1395 u64 gfn;
1396 unsigned long addr;
1397 u8 instructions[4];
1398
1399 /* if guest os id is not set hypercall should remain disabled */
1400 if (!kvm->arch.hv_guest_os_id)
1401 break;
1402 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1403 kvm->arch.hv_hypercall = data;
1404 break;
1405 }
1406 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1407 addr = gfn_to_hva(kvm, gfn);
1408 if (kvm_is_error_hva(addr))
1409 return 1;
1410 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1411 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1412 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1413 return 1;
1414 kvm->arch.hv_hypercall = data;
1415 break;
1416 }
1417 default:
1418 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1419 "data 0x%llx\n", msr, data);
1420 return 1;
1421 }
1422 return 0;
1423}
1424
1425static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1426{
10388a07
GN		 1427 switch (msr) {
1428 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1429 unsigned long addr;
55cd8e5a 1430
10388a07
GN		 1431 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1432 vcpu->arch.hv_vapic = data;
1433 break;
1434 }
1435 addr = gfn_to_hva(vcpu->kvm, data >>
1436 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1437 if (kvm_is_error_hva(addr))
1438 return 1;
8b0cedff 1439 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1440 return 1;
1441 vcpu->arch.hv_vapic = data;
1442 break;
1443 }
1444 case HV_X64_MSR_EOI:
1445 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1446 case HV_X64_MSR_ICR:
1447 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1448 case HV_X64_MSR_TPR:
1449 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1450 default:
1451 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1452 "data 0x%llx\n", msr, data);
1453 return 1;
1454 }
1455
1456 return 0;
55cd8e5a
GN		 1457}
1458
344d9588
GN		 1459static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1460{
1461 gpa_t gpa = data & ~0x3f;
1462
6adba527
GN		 1463 /* Bits 2:5 are resrved, Should be zero */
1464 if (data & 0x3c)
344d9588
GN		 1465 return 1;
1466
1467 vcpu->arch.apf.msr_val = data;
1468
1469 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1470 kvm_clear_async_pf_completion_queue(vcpu);
1471 kvm_async_pf_hash_reset(vcpu);
1472 return 0;
1473 }
1474
1475 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1476 return 1;
1477
6adba527 1478 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1479 kvm_async_pf_wakeup_all(vcpu);
1480 return 0;
1481}
1482
12f9a48f
GC		 1483static void kvmclock_reset(struct kvm_vcpu *vcpu)
1484{
1485 if (vcpu->arch.time_page) {
1486 kvm_release_page_dirty(vcpu->arch.time_page);
1487 vcpu->arch.time_page = NULL;
1488 }
1489}
1490
c9aaa895
GC		 1491static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1492{
1493 u64 delta;
1494
1495 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1496 return;
1497
1498 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1499 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1500 vcpu->arch.st.accum_steal = delta;
1501}
1502
1503static void record_steal_time(struct kvm_vcpu *vcpu)
1504{
1505 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1506 return;
1507
1508 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1509 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1510 return;
1511
1512 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1513 vcpu->arch.st.steal.version += 2;
1514 vcpu->arch.st.accum_steal = 0;
1515
1516 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1517 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1518}
1519
15c4a640
CO		 1520int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1521{
1522 switch (msr) {
15c4a640 1523 case MSR_EFER:
b69e8cae 1524 return set_efer(vcpu, data);
8f1589d9
AP		 1525 case MSR_K7_HWCR:
1526 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1527 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1528 if (data != 0) {
1529 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1530 data);
1531 return 1;
1532 }
15c4a640 1533 break;
f7c6d140
AP		 1534 case MSR_FAM10H_MMIO_CONF_BASE:
1535 if (data != 0) {
1536 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1537 "0x%llx\n", data);
1538 return 1;
1539 }
15c4a640 1540 break;
c323c0e5 1541 case MSR_AMD64_NB_CFG:
c7ac679c 1542 break;
b5e2fec0
AG		 1543 case MSR_IA32_DEBUGCTLMSR:
1544 if (!data) {
1545 /* We support the non-activated case already */
1546 break;
1547 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1548 /* Values other than LBR and BTF are vendor-specific,
1549 thus reserved and should throw a #GP */
1550 return 1;
1551 }
1552 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1553 __func__, data);
1554 break;
15c4a640
CO		 1555 case MSR_IA32_UCODE_REV:
1556 case MSR_IA32_UCODE_WRITE:
61a6bd67 1557 case MSR_VM_HSAVE_PA:
6098ca93 1558 case MSR_AMD64_PATCH_LOADER:
15c4a640 1559 break;
9ba075a6
AK		 1560 case 0x200 ... 0x2ff:
1561 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1562 case MSR_IA32_APICBASE:
1563 kvm_set_apic_base(vcpu, data);
1564 break;
0105d1a5
GN		 1565 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1566 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1567 case MSR_IA32_MISC_ENABLE:
ad312c7c 1568 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1569 break;
11c6bffa 1570 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1571 case MSR_KVM_WALL_CLOCK:
1572 vcpu->kvm->arch.wall_clock = data;
1573 kvm_write_wall_clock(vcpu->kvm, data);
1574 break;
11c6bffa 1575 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1576 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1577 kvmclock_reset(vcpu);
18068523
GOC		 1578
1579 vcpu->arch.time = data;
c285545f 1580 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1581
1582 /* we verify if the enable bit is set... */
1583 if (!(data & 1))
1584 break;
1585
1586 /* ...but clean it before doing the actual write */
1587 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1588
18068523
GOC		 1589 vcpu->arch.time_page =
1590 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1591
1592 if (is_error_page(vcpu->arch.time_page)) {
1593 kvm_release_page_clean(vcpu->arch.time_page);
1594 vcpu->arch.time_page = NULL;
1595 }
18068523
GOC		 1596 break;
1597 }
344d9588
GN		 1598 case MSR_KVM_ASYNC_PF_EN:
1599 if (kvm_pv_enable_async_pf(vcpu, data))
1600 return 1;
1601 break;
c9aaa895
GC		 1602 case MSR_KVM_STEAL_TIME:
1603
1604 if (unlikely(!sched_info_on()))
1605 return 1;
1606
1607 if (data & KVM_STEAL_RESERVED_MASK)
1608 return 1;
1609
1610 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1611 data & KVM_STEAL_VALID_BITS))
1612 return 1;
1613
1614 vcpu->arch.st.msr_val = data;
1615
1616 if (!(data & KVM_MSR_ENABLED))
1617 break;
1618
1619 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1620
1621 preempt_disable();
1622 accumulate_steal_time(vcpu);
1623 preempt_enable();
1624
1625 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1626
1627 break;
1628
890ca9ae
HY		 1629 case MSR_IA32_MCG_CTL:
1630 case MSR_IA32_MCG_STATUS:
1631 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1632 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1633
1634 /* Performance counters are not protected by a CPUID bit,
1635 * so we should check all of them in the generic path for the sake of
1636 * cross vendor migration.
1637 * Writing a zero into the event select MSRs disables them,
1638 * which we perfectly emulate ;-). Any other value should be at least
1639 * reported, some guests depend on them.
1640 */
1641 case MSR_P6_EVNTSEL0:
1642 case MSR_P6_EVNTSEL1:
1643 case MSR_K7_EVNTSEL0:
1644 case MSR_K7_EVNTSEL1:
1645 case MSR_K7_EVNTSEL2:
1646 case MSR_K7_EVNTSEL3:
1647 if (data != 0)
1648 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1649 "0x%x data 0x%llx\n", msr, data);
1650 break;
1651 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1652 * so we ignore writes to make it happy.
1653 */
1654 case MSR_P6_PERFCTR0:
1655 case MSR_P6_PERFCTR1:
1656 case MSR_K7_PERFCTR0:
1657 case MSR_K7_PERFCTR1:
1658 case MSR_K7_PERFCTR2:
1659 case MSR_K7_PERFCTR3:
1660 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1661 "0x%x data 0x%llx\n", msr, data);
1662 break;
84e0cefa
JS		 1663 case MSR_K7_CLK_CTL:
1664 /*
1665 * Ignore all writes to this no longer documented MSR.
1666 * Writes are only relevant for old K7 processors,
1667 * all pre-dating SVM, but a recommended workaround from
1668 * AMD for these chips. It is possible to speicify the
1669 * affected processor models on the command line, hence
1670 * the need to ignore the workaround.
1671 */
1672 break;
55cd8e5a
GN		 1673 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1674 if (kvm_hv_msr_partition_wide(msr)) {
1675 int r;
1676 mutex_lock(&vcpu->kvm->lock);
1677 r = set_msr_hyperv_pw(vcpu, msr, data);
1678 mutex_unlock(&vcpu->kvm->lock);
1679 return r;
1680 } else
1681 return set_msr_hyperv(vcpu, msr, data);
1682 break;
91c9c3ed 1683 case MSR_IA32_BBL_CR_CTL3:
1684 /* Drop writes to this legacy MSR -- see rdmsr
1685 * counterpart for further detail.
1686 */
1687 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1688 break;
15c4a640 1689 default:
ffde22ac
ES		 1690 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1691 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1692 if (!ignore_msrs) {
1693 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1694 msr, data);
1695 return 1;
1696 } else {
1697 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1698 msr, data);
1699 break;
1700 }
15c4a640
CO		 1701 }
1702 return 0;
1703}
1704EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1705
1706
1707/*
1708 * Reads an msr value (of 'msr_index') into 'pdata'.
1709 * Returns 0 on success, non-0 otherwise.
1710 * Assumes vcpu_load() was already called.
1711 */
1712int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1713{
1714 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1715}
1716
9ba075a6
AK		 1717static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1718{
0bed3b56
SY		 1719 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1720
9ba075a6
AK		 1721 if (!msr_mtrr_valid(msr))
1722 return 1;
1723
0bed3b56
SY		 1724 if (msr == MSR_MTRRdefType)
1725 *pdata = vcpu->arch.mtrr_state.def_type +
1726 (vcpu->arch.mtrr_state.enabled << 10);
1727 else if (msr == MSR_MTRRfix64K_00000)
1728 *pdata = p[0];
1729 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1730 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1731 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1732 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1733 else if (msr == MSR_IA32_CR_PAT)
1734 *pdata = vcpu->arch.pat;
1735 else { /* Variable MTRRs */
1736 int idx, is_mtrr_mask;
1737 u64 *pt;
1738
1739 idx = (msr - 0x200) / 2;
1740 is_mtrr_mask = msr - 0x200 - 2 * idx;
1741 if (!is_mtrr_mask)
1742 pt =
1743 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1744 else
1745 pt =
1746 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1747 *pdata = *pt;
1748 }
1749
9ba075a6
AK		 1750 return 0;
1751}
1752
890ca9ae 1753static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1754{
1755 u64 data;
890ca9ae
HY		 1756 u64 mcg_cap = vcpu->arch.mcg_cap;
1757 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1758
1759 switch (msr) {
15c4a640
CO		 1760 case MSR_IA32_P5_MC_ADDR:
1761 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1762 data = 0;
1763 break;
15c4a640 1764 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1765 data = vcpu->arch.mcg_cap;
1766 break;
c7ac679c 1767 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1768 if (!(mcg_cap & MCG_CTL_P))
1769 return 1;
1770 data = vcpu->arch.mcg_ctl;
1771 break;
1772 case MSR_IA32_MCG_STATUS:
1773 data = vcpu->arch.mcg_status;
1774 break;
1775 default:
1776 if (msr >= MSR_IA32_MC0_CTL &&
1777 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1778 u32 offset = msr - MSR_IA32_MC0_CTL;
1779 data = vcpu->arch.mce_banks[offset];
1780 break;
1781 }
1782 return 1;
1783 }
1784 *pdata = data;
1785 return 0;
1786}
1787
55cd8e5a
GN		 1788static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1789{
1790 u64 data = 0;
1791 struct kvm *kvm = vcpu->kvm;
1792
1793 switch (msr) {
1794 case HV_X64_MSR_GUEST_OS_ID:
1795 data = kvm->arch.hv_guest_os_id;
1796 break;
1797 case HV_X64_MSR_HYPERCALL:
1798 data = kvm->arch.hv_hypercall;
1799 break;
1800 default:
1801 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1802 return 1;
1803 }
1804
1805 *pdata = data;
1806 return 0;
1807}
1808
1809static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1810{
1811 u64 data = 0;
1812
1813 switch (msr) {
1814 case HV_X64_MSR_VP_INDEX: {
1815 int r;
1816 struct kvm_vcpu *v;
1817 kvm_for_each_vcpu(r, v, vcpu->kvm)
1818 if (v == vcpu)
1819 data = r;
1820 break;
1821 }
10388a07
GN		 1822 case HV_X64_MSR_EOI:
1823 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1824 case HV_X64_MSR_ICR:
1825 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1826 case HV_X64_MSR_TPR:
1827 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee
MW		 1828 case HV_X64_MSR_APIC_ASSIST_PAGE:
1829 return vcpu->arch.hv_vapic;
55cd8e5a
GN		 1830 default:
1831 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1832 return 1;
1833 }
1834 *pdata = data;
1835 return 0;
1836}
1837
890ca9ae
HY		 1838int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1839{
1840 u64 data;
1841
1842 switch (msr) {
890ca9ae 1843 case MSR_IA32_PLATFORM_ID:
15c4a640 1844 case MSR_IA32_UCODE_REV:
15c4a640 1845 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1846 case MSR_IA32_DEBUGCTLMSR:
1847 case MSR_IA32_LASTBRANCHFROMIP:
1848 case MSR_IA32_LASTBRANCHTOIP:
1849 case MSR_IA32_LASTINTFROMIP:
1850 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1851 case MSR_K8_SYSCFG:
1852 case MSR_K7_HWCR:
61a6bd67 1853 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1854 case MSR_P6_PERFCTR0:
1855 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1856 case MSR_P6_EVNTSEL0:
1857 case MSR_P6_EVNTSEL1:
9e699624 1858 case MSR_K7_EVNTSEL0:
1f3ee616 1859 case MSR_K7_PERFCTR0:
1fdbd48c 1860 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1861 case MSR_AMD64_NB_CFG:
f7c6d140 1862 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1863 data = 0;
1864 break;
9ba075a6
AK		 1865 case MSR_MTRRcap:
1866 data = 0x500 | KVM_NR_VAR_MTRR;
1867 break;
1868 case 0x200 ... 0x2ff:
1869 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1870 case 0xcd: /* fsb frequency */
1871 data = 3;
1872 break;
7b914098
JS		 1873 /*
1874 * MSR_EBC_FREQUENCY_ID
1875 * Conservative value valid for even the basic CPU models.
1876 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1877 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1878 * and 266MHz for model 3, or 4. Set Core Clock
1879 * Frequency to System Bus Frequency Ratio to 1 (bits
1880 * 31:24) even though these are only valid for CPU
1881 * models > 2, however guests may end up dividing or
1882 * multiplying by zero otherwise.
1883 */
1884 case MSR_EBC_FREQUENCY_ID:
1885 data = 1 << 24;
1886 break;
15c4a640
CO		 1887 case MSR_IA32_APICBASE:
1888 data = kvm_get_apic_base(vcpu);
1889 break;
0105d1a5
GN		 1890 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1891 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1892 break;
15c4a640 1893 case MSR_IA32_MISC_ENABLE:
ad312c7c 1894 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1895 break;
847f0ad8
AG		 1896 case MSR_IA32_PERF_STATUS:
1897 /* TSC increment by tick */
1898 data = 1000ULL;
1899 /* CPU multiplier */
1900 data |= (((uint64_t)4ULL) << 40);
1901 break;
15c4a640 1902 case MSR_EFER:
f6801dff 1903 data = vcpu->arch.efer;
15c4a640 1904 break;
18068523 1905 case MSR_KVM_WALL_CLOCK:
11c6bffa 1906 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1907 data = vcpu->kvm->arch.wall_clock;
1908 break;
1909 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1910 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1911 data = vcpu->arch.time;
1912 break;
344d9588
GN		 1913 case MSR_KVM_ASYNC_PF_EN:
1914 data = vcpu->arch.apf.msr_val;
1915 break;
c9aaa895
GC		 1916 case MSR_KVM_STEAL_TIME:
1917 data = vcpu->arch.st.msr_val;
1918 break;
890ca9ae
HY		 1919 case MSR_IA32_P5_MC_ADDR:
1920 case MSR_IA32_P5_MC_TYPE:
1921 case MSR_IA32_MCG_CAP:
1922 case MSR_IA32_MCG_CTL:
1923 case MSR_IA32_MCG_STATUS:
1924 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1925 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1926 case MSR_K7_CLK_CTL:
1927 /*
1928 * Provide expected ramp-up count for K7. All other
1929 * are set to zero, indicating minimum divisors for
1930 * every field.
1931 *
1932 * This prevents guest kernels on AMD host with CPU
1933 * type 6, model 8 and higher from exploding due to
1934 * the rdmsr failing.
1935 */
1936 data = 0x20000000;
1937 break;
55cd8e5a
GN		 1938 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1939 if (kvm_hv_msr_partition_wide(msr)) {
1940 int r;
1941 mutex_lock(&vcpu->kvm->lock);
1942 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1943 mutex_unlock(&vcpu->kvm->lock);
1944 return r;
1945 } else
1946 return get_msr_hyperv(vcpu, msr, pdata);
1947 break;
91c9c3ed 1948 case MSR_IA32_BBL_CR_CTL3:
1949 /* This legacy MSR exists but isn't fully documented in current
1950 * silicon. It is however accessed by winxp in very narrow
1951 * scenarios where it sets bit #19, itself documented as
1952 * a "reserved" bit. Best effort attempt to source coherent
1953 * read data here should the balance of the register be
1954 * interpreted by the guest:
1955 *
1956 * L2 cache control register 3: 64GB range, 256KB size,
1957 * enabled, latency 0x1, configured
1958 */
1959 data = 0xbe702111;
1960 break;
15c4a640 1961 default:
ed85c068
AP		 1962 if (!ignore_msrs) {
1963 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1964 return 1;
1965 } else {
1966 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1967 data = 0;
1968 }
1969 break;
15c4a640
CO		 1970 }
1971 *pdata = data;
1972 return 0;
1973}
1974EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1975
313a3dc7
CO		 1976/*
1977 * Read or write a bunch of msrs. All parameters are kernel addresses.
1978 *
1979 * @return number of msrs set successfully.
1980 */
1981static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1982 struct kvm_msr_entry *entries,
1983 int (*do_msr)(struct kvm_vcpu *vcpu,
1984 unsigned index, u64 *data))
1985{
f656ce01 1986 int i, idx;
313a3dc7 1987
f656ce01 1988 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1989 for (i = 0; i < msrs->nmsrs; ++i)
1990 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1991 break;
f656ce01 1992 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1993
313a3dc7
CO		 1994 return i;
1995}
1996
1997/*
1998 * Read or write a bunch of msrs. Parameters are user addresses.
1999 *
2000 * @return number of msrs set successfully.
2001 */
2002static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2003 int (*do_msr)(struct kvm_vcpu *vcpu,
2004 unsigned index, u64 *data),
2005 int writeback)
2006{
2007 struct kvm_msrs msrs;
2008 struct kvm_msr_entry *entries;
2009 int r, n;
2010 unsigned size;
2011
2012 r = -EFAULT;
2013 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2014 goto out;
2015
2016 r = -E2BIG;
2017 if (msrs.nmsrs >= MAX_IO_MSRS)
2018 goto out;
2019
2020 r = -ENOMEM;
2021 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 2022 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 2023 if (!entries)
2024 goto out;
2025
2026 r = -EFAULT;
2027 if (copy_from_user(entries, user_msrs->entries, size))
2028 goto out_free;
2029
2030 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2031 if (r < 0)
2032 goto out_free;
2033
2034 r = -EFAULT;
2035 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2036 goto out_free;
2037
2038 r = n;
2039
2040out_free:
7a73c028 2041 kfree(entries);
313a3dc7
CO		 2042out:
2043 return r;
2044}
2045
018d00d2
ZX		 2046int kvm_dev_ioctl_check_extension(long ext)
2047{
2048 int r;
2049
2050 switch (ext) {
2051 case KVM_CAP_IRQCHIP:
2052 case KVM_CAP_HLT:
2053 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2054 case KVM_CAP_SET_TSS_ADDR:
07716717 2055 case KVM_CAP_EXT_CPUID:
c8076604 2056 case KVM_CAP_CLOCKSOURCE:
7837699f 2057 case KVM_CAP_PIT:
a28e4f5a 2058 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2059 case KVM_CAP_MP_STATE:
ed848624 2060 case KVM_CAP_SYNC_MMU:
a355c85c 2061 case KVM_CAP_USER_NMI:
52d939a0 2062 case KVM_CAP_REINJECT_CONTROL:
4925663a 2063 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2064 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2065 case KVM_CAP_IRQFD:
d34e6b17 2066 case KVM_CAP_IOEVENTFD:
c5ff41ce 2067 case KVM_CAP_PIT2:
e9f42757 2068 case KVM_CAP_PIT_STATE2:
b927a3ce 2069 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2070 case KVM_CAP_XEN_HVM:
afbcf7ab 2071 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2072 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2073 case KVM_CAP_HYPERV:
10388a07 2074 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2075 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2076 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2077 case KVM_CAP_DEBUGREGS:
d2be1651 2078 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2079 case KVM_CAP_XSAVE:
344d9588 2080 case KVM_CAP_ASYNC_PF:
92a1f12d 2081 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 2082 r = 1;
2083 break;
542472b5
LV		 2084 case KVM_CAP_COALESCED_MMIO:
2085 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2086 break;
774ead3a
AK		 2087 case KVM_CAP_VAPIC:
2088 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2089 break;
f725230a 2090 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2091 r = KVM_SOFT_MAX_VCPUS;
2092 break;
2093 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2094 r = KVM_MAX_VCPUS;
2095 break;
a988b910
AK		 2096 case KVM_CAP_NR_MEMSLOTS:
2097 r = KVM_MEMORY_SLOTS;
2098 break;
a68a6a72
MT		 2099 case KVM_CAP_PV_MMU: /* obsolete */
2100 r = 0;
2f333bcb 2101 break;
62c476c7 2102 case KVM_CAP_IOMMU:
19de40a8 2103 r = iommu_found();
62c476c7 2104 break;
890ca9ae
HY		 2105 case KVM_CAP_MCE:
2106 r = KVM_MAX_MCE_BANKS;
2107 break;
2d5b5a66
SY		 2108 case KVM_CAP_XCRS:
2109 r = cpu_has_xsave;
2110 break;
92a1f12d
JR		 2111 case KVM_CAP_TSC_CONTROL:
2112 r = kvm_has_tsc_control;
2113 break;
018d00d2
ZX		 2114 default:
2115 r = 0;
2116 break;
2117 }
2118 return r;
2119
2120}
2121
043405e1
CO		 2122long kvm_arch_dev_ioctl(struct file *filp,
2123 unsigned int ioctl, unsigned long arg)
2124{
2125 void __user *argp = (void __user *)arg;
2126 long r;
2127
2128 switch (ioctl) {
2129 case KVM_GET_MSR_INDEX_LIST: {
2130 struct kvm_msr_list __user *user_msr_list = argp;
2131 struct kvm_msr_list msr_list;
2132 unsigned n;
2133
2134 r = -EFAULT;
2135 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2136 goto out;
2137 n = msr_list.nmsrs;
2138 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2139 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2140 goto out;
2141 r = -E2BIG;
e125e7b6 2142 if (n < msr_list.nmsrs)
043405e1
CO		 2143 goto out;
2144 r = -EFAULT;
2145 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2146 num_msrs_to_save * sizeof(u32)))
2147 goto out;
e125e7b6 2148 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2149 &emulated_msrs,
2150 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2151 goto out;
2152 r = 0;
2153 break;
2154 }
674eea0f
AK		 2155 case KVM_GET_SUPPORTED_CPUID: {
2156 struct kvm_cpuid2 __user *cpuid_arg = argp;
2157 struct kvm_cpuid2 cpuid;
2158
2159 r = -EFAULT;
2160 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2161 goto out;
2162 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2163 cpuid_arg->entries);
674eea0f
AK		 2164 if (r)
2165 goto out;
2166
2167 r = -EFAULT;
2168 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2169 goto out;
2170 r = 0;
2171 break;
2172 }
890ca9ae
HY		 2173 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2174 u64 mce_cap;
2175
2176 mce_cap = KVM_MCE_CAP_SUPPORTED;
2177 r = -EFAULT;
2178 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2179 goto out;
2180 r = 0;
2181 break;
2182 }
043405e1
CO		 2183 default:
2184 r = -EINVAL;
2185 }
2186out:
2187 return r;
2188}
2189
f5f48ee1
SY		 2190static void wbinvd_ipi(void *garbage)
2191{
2192 wbinvd();
2193}
2194
2195static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2196{
2197 return vcpu->kvm->arch.iommu_domain &&
2198 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2199}
2200
313a3dc7
CO		 2201void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2202{
f5f48ee1
SY		 2203 /* Address WBINVD may be executed by guest */
2204 if (need_emulate_wbinvd(vcpu)) {
2205 if (kvm_x86_ops->has_wbinvd_exit())
2206 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2207 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2208 smp_call_function_single(vcpu->cpu,
2209 wbinvd_ipi, NULL, 1);
2210 }
2211
313a3dc7 2212 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2213 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2214 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2215 s64 tsc_delta;
2216 u64 tsc;
2217
2218 kvm_get_msr(vcpu, MSR_IA32_TSC, &tsc);
2219 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2220 tsc - vcpu->arch.last_guest_tsc;
2221
e48672fa
ZA		 2222 if (tsc_delta < 0)
2223 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2224 if (check_tsc_unstable()) {
e48672fa 2225 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2226 vcpu->arch.tsc_catchup = 1;
c285545f 2227 }
1aa8ceef 2228 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2229 if (vcpu->cpu != cpu)
2230 kvm_migrate_timers(vcpu);
e48672fa 2231 vcpu->cpu = cpu;
6b7d7e76 2232 }
c9aaa895
GC		 2233
2234 accumulate_steal_time(vcpu);
2235 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2236}
2237
2238void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2239{
02daab21 2240 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2241 kvm_put_guest_fpu(vcpu);
7c4c0f4f 2242 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
313a3dc7
CO		 2243}
2244
07716717 2245static int is_efer_nx(void)
313a3dc7 2246{
e286e86e 2247 unsigned long long efer = 0;
313a3dc7 2248
e286e86e 2249 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2250 return efer & EFER_NX;
2251}
2252
2253static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2254{
2255 int i;
2256 struct kvm_cpuid_entry2 *e, *entry;
2257
313a3dc7 2258 entry = NULL;
ad312c7c
ZX		 2259 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2260 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2261 if (e->function == 0x80000001) {
2262 entry = e;
2263 break;
2264 }
2265 }
07716717 2266 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2267 entry->edx &= ~(1 << 20);
2268 printk(KERN_INFO "kvm: guest NX capability removed\n");
2269 }
2270}
2271
07716717 2272/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2273static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2274 struct kvm_cpuid *cpuid,
2275 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2276{
2277 int r, i;
2278 struct kvm_cpuid_entry *cpuid_entries;
2279
2280 r = -E2BIG;
2281 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2282 goto out;
2283 r = -ENOMEM;
2284 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2285 if (!cpuid_entries)
2286 goto out;
2287 r = -EFAULT;
2288 if (copy_from_user(cpuid_entries, entries,
2289 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2290 goto out_free;
2291 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2292 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2293 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2294 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2295 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2296 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2297 vcpu->arch.cpuid_entries[i].index = 0;
2298 vcpu->arch.cpuid_entries[i].flags = 0;
2299 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2300 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2301 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2302 }
2303 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2304 cpuid_fix_nx_cap(vcpu);
2305 r = 0;
fc61b800 2306 kvm_apic_set_version(vcpu);
0e851880 2307 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2308 update_cpuid(vcpu);
07716717
DK		 2309
2310out_free:
2311 vfree(cpuid_entries);
2312out:
2313 return r;
2314}
2315
2316static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2317 struct kvm_cpuid2 *cpuid,
2318 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2319{
2320 int r;
2321
2322 r = -E2BIG;
2323 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2324 goto out;
2325 r = -EFAULT;
ad312c7c 2326 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2327 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2328 goto out;
ad312c7c 2329 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2330 kvm_apic_set_version(vcpu);
0e851880 2331 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2332 update_cpuid(vcpu);
313a3dc7
CO		 2333 return 0;
2334
2335out:
2336 return r;
2337}
2338
07716717 2339static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2340 struct kvm_cpuid2 *cpuid,
2341 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2342{
2343 int r;
2344
2345 r = -E2BIG;
ad312c7c 2346 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2347 goto out;
2348 r = -EFAULT;
ad312c7c 2349 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2350 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2351 goto out;
2352 return 0;
2353
2354out:
ad312c7c 2355 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2356 return r;
2357}
2358
945ee35e
AK		 2359static void cpuid_mask(u32 *word, int wordnum)
2360{
2361 *word &= boot_cpu_data.x86_capability[wordnum];
2362}
2363
07716717 2364static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2365 u32 index)
07716717
DK		 2366{
2367 entry->function = function;
2368 entry->index = index;
2369 cpuid_count(entry->function, entry->index,
19355475 2370 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2371 entry->flags = 0;
2372}
2373
24c82e57
AK		 2374static bool supported_xcr0_bit(unsigned bit)
2375{
2376 u64 mask = ((u64)1 << bit);
2377
2378 return mask & (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) & host_xcr0;
2379}
2380
7faa4ee1
AK		 2381#define F(x) bit(X86_FEATURE_##x)
2382
07716717
DK		 2383static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2384 u32 index, int *nent, int maxnent)
2385{
7faa4ee1 2386 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2387#ifdef CONFIG_X86_64
17cc3935
SY		 2388 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2389 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2390 unsigned f_lm = F(LM);
2391#else
17cc3935 2392 unsigned f_gbpages = 0;
7faa4ee1 2393 unsigned f_lm = 0;
07716717 2394#endif
4e47c7a6 2395 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2396
2397 /* cpuid 1.edx */
2398 const u32 kvm_supported_word0_x86_features =
2399 F(FPU) | F(VME) | F(DE) | F(PSE) |
2400 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2401 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2402 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2403 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2404 0 /* Reserved, DS, ACPI */ | F(MMX) |
2405 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2406 0 /* HTT, TM, Reserved, PBE */;
2407 /* cpuid 0x80000001.edx */
2408 const u32 kvm_supported_word1_x86_features =
2409 F(FPU) | F(VME) | F(DE) | F(PSE) |
2410 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2411 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2412 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2413 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2414 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2415 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2416 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2417 /* cpuid 1.ecx */
2418 const u32 kvm_supported_word4_x86_features =
6c3f6041 2419 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2420 0 /* DS-CPL, VMX, SMX, EST */ |
2421 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2422 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2423 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2424 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0 2425 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
4a00efdf 2426 F(F16C) | F(RDRAND);
7faa4ee1 2427 /* cpuid 0x80000001.ecx */
07716717 2428 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2429 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2430 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2431 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2432 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2433
4429d5dc
B		 2434 /* cpuid 0xC0000001.edx */
2435 const u32 kvm_supported_word5_x86_features =
2436 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
2437 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
2438 F(PMM) | F(PMM_EN);
2439
611c120f
YW		 2440 /* cpuid 7.0.ebx */
2441 const u32 kvm_supported_word9_x86_features =
a01c8f9b 2442 F(SMEP) | F(FSGSBASE) | F(ERMS);
611c120f 2443
19355475 2444 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2445 get_cpu();
2446 do_cpuid_1_ent(entry, function, index);
2447 ++*nent;
2448
2449 switch (function) {
2450 case 0:
2acf923e 2451 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2452 break;
2453 case 1:
2454 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2455 cpuid_mask(&entry->edx, 0);
7faa4ee1 2456 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2457 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2458 /* we support x2apic emulation even if host does not support
2459 * it since we emulate x2apic in software */
2460 entry->ecx |= F(X2APIC);
07716717
DK		 2461 break;
2462 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2463 * may return different values. This forces us to get_cpu() before
2464 * issuing the first command, and also to emulate this annoying behavior
2465 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2466 case 2: {
2467 int t, times = entry->eax & 0xff;
2468
2469 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2470 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2471 for (t = 1; t < times && *nent < maxnent; ++t) {
2472 do_cpuid_1_ent(&entry[t], function, 0);
2473 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2474 ++*nent;
2475 }
2476 break;
2477 }
611c120f 2478 /* function 4 has additional index. */
07716717 2479 case 4: {
14af3f3c 2480 int i, cache_type;
07716717
DK		 2481
2482 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2483 /* read more entries until cache_type is zero */
14af3f3c
HH		 2484 for (i = 1; *nent < maxnent; ++i) {
2485 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2486 if (!cache_type)
2487 break;
14af3f3c
HH		 2488 do_cpuid_1_ent(&entry[i], function, i);
2489 entry[i].flags |=
07716717
DK		 2490 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2491 ++*nent;
2492 }
2493 break;
2494 }
611c120f
YW		 2495 case 7: {
2496 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2497 /* Mask ebx against host capbability word 9 */
2498 if (index == 0) {
2499 entry->ebx &= kvm_supported_word9_x86_features;
2500 cpuid_mask(&entry->ebx, 9);
2501 } else
2502 entry->ebx = 0;
2503 entry->eax = 0;
2504 entry->ecx = 0;
2505 entry->edx = 0;
2506 break;
2507 }
24c82e57
AK		 2508 case 9:
2509 break;
611c120f 2510 /* function 0xb has additional index. */
07716717 2511 case 0xb: {
14af3f3c 2512 int i, level_type;
07716717
DK		 2513
2514 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2515 /* read more entries until level_type is zero */
14af3f3c 2516 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2517 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2518 if (!level_type)
2519 break;
14af3f3c
HH		 2520 do_cpuid_1_ent(&entry[i], function, i);
2521 entry[i].flags |=
07716717
DK		 2522 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2523 ++*nent;
2524 }
2525 break;
2526 }
2acf923e 2527 case 0xd: {
02668b06 2528 int idx, i;
2acf923e
DC		 2529
2530 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
02668b06
AP		 2531 for (idx = 1, i = 1; *nent < maxnent && idx < 64; ++idx) {
2532 do_cpuid_1_ent(&entry[i], function, idx);
2533 if (entry[i].eax == 0 || !supported_xcr0_bit(idx))
20800bc9 2534 continue;
2acf923e
DC		 2535 entry[i].flags |=
2536 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2537 ++*nent;
02668b06 2538 ++i;
2acf923e
DC		 2539 }
2540 break;
2541 }
84478c82
GC		 2542 case KVM_CPUID_SIGNATURE: {
2543 char signature[12] = "KVMKVMKVM\0\0";
2544 u32 *sigptr = (u32 *)signature;
2545 entry->eax = 0;
2546 entry->ebx = sigptr[0];
2547 entry->ecx = sigptr[1];
2548 entry->edx = sigptr[2];
2549 break;
2550 }
2551 case KVM_CPUID_FEATURES:
2552 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2553 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64 2554 (1 << KVM_FEATURE_CLOCKSOURCE2) |
32918924 2555 (1 << KVM_FEATURE_ASYNC_PF) |
371bcf64 2556 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
c9aaa895
GC		 2557
2558 if (sched_info_on())
2559 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
2560
84478c82
GC		 2561 entry->ebx = 0;
2562 entry->ecx = 0;
2563 entry->edx = 0;
2564 break;
07716717
DK		 2565 case 0x80000000:
2566 entry->eax = min(entry->eax, 0x8000001a);
2567 break;
2568 case 0x80000001:
2569 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2570 cpuid_mask(&entry->edx, 1);
07716717 2571 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2572 cpuid_mask(&entry->ecx, 6);
07716717 2573 break;
24c82e57
AK		 2574 case 0x80000008: {
2575 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
2576 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
2577 unsigned phys_as = entry->eax & 0xff;
2578
2579 if (!g_phys_as)
2580 g_phys_as = phys_as;
2581 entry->eax = g_phys_as | (virt_as << 8);
2582 entry->ebx = entry->edx = 0;
2583 break;
2584 }
2585 case 0x80000019:
2586 entry->ecx = entry->edx = 0;
2587 break;
2588 case 0x8000001a:
2589 break;
2590 case 0x8000001d:
2591 break;
4429d5dc
B		 2592 /*Add support for Centaur's CPUID instruction*/
2593 case 0xC0000000:
2594 /*Just support up to 0xC0000004 now*/
2595 entry->eax = min(entry->eax, 0xC0000004);
2596 break;
2597 case 0xC0000001:
2598 entry->edx &= kvm_supported_word5_x86_features;
2599 cpuid_mask(&entry->edx, 5);
2600 break;
24c82e57
AK		 2601 case 3: /* Processor serial number */
2602 case 5: /* MONITOR/MWAIT */
2603 case 6: /* Thermal management */
2604 case 0xA: /* Architectural Performance Monitoring */
2605 case 0x80000007: /* Advanced power management */
4429d5dc
B		 2606 case 0xC0000002:
2607 case 0xC0000003:
2608 case 0xC0000004:
24c82e57
AK		 2609 default:
2610 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
4429d5dc 2611 break;
07716717 2612 }
d4330ef2
JR		 2613
2614 kvm_x86_ops->set_supported_cpuid(function, entry);
2615
07716717
DK		 2616 put_cpu();
2617}
2618
7faa4ee1
AK		 2619#undef F
2620
674eea0f 2621static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2622 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2623{
2624 struct kvm_cpuid_entry2 *cpuid_entries;
2625 int limit, nent = 0, r = -E2BIG;
2626 u32 func;
2627
2628 if (cpuid->nent < 1)
2629 goto out;
6a544355
AK		 2630 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2631 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2632 r = -ENOMEM;
2633 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2634 if (!cpuid_entries)
2635 goto out;
2636
2637 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2638 limit = cpuid_entries[0].eax;
2639 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2640 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2641 &nent, cpuid->nent);
07716717
DK		 2642 r = -E2BIG;
2643 if (nent >= cpuid->nent)
2644 goto out_free;
2645
2646 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2647 limit = cpuid_entries[nent - 1].eax;
2648 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2649 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2650 &nent, cpuid->nent);
84478c82
GC		 2651
2652
2653
2654 r = -E2BIG;
2655 if (nent >= cpuid->nent)
2656 goto out_free;
2657
4429d5dc
B		 2658 /* Add support for Centaur's CPUID instruction. */
2659 if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) {
2660 do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,
2661 &nent, cpuid->nent);
2662
2663 r = -E2BIG;
2664 if (nent >= cpuid->nent)
2665 goto out_free;
2666
2667 limit = cpuid_entries[nent - 1].eax;
2668 for (func = 0xC0000001;
2669 func <= limit && nent < cpuid->nent; ++func)
2670 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2671 &nent, cpuid->nent);
2672
2673 r = -E2BIG;
2674 if (nent >= cpuid->nent)
2675 goto out_free;
2676 }
2677
84478c82
GC		 2678 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2679 cpuid->nent);
2680
2681 r = -E2BIG;
2682 if (nent >= cpuid->nent)
2683 goto out_free;
2684
2685 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2686 cpuid->nent);
2687
cb007648
MM		 2688 r = -E2BIG;
2689 if (nent >= cpuid->nent)
2690 goto out_free;
2691
07716717
DK		 2692 r = -EFAULT;
2693 if (copy_to_user(entries, cpuid_entries,
19355475 2694 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2695 goto out_free;
2696 cpuid->nent = nent;
2697 r = 0;
2698
2699out_free:
2700 vfree(cpuid_entries);
2701out:
2702 return r;
2703}
2704
313a3dc7
CO		 2705static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2706 struct kvm_lapic_state *s)
2707{
ad312c7c 2708 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2709
2710 return 0;
2711}
2712
2713static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2714 struct kvm_lapic_state *s)
2715{
ad312c7c 2716 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2717 kvm_apic_post_state_restore(vcpu);
cb142eb7 2718 update_cr8_intercept(vcpu);
313a3dc7
CO		 2719
2720 return 0;
2721}
2722
f77bc6a4
ZX		 2723static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2724 struct kvm_interrupt *irq)
2725{
2726 if (irq->irq < 0 || irq->irq >= 256)
2727 return -EINVAL;
2728 if (irqchip_in_kernel(vcpu->kvm))
2729 return -ENXIO;
f77bc6a4 2730
66fd3f7f 2731 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2732 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2733
f77bc6a4
ZX		 2734 return 0;
2735}
2736
c4abb7c9
JK		 2737static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2738{
c4abb7c9 2739 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2740
2741 return 0;
2742}
2743
b209749f
AK		 2744static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2745 struct kvm_tpr_access_ctl *tac)
2746{
2747 if (tac->flags)
2748 return -EINVAL;
2749 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2750 return 0;
2751}
2752
890ca9ae
HY		 2753static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2754 u64 mcg_cap)
2755{
2756 int r;
2757 unsigned bank_num = mcg_cap & 0xff, bank;
2758
2759 r = -EINVAL;
a9e38c3e 2760 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2761 goto out;
2762 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2763 goto out;
2764 r = 0;
2765 vcpu->arch.mcg_cap = mcg_cap;
2766 /* Init IA32_MCG_CTL to all 1s */
2767 if (mcg_cap & MCG_CTL_P)
2768 vcpu->arch.mcg_ctl = ~(u64)0;
2769 /* Init IA32_MCi_CTL to all 1s */
2770 for (bank = 0; bank < bank_num; bank++)
2771 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2772out:
2773 return r;
2774}
2775
2776static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2777 struct kvm_x86_mce *mce)
2778{
2779 u64 mcg_cap = vcpu->arch.mcg_cap;
2780 unsigned bank_num = mcg_cap & 0xff;
2781 u64 *banks = vcpu->arch.mce_banks;
2782
2783 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2784 return -EINVAL;
2785 /*
2786 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2787 * reporting is disabled
2788 */
2789 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2790 vcpu->arch.mcg_ctl != ~(u64)0)
2791 return 0;
2792 banks += 4 * mce->bank;
2793 /*
2794 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2795 * reporting is disabled for the bank
2796 */
2797 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2798 return 0;
2799 if (mce->status & MCI_STATUS_UC) {
2800 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2801 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2802 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2803 return 0;
2804 }
2805 if (banks[1] & MCI_STATUS_VAL)
2806 mce->status |= MCI_STATUS_OVER;
2807 banks[2] = mce->addr;
2808 banks[3] = mce->misc;
2809 vcpu->arch.mcg_status = mce->mcg_status;
2810 banks[1] = mce->status;
2811 kvm_queue_exception(vcpu, MC_VECTOR);
2812 } else if (!(banks[1] & MCI_STATUS_VAL)
2813 || !(banks[1] & MCI_STATUS_UC)) {
2814 if (banks[1] & MCI_STATUS_VAL)
2815 mce->status |= MCI_STATUS_OVER;
2816 banks[2] = mce->addr;
2817 banks[3] = mce->misc;
2818 banks[1] = mce->status;
2819 } else
2820 banks[1] |= MCI_STATUS_OVER;
2821 return 0;
2822}
2823
3cfc3092
JK		 2824static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2825 struct kvm_vcpu_events *events)
2826{
03b82a30
JK		 2827 events->exception.injected =
2828 vcpu->arch.exception.pending &&
2829 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2830 events->exception.nr = vcpu->arch.exception.nr;
2831 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2832 events->exception.pad = 0;
3cfc3092
JK		 2833 events->exception.error_code = vcpu->arch.exception.error_code;
2834
03b82a30
JK		 2835 events->interrupt.injected =
2836 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2837 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2838 events->interrupt.soft = 0;
48005f64
JK		 2839 events->interrupt.shadow =
2840 kvm_x86_ops->get_interrupt_shadow(vcpu,
2841 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2842
2843 events->nmi.injected = vcpu->arch.nmi_injected;
2844 events->nmi.pending = vcpu->arch.nmi_pending;
2845 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2846 events->nmi.pad = 0;
3cfc3092
JK		 2847
2848 events->sipi_vector = vcpu->arch.sipi_vector;
2849
dab4b911 2850 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2851 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2852 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2853 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2854}
2855
2856static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2857 struct kvm_vcpu_events *events)
2858{
dab4b911 2859 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2860 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2861 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2862 return -EINVAL;
2863
3cfc3092
JK		 2864 vcpu->arch.exception.pending = events->exception.injected;
2865 vcpu->arch.exception.nr = events->exception.nr;
2866 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2867 vcpu->arch.exception.error_code = events->exception.error_code;
2868
2869 vcpu->arch.interrupt.pending = events->interrupt.injected;
2870 vcpu->arch.interrupt.nr = events->interrupt.nr;
2871 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2872 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2873 kvm_x86_ops->set_interrupt_shadow(vcpu,
2874 events->interrupt.shadow);
3cfc3092
JK		 2875
2876 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2877 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2878 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2879 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2880
dab4b911
JK		 2881 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2882 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2883
3842d135
AK		 2884 kvm_make_request(KVM_REQ_EVENT, vcpu);
2885
3cfc3092
JK		 2886 return 0;
2887}
2888
a1efbe77
JK		 2889static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2890 struct kvm_debugregs *dbgregs)
2891{
a1efbe77
JK		 2892 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2893 dbgregs->dr6 = vcpu->arch.dr6;
2894 dbgregs->dr7 = vcpu->arch.dr7;
2895 dbgregs->flags = 0;
97e69aa6 2896 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2897}
2898
2899static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2900 struct kvm_debugregs *dbgregs)
2901{
2902 if (dbgregs->flags)
2903 return -EINVAL;
2904
a1efbe77
JK		 2905 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2906 vcpu->arch.dr6 = dbgregs->dr6;
2907 vcpu->arch.dr7 = dbgregs->dr7;
2908
a1efbe77
JK		 2909 return 0;
2910}
2911
2d5b5a66
SY		 2912static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2913 struct kvm_xsave *guest_xsave)
2914{
2915 if (cpu_has_xsave)
2916 memcpy(guest_xsave->region,
2917 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2918 xstate_size);
2d5b5a66
SY		 2919 else {
2920 memcpy(guest_xsave->region,
2921 &vcpu->arch.guest_fpu.state->fxsave,
2922 sizeof(struct i387_fxsave_struct));
2923 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2924 XSTATE_FPSSE;
2925 }
2926}
2927
2928static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2929 struct kvm_xsave *guest_xsave)
2930{
2931 u64 xstate_bv =
2932 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2933
2934 if (cpu_has_xsave)
2935 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2936 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2937 else {
2938 if (xstate_bv & ~XSTATE_FPSSE)
2939 return -EINVAL;
2940 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2941 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2942 }
2943 return 0;
2944}
2945
2946static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2947 struct kvm_xcrs *guest_xcrs)
2948{
2949 if (!cpu_has_xsave) {
2950 guest_xcrs->nr_xcrs = 0;
2951 return;
2952 }
2953
2954 guest_xcrs->nr_xcrs = 1;
2955 guest_xcrs->flags = 0;
2956 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2957 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2958}
2959
2960static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2961 struct kvm_xcrs *guest_xcrs)
2962{
2963 int i, r = 0;
2964
2965 if (!cpu_has_xsave)
2966 return -EINVAL;
2967
2968 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2969 return -EINVAL;
2970
2971 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2972 /* Only support XCR0 currently */
2973 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2974 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2975 guest_xcrs->xcrs[0].value);
2976 break;
2977 }
2978 if (r)
2979 r = -EINVAL;
2980 return r;
2981}
2982
313a3dc7
CO		 2983long kvm_arch_vcpu_ioctl(struct file *filp,
2984 unsigned int ioctl, unsigned long arg)
2985{
2986 struct kvm_vcpu *vcpu = filp->private_data;
2987 void __user *argp = (void __user *)arg;
2988 int r;
d1ac91d8
AK		 2989 union {
2990 struct kvm_lapic_state *lapic;
2991 struct kvm_xsave *xsave;
2992 struct kvm_xcrs *xcrs;
2993 void *buffer;
2994 } u;
2995
2996 u.buffer = NULL;
313a3dc7
CO		 2997 switch (ioctl) {
2998 case KVM_GET_LAPIC: {
2204ae3c
MT		 2999 r = -EINVAL;
3000 if (!vcpu->arch.apic)
3001 goto out;
d1ac91d8 3002 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3003
b772ff36 3004 r = -ENOMEM;
d1ac91d8 3005 if (!u.lapic)
b772ff36 3006 goto out;
d1ac91d8 3007 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3008 if (r)
3009 goto out;
3010 r = -EFAULT;
d1ac91d8 3011 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3012 goto out;
3013 r = 0;
3014 break;
3015 }
3016 case KVM_SET_LAPIC: {
2204ae3c
MT		 3017 r = -EINVAL;
3018 if (!vcpu->arch.apic)
3019 goto out;
d1ac91d8 3020 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 3021 r = -ENOMEM;
d1ac91d8 3022 if (!u.lapic)
b772ff36 3023 goto out;
313a3dc7 3024 r = -EFAULT;
d1ac91d8 3025 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 3026 goto out;
d1ac91d8 3027 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3028 if (r)
3029 goto out;
3030 r = 0;
3031 break;
3032 }
f77bc6a4
ZX		 3033 case KVM_INTERRUPT: {
3034 struct kvm_interrupt irq;
3035
3036 r = -EFAULT;
3037 if (copy_from_user(&irq, argp, sizeof irq))
3038 goto out;
3039 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3040 if (r)
3041 goto out;
3042 r = 0;
3043 break;
3044 }
c4abb7c9
JK		 3045 case KVM_NMI: {
3046 r = kvm_vcpu_ioctl_nmi(vcpu);
3047 if (r)
3048 goto out;
3049 r = 0;
3050 break;
3051 }
313a3dc7
CO		 3052 case KVM_SET_CPUID: {
3053 struct kvm_cpuid __user *cpuid_arg = argp;
3054 struct kvm_cpuid cpuid;
3055
3056 r = -EFAULT;
3057 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3058 goto out;
3059 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3060 if (r)
3061 goto out;
3062 break;
3063 }
07716717
DK		 3064 case KVM_SET_CPUID2: {
3065 struct kvm_cpuid2 __user *cpuid_arg = argp;
3066 struct kvm_cpuid2 cpuid;
3067
3068 r = -EFAULT;
3069 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3070 goto out;
3071 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3072 cpuid_arg->entries);
07716717
DK		 3073 if (r)
3074 goto out;
3075 break;
3076 }
3077 case KVM_GET_CPUID2: {
3078 struct kvm_cpuid2 __user *cpuid_arg = argp;
3079 struct kvm_cpuid2 cpuid;
3080
3081 r = -EFAULT;
3082 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3083 goto out;
3084 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3085 cpuid_arg->entries);
07716717
DK		 3086 if (r)
3087 goto out;
3088 r = -EFAULT;
3089 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3090 goto out;
3091 r = 0;
3092 break;
3093 }
313a3dc7
CO		 3094 case KVM_GET_MSRS:
3095 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3096 break;
3097 case KVM_SET_MSRS:
3098 r = msr_io(vcpu, argp, do_set_msr, 0);
3099 break;
b209749f
AK		 3100 case KVM_TPR_ACCESS_REPORTING: {
3101 struct kvm_tpr_access_ctl tac;
3102
3103 r = -EFAULT;
3104 if (copy_from_user(&tac, argp, sizeof tac))
3105 goto out;
3106 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3107 if (r)
3108 goto out;
3109 r = -EFAULT;
3110 if (copy_to_user(argp, &tac, sizeof tac))
3111 goto out;
3112 r = 0;
3113 break;
3114 };
b93463aa
AK		 3115 case KVM_SET_VAPIC_ADDR: {
3116 struct kvm_vapic_addr va;
3117
3118 r = -EINVAL;
3119 if (!irqchip_in_kernel(vcpu->kvm))
3120 goto out;
3121 r = -EFAULT;
3122 if (copy_from_user(&va, argp, sizeof va))
3123 goto out;
3124 r = 0;
3125 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3126 break;
3127 }
890ca9ae
HY		 3128 case KVM_X86_SETUP_MCE: {
3129 u64 mcg_cap;
3130
3131 r = -EFAULT;
3132 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3133 goto out;
3134 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3135 break;
3136 }
3137 case KVM_X86_SET_MCE: {
3138 struct kvm_x86_mce mce;
3139
3140 r = -EFAULT;
3141 if (copy_from_user(&mce, argp, sizeof mce))
3142 goto out;
3143 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3144 break;
3145 }
3cfc3092
JK		 3146 case KVM_GET_VCPU_EVENTS: {
3147 struct kvm_vcpu_events events;
3148
3149 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3150
3151 r = -EFAULT;
3152 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3153 break;
3154 r = 0;
3155 break;
3156 }
3157 case KVM_SET_VCPU_EVENTS: {
3158 struct kvm_vcpu_events events;
3159
3160 r = -EFAULT;
3161 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3162 break;
3163
3164 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3165 break;
3166 }
a1efbe77
JK		 3167 case KVM_GET_DEBUGREGS: {
3168 struct kvm_debugregs dbgregs;
3169
3170 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3171
3172 r = -EFAULT;
3173 if (copy_to_user(argp, &dbgregs,
3174 sizeof(struct kvm_debugregs)))
3175 break;
3176 r = 0;
3177 break;
3178 }
3179 case KVM_SET_DEBUGREGS: {
3180 struct kvm_debugregs dbgregs;
3181
3182 r = -EFAULT;
3183 if (copy_from_user(&dbgregs, argp,
3184 sizeof(struct kvm_debugregs)))
3185 break;
3186
3187 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3188 break;
3189 }
2d5b5a66 3190 case KVM_GET_XSAVE: {
d1ac91d8 3191 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3192 r = -ENOMEM;
d1ac91d8 3193 if (!u.xsave)
2d5b5a66
SY		 3194 break;
3195
d1ac91d8 3196 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3197
3198 r = -EFAULT;
d1ac91d8 3199 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3200 break;
3201 r = 0;
3202 break;
3203 }
3204 case KVM_SET_XSAVE: {
d1ac91d8 3205 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3206 r = -ENOMEM;
d1ac91d8 3207 if (!u.xsave)
2d5b5a66
SY		 3208 break;
3209
3210 r = -EFAULT;
d1ac91d8 3211 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3212 break;
3213
d1ac91d8 3214 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3215 break;
3216 }
3217 case KVM_GET_XCRS: {
d1ac91d8 3218 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3219 r = -ENOMEM;
d1ac91d8 3220 if (!u.xcrs)
2d5b5a66
SY		 3221 break;
3222
d1ac91d8 3223 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3224
3225 r = -EFAULT;
d1ac91d8 3226 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3227 sizeof(struct kvm_xcrs)))
3228 break;
3229 r = 0;
3230 break;
3231 }
3232 case KVM_SET_XCRS: {
d1ac91d8 3233 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3234 r = -ENOMEM;
d1ac91d8 3235 if (!u.xcrs)
2d5b5a66
SY		 3236 break;
3237
3238 r = -EFAULT;
d1ac91d8 3239 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3240 sizeof(struct kvm_xcrs)))
3241 break;
3242
d1ac91d8 3243 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3244 break;
3245 }
92a1f12d
JR		 3246 case KVM_SET_TSC_KHZ: {
3247 u32 user_tsc_khz;
3248
3249 r = -EINVAL;
3250 if (!kvm_has_tsc_control)
3251 break;
3252
3253 user_tsc_khz = (u32)arg;
3254
3255 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3256 goto out;
3257
3258 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
3259
3260 r = 0;
3261 goto out;
3262 }
3263 case KVM_GET_TSC_KHZ: {
3264 r = -EIO;
3265 if (check_tsc_unstable())
3266 goto out;
3267
3268 r = vcpu_tsc_khz(vcpu);
3269
3270 goto out;
3271 }
313a3dc7
CO		 3272 default:
3273 r = -EINVAL;
3274 }
3275out:
d1ac91d8 3276 kfree(u.buffer);
313a3dc7
CO		 3277 return r;
3278}
3279
1fe779f8
CO		 3280static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3281{
3282 int ret;
3283
3284 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3285 return -1;
3286 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3287 return ret;
3288}
3289
b927a3ce
SY		 3290static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3291 u64 ident_addr)
3292{
3293 kvm->arch.ept_identity_map_addr = ident_addr;
3294 return 0;
3295}
3296
1fe779f8
CO		 3297static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3298 u32 kvm_nr_mmu_pages)
3299{
3300 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3301 return -EINVAL;
3302
79fac95e 3303 mutex_lock(&kvm->slots_lock);
7c8a83b7 3304 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3305
3306 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3307 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3308
7c8a83b7 3309 spin_unlock(&kvm->mmu_lock);
79fac95e 3310 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3311 return 0;
3312}
3313
3314static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3315{
39de71ec 3316 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3317}
3318
1fe779f8
CO		 3319static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3320{
3321 int r;
3322
3323 r = 0;
3324 switch (chip->chip_id) {
3325 case KVM_IRQCHIP_PIC_MASTER:
3326 memcpy(&chip->chip.pic,
3327 &pic_irqchip(kvm)->pics[0],
3328 sizeof(struct kvm_pic_state));
3329 break;
3330 case KVM_IRQCHIP_PIC_SLAVE:
3331 memcpy(&chip->chip.pic,
3332 &pic_irqchip(kvm)->pics[1],
3333 sizeof(struct kvm_pic_state));
3334 break;
3335 case KVM_IRQCHIP_IOAPIC:
eba0226b 3336 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3337 break;
3338 default:
3339 r = -EINVAL;
3340 break;
3341 }
3342 return r;
3343}
3344
3345static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3346{
3347 int r;
3348
3349 r = 0;
3350 switch (chip->chip_id) {
3351 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3352 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3353 memcpy(&pic_irqchip(kvm)->pics[0],
3354 &chip->chip.pic,
3355 sizeof(struct kvm_pic_state));
f4f51050 3356 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3357 break;
3358 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3359 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3360 memcpy(&pic_irqchip(kvm)->pics[1],
3361 &chip->chip.pic,
3362 sizeof(struct kvm_pic_state));
f4f51050 3363 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3364 break;
3365 case KVM_IRQCHIP_IOAPIC:
eba0226b 3366 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3367 break;
3368 default:
3369 r = -EINVAL;
3370 break;
3371 }
3372 kvm_pic_update_irq(pic_irqchip(kvm));
3373 return r;
3374}
3375
e0f63cb9
SY		 3376static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3377{
3378 int r = 0;
3379
894a9c55 3380 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3381 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3382 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3383 return r;
3384}
3385
3386static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3387{
3388 int r = 0;
3389
894a9c55 3390 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3391 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3392 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3393 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3394 return r;
3395}
3396
3397static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3398{
3399 int r = 0;
3400
3401 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3402 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3403 sizeof(ps->channels));
3404 ps->flags = kvm->arch.vpit->pit_state.flags;
3405 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3406 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3407 return r;
3408}
3409
3410static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3411{
3412 int r = 0, start = 0;
3413 u32 prev_legacy, cur_legacy;
3414 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3415 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3416 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3417 if (!prev_legacy && cur_legacy)
3418 start = 1;
3419 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3420 sizeof(kvm->arch.vpit->pit_state.channels));
3421 kvm->arch.vpit->pit_state.flags = ps->flags;
3422 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3423 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3424 return r;
3425}
3426
52d939a0
MT		 3427static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3428 struct kvm_reinject_control *control)
3429{
3430 if (!kvm->arch.vpit)
3431 return -ENXIO;
894a9c55 3432 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3433 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3434 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3435 return 0;
3436}
3437
5bb064dc
ZX		 3438/*
3439 * Get (and clear) the dirty memory log for a memory slot.
3440 */
3441int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3442 struct kvm_dirty_log *log)
3443{
87bf6e7d 3444 int r, i;
5bb064dc 3445 struct kvm_memory_slot *memslot;
87bf6e7d 3446 unsigned long n;
b050b015 3447 unsigned long is_dirty = 0;
5bb064dc 3448
79fac95e 3449 mutex_lock(&kvm->slots_lock);
5bb064dc 3450
b050b015
MT		 3451 r = -EINVAL;
3452 if (log->slot >= KVM_MEMORY_SLOTS)
3453 goto out;
3454
3455 memslot = &kvm->memslots->memslots[log->slot];
3456 r = -ENOENT;
3457 if (!memslot->dirty_bitmap)
3458 goto out;
3459
87bf6e7d 3460 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3461
b050b015
MT		 3462 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3463 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3464
3465 /* If nothing is dirty, don't bother messing with page tables. */
3466 if (is_dirty) {
b050b015 3467 struct kvm_memslots *slots, *old_slots;
914ebccd 3468 unsigned long *dirty_bitmap;
b050b015 3469
515a0127
TY		 3470 dirty_bitmap = memslot->dirty_bitmap_head;
3471 if (memslot->dirty_bitmap == dirty_bitmap)
3472 dirty_bitmap += n / sizeof(long);
914ebccd 3473 memset(dirty_bitmap, 0, n);
b050b015 3474
914ebccd
TY		 3475 r = -ENOMEM;
3476 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3477 if (!slots)
914ebccd 3478 goto out;
b050b015
MT		 3479 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3480 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3481 slots->generation++;
b050b015
MT		 3482
3483 old_slots = kvm->memslots;
3484 rcu_assign_pointer(kvm->memslots, slots);
3485 synchronize_srcu_expedited(&kvm->srcu);
3486 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3487 kfree(old_slots);
914ebccd 3488
edde99ce
MT		 3489 spin_lock(&kvm->mmu_lock);
3490 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3491 spin_unlock(&kvm->mmu_lock);
3492
914ebccd 3493 r = -EFAULT;
515a0127 3494 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3495 goto out;
914ebccd
TY		 3496 } else {
3497 r = -EFAULT;
3498 if (clear_user(log->dirty_bitmap, n))
3499 goto out;
5bb064dc 3500 }
b050b015 3501
5bb064dc
ZX		 3502 r = 0;
3503out:
79fac95e 3504 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3505 return r;
3506}
3507
1fe779f8
CO		 3508long kvm_arch_vm_ioctl(struct file *filp,
3509 unsigned int ioctl, unsigned long arg)
3510{
3511 struct kvm *kvm = filp->private_data;
3512 void __user *argp = (void __user *)arg;
367e1319 3513 int r = -ENOTTY;
f0d66275
DH		 3514 /*
3515 * This union makes it completely explicit to gcc-3.x
3516 * that these two variables' stack usage should be
3517 * combined, not added together.
3518 */
3519 union {
3520 struct kvm_pit_state ps;
e9f42757 3521 struct kvm_pit_state2 ps2;
c5ff41ce 3522 struct kvm_pit_config pit_config;
f0d66275 3523 } u;
1fe779f8
CO		 3524
3525 switch (ioctl) {
3526 case KVM_SET_TSS_ADDR:
3527 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3528 if (r < 0)
3529 goto out;
3530 break;
b927a3ce
SY		 3531 case KVM_SET_IDENTITY_MAP_ADDR: {
3532 u64 ident_addr;
3533
3534 r = -EFAULT;
3535 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3536 goto out;
3537 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3538 if (r < 0)
3539 goto out;
3540 break;
3541 }
1fe779f8
CO		 3542 case KVM_SET_NR_MMU_PAGES:
3543 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3544 if (r)
3545 goto out;
3546 break;
3547 case KVM_GET_NR_MMU_PAGES:
3548 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3549 break;
3ddea128
MT		 3550 case KVM_CREATE_IRQCHIP: {
3551 struct kvm_pic *vpic;
3552
3553 mutex_lock(&kvm->lock);
3554 r = -EEXIST;
3555 if (kvm->arch.vpic)
3556 goto create_irqchip_unlock;
1fe779f8 3557 r = -ENOMEM;
3ddea128
MT		 3558 vpic = kvm_create_pic(kvm);
3559 if (vpic) {
1fe779f8
CO		 3560 r = kvm_ioapic_init(kvm);
3561 if (r) {
175504cd 3562 mutex_lock(&kvm->slots_lock);
72bb2fcd
WY		 3563 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3564 &vpic->dev);
175504cd 3565 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3566 kfree(vpic);
3567 goto create_irqchip_unlock;
1fe779f8
CO		 3568 }
3569 } else
3ddea128
MT		 3570 goto create_irqchip_unlock;
3571 smp_wmb();
3572 kvm->arch.vpic = vpic;
3573 smp_wmb();
399ec807
AK		 3574 r = kvm_setup_default_irq_routing(kvm);
3575 if (r) {
175504cd 3576 mutex_lock(&kvm->slots_lock);
3ddea128 3577 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3578 kvm_ioapic_destroy(kvm);
3579 kvm_destroy_pic(kvm);
3ddea128 3580 mutex_unlock(&kvm->irq_lock);
175504cd 3581 mutex_unlock(&kvm->slots_lock);
399ec807 3582 }
3ddea128
MT		 3583 create_irqchip_unlock:
3584 mutex_unlock(&kvm->lock);
1fe779f8 3585 break;
3ddea128 3586 }
7837699f 3587 case KVM_CREATE_PIT:
c5ff41ce
JK		 3588 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3589 goto create_pit;
3590 case KVM_CREATE_PIT2:
3591 r = -EFAULT;
3592 if (copy_from_user(&u.pit_config, argp,
3593 sizeof(struct kvm_pit_config)))
3594 goto out;
3595 create_pit:
79fac95e 3596 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3597 r = -EEXIST;
3598 if (kvm->arch.vpit)
3599 goto create_pit_unlock;
7837699f 3600 r = -ENOMEM;
c5ff41ce 3601 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3602 if (kvm->arch.vpit)
3603 r = 0;
269e05e4 3604 create_pit_unlock:
79fac95e 3605 mutex_unlock(&kvm->slots_lock);
7837699f 3606 break;
4925663a 3607 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3608 case KVM_IRQ_LINE: {
3609 struct kvm_irq_level irq_event;
3610
3611 r = -EFAULT;
3612 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3613 goto out;
160d2f6c 3614 r = -ENXIO;
1fe779f8 3615 if (irqchip_in_kernel(kvm)) {
4925663a 3616 __s32 status;
4925663a
GN		 3617 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3618 irq_event.irq, irq_event.level);
4925663a 3619 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3620 r = -EFAULT;
4925663a
GN		 3621 irq_event.status = status;
3622 if (copy_to_user(argp, &irq_event,
3623 sizeof irq_event))
3624 goto out;
3625 }
1fe779f8
CO		 3626 r = 0;
3627 }
3628 break;
3629 }
3630 case KVM_GET_IRQCHIP: {
3631 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3632 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3633
f0d66275
DH		 3634 r = -ENOMEM;
3635 if (!chip)
1fe779f8 3636 goto out;
f0d66275
DH		 3637 r = -EFAULT;
3638 if (copy_from_user(chip, argp, sizeof *chip))
3639 goto get_irqchip_out;
1fe779f8
CO		 3640 r = -ENXIO;
3641 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3642 goto get_irqchip_out;
3643 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3644 if (r)
f0d66275 3645 goto get_irqchip_out;
1fe779f8 3646 r = -EFAULT;
f0d66275
DH		 3647 if (copy_to_user(argp, chip, sizeof *chip))
3648 goto get_irqchip_out;
1fe779f8 3649 r = 0;
f0d66275
DH		 3650 get_irqchip_out:
3651 kfree(chip);
3652 if (r)
3653 goto out;
1fe779f8
CO		 3654 break;
3655 }
3656 case KVM_SET_IRQCHIP: {
3657 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3658 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3659
f0d66275
DH		 3660 r = -ENOMEM;
3661 if (!chip)
1fe779f8 3662 goto out;
f0d66275
DH		 3663 r = -EFAULT;
3664 if (copy_from_user(chip, argp, sizeof *chip))
3665 goto set_irqchip_out;
1fe779f8
CO		 3666 r = -ENXIO;
3667 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3668 goto set_irqchip_out;
3669 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3670 if (r)
f0d66275 3671 goto set_irqchip_out;
1fe779f8 3672 r = 0;
f0d66275
DH		 3673 set_irqchip_out:
3674 kfree(chip);
3675 if (r)
3676 goto out;
1fe779f8
CO		 3677 break;
3678 }
e0f63cb9 3679 case KVM_GET_PIT: {
e0f63cb9 3680 r = -EFAULT;
f0d66275 3681 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3682 goto out;
3683 r = -ENXIO;
3684 if (!kvm->arch.vpit)
3685 goto out;
f0d66275 3686 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3687 if (r)
3688 goto out;
3689 r = -EFAULT;
f0d66275 3690 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3691 goto out;
3692 r = 0;
3693 break;
3694 }
3695 case KVM_SET_PIT: {
e0f63cb9 3696 r = -EFAULT;
f0d66275 3697 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3698 goto out;
3699 r = -ENXIO;
3700 if (!kvm->arch.vpit)
3701 goto out;
f0d66275 3702 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3703 if (r)
3704 goto out;
3705 r = 0;
3706 break;
3707 }
e9f42757
BK		 3708 case KVM_GET_PIT2: {
3709 r = -ENXIO;
3710 if (!kvm->arch.vpit)
3711 goto out;
3712 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3713 if (r)
3714 goto out;
3715 r = -EFAULT;
3716 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3717 goto out;
3718 r = 0;
3719 break;
3720 }
3721 case KVM_SET_PIT2: {
3722 r = -EFAULT;
3723 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3724 goto out;
3725 r = -ENXIO;
3726 if (!kvm->arch.vpit)
3727 goto out;
3728 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3729 if (r)
3730 goto out;
3731 r = 0;
3732 break;
3733 }
52d939a0
MT		 3734 case KVM_REINJECT_CONTROL: {
3735 struct kvm_reinject_control control;
3736 r = -EFAULT;
3737 if (copy_from_user(&control, argp, sizeof(control)))
3738 goto out;
3739 r = kvm_vm_ioctl_reinject(kvm, &control);
3740 if (r)
3741 goto out;
3742 r = 0;
3743 break;
3744 }
ffde22ac
ES		 3745 case KVM_XEN_HVM_CONFIG: {
3746 r = -EFAULT;
3747 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3748 sizeof(struct kvm_xen_hvm_config)))
3749 goto out;
3750 r = -EINVAL;
3751 if (kvm->arch.xen_hvm_config.flags)
3752 goto out;
3753 r = 0;
3754 break;
3755 }
afbcf7ab 3756 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3757 struct kvm_clock_data user_ns;
3758 u64 now_ns;
3759 s64 delta;
3760
3761 r = -EFAULT;
3762 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3763 goto out;
3764
3765 r = -EINVAL;
3766 if (user_ns.flags)
3767 goto out;
3768
3769 r = 0;
395c6b0a 3770 local_irq_disable();
759379dd 3771 now_ns = get_kernel_ns();
afbcf7ab 3772 delta = user_ns.clock - now_ns;
395c6b0a 3773 local_irq_enable();
afbcf7ab
GC		 3774 kvm->arch.kvmclock_offset = delta;
3775 break;
3776 }
3777 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3778 struct kvm_clock_data user_ns;
3779 u64 now_ns;
3780
395c6b0a 3781 local_irq_disable();
759379dd 3782 now_ns = get_kernel_ns();
afbcf7ab 3783 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3784 local_irq_enable();
afbcf7ab 3785 user_ns.flags = 0;
97e69aa6 3786 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3787
3788 r = -EFAULT;
3789 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3790 goto out;
3791 r = 0;
3792 break;
3793 }
3794
1fe779f8
CO		 3795 default:
3796 ;
3797 }
3798out:
3799 return r;
3800}
3801
a16b043c 3802static void kvm_init_msr_list(void)
043405e1
CO		 3803{
3804 u32 dummy[2];
3805 unsigned i, j;
3806
e3267cbb
GC		 3807 /* skip the first msrs in the list. KVM-specific */
3808 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3809 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3810 continue;
3811 if (j < i)
3812 msrs_to_save[j] = msrs_to_save[i];
3813 j++;
3814 }
3815 num_msrs_to_save = j;
3816}
3817
bda9020e
MT		 3818static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3819 const void *v)
bbd9b64e 3820{
70252a10
AK		 3821 int handled = 0;
3822 int n;
3823
3824 do {
3825 n = min(len, 8);
3826 if (!(vcpu->arch.apic &&
3827 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3828 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3829 break;
3830 handled += n;
3831 addr += n;
3832 len -= n;
3833 v += n;
3834 } while (len);
bbd9b64e 3835
70252a10 3836 return handled;
bbd9b64e
CO		 3837}
3838
bda9020e 3839static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3840{
70252a10
AK		 3841 int handled = 0;
3842 int n;
3843
3844 do {
3845 n = min(len, 8);
3846 if (!(vcpu->arch.apic &&
3847 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3848 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3849 break;
3850 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3851 handled += n;
3852 addr += n;
3853 len -= n;
3854 v += n;
3855 } while (len);
bbd9b64e 3856
70252a10 3857 return handled;
bbd9b64e
CO		 3858}
3859
2dafc6c2
GN		 3860static void kvm_set_segment(struct kvm_vcpu *vcpu,
3861 struct kvm_segment *var, int seg)
3862{
3863 kvm_x86_ops->set_segment(vcpu, var, seg);
3864}
3865
3866void kvm_get_segment(struct kvm_vcpu *vcpu,
3867 struct kvm_segment *var, int seg)
3868{
3869 kvm_x86_ops->get_segment(vcpu, var, seg);
3870}
3871
c30a358d
JR		 3872static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3873{
3874 return gpa;
3875}
3876
02f59dc9
JR		 3877static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3878{
3879 gpa_t t_gpa;
ab9ae313 3880 struct x86_exception exception;
02f59dc9
JR		 3881
3882 BUG_ON(!mmu_is_nested(vcpu));
3883
3884 /* NPT walks are always user-walks */
3885 access |= PFERR_USER_MASK;
ab9ae313 3886 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3887
3888 return t_gpa;
3889}
3890
ab9ae313
AK		 3891gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3892 struct x86_exception *exception)
1871c602
GN		 3893{
3894 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3895 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3896}
3897
ab9ae313
AK		 3898 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3899 struct x86_exception *exception)
1871c602
GN		 3900{
3901 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3902 access |= PFERR_FETCH_MASK;
ab9ae313 3903 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3904}
3905
ab9ae313
AK		 3906gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3907 struct x86_exception *exception)
1871c602
GN		 3908{
3909 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3910 access |= PFERR_WRITE_MASK;
ab9ae313 3911 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3912}
3913
3914/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3915gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3916 struct x86_exception *exception)
1871c602 3917{
ab9ae313 3918 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3919}
3920
3921static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3922 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3923 struct x86_exception *exception)
bbd9b64e
CO		 3924{
3925 void *data = val;
10589a46 3926 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3927
3928 while (bytes) {
14dfe855 3929 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3930 exception);
bbd9b64e 3931 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3932 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3933 int ret;
3934
bcc55cba 3935 if (gpa == UNMAPPED_GVA)
ab9ae313 3936 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3937 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3938 if (ret < 0) {
c3cd7ffa 3939 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3940 goto out;
3941 }
bbd9b64e 3942
77c2002e
IE		 3943 bytes -= toread;
3944 data += toread;
3945 addr += toread;
bbd9b64e 3946 }
10589a46 3947out:
10589a46 3948 return r;
bbd9b64e 3949}
77c2002e 3950
1871c602 3951/* used for instruction fetching */
0f65dd70
AK		 3952static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3953 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3954 struct x86_exception *exception)
1871c602 3955{
0f65dd70 3956 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3957 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3958
1871c602 3959 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3960 access | PFERR_FETCH_MASK,
3961 exception);
1871c602
GN		 3962}
3963
064aea77 3964int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3965 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3966 struct x86_exception *exception)
1871c602 3967{
0f65dd70 3968 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3969 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3970
1871c602 3971 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3972 exception);
1871c602 3973}
064aea77 3974EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3975
0f65dd70
AK		 3976static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3977 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3978 struct x86_exception *exception)
1871c602 3979{
0f65dd70 3980 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3981 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3982}
3983
6a4d7550 3984int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3985 gva_t addr, void *val,
2dafc6c2 3986 unsigned int bytes,
bcc55cba 3987 struct x86_exception *exception)
77c2002e 3988{
0f65dd70 3989 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3990 void *data = val;
3991 int r = X86EMUL_CONTINUE;
3992
3993 while (bytes) {
14dfe855
JR		 3994 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3995 PFERR_WRITE_MASK,
ab9ae313 3996 exception);
77c2002e
IE		 3997 unsigned offset = addr & (PAGE_SIZE-1);
3998 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3999 int ret;
4000
bcc55cba 4001 if (gpa == UNMAPPED_GVA)
ab9ae313 4002 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4003 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4004 if (ret < 0) {
c3cd7ffa 4005 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4006 goto out;
4007 }
4008
4009 bytes -= towrite;
4010 data += towrite;
4011 addr += towrite;
4012 }
4013out:
4014 return r;
4015}
6a4d7550 4016EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4017
af7cc7d1
XG		 4018static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4019 gpa_t *gpa, struct x86_exception *exception,
4020 bool write)
4021{
4022 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4023
bebb106a
XG		 4024 if (vcpu_match_mmio_gva(vcpu, gva) &&
4025 check_write_user_access(vcpu, write, access,
4026 vcpu->arch.access)) {
4027 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4028 (gva & (PAGE_SIZE - 1));
4f022648 4029 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4030 return 1;
4031 }
4032
af7cc7d1
XG		 4033 if (write)
4034 access |= PFERR_WRITE_MASK;
4035
4036 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4037
4038 if (*gpa == UNMAPPED_GVA)
4039 return -1;
4040
4041 /* For APIC access vmexit */
4042 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4043 return 1;
4044
4f022648
XG		 4045 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4046 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4047 return 1;
4f022648 4048 }
bebb106a 4049
af7cc7d1
XG		 4050 return 0;
4051}
4052
3200f405 4053int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4054 const void *val, int bytes)
bbd9b64e
CO		 4055{
4056 int ret;
4057
4058 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4059 if (ret < 0)
bbd9b64e 4060 return 0;
ad218f85 4061 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 4062 return 1;
4063}
4064
77d197b2
XG		 4065struct read_write_emulator_ops {
4066 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4067 int bytes);
4068 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4069 void *val, int bytes);
4070 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4071 int bytes, void *val);
4072 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4073 void *val, int bytes);
4074 bool write;
4075};
4076
4077static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4078{
4079 if (vcpu->mmio_read_completed) {
4080 memcpy(val, vcpu->mmio_data, bytes);
4081 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4082 vcpu->mmio_phys_addr, *(u64 *)val);
4083 vcpu->mmio_read_completed = 0;
4084 return 1;
4085 }
4086
4087 return 0;
4088}
4089
4090static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4091 void *val, int bytes)
4092{
4093 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4094}
4095
4096static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4097 void *val, int bytes)
4098{
4099 return emulator_write_phys(vcpu, gpa, val, bytes);
4100}
4101
4102static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4103{
4104 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4105 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4106}
4107
4108static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4109 void *val, int bytes)
4110{
4111 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4112 return X86EMUL_IO_NEEDED;
4113}
4114
4115static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4116 void *val, int bytes)
4117{
4118 memcpy(vcpu->mmio_data, val, bytes);
4119 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
4120 return X86EMUL_CONTINUE;
4121}
4122
4123static struct read_write_emulator_ops read_emultor = {
4124 .read_write_prepare = read_prepare,
4125 .read_write_emulate = read_emulate,
4126 .read_write_mmio = vcpu_mmio_read,
4127 .read_write_exit_mmio = read_exit_mmio,
4128};
4129
4130static struct read_write_emulator_ops write_emultor = {
4131 .read_write_emulate = write_emulate,
4132 .read_write_mmio = write_mmio,
4133 .read_write_exit_mmio = write_exit_mmio,
4134 .write = true,
4135};
4136
22388a3c
XG		 4137static int emulator_read_write_onepage(unsigned long addr, void *val,
4138 unsigned int bytes,
4139 struct x86_exception *exception,
4140 struct kvm_vcpu *vcpu,
4141 struct read_write_emulator_ops *ops)
bbd9b64e 4142{
af7cc7d1
XG		 4143 gpa_t gpa;
4144 int handled, ret;
22388a3c
XG		 4145 bool write = ops->write;
4146
4147 if (ops->read_write_prepare &&
4148 ops->read_write_prepare(vcpu, val, bytes))
4149 return X86EMUL_CONTINUE;
10589a46 4150
22388a3c 4151 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4152
af7cc7d1 4153 if (ret < 0)
bbd9b64e 4154 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4155
4156 /* For APIC access vmexit */
af7cc7d1 4157 if (ret)
bbd9b64e
CO		 4158 goto mmio;
4159
22388a3c 4160 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4161 return X86EMUL_CONTINUE;
4162
4163mmio:
4164 /*
4165 * Is this MMIO handled locally?
4166 */
22388a3c 4167 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4168 if (handled == bytes)
bbd9b64e 4169 return X86EMUL_CONTINUE;
bbd9b64e 4170
70252a10
AK		 4171 gpa += handled;
4172 bytes -= handled;
4173 val += handled;
4174
bbd9b64e 4175 vcpu->mmio_needed = 1;
411c35b7
GN		 4176 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4177 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 4178 vcpu->mmio_size = bytes;
4179 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
22388a3c 4180 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
cef4dea0 4181 vcpu->mmio_index = 0;
bbd9b64e 4182
22388a3c 4183 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4184}
4185
22388a3c
XG		 4186int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4187 void *val, unsigned int bytes,
4188 struct x86_exception *exception,
4189 struct read_write_emulator_ops *ops)
bbd9b64e 4190{
0f65dd70
AK		 4191 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4192
bbd9b64e
CO		 4193 /* Crossing a page boundary? */
4194 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4195 int rc, now;
4196
4197 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4198 rc = emulator_read_write_onepage(addr, val, now, exception,
4199 vcpu, ops);
4200
bbd9b64e
CO		 4201 if (rc != X86EMUL_CONTINUE)
4202 return rc;
4203 addr += now;
4204 val += now;
4205 bytes -= now;
4206 }
22388a3c
XG		 4207
4208 return emulator_read_write_onepage(addr, val, bytes, exception,
4209 vcpu, ops);
4210}
4211
4212static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4213 unsigned long addr,
4214 void *val,
4215 unsigned int bytes,
4216 struct x86_exception *exception)
4217{
4218 return emulator_read_write(ctxt, addr, val, bytes,
4219 exception, &read_emultor);
4220}
4221
4222int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4223 unsigned long addr,
4224 const void *val,
4225 unsigned int bytes,
4226 struct x86_exception *exception)
4227{
4228 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4229 exception, &write_emultor);
bbd9b64e 4230}
bbd9b64e 4231
daea3e73
AK		 4232#define CMPXCHG_TYPE(t, ptr, old, new) \
4233 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4234
4235#ifdef CONFIG_X86_64
4236# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4237#else
4238# define CMPXCHG64(ptr, old, new) \
9749a6c0 4239 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4240#endif
4241
0f65dd70
AK		 4242static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4243 unsigned long addr,
bbd9b64e
CO		 4244 const void *old,
4245 const void *new,
4246 unsigned int bytes,
0f65dd70 4247 struct x86_exception *exception)
bbd9b64e 4248{
0f65dd70 4249 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4250 gpa_t gpa;
4251 struct page *page;
4252 char *kaddr;
4253 bool exchanged;
2bacc55c 4254
daea3e73
AK		 4255 /* guests cmpxchg8b have to be emulated atomically */
4256 if (bytes > 8 || (bytes & (bytes - 1)))
4257 goto emul_write;
10589a46 4258
daea3e73 4259 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4260
daea3e73
AK		 4261 if (gpa == UNMAPPED_GVA ||
4262 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4263 goto emul_write;
2bacc55c 4264
daea3e73
AK		 4265 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4266 goto emul_write;
72dc67a6 4267
daea3e73 4268 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 4269 if (is_error_page(page)) {
4270 kvm_release_page_clean(page);
4271 goto emul_write;
4272 }
72dc67a6 4273
daea3e73
AK		 4274 kaddr = kmap_atomic(page, KM_USER0);
4275 kaddr += offset_in_page(gpa);
4276 switch (bytes) {
4277 case 1:
4278 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4279 break;
4280 case 2:
4281 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4282 break;
4283 case 4:
4284 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4285 break;
4286 case 8:
4287 exchanged = CMPXCHG64(kaddr, old, new);
4288 break;
4289 default:
4290 BUG();
2bacc55c 4291 }
daea3e73
AK		 4292 kunmap_atomic(kaddr, KM_USER0);
4293 kvm_release_page_dirty(page);
4294
4295 if (!exchanged)
4296 return X86EMUL_CMPXCHG_FAILED;
4297
8f6abd06
GN		 4298 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
4299
4300 return X86EMUL_CONTINUE;
4a5f48f6 4301
3200f405 4302emul_write:
daea3e73 4303 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4304
0f65dd70 4305 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4306}
4307
cf8f70bf
GN		 4308static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4309{
4310 /* TODO: String I/O for in kernel device */
4311 int r;
4312
4313 if (vcpu->arch.pio.in)
4314 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4315 vcpu->arch.pio.size, pd);
4316 else
4317 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4318 vcpu->arch.pio.port, vcpu->arch.pio.size,
4319 pd);
4320 return r;
4321}
4322
4323
ca1d4a9e
AK		 4324static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4325 int size, unsigned short port, void *val,
4326 unsigned int count)
cf8f70bf 4327{
ca1d4a9e
AK		 4328 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4329
7972995b 4330 if (vcpu->arch.pio.count)
cf8f70bf
GN		 4331 goto data_avail;
4332
61cfab2e 4333 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 4334
4335 vcpu->arch.pio.port = port;
4336 vcpu->arch.pio.in = 1;
7972995b 4337 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4338 vcpu->arch.pio.size = size;
4339
4340 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4341 data_avail:
4342 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4343 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4344 return 1;
4345 }
4346
4347 vcpu->run->exit_reason = KVM_EXIT_IO;
4348 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4349 vcpu->run->io.size = size;
4350 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4351 vcpu->run->io.count = count;
4352 vcpu->run->io.port = port;
4353
4354 return 0;
4355}
4356
ca1d4a9e
AK		 4357static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4358 int size, unsigned short port,
4359 const void *val, unsigned int count)
cf8f70bf 4360{
ca1d4a9e
AK		 4361 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4362
61cfab2e 4363 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 4364
4365 vcpu->arch.pio.port = port;
4366 vcpu->arch.pio.in = 0;
7972995b 4367 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4368 vcpu->arch.pio.size = size;
4369
4370 memcpy(vcpu->arch.pio_data, val, size * count);
4371
4372 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4373 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4374 return 1;
4375 }
4376
4377 vcpu->run->exit_reason = KVM_EXIT_IO;
4378 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4379 vcpu->run->io.size = size;
4380 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4381 vcpu->run->io.count = count;
4382 vcpu->run->io.port = port;
4383
4384 return 0;
4385}
4386
bbd9b64e
CO		 4387static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4388{
4389 return kvm_x86_ops->get_segment_base(vcpu, seg);
4390}
4391
3cb16fe7 4392static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4393{
3cb16fe7 4394 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4395}
4396
f5f48ee1
SY		 4397int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4398{
4399 if (!need_emulate_wbinvd(vcpu))
4400 return X86EMUL_CONTINUE;
4401
4402 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4403 int cpu = get_cpu();
4404
4405 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4406 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4407 wbinvd_ipi, NULL, 1);
2eec7343 4408 put_cpu();
f5f48ee1 4409 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4410 } else
4411 wbinvd();
f5f48ee1
SY		 4412 return X86EMUL_CONTINUE;
4413}
4414EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4415
bcaf5cc5
AK		 4416static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4417{
4418 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4419}
4420
717746e3 4421int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4422{
717746e3 4423 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4424}
4425
717746e3 4426int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4427{
338dbc97 4428
717746e3 4429 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4430}
4431
52a46617 4432static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4433{
52a46617 4434 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4435}
4436
717746e3 4437static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4438{
717746e3 4439 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4440 unsigned long value;
4441
4442 switch (cr) {
4443 case 0:
4444 value = kvm_read_cr0(vcpu);
4445 break;
4446 case 2:
4447 value = vcpu->arch.cr2;
4448 break;
4449 case 3:
9f8fe504 4450 value = kvm_read_cr3(vcpu);
52a46617
GN		 4451 break;
4452 case 4:
4453 value = kvm_read_cr4(vcpu);
4454 break;
4455 case 8:
4456 value = kvm_get_cr8(vcpu);
4457 break;
4458 default:
4459 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4460 return 0;
4461 }
4462
4463 return value;
4464}
4465
717746e3 4466static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4467{
717746e3 4468 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4469 int res = 0;
4470
52a46617
GN		 4471 switch (cr) {
4472 case 0:
49a9b07e 4473 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4474 break;
4475 case 2:
4476 vcpu->arch.cr2 = val;
4477 break;
4478 case 3:
2390218b 4479 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4480 break;
4481 case 4:
a83b29c6 4482 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4483 break;
4484 case 8:
eea1cff9 4485 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4486 break;
4487 default:
4488 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4489 res = -1;
52a46617 4490 }
0f12244f
GN		 4491
4492 return res;
52a46617
GN		 4493}
4494
717746e3 4495static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4496{
717746e3 4497 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4498}
4499
4bff1e86 4500static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4501{
4bff1e86 4502 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4503}
4504
4bff1e86 4505static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4506{
4bff1e86 4507 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4508}
4509
1ac9d0cf
AK		 4510static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4511{
4512 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4513}
4514
4515static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4516{
4517 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4518}
4519
4bff1e86
AK		 4520static unsigned long emulator_get_cached_segment_base(
4521 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4522{
4bff1e86 4523 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4524}
4525
1aa36616
AK		 4526static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4527 struct desc_struct *desc, u32 *base3,
4528 int seg)
2dafc6c2
GN		 4529{
4530 struct kvm_segment var;
4531
4bff1e86 4532 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4533 *selector = var.selector;
2dafc6c2
GN		 4534
4535 if (var.unusable)
4536 return false;
4537
4538 if (var.g)
4539 var.limit >>= 12;
4540 set_desc_limit(desc, var.limit);
4541 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4542#ifdef CONFIG_X86_64
4543 if (base3)
4544 *base3 = var.base >> 32;
4545#endif
2dafc6c2
GN		 4546 desc->type = var.type;
4547 desc->s = var.s;
4548 desc->dpl = var.dpl;
4549 desc->p = var.present;
4550 desc->avl = var.avl;
4551 desc->l = var.l;
4552 desc->d = var.db;
4553 desc->g = var.g;
4554
4555 return true;
4556}
4557
1aa36616
AK		 4558static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4559 struct desc_struct *desc, u32 base3,
4560 int seg)
2dafc6c2 4561{
4bff1e86 4562 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4563 struct kvm_segment var;
4564
1aa36616 4565 var.selector = selector;
2dafc6c2 4566 var.base = get_desc_base(desc);
5601d05b
GN		 4567#ifdef CONFIG_X86_64
4568 var.base |= ((u64)base3) << 32;
4569#endif
2dafc6c2
GN		 4570 var.limit = get_desc_limit(desc);
4571 if (desc->g)
4572 var.limit = (var.limit << 12) | 0xfff;
4573 var.type = desc->type;
4574 var.present = desc->p;
4575 var.dpl = desc->dpl;
4576 var.db = desc->d;
4577 var.s = desc->s;
4578 var.l = desc->l;
4579 var.g = desc->g;
4580 var.avl = desc->avl;
4581 var.present = desc->p;
4582 var.unusable = !var.present;
4583 var.padding = 0;
4584
4585 kvm_set_segment(vcpu, &var, seg);
4586 return;
4587}
4588
717746e3
AK		 4589static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4590 u32 msr_index, u64 *pdata)
4591{
4592 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4593}
4594
4595static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4596 u32 msr_index, u64 data)
4597{
4598 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4599}
4600
6c3287f7
AK		 4601static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4602{
4603 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4604}
4605
5037f6f3
AK		 4606static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4607{
4608 preempt_disable();
5197b808 4609 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4610 /*
4611 * CR0.TS may reference the host fpu state, not the guest fpu state,
4612 * so it may be clear at this point.
4613 */
4614 clts();
4615}
4616
4617static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4618{
4619 preempt_enable();
4620}
4621
2953538e 4622static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4623 struct x86_instruction_info *info,
c4f035c6
AK		 4624 enum x86_intercept_stage stage)
4625{
2953538e 4626 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4627}
4628
14af3f3c 4629static struct x86_emulate_ops emulate_ops = {
1871c602 4630 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4631 .write_std = kvm_write_guest_virt_system,
1871c602 4632 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4633 .read_emulated = emulator_read_emulated,
4634 .write_emulated = emulator_write_emulated,
4635 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4636 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4637 .pio_in_emulated = emulator_pio_in_emulated,
4638 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4639 .get_segment = emulator_get_segment,
4640 .set_segment = emulator_set_segment,
5951c442 4641 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4642 .get_gdt = emulator_get_gdt,
160ce1f1 4643 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4644 .set_gdt = emulator_set_gdt,
4645 .set_idt = emulator_set_idt,
52a46617
GN		 4646 .get_cr = emulator_get_cr,
4647 .set_cr = emulator_set_cr,
9c537244 4648 .cpl = emulator_get_cpl,
35aa5375
GN		 4649 .get_dr = emulator_get_dr,
4650 .set_dr = emulator_set_dr,
717746e3
AK		 4651 .set_msr = emulator_set_msr,
4652 .get_msr = emulator_get_msr,
6c3287f7 4653 .halt = emulator_halt,
bcaf5cc5 4654 .wbinvd = emulator_wbinvd,
d6aa1000 4655 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4656 .get_fpu = emulator_get_fpu,
4657 .put_fpu = emulator_put_fpu,
c4f035c6 4658 .intercept = emulator_intercept,
bbd9b64e
CO		 4659};
4660
5fdbf976
MT		 4661static void cache_all_regs(struct kvm_vcpu *vcpu)
4662{
4663 kvm_register_read(vcpu, VCPU_REGS_RAX);
4664 kvm_register_read(vcpu, VCPU_REGS_RSP);
4665 kvm_register_read(vcpu, VCPU_REGS_RIP);
4666 vcpu->arch.regs_dirty = ~0;
4667}
4668
95cb2295
GN		 4669static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4670{
4671 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4672 /*
4673 * an sti; sti; sequence only disable interrupts for the first
4674 * instruction. So, if the last instruction, be it emulated or
4675 * not, left the system with the INT_STI flag enabled, it
4676 * means that the last instruction is an sti. We should not
4677 * leave the flag on in this case. The same goes for mov ss
4678 */
4679 if (!(int_shadow & mask))
4680 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4681}
4682
54b8486f
GN		 4683static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4684{
4685 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4686 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4687 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4688 else if (ctxt->exception.error_code_valid)
4689 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4690 ctxt->exception.error_code);
54b8486f 4691 else
da9cb575 4692 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4693}
4694
9dac77fa 4695static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4696 const unsigned long *regs)
4697{
9dac77fa
AK		 4698 memset(&ctxt->twobyte, 0,
4699 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4700 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4701
9dac77fa
AK		 4702 ctxt->fetch.start = 0;
4703 ctxt->fetch.end = 0;
4704 ctxt->io_read.pos = 0;
4705 ctxt->io_read.end = 0;
4706 ctxt->mem_read.pos = 0;
4707 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4708}
4709
8ec4722d
MG		 4710static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4711{
adf52235 4712 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4713 int cs_db, cs_l;
4714
2aab2c5b
GN		 4715 /*
4716 * TODO: fix emulate.c to use guest_read/write_register
4717 * instead of direct ->regs accesses, can save hundred cycles
4718 * on Intel for instructions that don't read/change RSP, for
4719 * for example.
4720 */
8ec4722d
MG		 4721 cache_all_regs(vcpu);
4722
4723 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4724
adf52235
TY		 4725 ctxt->eflags = kvm_get_rflags(vcpu);
4726 ctxt->eip = kvm_rip_read(vcpu);
4727 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4728 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4729 cs_l ? X86EMUL_MODE_PROT64 :
4730 cs_db ? X86EMUL_MODE_PROT32 :
4731 X86EMUL_MODE_PROT16;
4732 ctxt->guest_mode = is_guest_mode(vcpu);
4733
9dac77fa 4734 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4735 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4736}
4737
71f9833b 4738int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4739{
9d74191a 4740 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4741 int ret;
4742
4743 init_emulate_ctxt(vcpu);
4744
9dac77fa
AK		 4745 ctxt->op_bytes = 2;
4746 ctxt->ad_bytes = 2;
4747 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4748 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4749
4750 if (ret != X86EMUL_CONTINUE)
4751 return EMULATE_FAIL;
4752
9dac77fa
AK		 4753 ctxt->eip = ctxt->_eip;
4754 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4755 kvm_rip_write(vcpu, ctxt->eip);
4756 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4757
4758 if (irq == NMI_VECTOR)
4759 vcpu->arch.nmi_pending = false;
4760 else
4761 vcpu->arch.interrupt.pending = false;
4762
4763 return EMULATE_DONE;
4764}
4765EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4766
6d77dbfc
GN		 4767static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4768{
fc3a9157
JR		 4769 int r = EMULATE_DONE;
4770
6d77dbfc
GN		 4771 ++vcpu->stat.insn_emulation_fail;
4772 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4773 if (!is_guest_mode(vcpu)) {
4774 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4775 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4776 vcpu->run->internal.ndata = 0;
4777 r = EMULATE_FAIL;
4778 }
6d77dbfc 4779 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4780
4781 return r;
6d77dbfc
GN		 4782}
4783
a6f177ef
GN		 4784static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4785{
4786 gpa_t gpa;
4787
68be0803
GN		 4788 if (tdp_enabled)
4789 return false;
4790
a6f177ef
GN		 4791 /*
4792 * if emulation was due to access to shadowed page table
4793 * and it failed try to unshadow page and re-entetr the
4794 * guest to let CPU execute the instruction.
4795 */
4796 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4797 return true;
4798
4799 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4800
4801 if (gpa == UNMAPPED_GVA)
4802 return true; /* let cpu generate fault */
4803
4804 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4805 return true;
4806
4807 return false;
4808}
4809
51d8b661
AP		 4810int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4811 unsigned long cr2,
dc25e89e
AP		 4812 int emulation_type,
4813 void *insn,
4814 int insn_len)
bbd9b64e 4815{
95cb2295 4816 int r;
9d74191a 4817 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4818 bool writeback = true;
bbd9b64e 4819
26eef70c 4820 kvm_clear_exception_queue(vcpu);
8d7d8102 4821
571008da 4822 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4823 init_emulate_ctxt(vcpu);
9d74191a
TY		 4824 ctxt->interruptibility = 0;
4825 ctxt->have_exception = false;
4826 ctxt->perm_ok = false;
bbd9b64e 4827
9d74191a 4828 ctxt->only_vendor_specific_insn
4005996e
AK		 4829 = emulation_type & EMULTYPE_TRAP_UD;
4830
9d74191a 4831 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4832
e46479f8 4833 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4834 ++vcpu->stat.insn_emulation;
bbd9b64e 4835 if (r) {
4005996e
AK		 4836 if (emulation_type & EMULTYPE_TRAP_UD)
4837 return EMULATE_FAIL;
a6f177ef 4838 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4839 return EMULATE_DONE;
6d77dbfc
GN		 4840 if (emulation_type & EMULTYPE_SKIP)
4841 return EMULATE_FAIL;
4842 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4843 }
4844 }
4845
ba8afb6b 4846 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4847 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4848 return EMULATE_DONE;
4849 }
4850
7ae441ea 4851 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4852 changes registers values during IO operation */
7ae441ea
GN		 4853 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4854 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4855 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4856 }
4d2179e1 4857
5cd21917 4858restart:
9d74191a 4859 r = x86_emulate_insn(ctxt);
bbd9b64e 4860
775fde86
JR		 4861 if (r == EMULATION_INTERCEPTED)
4862 return EMULATE_DONE;
4863
d2ddd1c4 4864 if (r == EMULATION_FAILED) {
a6f177ef 4865 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4866 return EMULATE_DONE;
4867
6d77dbfc 4868 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4869 }
4870
9d74191a 4871 if (ctxt->have_exception) {
54b8486f 4872 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4873 r = EMULATE_DONE;
4874 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4875 if (!vcpu->arch.pio.in)
4876 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4877 else
4878 writeback = false;
e85d28f8 4879 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4880 } else if (vcpu->mmio_needed) {
4881 if (!vcpu->mmio_is_write)
4882 writeback = false;
e85d28f8 4883 r = EMULATE_DO_MMIO;
7ae441ea 4884 } else if (r == EMULATION_RESTART)
5cd21917 4885 goto restart;
d2ddd1c4
GN		 4886 else
4887 r = EMULATE_DONE;
f850e2e6 4888
7ae441ea 4889 if (writeback) {
9d74191a
TY		 4890 toggle_interruptibility(vcpu, ctxt->interruptibility);
4891 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4892 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4893 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4894 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4895 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4896 } else
4897 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4898
4899 return r;
de7d789a 4900}
51d8b661 4901EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4902
cf8f70bf 4903int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4904{
cf8f70bf 4905 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4906 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4907 size, port, &val, 1);
cf8f70bf 4908 /* do not return to emulator after return from userspace */
7972995b 4909 vcpu->arch.pio.count = 0;
de7d789a
CO		 4910 return ret;
4911}
cf8f70bf 4912EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4913
8cfdc000
ZA		 4914static void tsc_bad(void *info)
4915{
0a3aee0d 4916 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4917}
4918
4919static void tsc_khz_changed(void *data)
c8076604 4920{
8cfdc000
ZA		 4921 struct cpufreq_freqs *freq = data;
4922 unsigned long khz = 0;
4923
4924 if (data)
4925 khz = freq->new;
4926 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4927 khz = cpufreq_quick_get(raw_smp_processor_id());
4928 if (!khz)
4929 khz = tsc_khz;
0a3aee0d 4930 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4931}
4932
c8076604
GH		 4933static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4934 void *data)
4935{
4936 struct cpufreq_freqs *freq = data;
4937 struct kvm *kvm;
4938 struct kvm_vcpu *vcpu;
4939 int i, send_ipi = 0;
4940
8cfdc000
ZA		 4941 /*
4942 * We allow guests to temporarily run on slowing clocks,
4943 * provided we notify them after, or to run on accelerating
4944 * clocks, provided we notify them before. Thus time never
4945 * goes backwards.
4946 *
4947 * However, we have a problem. We can't atomically update
4948 * the frequency of a given CPU from this function; it is
4949 * merely a notifier, which can be called from any CPU.
4950 * Changing the TSC frequency at arbitrary points in time
4951 * requires a recomputation of local variables related to
4952 * the TSC for each VCPU. We must flag these local variables
4953 * to be updated and be sure the update takes place with the
4954 * new frequency before any guests proceed.
4955 *
4956 * Unfortunately, the combination of hotplug CPU and frequency
4957 * change creates an intractable locking scenario; the order
4958 * of when these callouts happen is undefined with respect to
4959 * CPU hotplug, and they can race with each other. As such,
4960 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4961 * undefined; you can actually have a CPU frequency change take
4962 * place in between the computation of X and the setting of the
4963 * variable. To protect against this problem, all updates of
4964 * the per_cpu tsc_khz variable are done in an interrupt
4965 * protected IPI, and all callers wishing to update the value
4966 * must wait for a synchronous IPI to complete (which is trivial
4967 * if the caller is on the CPU already). This establishes the
4968 * necessary total order on variable updates.
4969 *
4970 * Note that because a guest time update may take place
4971 * anytime after the setting of the VCPU's request bit, the
4972 * correct TSC value must be set before the request. However,
4973 * to ensure the update actually makes it to any guest which
4974 * starts running in hardware virtualization between the set
4975 * and the acquisition of the spinlock, we must also ping the
4976 * CPU after setting the request bit.
4977 *
4978 */
4979
c8076604
GH		 4980 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4981 return 0;
4982 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4983 return 0;
8cfdc000
ZA		 4984
4985 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4986
e935b837 4987 raw_spin_lock(&kvm_lock);
c8076604 4988 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4989 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4990 if (vcpu->cpu != freq->cpu)
4991 continue;
c285545f 4992 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4993 if (vcpu->cpu != smp_processor_id())
8cfdc000 4994 send_ipi = 1;
c8076604
GH		 4995 }
4996 }
e935b837 4997 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4998
4999 if (freq->old < freq->new && send_ipi) {
5000 /*
5001 * We upscale the frequency. Must make the guest
5002 * doesn't see old kvmclock values while running with
5003 * the new frequency, otherwise we risk the guest sees
5004 * time go backwards.
5005 *
5006 * In case we update the frequency for another cpu
5007 * (which might be in guest context) send an interrupt
5008 * to kick the cpu out of guest context. Next time
5009 * guest context is entered kvmclock will be updated,
5010 * so the guest will not see stale values.
5011 */
8cfdc000 5012 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5013 }
5014 return 0;
5015}
5016
5017static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5018 .notifier_call = kvmclock_cpufreq_notifier
5019};
5020
5021static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5022 unsigned long action, void *hcpu)
5023{
5024 unsigned int cpu = (unsigned long)hcpu;
5025
5026 switch (action) {
5027 case CPU_ONLINE:
5028 case CPU_DOWN_FAILED:
5029 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5030 break;
5031 case CPU_DOWN_PREPARE:
5032 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5033 break;
5034 }
5035 return NOTIFY_OK;
5036}
5037
5038static struct notifier_block kvmclock_cpu_notifier_block = {
5039 .notifier_call = kvmclock_cpu_notifier,
5040 .priority = -INT_MAX
c8076604
GH		 5041};
5042
b820cc0c
ZA		 5043static void kvm_timer_init(void)
5044{
5045 int cpu;
5046
c285545f 5047 max_tsc_khz = tsc_khz;
8cfdc000 5048 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5049 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5050#ifdef CONFIG_CPU_FREQ
5051 struct cpufreq_policy policy;
5052 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5053 cpu = get_cpu();
5054 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5055 if (policy.cpuinfo.max_freq)
5056 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5057 put_cpu();
c285545f 5058#endif
b820cc0c
ZA		 5059 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5060 CPUFREQ_TRANSITION_NOTIFIER);
5061 }
c285545f 5062 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5063 for_each_online_cpu(cpu)
5064 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5065}
5066
ff9d07a0
ZY		 5067static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5068
5069static int kvm_is_in_guest(void)
5070{
5071 return percpu_read(current_vcpu) != NULL;
5072}
5073
5074static int kvm_is_user_mode(void)
5075{
5076 int user_mode = 3;
dcf46b94 5077
ff9d07a0
ZY		 5078 if (percpu_read(current_vcpu))
5079 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 5080
ff9d07a0
ZY		 5081 return user_mode != 0;
5082}
5083
5084static unsigned long kvm_get_guest_ip(void)
5085{
5086 unsigned long ip = 0;
dcf46b94 5087
ff9d07a0
ZY		 5088 if (percpu_read(current_vcpu))
5089 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 5090
ff9d07a0
ZY		 5091 return ip;
5092}
5093
5094static struct perf_guest_info_callbacks kvm_guest_cbs = {
5095 .is_in_guest = kvm_is_in_guest,
5096 .is_user_mode = kvm_is_user_mode,
5097 .get_guest_ip = kvm_get_guest_ip,
5098};
5099
5100void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5101{
5102 percpu_write(current_vcpu, vcpu);
5103}
5104EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5105
5106void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5107{
5108 percpu_write(current_vcpu, NULL);
5109}
5110EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5111
ce88decf
XG		 5112static void kvm_set_mmio_spte_mask(void)
5113{
5114 u64 mask;
5115 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5116
5117 /*
5118 * Set the reserved bits and the present bit of an paging-structure
5119 * entry to generate page fault with PFER.RSV = 1.
5120 */
5121 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5122 mask |= 1ull;
5123
5124#ifdef CONFIG_X86_64
5125 /*
5126 * If reserved bit is not supported, clear the present bit to disable
5127 * mmio page fault.
5128 */
5129 if (maxphyaddr == 52)
5130 mask &= ~1ull;
5131#endif
5132
5133 kvm_mmu_set_mmio_spte_mask(mask);
5134}
5135
f8c16bba 5136int kvm_arch_init(void *opaque)
043405e1 5137{
b820cc0c 5138 int r;
f8c16bba
ZX		 5139 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5140
f8c16bba
ZX		 5141 if (kvm_x86_ops) {
5142 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5143 r = -EEXIST;
5144 goto out;
f8c16bba
ZX		 5145 }
5146
5147 if (!ops->cpu_has_kvm_support()) {
5148 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5149 r = -EOPNOTSUPP;
5150 goto out;
f8c16bba
ZX		 5151 }
5152 if (ops->disabled_by_bios()) {
5153 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5154 r = -EOPNOTSUPP;
5155 goto out;
f8c16bba
ZX		 5156 }
5157
97db56ce
AK		 5158 r = kvm_mmu_module_init();
5159 if (r)
5160 goto out;
5161
ce88decf 5162 kvm_set_mmio_spte_mask();
97db56ce
AK		 5163 kvm_init_msr_list();
5164
f8c16bba 5165 kvm_x86_ops = ops;
7b52345e 5166 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5167 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5168
b820cc0c 5169 kvm_timer_init();
c8076604 5170
ff9d07a0
ZY		 5171 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5172
2acf923e
DC		 5173 if (cpu_has_xsave)
5174 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5175
f8c16bba 5176 return 0;
56c6d28a
ZX		 5177
5178out:
56c6d28a 5179 return r;
043405e1 5180}
8776e519 5181
f8c16bba
ZX		 5182void kvm_arch_exit(void)
5183{
ff9d07a0
ZY		 5184 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5185
888d256e
JK		 5186 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5187 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5188 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5189 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 5190 kvm_x86_ops = NULL;
56c6d28a
ZX		 5191 kvm_mmu_module_exit();
5192}
f8c16bba 5193
8776e519
HB		 5194int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5195{
5196 ++vcpu->stat.halt_exits;
5197 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5198 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5199 return 1;
5200 } else {
5201 vcpu->run->exit_reason = KVM_EXIT_HLT;
5202 return 0;
5203 }
5204}
5205EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5206
2f333bcb
MT		 5207static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
5208 unsigned long a1)
5209{
5210 if (is_long_mode(vcpu))
5211 return a0;
5212 else
5213 return a0 | ((gpa_t)a1 << 32);
5214}
5215
55cd8e5a
GN		 5216int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5217{
5218 u64 param, ingpa, outgpa, ret;
5219 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5220 bool fast, longmode;
5221 int cs_db, cs_l;
5222
5223 /*
5224 * hypercall generates UD from non zero cpl and real mode
5225 * per HYPER-V spec
5226 */
3eeb3288 5227 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5228 kvm_queue_exception(vcpu, UD_VECTOR);
5229 return 0;
5230 }
5231
5232 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5233 longmode = is_long_mode(vcpu) && cs_l == 1;
5234
5235 if (!longmode) {
ccd46936
GN		 5236 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5237 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5238 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5239 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5240 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5241 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5242 }
5243#ifdef CONFIG_X86_64
5244 else {
5245 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5246 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5247 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5248 }
5249#endif
5250
5251 code = param & 0xffff;
5252 fast = (param >> 16) & 0x1;
5253 rep_cnt = (param >> 32) & 0xfff;
5254 rep_idx = (param >> 48) & 0xfff;
5255
5256 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5257
c25bc163
GN		 5258 switch (code) {
5259 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5260 kvm_vcpu_on_spin(vcpu);
5261 break;
5262 default:
5263 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5264 break;
5265 }
55cd8e5a
GN		 5266
5267 ret = res | (((u64)rep_done & 0xfff) << 32);
5268 if (longmode) {
5269 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5270 } else {
5271 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5272 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5273 }
5274
5275 return 1;
5276}
5277
8776e519
HB		 5278int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5279{
5280 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5281 int r = 1;
8776e519 5282
55cd8e5a
GN		 5283 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5284 return kvm_hv_hypercall(vcpu);
5285
5fdbf976
MT		 5286 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5287 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5288 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5289 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5290 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5291
229456fc 5292 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5293
8776e519
HB		 5294 if (!is_long_mode(vcpu)) {
5295 nr &= 0xFFFFFFFF;
5296 a0 &= 0xFFFFFFFF;
5297 a1 &= 0xFFFFFFFF;
5298 a2 &= 0xFFFFFFFF;
5299 a3 &= 0xFFFFFFFF;
5300 }
5301
07708c4a
JK		 5302 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5303 ret = -KVM_EPERM;
5304 goto out;
5305 }
5306
8776e519 5307 switch (nr) {
b93463aa
AK		 5308 case KVM_HC_VAPIC_POLL_IRQ:
5309 ret = 0;
5310 break;
2f333bcb
MT		 5311 case KVM_HC_MMU_OP:
5312 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
5313 break;
8776e519
HB		 5314 default:
5315 ret = -KVM_ENOSYS;
5316 break;
5317 }
07708c4a 5318out:
5fdbf976 5319 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5320 ++vcpu->stat.hypercalls;
2f333bcb 5321 return r;
8776e519
HB		 5322}
5323EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5324
d6aa1000 5325int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5326{
d6aa1000 5327 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5328 char instruction[3];
5fdbf976 5329 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5330
8776e519
HB		 5331 /*
5332 * Blow out the MMU to ensure that no other VCPU has an active mapping
5333 * to ensure that the updated hypercall appears atomically across all
5334 * VCPUs.
5335 */
5336 kvm_mmu_zap_all(vcpu->kvm);
5337
8776e519 5338 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5339
9d74191a 5340 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5341}
5342
07716717
DK		 5343static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
5344{
ad312c7c
ZX		 5345 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
5346 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 5347
5348 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
5349 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 5350 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 5351 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 5352 if (ej->function == e->function) {
5353 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
5354 return j;
5355 }
5356 }
5357 return 0; /* silence gcc, even though control never reaches here */
5358}
5359
5360/* find an entry with matching function, matching index (if needed), and that
5361 * should be read next (if it's stateful) */
5362static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
5363 u32 function, u32 index)
5364{
5365 if (e->function != function)
5366 return 0;
5367 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
5368 return 0;
5369 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 5370 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 5371 return 0;
5372 return 1;
5373}
5374
d8017474
AG		 5375struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5376 u32 function, u32 index)
8776e519
HB		 5377{
5378 int i;
d8017474 5379 struct kvm_cpuid_entry2 *best = NULL;
8776e519 5380
ad312c7c 5381 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 5382 struct kvm_cpuid_entry2 *e;
5383
ad312c7c 5384 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 5385 if (is_matching_cpuid_entry(e, function, index)) {
5386 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5387 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 5388 best = e;
5389 break;
5390 }
8776e519 5391 }
d8017474
AG		 5392 return best;
5393}
0e851880 5394EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 5395
82725b20
DE		 5396int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5397{
5398 struct kvm_cpuid_entry2 *best;
5399
f7a71197
AK		 5400 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5401 if (!best || best->eax < 0x80000008)
5402 goto not_found;
82725b20
DE		 5403 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5404 if (best)
5405 return best->eax & 0xff;
f7a71197 5406not_found:
82725b20
DE		 5407 return 36;
5408}
5409
bd22f5cf
AP		 5410/*
5411 * If no match is found, check whether we exceed the vCPU's limit
5412 * and return the content of the highest valid _standard_ leaf instead.
5413 * This is to satisfy the CPUID specification.
5414 */
5415static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5416 u32 function, u32 index)
5417{
5418 struct kvm_cpuid_entry2 *maxlevel;
5419
5420 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5421 if (!maxlevel || maxlevel->eax >= function)
5422 return NULL;
5423 if (function & 0x80000000) {
5424 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5425 if (!maxlevel)
5426 return NULL;
5427 }
5428 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5429}
5430
d8017474
AG		 5431void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5432{
5433 u32 function, index;
5434 struct kvm_cpuid_entry2 *best;
5435
5436 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5437 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5438 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5439 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5440 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5441 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5442 best = kvm_find_cpuid_entry(vcpu, function, index);
bd22f5cf
AP		 5443
5444 if (!best)
5445 best = check_cpuid_limit(vcpu, function, index);
5446
8776e519 5447 if (best) {
5fdbf976
MT		 5448 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5449 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5450 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5451 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 5452 }
8776e519 5453 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5454 trace_kvm_cpuid(function,
5455 kvm_register_read(vcpu, VCPU_REGS_RAX),
5456 kvm_register_read(vcpu, VCPU_REGS_RBX),
5457 kvm_register_read(vcpu, VCPU_REGS_RCX),
5458 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5459}
5460EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5461
b6c7a5dc
HB		 5462/*
5463 * Check if userspace requested an interrupt window, and that the
5464 * interrupt window is open.
5465 *
5466 * No need to exit to userspace if we already have an interrupt queued.
5467 */
851ba692 5468static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5469{
8061823a 5470 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5471 vcpu->run->request_interrupt_window &&
5df56646 5472 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5473}
5474
851ba692 5475static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5476{
851ba692
AK		 5477 struct kvm_run *kvm_run = vcpu->run;
5478
91586a3b 5479 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5480 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5481 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5482 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5483 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5484 else
b6c7a5dc 5485 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5486 kvm_arch_interrupt_allowed(vcpu) &&
5487 !kvm_cpu_has_interrupt(vcpu) &&
5488 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5489}
5490
b93463aa
AK		 5491static void vapic_enter(struct kvm_vcpu *vcpu)
5492{
5493 struct kvm_lapic *apic = vcpu->arch.apic;
5494 struct page *page;
5495
5496 if (!apic || !apic->vapic_addr)
5497 return;
5498
5499 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5500
5501 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5502}
5503
5504static void vapic_exit(struct kvm_vcpu *vcpu)
5505{
5506 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5507 int idx;
b93463aa
AK		 5508
5509 if (!apic || !apic->vapic_addr)
5510 return;
5511
f656ce01 5512 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5513 kvm_release_page_dirty(apic->vapic_page);
5514 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5515 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5516}
5517
95ba8273
GN		 5518static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5519{
5520 int max_irr, tpr;
5521
5522 if (!kvm_x86_ops->update_cr8_intercept)
5523 return;
5524
88c808fd
AK		 5525 if (!vcpu->arch.apic)
5526 return;
5527
8db3baa2
GN		 5528 if (!vcpu->arch.apic->vapic_addr)
5529 max_irr = kvm_lapic_find_highest_irr(vcpu);
5530 else
5531 max_irr = -1;
95ba8273
GN		 5532
5533 if (max_irr != -1)
5534 max_irr >>= 4;
5535
5536 tpr = kvm_lapic_get_cr8(vcpu);
5537
5538 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5539}
5540
851ba692 5541static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5542{
5543 /* try to reinject previous events if any */
b59bb7bd 5544 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5545 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5546 vcpu->arch.exception.has_error_code,
5547 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5548 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5549 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5550 vcpu->arch.exception.error_code,
5551 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5552 return;
5553 }
5554
95ba8273
GN		 5555 if (vcpu->arch.nmi_injected) {
5556 kvm_x86_ops->set_nmi(vcpu);
5557 return;
5558 }
5559
5560 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5561 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5562 return;
5563 }
5564
5565 /* try to inject new event if pending */
5566 if (vcpu->arch.nmi_pending) {
5567 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5568 vcpu->arch.nmi_pending = false;
5569 vcpu->arch.nmi_injected = true;
5570 kvm_x86_ops->set_nmi(vcpu);
5571 }
5572 } else if (kvm_cpu_has_interrupt(vcpu)) {
5573 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5574 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5575 false);
5576 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5577 }
5578 }
5579}
5580
2acf923e
DC		 5581static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5582{
5583 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5584 !vcpu->guest_xcr0_loaded) {
5585 /* kvm_set_xcr() also depends on this */
5586 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5587 vcpu->guest_xcr0_loaded = 1;
5588 }
5589}
5590
5591static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5592{
5593 if (vcpu->guest_xcr0_loaded) {
5594 if (vcpu->arch.xcr0 != host_xcr0)
5595 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5596 vcpu->guest_xcr0_loaded = 0;
5597 }
5598}
5599
851ba692 5600static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5601{
5602 int r;
1499e54a 5603 bool nmi_pending;
6a8b1d13 5604 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5605 vcpu->run->request_interrupt_window;
b6c7a5dc 5606
3e007509 5607 if (vcpu->requests) {
a8eeb04a 5608 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5609 kvm_mmu_unload(vcpu);
a8eeb04a 5610 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5611 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5612 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5613 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5614 if (unlikely(r))
5615 goto out;
5616 }
a8eeb04a 5617 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5618 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5619 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5620 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5621 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5622 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5623 r = 0;
5624 goto out;
5625 }
a8eeb04a 5626 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5627 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5628 r = 0;
5629 goto out;
5630 }
a8eeb04a 5631 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5632 vcpu->fpu_active = 0;
5633 kvm_x86_ops->fpu_deactivate(vcpu);
5634 }
af585b92
GN		 5635 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5636 /* Page is swapped out. Do synthetic halt */
5637 vcpu->arch.apf.halted = true;
5638 r = 1;
5639 goto out;
5640 }
c9aaa895
GC		 5641 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5642 record_steal_time(vcpu);
5643
2f52d58c 5644 }
b93463aa 5645
3e007509
AK		 5646 r = kvm_mmu_reload(vcpu);
5647 if (unlikely(r))
5648 goto out;
5649
1499e54a
GN		 5650 /*
5651 * An NMI can be injected between local nmi_pending read and
5652 * vcpu->arch.nmi_pending read inside inject_pending_event().
5653 * But in that case, KVM_REQ_EVENT will be set, which makes
5654 * the race described above benign.
5655 */
5656 nmi_pending = ACCESS_ONCE(vcpu->arch.nmi_pending);
5657
b463a6f7
AK		 5658 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5659 inject_pending_event(vcpu);
5660
5661 /* enable NMI/IRQ window open exits if needed */
1499e54a 5662 if (nmi_pending)
b463a6f7
AK		 5663 kvm_x86_ops->enable_nmi_window(vcpu);
5664 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5665 kvm_x86_ops->enable_irq_window(vcpu);
5666
5667 if (kvm_lapic_enabled(vcpu)) {
5668 update_cr8_intercept(vcpu);
5669 kvm_lapic_sync_to_vapic(vcpu);
5670 }
5671 }
5672
b6c7a5dc
HB		 5673 preempt_disable();
5674
5675 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5676 if (vcpu->fpu_active)
5677 kvm_load_guest_fpu(vcpu);
2acf923e 5678 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5679
6b7e2d09
XG		 5680 vcpu->mode = IN_GUEST_MODE;
5681
5682 /* We should set ->mode before check ->requests,
5683 * see the comment in make_all_cpus_request.
5684 */
5685 smp_mb();
b6c7a5dc 5686
d94e1dc9 5687 local_irq_disable();
32f88400 5688
6b7e2d09 5689 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5690 || need_resched() || signal_pending(current)) {
6b7e2d09 5691 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5692 smp_wmb();
6c142801
AK		 5693 local_irq_enable();
5694 preempt_enable();
b463a6f7 5695 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5696 r = 1;
5697 goto out;
5698 }
5699
f656ce01 5700 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5701
b6c7a5dc
HB		 5702 kvm_guest_enter();
5703
42dbaa5a 5704 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5705 set_debugreg(0, 7);
5706 set_debugreg(vcpu->arch.eff_db[0], 0);
5707 set_debugreg(vcpu->arch.eff_db[1], 1);
5708 set_debugreg(vcpu->arch.eff_db[2], 2);
5709 set_debugreg(vcpu->arch.eff_db[3], 3);
5710 }
b6c7a5dc 5711
229456fc 5712 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5713 kvm_x86_ops->run(vcpu);
b6c7a5dc 5714
24f1e32c
FW		 5715 /*
5716 * If the guest has used debug registers, at least dr7
5717 * will be disabled while returning to the host.
5718 * If we don't have active breakpoints in the host, we don't
5719 * care about the messed up debug address registers. But if
5720 * we have some of them active, restore the old state.
5721 */
59d8eb53 5722 if (hw_breakpoint_active())
24f1e32c 5723 hw_breakpoint_restore();
42dbaa5a 5724
1d5f066e
ZA		 5725 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5726
6b7e2d09 5727 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5728 smp_wmb();
b6c7a5dc
HB		 5729 local_irq_enable();
5730
5731 ++vcpu->stat.exits;
5732
5733 /*
5734 * We must have an instruction between local_irq_enable() and
5735 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5736 * the interrupt shadow. The stat.exits increment will do nicely.
5737 * But we need to prevent reordering, hence this barrier():
5738 */
5739 barrier();
5740
5741 kvm_guest_exit();
5742
5743 preempt_enable();
5744
f656ce01 5745 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5746
b6c7a5dc
HB		 5747 /*
5748 * Profile KVM exit RIPs:
5749 */
5750 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5751 unsigned long rip = kvm_rip_read(vcpu);
5752 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5753 }
5754
298101da 5755
b93463aa
AK		 5756 kvm_lapic_sync_from_vapic(vcpu);
5757
851ba692 5758 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5759out:
5760 return r;
5761}
b6c7a5dc 5762
09cec754 5763
851ba692 5764static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5765{
5766 int r;
f656ce01 5767 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5768
5769 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5770 pr_debug("vcpu %d received sipi with vector # %x\n",
5771 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5772 kvm_lapic_reset(vcpu);
5f179287 5773 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5774 if (r)
5775 return r;
5776 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5777 }
5778
f656ce01 5779 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5780 vapic_enter(vcpu);
5781
5782 r = 1;
5783 while (r > 0) {
af585b92
GN		 5784 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5785 !vcpu->arch.apf.halted)
851ba692 5786 r = vcpu_enter_guest(vcpu);
d7690175 5787 else {
f656ce01 5788 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5789 kvm_vcpu_block(vcpu);
f656ce01 5790 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5791 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5792 {
5793 switch(vcpu->arch.mp_state) {
5794 case KVM_MP_STATE_HALTED:
d7690175 5795 vcpu->arch.mp_state =
09cec754
GN		 5796 KVM_MP_STATE_RUNNABLE;
5797 case KVM_MP_STATE_RUNNABLE:
af585b92 5798 vcpu->arch.apf.halted = false;
09cec754
GN		 5799 break;
5800 case KVM_MP_STATE_SIPI_RECEIVED:
5801 default:
5802 r = -EINTR;
5803 break;
5804 }
5805 }
d7690175
MT		 5806 }
5807
09cec754
GN		 5808 if (r <= 0)
5809 break;
5810
5811 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5812 if (kvm_cpu_has_pending_timer(vcpu))
5813 kvm_inject_pending_timer_irqs(vcpu);
5814
851ba692 5815 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5816 r = -EINTR;
851ba692 5817 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5818 ++vcpu->stat.request_irq_exits;
5819 }
af585b92
GN		 5820
5821 kvm_check_async_pf_completion(vcpu);
5822
09cec754
GN		 5823 if (signal_pending(current)) {
5824 r = -EINTR;
851ba692 5825 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5826 ++vcpu->stat.signal_exits;
5827 }
5828 if (need_resched()) {
f656ce01 5829 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5830 kvm_resched(vcpu);
f656ce01 5831 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5832 }
b6c7a5dc
HB		 5833 }
5834
f656ce01 5835 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5836
b93463aa
AK		 5837 vapic_exit(vcpu);
5838
b6c7a5dc
HB		 5839 return r;
5840}
5841
5287f194
AK		 5842static int complete_mmio(struct kvm_vcpu *vcpu)
5843{
5844 struct kvm_run *run = vcpu->run;
5845 int r;
5846
5847 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5848 return 1;
5849
5850 if (vcpu->mmio_needed) {
5287f194 5851 vcpu->mmio_needed = 0;
cef4dea0 5852 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5853 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5854 run->mmio.data, 8);
cef4dea0
AK		 5855 vcpu->mmio_index += 8;
5856 if (vcpu->mmio_index < vcpu->mmio_size) {
5857 run->exit_reason = KVM_EXIT_MMIO;
5858 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5859 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5860 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5861 run->mmio.is_write = vcpu->mmio_is_write;
5862 vcpu->mmio_needed = 1;
5863 return 0;
5864 }
5865 if (vcpu->mmio_is_write)
5866 return 1;
5867 vcpu->mmio_read_completed = 1;
5287f194
AK		 5868 }
5869 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5870 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5871 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5872 if (r != EMULATE_DONE)
5873 return 0;
5874 return 1;
5875}
5876
b6c7a5dc
HB		 5877int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5878{
5879 int r;
5880 sigset_t sigsaved;
5881
e5c30142
AK		 5882 if (!tsk_used_math(current) && init_fpu(current))
5883 return -ENOMEM;
5884
ac9f6dc0
AK		 5885 if (vcpu->sigset_active)
5886 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5887
a4535290 5888 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5889 kvm_vcpu_block(vcpu);
d7690175 5890 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5891 r = -EAGAIN;
5892 goto out;
b6c7a5dc
HB		 5893 }
5894
b6c7a5dc 5895 /* re-sync apic's tpr */
eea1cff9
AP		 5896 if (!irqchip_in_kernel(vcpu->kvm)) {
5897 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5898 r = -EINVAL;
5899 goto out;
5900 }
5901 }
b6c7a5dc 5902
5287f194
AK		 5903 r = complete_mmio(vcpu);
5904 if (r <= 0)
5905 goto out;
5906
5fdbf976
MT		 5907 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5908 kvm_register_write(vcpu, VCPU_REGS_RAX,
5909 kvm_run->hypercall.ret);
b6c7a5dc 5910
851ba692 5911 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5912
5913out:
f1d86e46 5914 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5915 if (vcpu->sigset_active)
5916 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5917
b6c7a5dc
HB		 5918 return r;
5919}
5920
5921int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5922{
7ae441ea
GN		 5923 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5924 /*
5925 * We are here if userspace calls get_regs() in the middle of
5926 * instruction emulation. Registers state needs to be copied
5927 * back from emulation context to vcpu. Usrapace shouldn't do
5928 * that usually, but some bad designed PV devices (vmware
5929 * backdoor interface) need this to work
5930 */
9dac77fa
AK		 5931 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5932 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5933 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5934 }
5fdbf976
MT		 5935 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5936 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5937 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5938 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5939 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5940 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5941 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5942 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5943#ifdef CONFIG_X86_64
5fdbf976
MT		 5944 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5945 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5946 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5947 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5948 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5949 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5950 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5951 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5952#endif
5953
5fdbf976 5954 regs->rip = kvm_rip_read(vcpu);
91586a3b 5955 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5956
b6c7a5dc
HB		 5957 return 0;
5958}
5959
5960int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5961{
7ae441ea
GN		 5962 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5963 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5964
5fdbf976
MT		 5965 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5966 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5967 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5968 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5969 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5970 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5971 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5972 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5973#ifdef CONFIG_X86_64
5fdbf976
MT		 5974 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5975 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5976 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5977 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5978 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5979 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5980 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5981 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5982#endif
5983
5fdbf976 5984 kvm_rip_write(vcpu, regs->rip);
91586a3b 5985 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5986
b4f14abd
JK		 5987 vcpu->arch.exception.pending = false;
5988
3842d135
AK		 5989 kvm_make_request(KVM_REQ_EVENT, vcpu);
5990
b6c7a5dc
HB		 5991 return 0;
5992}
5993
b6c7a5dc
HB		 5994void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5995{
5996 struct kvm_segment cs;
5997
3e6e0aab 5998 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5999 *db = cs.db;
6000 *l = cs.l;
6001}
6002EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6003
6004int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6005 struct kvm_sregs *sregs)
6006{
89a27f4d 6007 struct desc_ptr dt;
b6c7a5dc 6008
3e6e0aab
GT		 6009 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6010 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6011 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6012 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6013 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6014 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6015
3e6e0aab
GT		 6016 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6017 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6018
6019 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6020 sregs->idt.limit = dt.size;
6021 sregs->idt.base = dt.address;
b6c7a5dc 6022 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6023 sregs->gdt.limit = dt.size;
6024 sregs->gdt.base = dt.address;
b6c7a5dc 6025
4d4ec087 6026 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6027 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6028 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6029 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6030 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6031 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6032 sregs->apic_base = kvm_get_apic_base(vcpu);
6033
923c61bb 6034 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6035
36752c9b 6036 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6037 set_bit(vcpu->arch.interrupt.nr,
6038 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6039
b6c7a5dc
HB		 6040 return 0;
6041}
6042
62d9f0db
MT		 6043int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6044 struct kvm_mp_state *mp_state)
6045{
62d9f0db 6046 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6047 return 0;
6048}
6049
6050int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6051 struct kvm_mp_state *mp_state)
6052{
62d9f0db 6053 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6054 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6055 return 0;
6056}
6057
e269fb21
JK		 6058int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
6059 bool has_error_code, u32 error_code)
b6c7a5dc 6060{
9d74191a 6061 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6062 int ret;
e01c2426 6063
8ec4722d 6064 init_emulate_ctxt(vcpu);
c697518a 6065
9d74191a
TY		 6066 ret = emulator_task_switch(ctxt, tss_selector, reason,
6067 has_error_code, error_code);
c697518a 6068
c697518a 6069 if (ret)
19d04437 6070 return EMULATE_FAIL;
37817f29 6071
9dac77fa 6072 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 6073 kvm_rip_write(vcpu, ctxt->eip);
6074 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6075 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6076 return EMULATE_DONE;
37817f29
IE		 6077}
6078EXPORT_SYMBOL_GPL(kvm_task_switch);
6079
b6c7a5dc
HB		 6080int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6081 struct kvm_sregs *sregs)
6082{
6083 int mmu_reset_needed = 0;
63f42e02 6084 int pending_vec, max_bits, idx;
89a27f4d 6085 struct desc_ptr dt;
b6c7a5dc 6086
89a27f4d
GN		 6087 dt.size = sregs->idt.limit;
6088 dt.address = sregs->idt.base;
b6c7a5dc 6089 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6090 dt.size = sregs->gdt.limit;
6091 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6092 kvm_x86_ops->set_gdt(vcpu, &dt);
6093
ad312c7c 6094 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6095 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6096 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6097 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6098
2d3ad1f4 6099 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6100
f6801dff 6101 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6102 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6103 kvm_set_apic_base(vcpu, sregs->apic_base);
6104
4d4ec087 6105 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6106 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6107 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6108
fc78f519 6109 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6110 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 6111 if (sregs->cr4 & X86_CR4_OSXSAVE)
6112 update_cpuid(vcpu);
63f42e02
XG		 6113
6114 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6115 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6116 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6117 mmu_reset_needed = 1;
6118 }
63f42e02 6119 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6120
6121 if (mmu_reset_needed)
6122 kvm_mmu_reset_context(vcpu);
6123
923c61bb
GN		 6124 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
6125 pending_vec = find_first_bit(
6126 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6127 if (pending_vec < max_bits) {
66fd3f7f 6128 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6129 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6130 }
6131
3e6e0aab
GT		 6132 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6133 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6134 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6135 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6136 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6137 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6138
3e6e0aab
GT		 6139 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6140 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6141
5f0269f5
ME		 6142 update_cr8_intercept(vcpu);
6143
9c3e4aab 6144 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6145 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6146 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6147 !is_protmode(vcpu))
9c3e4aab
MT		 6148 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6149
3842d135
AK		 6150 kvm_make_request(KVM_REQ_EVENT, vcpu);
6151
b6c7a5dc
HB		 6152 return 0;
6153}
6154
d0bfb940
JK		 6155int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6156 struct kvm_guest_debug *dbg)
b6c7a5dc 6157{
355be0b9 6158 unsigned long rflags;
ae675ef0 6159 int i, r;
b6c7a5dc 6160
4f926bf2
JK		 6161 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6162 r = -EBUSY;
6163 if (vcpu->arch.exception.pending)
2122ff5e 6164 goto out;
4f926bf2
JK		 6165 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6166 kvm_queue_exception(vcpu, DB_VECTOR);
6167 else
6168 kvm_queue_exception(vcpu, BP_VECTOR);
6169 }
6170
91586a3b
JK		 6171 /*
6172 * Read rflags as long as potentially injected trace flags are still
6173 * filtered out.
6174 */
6175 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6176
6177 vcpu->guest_debug = dbg->control;
6178 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6179 vcpu->guest_debug = 0;
6180
6181 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6182 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6183 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6184 vcpu->arch.switch_db_regs =
6185 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
6186 } else {
6187 for (i = 0; i < KVM_NR_DB_REGS; i++)
6188 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6189 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
6190 }
6191
f92653ee
JK		 6192 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6193 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6194 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6195
91586a3b
JK		 6196 /*
6197 * Trigger an rflags update that will inject or remove the trace
6198 * flags.
6199 */
6200 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6201
355be0b9 6202 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 6203
4f926bf2 6204 r = 0;
d0bfb940 6205
2122ff5e 6206out:
b6c7a5dc
HB		 6207
6208 return r;
6209}
6210
8b006791
ZX		 6211/*
6212 * Translate a guest virtual address to a guest physical address.
6213 */
6214int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6215 struct kvm_translation *tr)
6216{
6217 unsigned long vaddr = tr->linear_address;
6218 gpa_t gpa;
f656ce01 6219 int idx;
8b006791 6220
f656ce01 6221 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6222 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6223 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6224 tr->physical_address = gpa;
6225 tr->valid = gpa != UNMAPPED_GVA;
6226 tr->writeable = 1;
6227 tr->usermode = 0;
8b006791
ZX		 6228
6229 return 0;
6230}
6231
d0752060
HB		 6232int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6233{
98918833
SY		 6234 struct i387_fxsave_struct *fxsave =
6235 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6236
d0752060
HB		 6237 memcpy(fpu->fpr, fxsave->st_space, 128);
6238 fpu->fcw = fxsave->cwd;
6239 fpu->fsw = fxsave->swd;
6240 fpu->ftwx = fxsave->twd;
6241 fpu->last_opcode = fxsave->fop;
6242 fpu->last_ip = fxsave->rip;
6243 fpu->last_dp = fxsave->rdp;
6244 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6245
d0752060
HB		 6246 return 0;
6247}
6248
6249int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6250{
98918833
SY		 6251 struct i387_fxsave_struct *fxsave =
6252 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6253
d0752060
HB		 6254 memcpy(fxsave->st_space, fpu->fpr, 128);
6255 fxsave->cwd = fpu->fcw;
6256 fxsave->swd = fpu->fsw;
6257 fxsave->twd = fpu->ftwx;
6258 fxsave->fop = fpu->last_opcode;
6259 fxsave->rip = fpu->last_ip;
6260 fxsave->rdp = fpu->last_dp;
6261 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6262
d0752060
HB		 6263 return 0;
6264}
6265
10ab25cd 6266int fx_init(struct kvm_vcpu *vcpu)
d0752060 6267{
10ab25cd
JK		 6268 int err;
6269
6270 err = fpu_alloc(&vcpu->arch.guest_fpu);
6271 if (err)
6272 return err;
6273
98918833 6274 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6275
2acf923e
DC		 6276 /*
6277 * Ensure guest xcr0 is valid for loading
6278 */
6279 vcpu->arch.xcr0 = XSTATE_FP;
6280
ad312c7c 6281 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6282
6283 return 0;
d0752060
HB		 6284}
6285EXPORT_SYMBOL_GPL(fx_init);
6286
98918833
SY		 6287static void fx_free(struct kvm_vcpu *vcpu)
6288{
6289 fpu_free(&vcpu->arch.guest_fpu);
6290}
6291
d0752060
HB		 6292void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6293{
2608d7a1 6294 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6295 return;
6296
2acf923e
DC		 6297 /*
6298 * Restore all possible states in the guest,
6299 * and assume host would use all available bits.
6300 * Guest xcr0 would be loaded later.
6301 */
6302 kvm_put_guest_xcr0(vcpu);
d0752060 6303 vcpu->guest_fpu_loaded = 1;
7cf30855 6304 unlazy_fpu(current);
98918833 6305 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6306 trace_kvm_fpu(1);
d0752060 6307}
d0752060
HB		 6308
6309void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6310{
2acf923e
DC		 6311 kvm_put_guest_xcr0(vcpu);
6312
d0752060
HB		 6313 if (!vcpu->guest_fpu_loaded)
6314 return;
6315
6316 vcpu->guest_fpu_loaded = 0;
98918833 6317 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 6318 ++vcpu->stat.fpu_reload;
a8eeb04a 6319 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6320 trace_kvm_fpu(0);
d0752060 6321}
e9b11c17
ZX		 6322
6323void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6324{
12f9a48f 6325 kvmclock_reset(vcpu);
7f1ea208 6326
f5f48ee1 6327 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6328 fx_free(vcpu);
e9b11c17
ZX		 6329 kvm_x86_ops->vcpu_free(vcpu);
6330}
6331
6332struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6333 unsigned int id)
6334{
6755bae8
ZA		 6335 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6336 printk_once(KERN_WARNING
6337 "kvm: SMP vm created on host with unstable TSC; "
6338 "guest TSC will not be reliable\n");
26e5215f
AK		 6339 return kvm_x86_ops->vcpu_create(kvm, id);
6340}
e9b11c17 6341
26e5215f
AK		 6342int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6343{
6344 int r;
e9b11c17 6345
0bed3b56 6346 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 6347 vcpu_load(vcpu);
6348 r = kvm_arch_vcpu_reset(vcpu);
6349 if (r == 0)
6350 r = kvm_mmu_setup(vcpu);
6351 vcpu_put(vcpu);
e9b11c17 6352
26e5215f 6353 return r;
e9b11c17
ZX		 6354}
6355
d40ccc62 6356void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6357{
344d9588
GN		 6358 vcpu->arch.apf.msr_val = 0;
6359
e9b11c17
ZX		 6360 vcpu_load(vcpu);
6361 kvm_mmu_unload(vcpu);
6362 vcpu_put(vcpu);
6363
98918833 6364 fx_free(vcpu);
e9b11c17
ZX		 6365 kvm_x86_ops->vcpu_free(vcpu);
6366}
6367
6368int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6369{
448fa4a9
JK		 6370 vcpu->arch.nmi_pending = false;
6371 vcpu->arch.nmi_injected = false;
6372
42dbaa5a
JK		 6373 vcpu->arch.switch_db_regs = 0;
6374 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6375 vcpu->arch.dr6 = DR6_FIXED_1;
6376 vcpu->arch.dr7 = DR7_FIXED_1;
6377
3842d135 6378 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6379 vcpu->arch.apf.msr_val = 0;
c9aaa895 6380 vcpu->arch.st.msr_val = 0;
3842d135 6381
12f9a48f
GC		 6382 kvmclock_reset(vcpu);
6383
af585b92
GN		 6384 kvm_clear_async_pf_completion_queue(vcpu);
6385 kvm_async_pf_hash_reset(vcpu);
6386 vcpu->arch.apf.halted = false;
3842d135 6387
e9b11c17
ZX		 6388 return kvm_x86_ops->vcpu_reset(vcpu);
6389}
6390
10474ae8 6391int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6392{
ca84d1a2
ZA		 6393 struct kvm *kvm;
6394 struct kvm_vcpu *vcpu;
6395 int i;
18863bdd
AK		 6396
6397 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 6398 list_for_each_entry(kvm, &vm_list, vm_list)
6399 kvm_for_each_vcpu(i, vcpu, kvm)
6400 if (vcpu->cpu == smp_processor_id())
c285545f 6401 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 6402 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 6403}
6404
6405void kvm_arch_hardware_disable(void *garbage)
6406{
6407 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6408 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6409}
6410
6411int kvm_arch_hardware_setup(void)
6412{
6413 return kvm_x86_ops->hardware_setup();
6414}
6415
6416void kvm_arch_hardware_unsetup(void)
6417{
6418 kvm_x86_ops->hardware_unsetup();
6419}
6420
6421void kvm_arch_check_processor_compat(void *rtn)
6422{
6423 kvm_x86_ops->check_processor_compatibility(rtn);
6424}
6425
6426int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6427{
6428 struct page *page;
6429 struct kvm *kvm;
6430 int r;
6431
6432 BUG_ON(vcpu->kvm == NULL);
6433 kvm = vcpu->kvm;
6434
9aabc88f 6435 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 6436 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 6437 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 6438 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 6439 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 6440 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6441 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6442 else
a4535290 6443 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6444
6445 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6446 if (!page) {
6447 r = -ENOMEM;
6448 goto fail;
6449 }
ad312c7c 6450 vcpu->arch.pio_data = page_address(page);
e9b11c17 6451
1e993611 6452 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 6453
e9b11c17
ZX		 6454 r = kvm_mmu_create(vcpu);
6455 if (r < 0)
6456 goto fail_free_pio_data;
6457
6458 if (irqchip_in_kernel(kvm)) {
6459 r = kvm_create_lapic(vcpu);
6460 if (r < 0)
6461 goto fail_mmu_destroy;
6462 }
6463
890ca9ae
HY		 6464 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6465 GFP_KERNEL);
6466 if (!vcpu->arch.mce_banks) {
6467 r = -ENOMEM;
443c39bc 6468 goto fail_free_lapic;
890ca9ae
HY		 6469 }
6470 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6471
f5f48ee1
SY		 6472 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6473 goto fail_free_mce_banks;
6474
af585b92
GN		 6475 kvm_async_pf_hash_reset(vcpu);
6476
e9b11c17 6477 return 0;
f5f48ee1
SY		 6478fail_free_mce_banks:
6479 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6480fail_free_lapic:
6481 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6482fail_mmu_destroy:
6483 kvm_mmu_destroy(vcpu);
6484fail_free_pio_data:
ad312c7c 6485 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6486fail:
6487 return r;
6488}
6489
6490void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6491{
f656ce01
MT		 6492 int idx;
6493
36cb93fd 6494 kfree(vcpu->arch.mce_banks);
e9b11c17 6495 kvm_free_lapic(vcpu);
f656ce01 6496 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6497 kvm_mmu_destroy(vcpu);
f656ce01 6498 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6499 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6500}
d19a9cd2 6501
d89f5eff 6502int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6503{
f05e70ac 6504 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6505 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6506
5550af4d
SY		 6507 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6508 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6509
038f8c11 6510 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6511
d89f5eff 6512 return 0;
d19a9cd2
ZX		 6513}
6514
6515static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6516{
6517 vcpu_load(vcpu);
6518 kvm_mmu_unload(vcpu);
6519 vcpu_put(vcpu);
6520}
6521
6522static void kvm_free_vcpus(struct kvm *kvm)
6523{
6524 unsigned int i;
988a2cae 6525 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6526
6527 /*
6528 * Unpin any mmu pages first.
6529 */
af585b92
GN		 6530 kvm_for_each_vcpu(i, vcpu, kvm) {
6531 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6532 kvm_unload_vcpu_mmu(vcpu);
af585b92 6533 }
988a2cae
GN		 6534 kvm_for_each_vcpu(i, vcpu, kvm)
6535 kvm_arch_vcpu_free(vcpu);
6536
6537 mutex_lock(&kvm->lock);
6538 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6539 kvm->vcpus[i] = NULL;
d19a9cd2 6540
988a2cae
GN		 6541 atomic_set(&kvm->online_vcpus, 0);
6542 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6543}
6544
ad8ba2cd
SY		 6545void kvm_arch_sync_events(struct kvm *kvm)
6546{
ba4cef31 6547 kvm_free_all_assigned_devices(kvm);
aea924f6 6548 kvm_free_pit(kvm);
ad8ba2cd
SY		 6549}
6550
d19a9cd2
ZX		 6551void kvm_arch_destroy_vm(struct kvm *kvm)
6552{
6eb55818 6553 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6554 kfree(kvm->arch.vpic);
6555 kfree(kvm->arch.vioapic);
d19a9cd2 6556 kvm_free_vcpus(kvm);
3d45830c
AK		 6557 if (kvm->arch.apic_access_page)
6558 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6559 if (kvm->arch.ept_identity_pagetable)
6560 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6561}
0de10343 6562
f7784b8e
MT		 6563int kvm_arch_prepare_memory_region(struct kvm *kvm,
6564 struct kvm_memory_slot *memslot,
0de10343 6565 struct kvm_memory_slot old,
f7784b8e 6566 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6567 int user_alloc)
6568{
f7784b8e 6569 int npages = memslot->npages;
7ac77099
AK		 6570 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6571
6572 /* Prevent internal slot pages from being moved by fork()/COW. */
6573 if (memslot->id >= KVM_MEMORY_SLOTS)
6574 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6575
6576 /*To keep backward compatibility with older userspace,
6577 *x86 needs to hanlde !user_alloc case.
6578 */
6579 if (!user_alloc) {
6580 if (npages && !old.rmap) {
604b38ac
AA		 6581 unsigned long userspace_addr;
6582
72dc67a6 6583 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6584 userspace_addr = do_mmap(NULL, 0,
6585 npages * PAGE_SIZE,
6586 PROT_READ | PROT_WRITE,
7ac77099 6587 map_flags,
604b38ac 6588 0);
72dc67a6 6589 up_write(&current->mm->mmap_sem);
0de10343 6590
604b38ac
AA		 6591 if (IS_ERR((void *)userspace_addr))
6592 return PTR_ERR((void *)userspace_addr);
6593
604b38ac 6594 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6595 }
6596 }
6597
f7784b8e
MT		 6598
6599 return 0;
6600}
6601
6602void kvm_arch_commit_memory_region(struct kvm *kvm,
6603 struct kvm_userspace_memory_region *mem,
6604 struct kvm_memory_slot old,
6605 int user_alloc)
6606{
6607
48c0e4e9 6608 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6609
6610 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6611 int ret;
6612
6613 down_write(&current->mm->mmap_sem);
6614 ret = do_munmap(current->mm, old.userspace_addr,
6615 old.npages * PAGE_SIZE);
6616 up_write(&current->mm->mmap_sem);
6617 if (ret < 0)
6618 printk(KERN_WARNING
6619 "kvm_vm_ioctl_set_memory_region: "
6620 "failed to munmap memory\n");
6621 }
6622
48c0e4e9
XG		 6623 if (!kvm->arch.n_requested_mmu_pages)
6624 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6625
7c8a83b7 6626 spin_lock(&kvm->mmu_lock);
48c0e4e9 6627 if (nr_mmu_pages)
0de10343 6628 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6629 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6630 spin_unlock(&kvm->mmu_lock);
0de10343 6631}
1d737c8a 6632
34d4cb8f
MT		 6633void kvm_arch_flush_shadow(struct kvm *kvm)
6634{
6635 kvm_mmu_zap_all(kvm);
8986ecc0 6636 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6637}
6638
1d737c8a
ZX		 6639int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6640{
af585b92
GN		 6641 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6642 !vcpu->arch.apf.halted)
6643 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6644 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6645 || vcpu->arch.nmi_pending ||
6646 (kvm_arch_interrupt_allowed(vcpu) &&
6647 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6648}
5736199a 6649
5736199a
ZX		 6650void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6651{
32f88400
MT		 6652 int me;
6653 int cpu = vcpu->cpu;
5736199a
ZX		 6654
6655 if (waitqueue_active(&vcpu->wq)) {
6656 wake_up_interruptible(&vcpu->wq);
6657 ++vcpu->stat.halt_wakeup;
6658 }
32f88400
MT		 6659
6660 me = get_cpu();
6661 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6662 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6663 smp_send_reschedule(cpu);
e9571ed5 6664 put_cpu();
5736199a 6665}
78646121
GN		 6666
6667int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6668{
6669 return kvm_x86_ops->interrupt_allowed(vcpu);
6670}
229456fc 6671
f92653ee
JK		 6672bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6673{
6674 unsigned long current_rip = kvm_rip_read(vcpu) +
6675 get_segment_base(vcpu, VCPU_SREG_CS);
6676
6677 return current_rip == linear_rip;
6678}
6679EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6680
94fe45da
JK		 6681unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6682{
6683 unsigned long rflags;
6684
6685 rflags = kvm_x86_ops->get_rflags(vcpu);
6686 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6687 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6688 return rflags;
6689}
6690EXPORT_SYMBOL_GPL(kvm_get_rflags);
6691
6692void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6693{
6694 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6695 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6696 rflags |= X86_EFLAGS_TF;
94fe45da 6697 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6698 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6699}
6700EXPORT_SYMBOL_GPL(kvm_set_rflags);
6701
56028d08
GN		 6702void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6703{
6704 int r;
6705
fb67e14f 6706 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6707 is_error_page(work->page))
56028d08
GN		 6708 return;
6709
6710 r = kvm_mmu_reload(vcpu);
6711 if (unlikely(r))
6712 return;
6713
fb67e14f
XG		 6714 if (!vcpu->arch.mmu.direct_map &&
6715 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6716 return;
6717
56028d08
GN		 6718 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6719}
6720
af585b92
GN		 6721static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6722{
6723 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6724}
6725
6726static inline u32 kvm_async_pf_next_probe(u32 key)
6727{
6728 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6729}
6730
6731static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6732{
6733 u32 key = kvm_async_pf_hash_fn(gfn);
6734
6735 while (vcpu->arch.apf.gfns[key] != ~0)
6736 key = kvm_async_pf_next_probe(key);
6737
6738 vcpu->arch.apf.gfns[key] = gfn;
6739}
6740
6741static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6742{
6743 int i;
6744 u32 key = kvm_async_pf_hash_fn(gfn);
6745
6746 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6747 (vcpu->arch.apf.gfns[key] != gfn &&
6748 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6749 key = kvm_async_pf_next_probe(key);
6750
6751 return key;
6752}
6753
6754bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6755{
6756 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6757}
6758
6759static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6760{
6761 u32 i, j, k;
6762
6763 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6764 while (true) {
6765 vcpu->arch.apf.gfns[i] = ~0;
6766 do {
6767 j = kvm_async_pf_next_probe(j);
6768 if (vcpu->arch.apf.gfns[j] == ~0)
6769 return;
6770 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6771 /*
6772 * k lies cyclically in ]i,j]
6773 * | i.k.j |
6774 * |....j i.k.| or |.k..j i...|
6775 */
6776 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6777 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6778 i = j;
6779 }
6780}
6781
7c90705b
GN		 6782static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6783{
6784
6785 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6786 sizeof(val));
6787}
6788
af585b92
GN		 6789void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6790 struct kvm_async_pf *work)
6791{
6389ee94
AK		 6792 struct x86_exception fault;
6793
7c90705b 6794 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6795 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6796
6797 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6798 (vcpu->arch.apf.send_user_only &&
6799 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6800 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6801 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6802 fault.vector = PF_VECTOR;
6803 fault.error_code_valid = true;
6804 fault.error_code = 0;
6805 fault.nested_page_fault = false;
6806 fault.address = work->arch.token;
6807 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6808 }
af585b92
GN		 6809}
6810
6811void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6812 struct kvm_async_pf *work)
6813{
6389ee94
AK		 6814 struct x86_exception fault;
6815
7c90705b
GN		 6816 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6817 if (is_error_page(work->page))
6818 work->arch.token = ~0; /* broadcast wakeup */
6819 else
6820 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6821
6822 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6823 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6824 fault.vector = PF_VECTOR;
6825 fault.error_code_valid = true;
6826 fault.error_code = 0;
6827 fault.nested_page_fault = false;
6828 fault.address = work->arch.token;
6829 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6830 }
e6d53e3b 6831 vcpu->arch.apf.halted = false;
7c90705b
GN		 6832}
6833
6834bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6835{
6836 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6837 return true;
6838 else
6839 return !kvm_event_needs_reinjection(vcpu) &&
6840 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6841}
6842
229456fc
MT		 6843EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6844EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6845EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6846EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6847EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6848EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6849EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6850EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6851EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6852EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6853EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6854EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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