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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
9611c187 | 9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
313a3dc7 | 29 | |
18068523 | 30 | #include <linux/clocksource.h> |
4d5c5d0f | 31 | #include <linux/interrupt.h> |
313a3dc7 CO |
32 | #include <linux/kvm.h> |
33 | #include <linux/fs.h> | |
34 | #include <linux/vmalloc.h> | |
5fb76f9b | 35 | #include <linux/module.h> |
0de10343 | 36 | #include <linux/mman.h> |
2bacc55c | 37 | #include <linux/highmem.h> |
19de40a8 | 38 | #include <linux/iommu.h> |
62c476c7 | 39 | #include <linux/intel-iommu.h> |
c8076604 | 40 | #include <linux/cpufreq.h> |
18863bdd | 41 | #include <linux/user-return-notifier.h> |
a983fb23 | 42 | #include <linux/srcu.h> |
5a0e3ad6 | 43 | #include <linux/slab.h> |
ff9d07a0 | 44 | #include <linux/perf_event.h> |
7bee342a | 45 | #include <linux/uaccess.h> |
af585b92 | 46 | #include <linux/hash.h> |
aec51dc4 | 47 | #include <trace/events/kvm.h> |
2ed152af | 48 | |
229456fc MT |
49 | #define CREATE_TRACE_POINTS |
50 | #include "trace.h" | |
043405e1 | 51 | |
24f1e32c | 52 | #include <asm/debugreg.h> |
d825ed0a | 53 | #include <asm/msr.h> |
a5f61300 | 54 | #include <asm/desc.h> |
0bed3b56 | 55 | #include <asm/mtrr.h> |
890ca9ae | 56 | #include <asm/mce.h> |
7cf30855 | 57 | #include <asm/i387.h> |
98918833 | 58 | #include <asm/xcr.h> |
1d5f066e | 59 | #include <asm/pvclock.h> |
217fc9cf | 60 | #include <asm/div64.h> |
043405e1 | 61 | |
313a3dc7 | 62 | #define MAX_IO_MSRS 256 |
a03490ed CO |
63 | #define CR0_RESERVED_BITS \ |
64 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
65 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
66 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
67 | #define CR4_RESERVED_BITS \ | |
68 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
69 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
70 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
2acf923e | 71 | | X86_CR4_OSXSAVE \ |
a03490ed CO |
72 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) |
73 | ||
74 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
890ca9ae HY |
75 | |
76 | #define KVM_MAX_MCE_BANKS 32 | |
5854dbca | 77 | #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) |
890ca9ae | 78 | |
50a37eb4 JR |
79 | /* EFER defaults: |
80 | * - enable syscall per default because its emulated by KVM | |
81 | * - enable LME and LMA per default on 64 bit KVM | |
82 | */ | |
83 | #ifdef CONFIG_X86_64 | |
84 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL; | |
85 | #else | |
86 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL; | |
87 | #endif | |
313a3dc7 | 88 | |
ba1389b7 AK |
89 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
90 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 91 | |
cb142eb7 | 92 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
674eea0f AK |
93 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
94 | struct kvm_cpuid_entry2 __user *entries); | |
95 | ||
97896d04 | 96 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 97 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 98 | |
ed85c068 AP |
99 | int ignore_msrs = 0; |
100 | module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
101 | ||
18863bdd AK |
102 | #define KVM_NR_SHARED_MSRS 16 |
103 | ||
104 | struct kvm_shared_msrs_global { | |
105 | int nr; | |
2bf78fa7 | 106 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
107 | }; |
108 | ||
109 | struct kvm_shared_msrs { | |
110 | struct user_return_notifier urn; | |
111 | bool registered; | |
2bf78fa7 SY |
112 | struct kvm_shared_msr_values { |
113 | u64 host; | |
114 | u64 curr; | |
115 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
116 | }; |
117 | ||
118 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
119 | static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs); | |
120 | ||
417bc304 | 121 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
122 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
123 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
124 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
125 | { "invlpg", VCPU_STAT(invlpg) }, | |
126 | { "exits", VCPU_STAT(exits) }, | |
127 | { "io_exits", VCPU_STAT(io_exits) }, | |
128 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
129 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
130 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 131 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 AK |
132 | { "halt_exits", VCPU_STAT(halt_exits) }, |
133 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
f11c3a8d | 134 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
135 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
136 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
137 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
138 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
139 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
140 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
141 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 142 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 143 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
144 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
145 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
146 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
147 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
148 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
149 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 150 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 151 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 152 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 153 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
154 | { NULL } |
155 | }; | |
156 | ||
2acf923e DC |
157 | u64 __read_mostly host_xcr0; |
158 | ||
af585b92 GN |
159 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
160 | { | |
161 | int i; | |
162 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
163 | vcpu->arch.apf.gfns[i] = ~0; | |
164 | } | |
165 | ||
18863bdd AK |
166 | static void kvm_on_user_return(struct user_return_notifier *urn) |
167 | { | |
168 | unsigned slot; | |
18863bdd AK |
169 | struct kvm_shared_msrs *locals |
170 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 171 | struct kvm_shared_msr_values *values; |
18863bdd AK |
172 | |
173 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
174 | values = &locals->values[slot]; |
175 | if (values->host != values->curr) { | |
176 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
177 | values->curr = values->host; | |
18863bdd AK |
178 | } |
179 | } | |
180 | locals->registered = false; | |
181 | user_return_notifier_unregister(urn); | |
182 | } | |
183 | ||
2bf78fa7 | 184 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 185 | { |
2bf78fa7 | 186 | struct kvm_shared_msrs *smsr; |
18863bdd AK |
187 | u64 value; |
188 | ||
2bf78fa7 SY |
189 | smsr = &__get_cpu_var(shared_msrs); |
190 | /* only read, and nobody should modify it at this time, | |
191 | * so don't need lock */ | |
192 | if (slot >= shared_msrs_global.nr) { | |
193 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
194 | return; | |
195 | } | |
196 | rdmsrl_safe(msr, &value); | |
197 | smsr->values[slot].host = value; | |
198 | smsr->values[slot].curr = value; | |
199 | } | |
200 | ||
201 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
202 | { | |
18863bdd AK |
203 | if (slot >= shared_msrs_global.nr) |
204 | shared_msrs_global.nr = slot + 1; | |
2bf78fa7 SY |
205 | shared_msrs_global.msrs[slot] = msr; |
206 | /* we need ensured the shared_msr_global have been updated */ | |
207 | smp_wmb(); | |
18863bdd AK |
208 | } |
209 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
210 | ||
211 | static void kvm_shared_msr_cpu_online(void) | |
212 | { | |
213 | unsigned i; | |
18863bdd AK |
214 | |
215 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 216 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
217 | } |
218 | ||
d5696725 | 219 | void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd AK |
220 | { |
221 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
222 | ||
2bf78fa7 | 223 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
18863bdd | 224 | return; |
2bf78fa7 SY |
225 | smsr->values[slot].curr = value; |
226 | wrmsrl(shared_msrs_global.msrs[slot], value); | |
18863bdd AK |
227 | if (!smsr->registered) { |
228 | smsr->urn.on_user_return = kvm_on_user_return; | |
229 | user_return_notifier_register(&smsr->urn); | |
230 | smsr->registered = true; | |
231 | } | |
232 | } | |
233 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
234 | ||
3548bab5 AK |
235 | static void drop_user_return_notifiers(void *ignore) |
236 | { | |
237 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
238 | ||
239 | if (smsr->registered) | |
240 | kvm_on_user_return(&smsr->urn); | |
241 | } | |
242 | ||
6866b83e CO |
243 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
244 | { | |
245 | if (irqchip_in_kernel(vcpu->kvm)) | |
ad312c7c | 246 | return vcpu->arch.apic_base; |
6866b83e | 247 | else |
ad312c7c | 248 | return vcpu->arch.apic_base; |
6866b83e CO |
249 | } |
250 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
251 | ||
252 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data) | |
253 | { | |
254 | /* TODO: reserve bits check */ | |
255 | if (irqchip_in_kernel(vcpu->kvm)) | |
256 | kvm_lapic_set_base(vcpu, data); | |
257 | else | |
ad312c7c | 258 | vcpu->arch.apic_base = data; |
6866b83e CO |
259 | } |
260 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
261 | ||
3fd28fce ED |
262 | #define EXCPT_BENIGN 0 |
263 | #define EXCPT_CONTRIBUTORY 1 | |
264 | #define EXCPT_PF 2 | |
265 | ||
266 | static int exception_class(int vector) | |
267 | { | |
268 | switch (vector) { | |
269 | case PF_VECTOR: | |
270 | return EXCPT_PF; | |
271 | case DE_VECTOR: | |
272 | case TS_VECTOR: | |
273 | case NP_VECTOR: | |
274 | case SS_VECTOR: | |
275 | case GP_VECTOR: | |
276 | return EXCPT_CONTRIBUTORY; | |
277 | default: | |
278 | break; | |
279 | } | |
280 | return EXCPT_BENIGN; | |
281 | } | |
282 | ||
283 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, | |
ce7ddec4 JR |
284 | unsigned nr, bool has_error, u32 error_code, |
285 | bool reinject) | |
3fd28fce ED |
286 | { |
287 | u32 prev_nr; | |
288 | int class1, class2; | |
289 | ||
3842d135 AK |
290 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
291 | ||
3fd28fce ED |
292 | if (!vcpu->arch.exception.pending) { |
293 | queue: | |
294 | vcpu->arch.exception.pending = true; | |
295 | vcpu->arch.exception.has_error_code = has_error; | |
296 | vcpu->arch.exception.nr = nr; | |
297 | vcpu->arch.exception.error_code = error_code; | |
3f0fd292 | 298 | vcpu->arch.exception.reinject = reinject; |
3fd28fce ED |
299 | return; |
300 | } | |
301 | ||
302 | /* to check exception */ | |
303 | prev_nr = vcpu->arch.exception.nr; | |
304 | if (prev_nr == DF_VECTOR) { | |
305 | /* triple fault -> shutdown */ | |
a8eeb04a | 306 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
307 | return; |
308 | } | |
309 | class1 = exception_class(prev_nr); | |
310 | class2 = exception_class(nr); | |
311 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
312 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
313 | /* generate double fault per SDM Table 5-5 */ | |
314 | vcpu->arch.exception.pending = true; | |
315 | vcpu->arch.exception.has_error_code = true; | |
316 | vcpu->arch.exception.nr = DF_VECTOR; | |
317 | vcpu->arch.exception.error_code = 0; | |
318 | } else | |
319 | /* replace previous exception with a new one in a hope | |
320 | that instruction re-execution will regenerate lost | |
321 | exception */ | |
322 | goto queue; | |
323 | } | |
324 | ||
298101da AK |
325 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
326 | { | |
ce7ddec4 | 327 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
328 | } |
329 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
330 | ||
ce7ddec4 JR |
331 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
332 | { | |
333 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
334 | } | |
335 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
336 | ||
8df25a32 | 337 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu) |
c3c91fee | 338 | { |
8df25a32 JR |
339 | unsigned error_code = vcpu->arch.fault.error_code; |
340 | ||
c3c91fee | 341 | ++vcpu->stat.pf_guest; |
8df25a32 | 342 | vcpu->arch.cr2 = vcpu->arch.fault.address; |
c3c91fee AK |
343 | kvm_queue_exception_e(vcpu, PF_VECTOR, error_code); |
344 | } | |
345 | ||
d4f8cf66 JR |
346 | void kvm_propagate_fault(struct kvm_vcpu *vcpu) |
347 | { | |
0959ffac | 348 | if (mmu_is_nested(vcpu) && !vcpu->arch.fault.nested) |
d4f8cf66 JR |
349 | vcpu->arch.nested_mmu.inject_page_fault(vcpu); |
350 | else | |
351 | vcpu->arch.mmu.inject_page_fault(vcpu); | |
0959ffac JR |
352 | |
353 | vcpu->arch.fault.nested = false; | |
d4f8cf66 JR |
354 | } |
355 | ||
3419ffc8 SY |
356 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
357 | { | |
3842d135 | 358 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3419ffc8 SY |
359 | vcpu->arch.nmi_pending = 1; |
360 | } | |
361 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
362 | ||
298101da AK |
363 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
364 | { | |
ce7ddec4 | 365 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
366 | } |
367 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
368 | ||
ce7ddec4 JR |
369 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
370 | { | |
371 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
372 | } | |
373 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
374 | ||
0a79b009 AK |
375 | /* |
376 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
377 | * a #GP and return false. | |
378 | */ | |
379 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 380 | { |
0a79b009 AK |
381 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
382 | return true; | |
383 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
384 | return false; | |
298101da | 385 | } |
0a79b009 | 386 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 387 | |
ec92fe44 JR |
388 | /* |
389 | * This function will be used to read from the physical memory of the currently | |
390 | * running guest. The difference to kvm_read_guest_page is that this function | |
391 | * can read from guest physical or from the guest's guest physical memory. | |
392 | */ | |
393 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
394 | gfn_t ngfn, void *data, int offset, int len, | |
395 | u32 access) | |
396 | { | |
397 | gfn_t real_gfn; | |
398 | gpa_t ngpa; | |
399 | ||
400 | ngpa = gfn_to_gpa(ngfn); | |
401 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access); | |
402 | if (real_gfn == UNMAPPED_GVA) | |
403 | return -EFAULT; | |
404 | ||
405 | real_gfn = gpa_to_gfn(real_gfn); | |
406 | ||
407 | return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); | |
408 | } | |
409 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
410 | ||
3d06b8bf JR |
411 | int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
412 | void *data, int offset, int len, u32 access) | |
413 | { | |
414 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
415 | data, offset, len, access); | |
416 | } | |
417 | ||
a03490ed CO |
418 | /* |
419 | * Load the pae pdptrs. Return true is they are all valid. | |
420 | */ | |
ff03a073 | 421 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
422 | { |
423 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
424 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
425 | int i; | |
426 | int ret; | |
ff03a073 | 427 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 428 | |
ff03a073 JR |
429 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
430 | offset * sizeof(u64), sizeof(pdpte), | |
431 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
432 | if (ret < 0) { |
433 | ret = 0; | |
434 | goto out; | |
435 | } | |
436 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 437 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 438 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
439 | ret = 0; |
440 | goto out; | |
441 | } | |
442 | } | |
443 | ret = 1; | |
444 | ||
ff03a073 | 445 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
446 | __set_bit(VCPU_EXREG_PDPTR, |
447 | (unsigned long *)&vcpu->arch.regs_avail); | |
448 | __set_bit(VCPU_EXREG_PDPTR, | |
449 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 450 | out: |
a03490ed CO |
451 | |
452 | return ret; | |
453 | } | |
cc4b6871 | 454 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 455 | |
d835dfec AK |
456 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
457 | { | |
ff03a073 | 458 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 459 | bool changed = true; |
3d06b8bf JR |
460 | int offset; |
461 | gfn_t gfn; | |
d835dfec AK |
462 | int r; |
463 | ||
464 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
465 | return false; | |
466 | ||
6de4f3ad AK |
467 | if (!test_bit(VCPU_EXREG_PDPTR, |
468 | (unsigned long *)&vcpu->arch.regs_avail)) | |
469 | return true; | |
470 | ||
3d06b8bf JR |
471 | gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT; |
472 | offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1); | |
473 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), | |
474 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
475 | if (r < 0) |
476 | goto out; | |
ff03a073 | 477 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 478 | out: |
d835dfec AK |
479 | |
480 | return changed; | |
481 | } | |
482 | ||
49a9b07e | 483 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 484 | { |
aad82703 SY |
485 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
486 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | | |
487 | X86_CR0_CD | X86_CR0_NW; | |
488 | ||
f9a48e6a AK |
489 | cr0 |= X86_CR0_ET; |
490 | ||
ab344828 | 491 | #ifdef CONFIG_X86_64 |
0f12244f GN |
492 | if (cr0 & 0xffffffff00000000UL) |
493 | return 1; | |
ab344828 GN |
494 | #endif |
495 | ||
496 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 497 | |
0f12244f GN |
498 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
499 | return 1; | |
a03490ed | 500 | |
0f12244f GN |
501 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
502 | return 1; | |
a03490ed CO |
503 | |
504 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
505 | #ifdef CONFIG_X86_64 | |
f6801dff | 506 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
507 | int cs_db, cs_l; |
508 | ||
0f12244f GN |
509 | if (!is_pae(vcpu)) |
510 | return 1; | |
a03490ed | 511 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
512 | if (cs_l) |
513 | return 1; | |
a03490ed CO |
514 | } else |
515 | #endif | |
ff03a073 JR |
516 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
517 | vcpu->arch.cr3)) | |
0f12244f | 518 | return 1; |
a03490ed CO |
519 | } |
520 | ||
521 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
a03490ed | 522 | |
aad82703 SY |
523 | if ((cr0 ^ old_cr0) & update_bits) |
524 | kvm_mmu_reset_context(vcpu); | |
0f12244f GN |
525 | return 0; |
526 | } | |
2d3ad1f4 | 527 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 528 | |
2d3ad1f4 | 529 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 530 | { |
49a9b07e | 531 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 532 | } |
2d3ad1f4 | 533 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 534 | |
2acf923e DC |
535 | int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
536 | { | |
537 | u64 xcr0; | |
538 | ||
539 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
540 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
541 | return 1; | |
542 | xcr0 = xcr; | |
543 | if (kvm_x86_ops->get_cpl(vcpu) != 0) | |
544 | return 1; | |
545 | if (!(xcr0 & XSTATE_FP)) | |
546 | return 1; | |
547 | if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) | |
548 | return 1; | |
549 | if (xcr0 & ~host_xcr0) | |
550 | return 1; | |
551 | vcpu->arch.xcr0 = xcr0; | |
552 | vcpu->guest_xcr0_loaded = 0; | |
553 | return 0; | |
554 | } | |
555 | ||
556 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
557 | { | |
558 | if (__kvm_set_xcr(vcpu, index, xcr)) { | |
559 | kvm_inject_gp(vcpu, 0); | |
560 | return 1; | |
561 | } | |
562 | return 0; | |
563 | } | |
564 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
565 | ||
566 | static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu) | |
567 | { | |
568 | struct kvm_cpuid_entry2 *best; | |
569 | ||
570 | best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
571 | return best && (best->ecx & bit(X86_FEATURE_XSAVE)); | |
572 | } | |
573 | ||
574 | static void update_cpuid(struct kvm_vcpu *vcpu) | |
575 | { | |
576 | struct kvm_cpuid_entry2 *best; | |
577 | ||
578 | best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
579 | if (!best) | |
580 | return; | |
581 | ||
582 | /* Update OSXSAVE bit */ | |
583 | if (cpu_has_xsave && best->function == 0x1) { | |
584 | best->ecx &= ~(bit(X86_FEATURE_OSXSAVE)); | |
585 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) | |
586 | best->ecx |= bit(X86_FEATURE_OSXSAVE); | |
587 | } | |
588 | } | |
589 | ||
a83b29c6 | 590 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 591 | { |
fc78f519 | 592 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
a2edf57f AK |
593 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE; |
594 | ||
0f12244f GN |
595 | if (cr4 & CR4_RESERVED_BITS) |
596 | return 1; | |
a03490ed | 597 | |
2acf923e DC |
598 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) |
599 | return 1; | |
600 | ||
a03490ed | 601 | if (is_long_mode(vcpu)) { |
0f12244f GN |
602 | if (!(cr4 & X86_CR4_PAE)) |
603 | return 1; | |
a2edf57f AK |
604 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
605 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
ff03a073 | 606 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3)) |
0f12244f GN |
607 | return 1; |
608 | ||
609 | if (cr4 & X86_CR4_VMXE) | |
610 | return 1; | |
a03490ed | 611 | |
a03490ed | 612 | kvm_x86_ops->set_cr4(vcpu, cr4); |
62ad0755 | 613 | |
aad82703 SY |
614 | if ((cr4 ^ old_cr4) & pdptr_bits) |
615 | kvm_mmu_reset_context(vcpu); | |
0f12244f | 616 | |
2acf923e DC |
617 | if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) |
618 | update_cpuid(vcpu); | |
619 | ||
0f12244f GN |
620 | return 0; |
621 | } | |
2d3ad1f4 | 622 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 623 | |
2390218b | 624 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 625 | { |
ad312c7c | 626 | if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) { |
0ba73cda | 627 | kvm_mmu_sync_roots(vcpu); |
d835dfec | 628 | kvm_mmu_flush_tlb(vcpu); |
0f12244f | 629 | return 0; |
d835dfec AK |
630 | } |
631 | ||
a03490ed | 632 | if (is_long_mode(vcpu)) { |
0f12244f GN |
633 | if (cr3 & CR3_L_MODE_RESERVED_BITS) |
634 | return 1; | |
a03490ed CO |
635 | } else { |
636 | if (is_pae(vcpu)) { | |
0f12244f GN |
637 | if (cr3 & CR3_PAE_RESERVED_BITS) |
638 | return 1; | |
ff03a073 JR |
639 | if (is_paging(vcpu) && |
640 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
0f12244f | 641 | return 1; |
a03490ed CO |
642 | } |
643 | /* | |
644 | * We don't check reserved bits in nonpae mode, because | |
645 | * this isn't enforced, and VMware depends on this. | |
646 | */ | |
647 | } | |
648 | ||
a03490ed CO |
649 | /* |
650 | * Does the new cr3 value map to physical memory? (Note, we | |
651 | * catch an invalid cr3 even in real-mode, because it would | |
652 | * cause trouble later on when we turn on paging anyway.) | |
653 | * | |
654 | * A real CPU would silently accept an invalid cr3 and would | |
655 | * attempt to use it - with largely undefined (and often hard | |
656 | * to debug) behavior on the guest side. | |
657 | */ | |
658 | if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT))) | |
0f12244f GN |
659 | return 1; |
660 | vcpu->arch.cr3 = cr3; | |
661 | vcpu->arch.mmu.new_cr3(vcpu); | |
662 | return 0; | |
663 | } | |
2d3ad1f4 | 664 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 665 | |
0f12244f | 666 | int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 667 | { |
0f12244f GN |
668 | if (cr8 & CR8_RESERVED_BITS) |
669 | return 1; | |
a03490ed CO |
670 | if (irqchip_in_kernel(vcpu->kvm)) |
671 | kvm_lapic_set_tpr(vcpu, cr8); | |
672 | else | |
ad312c7c | 673 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
674 | return 0; |
675 | } | |
676 | ||
677 | void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) | |
678 | { | |
679 | if (__kvm_set_cr8(vcpu, cr8)) | |
680 | kvm_inject_gp(vcpu, 0); | |
a03490ed | 681 | } |
2d3ad1f4 | 682 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 683 | |
2d3ad1f4 | 684 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
685 | { |
686 | if (irqchip_in_kernel(vcpu->kvm)) | |
687 | return kvm_lapic_get_cr8(vcpu); | |
688 | else | |
ad312c7c | 689 | return vcpu->arch.cr8; |
a03490ed | 690 | } |
2d3ad1f4 | 691 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 692 | |
338dbc97 | 693 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
694 | { |
695 | switch (dr) { | |
696 | case 0 ... 3: | |
697 | vcpu->arch.db[dr] = val; | |
698 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
699 | vcpu->arch.eff_db[dr] = val; | |
700 | break; | |
701 | case 4: | |
338dbc97 GN |
702 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
703 | return 1; /* #UD */ | |
020df079 GN |
704 | /* fall through */ |
705 | case 6: | |
338dbc97 GN |
706 | if (val & 0xffffffff00000000ULL) |
707 | return -1; /* #GP */ | |
020df079 GN |
708 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1; |
709 | break; | |
710 | case 5: | |
338dbc97 GN |
711 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
712 | return 1; /* #UD */ | |
020df079 GN |
713 | /* fall through */ |
714 | default: /* 7 */ | |
338dbc97 GN |
715 | if (val & 0xffffffff00000000ULL) |
716 | return -1; /* #GP */ | |
020df079 GN |
717 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
718 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
719 | kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7); | |
720 | vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK); | |
721 | } | |
722 | break; | |
723 | } | |
724 | ||
725 | return 0; | |
726 | } | |
338dbc97 GN |
727 | |
728 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
729 | { | |
730 | int res; | |
731 | ||
732 | res = __kvm_set_dr(vcpu, dr, val); | |
733 | if (res > 0) | |
734 | kvm_queue_exception(vcpu, UD_VECTOR); | |
735 | else if (res < 0) | |
736 | kvm_inject_gp(vcpu, 0); | |
737 | ||
738 | return res; | |
739 | } | |
020df079 GN |
740 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
741 | ||
338dbc97 | 742 | static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
743 | { |
744 | switch (dr) { | |
745 | case 0 ... 3: | |
746 | *val = vcpu->arch.db[dr]; | |
747 | break; | |
748 | case 4: | |
338dbc97 | 749 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 750 | return 1; |
020df079 GN |
751 | /* fall through */ |
752 | case 6: | |
753 | *val = vcpu->arch.dr6; | |
754 | break; | |
755 | case 5: | |
338dbc97 | 756 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 757 | return 1; |
020df079 GN |
758 | /* fall through */ |
759 | default: /* 7 */ | |
760 | *val = vcpu->arch.dr7; | |
761 | break; | |
762 | } | |
763 | ||
764 | return 0; | |
765 | } | |
338dbc97 GN |
766 | |
767 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) | |
768 | { | |
769 | if (_kvm_get_dr(vcpu, dr, val)) { | |
770 | kvm_queue_exception(vcpu, UD_VECTOR); | |
771 | return 1; | |
772 | } | |
773 | return 0; | |
774 | } | |
020df079 GN |
775 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
776 | ||
043405e1 CO |
777 | /* |
778 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
779 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
780 | * | |
781 | * This list is modified at module load time to reflect the | |
e3267cbb GC |
782 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
783 | * kvm-specific. Those are put in the beginning of the list. | |
043405e1 | 784 | */ |
e3267cbb | 785 | |
344d9588 | 786 | #define KVM_SAVE_MSRS_BEGIN 8 |
043405e1 | 787 | static u32 msrs_to_save[] = { |
e3267cbb | 788 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
11c6bffa | 789 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, |
55cd8e5a | 790 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, |
344d9588 | 791 | HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, |
043405e1 | 792 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 793 | MSR_STAR, |
043405e1 CO |
794 | #ifdef CONFIG_X86_64 |
795 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
796 | #endif | |
e90aa41e | 797 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA |
043405e1 CO |
798 | }; |
799 | ||
800 | static unsigned num_msrs_to_save; | |
801 | ||
802 | static u32 emulated_msrs[] = { | |
803 | MSR_IA32_MISC_ENABLE, | |
908e75f3 AK |
804 | MSR_IA32_MCG_STATUS, |
805 | MSR_IA32_MCG_CTL, | |
043405e1 CO |
806 | }; |
807 | ||
b69e8cae | 808 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 809 | { |
aad82703 SY |
810 | u64 old_efer = vcpu->arch.efer; |
811 | ||
b69e8cae RJ |
812 | if (efer & efer_reserved_bits) |
813 | return 1; | |
15c4a640 CO |
814 | |
815 | if (is_paging(vcpu) | |
b69e8cae RJ |
816 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) |
817 | return 1; | |
15c4a640 | 818 | |
1b2fd70c AG |
819 | if (efer & EFER_FFXSR) { |
820 | struct kvm_cpuid_entry2 *feat; | |
821 | ||
822 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae RJ |
823 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) |
824 | return 1; | |
1b2fd70c AG |
825 | } |
826 | ||
d8017474 AG |
827 | if (efer & EFER_SVME) { |
828 | struct kvm_cpuid_entry2 *feat; | |
829 | ||
830 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae RJ |
831 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) |
832 | return 1; | |
d8017474 AG |
833 | } |
834 | ||
15c4a640 | 835 | efer &= ~EFER_LMA; |
f6801dff | 836 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 837 | |
a3d204e2 SY |
838 | kvm_x86_ops->set_efer(vcpu, efer); |
839 | ||
9645bb56 | 840 | vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled; |
b69e8cae | 841 | |
aad82703 SY |
842 | /* Update reserved bits */ |
843 | if ((efer ^ old_efer) & EFER_NX) | |
844 | kvm_mmu_reset_context(vcpu); | |
845 | ||
b69e8cae | 846 | return 0; |
15c4a640 CO |
847 | } |
848 | ||
f2b4b7dd JR |
849 | void kvm_enable_efer_bits(u64 mask) |
850 | { | |
851 | efer_reserved_bits &= ~mask; | |
852 | } | |
853 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
854 | ||
855 | ||
15c4a640 CO |
856 | /* |
857 | * Writes msr value into into the appropriate "register". | |
858 | * Returns 0 on success, non-0 otherwise. | |
859 | * Assumes vcpu_load() was already called. | |
860 | */ | |
861 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
862 | { | |
863 | return kvm_x86_ops->set_msr(vcpu, msr_index, data); | |
864 | } | |
865 | ||
313a3dc7 CO |
866 | /* |
867 | * Adapt set_msr() to msr_io()'s calling convention | |
868 | */ | |
869 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
870 | { | |
871 | return kvm_set_msr(vcpu, index, *data); | |
872 | } | |
873 | ||
18068523 GOC |
874 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
875 | { | |
9ed3c444 AK |
876 | int version; |
877 | int r; | |
50d0a0f9 | 878 | struct pvclock_wall_clock wc; |
923de3cf | 879 | struct timespec boot; |
18068523 GOC |
880 | |
881 | if (!wall_clock) | |
882 | return; | |
883 | ||
9ed3c444 AK |
884 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
885 | if (r) | |
886 | return; | |
887 | ||
888 | if (version & 1) | |
889 | ++version; /* first time write, random junk */ | |
890 | ||
891 | ++version; | |
18068523 | 892 | |
18068523 GOC |
893 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
894 | ||
50d0a0f9 GH |
895 | /* |
896 | * The guest calculates current wall clock time by adding | |
34c238a1 | 897 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
898 | * wall clock specified here. guest system time equals host |
899 | * system time for us, thus we must fill in host boot time here. | |
900 | */ | |
923de3cf | 901 | getboottime(&boot); |
50d0a0f9 GH |
902 | |
903 | wc.sec = boot.tv_sec; | |
904 | wc.nsec = boot.tv_nsec; | |
905 | wc.version = version; | |
18068523 GOC |
906 | |
907 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
908 | ||
909 | version++; | |
910 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
911 | } |
912 | ||
50d0a0f9 GH |
913 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
914 | { | |
915 | uint32_t quotient, remainder; | |
916 | ||
917 | /* Don't try to replace with do_div(), this one calculates | |
918 | * "(dividend << 32) / divisor" */ | |
919 | __asm__ ( "divl %4" | |
920 | : "=a" (quotient), "=d" (remainder) | |
921 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
922 | return quotient; | |
923 | } | |
924 | ||
5f4e3f88 ZA |
925 | static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, |
926 | s8 *pshift, u32 *pmultiplier) | |
50d0a0f9 | 927 | { |
5f4e3f88 | 928 | uint64_t scaled64; |
50d0a0f9 GH |
929 | int32_t shift = 0; |
930 | uint64_t tps64; | |
931 | uint32_t tps32; | |
932 | ||
5f4e3f88 ZA |
933 | tps64 = base_khz * 1000LL; |
934 | scaled64 = scaled_khz * 1000LL; | |
50933623 | 935 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
936 | tps64 >>= 1; |
937 | shift--; | |
938 | } | |
939 | ||
940 | tps32 = (uint32_t)tps64; | |
50933623 JK |
941 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
942 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
943 | scaled64 >>= 1; |
944 | else | |
945 | tps32 <<= 1; | |
50d0a0f9 GH |
946 | shift++; |
947 | } | |
948 | ||
5f4e3f88 ZA |
949 | *pshift = shift; |
950 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 | 951 | |
5f4e3f88 ZA |
952 | pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", |
953 | __func__, base_khz, scaled_khz, shift, *pmultiplier); | |
50d0a0f9 GH |
954 | } |
955 | ||
759379dd ZA |
956 | static inline u64 get_kernel_ns(void) |
957 | { | |
958 | struct timespec ts; | |
959 | ||
960 | WARN_ON(preemptible()); | |
961 | ktime_get_ts(&ts); | |
962 | monotonic_to_bootbased(&ts); | |
963 | return timespec_to_ns(&ts); | |
50d0a0f9 GH |
964 | } |
965 | ||
c8076604 | 966 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
c285545f | 967 | unsigned long max_tsc_khz; |
c8076604 | 968 | |
8cfdc000 ZA |
969 | static inline int kvm_tsc_changes_freq(void) |
970 | { | |
971 | int cpu = get_cpu(); | |
972 | int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) && | |
973 | cpufreq_quick_get(cpu) != 0; | |
974 | put_cpu(); | |
975 | return ret; | |
976 | } | |
977 | ||
759379dd ZA |
978 | static inline u64 nsec_to_cycles(u64 nsec) |
979 | { | |
217fc9cf AK |
980 | u64 ret; |
981 | ||
759379dd ZA |
982 | WARN_ON(preemptible()); |
983 | if (kvm_tsc_changes_freq()) | |
984 | printk_once(KERN_WARNING | |
985 | "kvm: unreliable cycle conversion on adjustable rate TSC\n"); | |
217fc9cf AK |
986 | ret = nsec * __get_cpu_var(cpu_tsc_khz); |
987 | do_div(ret, USEC_PER_SEC); | |
988 | return ret; | |
759379dd ZA |
989 | } |
990 | ||
c285545f ZA |
991 | static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz) |
992 | { | |
993 | /* Compute a scale to convert nanoseconds in TSC cycles */ | |
994 | kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, | |
995 | &kvm->arch.virtual_tsc_shift, | |
996 | &kvm->arch.virtual_tsc_mult); | |
997 | kvm->arch.virtual_tsc_khz = this_tsc_khz; | |
998 | } | |
999 | ||
1000 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1001 | { | |
1002 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec, | |
1003 | vcpu->kvm->arch.virtual_tsc_mult, | |
1004 | vcpu->kvm->arch.virtual_tsc_shift); | |
1005 | tsc += vcpu->arch.last_tsc_write; | |
1006 | return tsc; | |
1007 | } | |
1008 | ||
99e3e30a ZA |
1009 | void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data) |
1010 | { | |
1011 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1012 | u64 offset, ns, elapsed; |
99e3e30a | 1013 | unsigned long flags; |
46543ba4 | 1014 | s64 sdiff; |
99e3e30a ZA |
1015 | |
1016 | spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); | |
1017 | offset = data - native_read_tsc(); | |
759379dd | 1018 | ns = get_kernel_ns(); |
f38e098f | 1019 | elapsed = ns - kvm->arch.last_tsc_nsec; |
46543ba4 ZA |
1020 | sdiff = data - kvm->arch.last_tsc_write; |
1021 | if (sdiff < 0) | |
1022 | sdiff = -sdiff; | |
f38e098f ZA |
1023 | |
1024 | /* | |
46543ba4 | 1025 | * Special case: close write to TSC within 5 seconds of |
f38e098f | 1026 | * another CPU is interpreted as an attempt to synchronize |
46543ba4 ZA |
1027 | * The 5 seconds is to accomodate host load / swapping as |
1028 | * well as any reset of TSC during the boot process. | |
f38e098f ZA |
1029 | * |
1030 | * In that case, for a reliable TSC, we can match TSC offsets, | |
46543ba4 | 1031 | * or make a best guest using elapsed value. |
f38e098f | 1032 | */ |
46543ba4 ZA |
1033 | if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) && |
1034 | elapsed < 5ULL * NSEC_PER_SEC) { | |
f38e098f ZA |
1035 | if (!check_tsc_unstable()) { |
1036 | offset = kvm->arch.last_tsc_offset; | |
1037 | pr_debug("kvm: matched tsc offset for %llu\n", data); | |
1038 | } else { | |
759379dd ZA |
1039 | u64 delta = nsec_to_cycles(elapsed); |
1040 | offset += delta; | |
1041 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); | |
f38e098f ZA |
1042 | } |
1043 | ns = kvm->arch.last_tsc_nsec; | |
1044 | } | |
1045 | kvm->arch.last_tsc_nsec = ns; | |
1046 | kvm->arch.last_tsc_write = data; | |
1047 | kvm->arch.last_tsc_offset = offset; | |
99e3e30a ZA |
1048 | kvm_x86_ops->write_tsc_offset(vcpu, offset); |
1049 | spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
1050 | ||
1051 | /* Reset of TSC must disable overshoot protection below */ | |
1052 | vcpu->arch.hv_clock.tsc_timestamp = 0; | |
c285545f ZA |
1053 | vcpu->arch.last_tsc_write = data; |
1054 | vcpu->arch.last_tsc_nsec = ns; | |
99e3e30a ZA |
1055 | } |
1056 | EXPORT_SYMBOL_GPL(kvm_write_tsc); | |
1057 | ||
34c238a1 | 1058 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 1059 | { |
18068523 GOC |
1060 | unsigned long flags; |
1061 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
1062 | void *shared_kaddr; | |
463656c0 | 1063 | unsigned long this_tsc_khz; |
1d5f066e ZA |
1064 | s64 kernel_ns, max_kernel_ns; |
1065 | u64 tsc_timestamp; | |
18068523 | 1066 | |
18068523 GOC |
1067 | /* Keep irq disabled to prevent changes to the clock */ |
1068 | local_irq_save(flags); | |
1d5f066e | 1069 | kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp); |
759379dd | 1070 | kernel_ns = get_kernel_ns(); |
8cfdc000 | 1071 | this_tsc_khz = __get_cpu_var(cpu_tsc_khz); |
18068523 | 1072 | |
8cfdc000 | 1073 | if (unlikely(this_tsc_khz == 0)) { |
c285545f | 1074 | local_irq_restore(flags); |
34c238a1 | 1075 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
8cfdc000 ZA |
1076 | return 1; |
1077 | } | |
18068523 | 1078 | |
c285545f ZA |
1079 | /* |
1080 | * We may have to catch up the TSC to match elapsed wall clock | |
1081 | * time for two reasons, even if kvmclock is used. | |
1082 | * 1) CPU could have been running below the maximum TSC rate | |
1083 | * 2) Broken TSC compensation resets the base at each VCPU | |
1084 | * entry to avoid unknown leaps of TSC even when running | |
1085 | * again on the same CPU. This may cause apparent elapsed | |
1086 | * time to disappear, and the guest to stand still or run | |
1087 | * very slowly. | |
1088 | */ | |
1089 | if (vcpu->tsc_catchup) { | |
1090 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
1091 | if (tsc > tsc_timestamp) { | |
1092 | kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp); | |
1093 | tsc_timestamp = tsc; | |
1094 | } | |
50d0a0f9 GH |
1095 | } |
1096 | ||
18068523 GOC |
1097 | local_irq_restore(flags); |
1098 | ||
c285545f ZA |
1099 | if (!vcpu->time_page) |
1100 | return 0; | |
18068523 | 1101 | |
1d5f066e ZA |
1102 | /* |
1103 | * Time as measured by the TSC may go backwards when resetting the base | |
1104 | * tsc_timestamp. The reason for this is that the TSC resolution is | |
1105 | * higher than the resolution of the other clock scales. Thus, many | |
1106 | * possible measurments of the TSC correspond to one measurement of any | |
1107 | * other clock, and so a spread of values is possible. This is not a | |
1108 | * problem for the computation of the nanosecond clock; with TSC rates | |
1109 | * around 1GHZ, there can only be a few cycles which correspond to one | |
1110 | * nanosecond value, and any path through this code will inevitably | |
1111 | * take longer than that. However, with the kernel_ns value itself, | |
1112 | * the precision may be much lower, down to HZ granularity. If the | |
1113 | * first sampling of TSC against kernel_ns ends in the low part of the | |
1114 | * range, and the second in the high end of the range, we can get: | |
1115 | * | |
1116 | * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new | |
1117 | * | |
1118 | * As the sampling errors potentially range in the thousands of cycles, | |
1119 | * it is possible such a time value has already been observed by the | |
1120 | * guest. To protect against this, we must compute the system time as | |
1121 | * observed by the guest and ensure the new system time is greater. | |
1122 | */ | |
1123 | max_kernel_ns = 0; | |
1124 | if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) { | |
1125 | max_kernel_ns = vcpu->last_guest_tsc - | |
1126 | vcpu->hv_clock.tsc_timestamp; | |
1127 | max_kernel_ns = pvclock_scale_delta(max_kernel_ns, | |
1128 | vcpu->hv_clock.tsc_to_system_mul, | |
1129 | vcpu->hv_clock.tsc_shift); | |
1130 | max_kernel_ns += vcpu->last_kernel_ns; | |
1131 | } | |
afbcf7ab | 1132 | |
e48672fa | 1133 | if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { |
5f4e3f88 ZA |
1134 | kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, |
1135 | &vcpu->hv_clock.tsc_shift, | |
1136 | &vcpu->hv_clock.tsc_to_system_mul); | |
e48672fa | 1137 | vcpu->hw_tsc_khz = this_tsc_khz; |
8cfdc000 ZA |
1138 | } |
1139 | ||
1d5f066e ZA |
1140 | if (max_kernel_ns > kernel_ns) |
1141 | kernel_ns = max_kernel_ns; | |
1142 | ||
8cfdc000 | 1143 | /* With all the info we got, fill in the values */ |
1d5f066e | 1144 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 1145 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
1d5f066e | 1146 | vcpu->last_kernel_ns = kernel_ns; |
28e4639a | 1147 | vcpu->last_guest_tsc = tsc_timestamp; |
371bcf64 GC |
1148 | vcpu->hv_clock.flags = 0; |
1149 | ||
18068523 GOC |
1150 | /* |
1151 | * The interface expects us to write an even number signaling that the | |
1152 | * update is finished. Since the guest won't see the intermediate | |
50d0a0f9 | 1153 | * state, we just increase by 2 at the end. |
18068523 | 1154 | */ |
50d0a0f9 | 1155 | vcpu->hv_clock.version += 2; |
18068523 GOC |
1156 | |
1157 | shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0); | |
1158 | ||
1159 | memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock, | |
50d0a0f9 | 1160 | sizeof(vcpu->hv_clock)); |
18068523 GOC |
1161 | |
1162 | kunmap_atomic(shared_kaddr, KM_USER0); | |
1163 | ||
1164 | mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT); | |
8cfdc000 | 1165 | return 0; |
c8076604 GH |
1166 | } |
1167 | ||
9ba075a6 AK |
1168 | static bool msr_mtrr_valid(unsigned msr) |
1169 | { | |
1170 | switch (msr) { | |
1171 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
1172 | case MSR_MTRRfix64K_00000: | |
1173 | case MSR_MTRRfix16K_80000: | |
1174 | case MSR_MTRRfix16K_A0000: | |
1175 | case MSR_MTRRfix4K_C0000: | |
1176 | case MSR_MTRRfix4K_C8000: | |
1177 | case MSR_MTRRfix4K_D0000: | |
1178 | case MSR_MTRRfix4K_D8000: | |
1179 | case MSR_MTRRfix4K_E0000: | |
1180 | case MSR_MTRRfix4K_E8000: | |
1181 | case MSR_MTRRfix4K_F0000: | |
1182 | case MSR_MTRRfix4K_F8000: | |
1183 | case MSR_MTRRdefType: | |
1184 | case MSR_IA32_CR_PAT: | |
1185 | return true; | |
1186 | case 0x2f8: | |
1187 | return true; | |
1188 | } | |
1189 | return false; | |
1190 | } | |
1191 | ||
d6289b93 MT |
1192 | static bool valid_pat_type(unsigned t) |
1193 | { | |
1194 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
1195 | } | |
1196 | ||
1197 | static bool valid_mtrr_type(unsigned t) | |
1198 | { | |
1199 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
1200 | } | |
1201 | ||
1202 | static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1203 | { | |
1204 | int i; | |
1205 | ||
1206 | if (!msr_mtrr_valid(msr)) | |
1207 | return false; | |
1208 | ||
1209 | if (msr == MSR_IA32_CR_PAT) { | |
1210 | for (i = 0; i < 8; i++) | |
1211 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
1212 | return false; | |
1213 | return true; | |
1214 | } else if (msr == MSR_MTRRdefType) { | |
1215 | if (data & ~0xcff) | |
1216 | return false; | |
1217 | return valid_mtrr_type(data & 0xff); | |
1218 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
1219 | for (i = 0; i < 8 ; i++) | |
1220 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
1221 | return false; | |
1222 | return true; | |
1223 | } | |
1224 | ||
1225 | /* variable MTRRs */ | |
1226 | return valid_mtrr_type(data & 0xff); | |
1227 | } | |
1228 | ||
9ba075a6 AK |
1229 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1230 | { | |
0bed3b56 SY |
1231 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1232 | ||
d6289b93 | 1233 | if (!mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
1234 | return 1; |
1235 | ||
0bed3b56 SY |
1236 | if (msr == MSR_MTRRdefType) { |
1237 | vcpu->arch.mtrr_state.def_type = data; | |
1238 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
1239 | } else if (msr == MSR_MTRRfix64K_00000) | |
1240 | p[0] = data; | |
1241 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1242 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
1243 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1244 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
1245 | else if (msr == MSR_IA32_CR_PAT) | |
1246 | vcpu->arch.pat = data; | |
1247 | else { /* Variable MTRRs */ | |
1248 | int idx, is_mtrr_mask; | |
1249 | u64 *pt; | |
1250 | ||
1251 | idx = (msr - 0x200) / 2; | |
1252 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1253 | if (!is_mtrr_mask) | |
1254 | pt = | |
1255 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1256 | else | |
1257 | pt = | |
1258 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1259 | *pt = data; | |
1260 | } | |
1261 | ||
1262 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
1263 | return 0; |
1264 | } | |
15c4a640 | 1265 | |
890ca9ae | 1266 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 1267 | { |
890ca9ae HY |
1268 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1269 | unsigned bank_num = mcg_cap & 0xff; | |
1270 | ||
15c4a640 | 1271 | switch (msr) { |
15c4a640 | 1272 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 1273 | vcpu->arch.mcg_status = data; |
15c4a640 | 1274 | break; |
c7ac679c | 1275 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1276 | if (!(mcg_cap & MCG_CTL_P)) |
1277 | return 1; | |
1278 | if (data != 0 && data != ~(u64)0) | |
1279 | return -1; | |
1280 | vcpu->arch.mcg_ctl = data; | |
1281 | break; | |
1282 | default: | |
1283 | if (msr >= MSR_IA32_MC0_CTL && | |
1284 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1285 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
114be429 AP |
1286 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
1287 | * some Linux kernels though clear bit 10 in bank 4 to | |
1288 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1289 | * this to avoid an uncatched #GP in the guest | |
1290 | */ | |
890ca9ae | 1291 | if ((offset & 0x3) == 0 && |
114be429 | 1292 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
1293 | return -1; |
1294 | vcpu->arch.mce_banks[offset] = data; | |
1295 | break; | |
1296 | } | |
1297 | return 1; | |
1298 | } | |
1299 | return 0; | |
1300 | } | |
1301 | ||
ffde22ac ES |
1302 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
1303 | { | |
1304 | struct kvm *kvm = vcpu->kvm; | |
1305 | int lm = is_long_mode(vcpu); | |
1306 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
1307 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
1308 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
1309 | : kvm->arch.xen_hvm_config.blob_size_32; | |
1310 | u32 page_num = data & ~PAGE_MASK; | |
1311 | u64 page_addr = data & PAGE_MASK; | |
1312 | u8 *page; | |
1313 | int r; | |
1314 | ||
1315 | r = -E2BIG; | |
1316 | if (page_num >= blob_size) | |
1317 | goto out; | |
1318 | r = -ENOMEM; | |
1319 | page = kzalloc(PAGE_SIZE, GFP_KERNEL); | |
1320 | if (!page) | |
1321 | goto out; | |
1322 | r = -EFAULT; | |
1323 | if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE)) | |
1324 | goto out_free; | |
1325 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) | |
1326 | goto out_free; | |
1327 | r = 0; | |
1328 | out_free: | |
1329 | kfree(page); | |
1330 | out: | |
1331 | return r; | |
1332 | } | |
1333 | ||
55cd8e5a GN |
1334 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) |
1335 | { | |
1336 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
1337 | } | |
1338 | ||
1339 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
1340 | { | |
1341 | bool r = false; | |
1342 | switch (msr) { | |
1343 | case HV_X64_MSR_GUEST_OS_ID: | |
1344 | case HV_X64_MSR_HYPERCALL: | |
1345 | r = true; | |
1346 | break; | |
1347 | } | |
1348 | ||
1349 | return r; | |
1350 | } | |
1351 | ||
1352 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1353 | { | |
1354 | struct kvm *kvm = vcpu->kvm; | |
1355 | ||
1356 | switch (msr) { | |
1357 | case HV_X64_MSR_GUEST_OS_ID: | |
1358 | kvm->arch.hv_guest_os_id = data; | |
1359 | /* setting guest os id to zero disables hypercall page */ | |
1360 | if (!kvm->arch.hv_guest_os_id) | |
1361 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
1362 | break; | |
1363 | case HV_X64_MSR_HYPERCALL: { | |
1364 | u64 gfn; | |
1365 | unsigned long addr; | |
1366 | u8 instructions[4]; | |
1367 | ||
1368 | /* if guest os id is not set hypercall should remain disabled */ | |
1369 | if (!kvm->arch.hv_guest_os_id) | |
1370 | break; | |
1371 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
1372 | kvm->arch.hv_hypercall = data; | |
1373 | break; | |
1374 | } | |
1375 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
1376 | addr = gfn_to_hva(kvm, gfn); | |
1377 | if (kvm_is_error_hva(addr)) | |
1378 | return 1; | |
1379 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
1380 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
1381 | if (copy_to_user((void __user *)addr, instructions, 4)) | |
1382 | return 1; | |
1383 | kvm->arch.hv_hypercall = data; | |
1384 | break; | |
1385 | } | |
1386 | default: | |
1387 | pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1388 | "data 0x%llx\n", msr, data); | |
1389 | return 1; | |
1390 | } | |
1391 | return 0; | |
1392 | } | |
1393 | ||
1394 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1395 | { | |
10388a07 GN |
1396 | switch (msr) { |
1397 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
1398 | unsigned long addr; | |
55cd8e5a | 1399 | |
10388a07 GN |
1400 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { |
1401 | vcpu->arch.hv_vapic = data; | |
1402 | break; | |
1403 | } | |
1404 | addr = gfn_to_hva(vcpu->kvm, data >> | |
1405 | HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT); | |
1406 | if (kvm_is_error_hva(addr)) | |
1407 | return 1; | |
1408 | if (clear_user((void __user *)addr, PAGE_SIZE)) | |
1409 | return 1; | |
1410 | vcpu->arch.hv_vapic = data; | |
1411 | break; | |
1412 | } | |
1413 | case HV_X64_MSR_EOI: | |
1414 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
1415 | case HV_X64_MSR_ICR: | |
1416 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
1417 | case HV_X64_MSR_TPR: | |
1418 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
1419 | default: | |
1420 | pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1421 | "data 0x%llx\n", msr, data); | |
1422 | return 1; | |
1423 | } | |
1424 | ||
1425 | return 0; | |
55cd8e5a GN |
1426 | } |
1427 | ||
344d9588 GN |
1428 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
1429 | { | |
1430 | gpa_t gpa = data & ~0x3f; | |
1431 | ||
6adba527 GN |
1432 | /* Bits 2:5 are resrved, Should be zero */ |
1433 | if (data & 0x3c) | |
344d9588 GN |
1434 | return 1; |
1435 | ||
1436 | vcpu->arch.apf.msr_val = data; | |
1437 | ||
1438 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
1439 | kvm_clear_async_pf_completion_queue(vcpu); | |
1440 | kvm_async_pf_hash_reset(vcpu); | |
1441 | return 0; | |
1442 | } | |
1443 | ||
1444 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa)) | |
1445 | return 1; | |
1446 | ||
6adba527 | 1447 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
344d9588 GN |
1448 | kvm_async_pf_wakeup_all(vcpu); |
1449 | return 0; | |
1450 | } | |
1451 | ||
15c4a640 CO |
1452 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1453 | { | |
1454 | switch (msr) { | |
15c4a640 | 1455 | case MSR_EFER: |
b69e8cae | 1456 | return set_efer(vcpu, data); |
8f1589d9 AP |
1457 | case MSR_K7_HWCR: |
1458 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 1459 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
8f1589d9 AP |
1460 | if (data != 0) { |
1461 | pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", | |
1462 | data); | |
1463 | return 1; | |
1464 | } | |
15c4a640 | 1465 | break; |
f7c6d140 AP |
1466 | case MSR_FAM10H_MMIO_CONF_BASE: |
1467 | if (data != 0) { | |
1468 | pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " | |
1469 | "0x%llx\n", data); | |
1470 | return 1; | |
1471 | } | |
15c4a640 | 1472 | break; |
c323c0e5 | 1473 | case MSR_AMD64_NB_CFG: |
c7ac679c | 1474 | break; |
b5e2fec0 AG |
1475 | case MSR_IA32_DEBUGCTLMSR: |
1476 | if (!data) { | |
1477 | /* We support the non-activated case already */ | |
1478 | break; | |
1479 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
1480 | /* Values other than LBR and BTF are vendor-specific, | |
1481 | thus reserved and should throw a #GP */ | |
1482 | return 1; | |
1483 | } | |
1484 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
1485 | __func__, data); | |
1486 | break; | |
15c4a640 CO |
1487 | case MSR_IA32_UCODE_REV: |
1488 | case MSR_IA32_UCODE_WRITE: | |
61a6bd67 | 1489 | case MSR_VM_HSAVE_PA: |
6098ca93 | 1490 | case MSR_AMD64_PATCH_LOADER: |
15c4a640 | 1491 | break; |
9ba075a6 AK |
1492 | case 0x200 ... 0x2ff: |
1493 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 CO |
1494 | case MSR_IA32_APICBASE: |
1495 | kvm_set_apic_base(vcpu, data); | |
1496 | break; | |
0105d1a5 GN |
1497 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1498 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
15c4a640 | 1499 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1500 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 1501 | break; |
11c6bffa | 1502 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
1503 | case MSR_KVM_WALL_CLOCK: |
1504 | vcpu->kvm->arch.wall_clock = data; | |
1505 | kvm_write_wall_clock(vcpu->kvm, data); | |
1506 | break; | |
11c6bffa | 1507 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 GOC |
1508 | case MSR_KVM_SYSTEM_TIME: { |
1509 | if (vcpu->arch.time_page) { | |
1510 | kvm_release_page_dirty(vcpu->arch.time_page); | |
1511 | vcpu->arch.time_page = NULL; | |
1512 | } | |
1513 | ||
1514 | vcpu->arch.time = data; | |
c285545f | 1515 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
18068523 GOC |
1516 | |
1517 | /* we verify if the enable bit is set... */ | |
1518 | if (!(data & 1)) | |
1519 | break; | |
1520 | ||
1521 | /* ...but clean it before doing the actual write */ | |
1522 | vcpu->arch.time_offset = data & ~(PAGE_MASK | 1); | |
1523 | ||
18068523 GOC |
1524 | vcpu->arch.time_page = |
1525 | gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT); | |
18068523 GOC |
1526 | |
1527 | if (is_error_page(vcpu->arch.time_page)) { | |
1528 | kvm_release_page_clean(vcpu->arch.time_page); | |
1529 | vcpu->arch.time_page = NULL; | |
1530 | } | |
18068523 GOC |
1531 | break; |
1532 | } | |
344d9588 GN |
1533 | case MSR_KVM_ASYNC_PF_EN: |
1534 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
1535 | return 1; | |
1536 | break; | |
890ca9ae HY |
1537 | case MSR_IA32_MCG_CTL: |
1538 | case MSR_IA32_MCG_STATUS: | |
1539 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1540 | return set_msr_mce(vcpu, msr, data); | |
71db6023 AP |
1541 | |
1542 | /* Performance counters are not protected by a CPUID bit, | |
1543 | * so we should check all of them in the generic path for the sake of | |
1544 | * cross vendor migration. | |
1545 | * Writing a zero into the event select MSRs disables them, | |
1546 | * which we perfectly emulate ;-). Any other value should be at least | |
1547 | * reported, some guests depend on them. | |
1548 | */ | |
1549 | case MSR_P6_EVNTSEL0: | |
1550 | case MSR_P6_EVNTSEL1: | |
1551 | case MSR_K7_EVNTSEL0: | |
1552 | case MSR_K7_EVNTSEL1: | |
1553 | case MSR_K7_EVNTSEL2: | |
1554 | case MSR_K7_EVNTSEL3: | |
1555 | if (data != 0) | |
1556 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1557 | "0x%x data 0x%llx\n", msr, data); | |
1558 | break; | |
1559 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
1560 | * so we ignore writes to make it happy. | |
1561 | */ | |
1562 | case MSR_P6_PERFCTR0: | |
1563 | case MSR_P6_PERFCTR1: | |
1564 | case MSR_K7_PERFCTR0: | |
1565 | case MSR_K7_PERFCTR1: | |
1566 | case MSR_K7_PERFCTR2: | |
1567 | case MSR_K7_PERFCTR3: | |
1568 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1569 | "0x%x data 0x%llx\n", msr, data); | |
1570 | break; | |
84e0cefa JS |
1571 | case MSR_K7_CLK_CTL: |
1572 | /* | |
1573 | * Ignore all writes to this no longer documented MSR. | |
1574 | * Writes are only relevant for old K7 processors, | |
1575 | * all pre-dating SVM, but a recommended workaround from | |
1576 | * AMD for these chips. It is possible to speicify the | |
1577 | * affected processor models on the command line, hence | |
1578 | * the need to ignore the workaround. | |
1579 | */ | |
1580 | break; | |
55cd8e5a GN |
1581 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1582 | if (kvm_hv_msr_partition_wide(msr)) { | |
1583 | int r; | |
1584 | mutex_lock(&vcpu->kvm->lock); | |
1585 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
1586 | mutex_unlock(&vcpu->kvm->lock); | |
1587 | return r; | |
1588 | } else | |
1589 | return set_msr_hyperv(vcpu, msr, data); | |
1590 | break; | |
15c4a640 | 1591 | default: |
ffde22ac ES |
1592 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
1593 | return xen_hvm_config(vcpu, data); | |
ed85c068 AP |
1594 | if (!ignore_msrs) { |
1595 | pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", | |
1596 | msr, data); | |
1597 | return 1; | |
1598 | } else { | |
1599 | pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", | |
1600 | msr, data); | |
1601 | break; | |
1602 | } | |
15c4a640 CO |
1603 | } |
1604 | return 0; | |
1605 | } | |
1606 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
1607 | ||
1608 | ||
1609 | /* | |
1610 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
1611 | * Returns 0 on success, non-0 otherwise. | |
1612 | * Assumes vcpu_load() was already called. | |
1613 | */ | |
1614 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1615 | { | |
1616 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
1617 | } | |
1618 | ||
9ba075a6 AK |
1619 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1620 | { | |
0bed3b56 SY |
1621 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1622 | ||
9ba075a6 AK |
1623 | if (!msr_mtrr_valid(msr)) |
1624 | return 1; | |
1625 | ||
0bed3b56 SY |
1626 | if (msr == MSR_MTRRdefType) |
1627 | *pdata = vcpu->arch.mtrr_state.def_type + | |
1628 | (vcpu->arch.mtrr_state.enabled << 10); | |
1629 | else if (msr == MSR_MTRRfix64K_00000) | |
1630 | *pdata = p[0]; | |
1631 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1632 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
1633 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1634 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
1635 | else if (msr == MSR_IA32_CR_PAT) | |
1636 | *pdata = vcpu->arch.pat; | |
1637 | else { /* Variable MTRRs */ | |
1638 | int idx, is_mtrr_mask; | |
1639 | u64 *pt; | |
1640 | ||
1641 | idx = (msr - 0x200) / 2; | |
1642 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1643 | if (!is_mtrr_mask) | |
1644 | pt = | |
1645 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1646 | else | |
1647 | pt = | |
1648 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1649 | *pdata = *pt; | |
1650 | } | |
1651 | ||
9ba075a6 AK |
1652 | return 0; |
1653 | } | |
1654 | ||
890ca9ae | 1655 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
1656 | { |
1657 | u64 data; | |
890ca9ae HY |
1658 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1659 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
1660 | |
1661 | switch (msr) { | |
15c4a640 CO |
1662 | case MSR_IA32_P5_MC_ADDR: |
1663 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
1664 | data = 0; |
1665 | break; | |
15c4a640 | 1666 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
1667 | data = vcpu->arch.mcg_cap; |
1668 | break; | |
c7ac679c | 1669 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1670 | if (!(mcg_cap & MCG_CTL_P)) |
1671 | return 1; | |
1672 | data = vcpu->arch.mcg_ctl; | |
1673 | break; | |
1674 | case MSR_IA32_MCG_STATUS: | |
1675 | data = vcpu->arch.mcg_status; | |
1676 | break; | |
1677 | default: | |
1678 | if (msr >= MSR_IA32_MC0_CTL && | |
1679 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1680 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
1681 | data = vcpu->arch.mce_banks[offset]; | |
1682 | break; | |
1683 | } | |
1684 | return 1; | |
1685 | } | |
1686 | *pdata = data; | |
1687 | return 0; | |
1688 | } | |
1689 | ||
55cd8e5a GN |
1690 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1691 | { | |
1692 | u64 data = 0; | |
1693 | struct kvm *kvm = vcpu->kvm; | |
1694 | ||
1695 | switch (msr) { | |
1696 | case HV_X64_MSR_GUEST_OS_ID: | |
1697 | data = kvm->arch.hv_guest_os_id; | |
1698 | break; | |
1699 | case HV_X64_MSR_HYPERCALL: | |
1700 | data = kvm->arch.hv_hypercall; | |
1701 | break; | |
1702 | default: | |
1703 | pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
1704 | return 1; | |
1705 | } | |
1706 | ||
1707 | *pdata = data; | |
1708 | return 0; | |
1709 | } | |
1710 | ||
1711 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
1712 | { | |
1713 | u64 data = 0; | |
1714 | ||
1715 | switch (msr) { | |
1716 | case HV_X64_MSR_VP_INDEX: { | |
1717 | int r; | |
1718 | struct kvm_vcpu *v; | |
1719 | kvm_for_each_vcpu(r, v, vcpu->kvm) | |
1720 | if (v == vcpu) | |
1721 | data = r; | |
1722 | break; | |
1723 | } | |
10388a07 GN |
1724 | case HV_X64_MSR_EOI: |
1725 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
1726 | case HV_X64_MSR_ICR: | |
1727 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
1728 | case HV_X64_MSR_TPR: | |
1729 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
55cd8e5a GN |
1730 | default: |
1731 | pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
1732 | return 1; | |
1733 | } | |
1734 | *pdata = data; | |
1735 | return 0; | |
1736 | } | |
1737 | ||
890ca9ae HY |
1738 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1739 | { | |
1740 | u64 data; | |
1741 | ||
1742 | switch (msr) { | |
890ca9ae | 1743 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 1744 | case MSR_IA32_UCODE_REV: |
15c4a640 | 1745 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
1746 | case MSR_IA32_DEBUGCTLMSR: |
1747 | case MSR_IA32_LASTBRANCHFROMIP: | |
1748 | case MSR_IA32_LASTBRANCHTOIP: | |
1749 | case MSR_IA32_LASTINTFROMIP: | |
1750 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
1751 | case MSR_K8_SYSCFG: |
1752 | case MSR_K7_HWCR: | |
61a6bd67 | 1753 | case MSR_VM_HSAVE_PA: |
1f3ee616 AS |
1754 | case MSR_P6_PERFCTR0: |
1755 | case MSR_P6_PERFCTR1: | |
7fe29e0f AS |
1756 | case MSR_P6_EVNTSEL0: |
1757 | case MSR_P6_EVNTSEL1: | |
9e699624 | 1758 | case MSR_K7_EVNTSEL0: |
1f3ee616 | 1759 | case MSR_K7_PERFCTR0: |
1fdbd48c | 1760 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 1761 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 1762 | case MSR_FAM10H_MMIO_CONF_BASE: |
15c4a640 CO |
1763 | data = 0; |
1764 | break; | |
9ba075a6 AK |
1765 | case MSR_MTRRcap: |
1766 | data = 0x500 | KVM_NR_VAR_MTRR; | |
1767 | break; | |
1768 | case 0x200 ... 0x2ff: | |
1769 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
1770 | case 0xcd: /* fsb frequency */ |
1771 | data = 3; | |
1772 | break; | |
7b914098 JS |
1773 | /* |
1774 | * MSR_EBC_FREQUENCY_ID | |
1775 | * Conservative value valid for even the basic CPU models. | |
1776 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
1777 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
1778 | * and 266MHz for model 3, or 4. Set Core Clock | |
1779 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
1780 | * 31:24) even though these are only valid for CPU | |
1781 | * models > 2, however guests may end up dividing or | |
1782 | * multiplying by zero otherwise. | |
1783 | */ | |
1784 | case MSR_EBC_FREQUENCY_ID: | |
1785 | data = 1 << 24; | |
1786 | break; | |
15c4a640 CO |
1787 | case MSR_IA32_APICBASE: |
1788 | data = kvm_get_apic_base(vcpu); | |
1789 | break; | |
0105d1a5 GN |
1790 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1791 | return kvm_x2apic_msr_read(vcpu, msr, pdata); | |
1792 | break; | |
15c4a640 | 1793 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1794 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 1795 | break; |
847f0ad8 AG |
1796 | case MSR_IA32_PERF_STATUS: |
1797 | /* TSC increment by tick */ | |
1798 | data = 1000ULL; | |
1799 | /* CPU multiplier */ | |
1800 | data |= (((uint64_t)4ULL) << 40); | |
1801 | break; | |
15c4a640 | 1802 | case MSR_EFER: |
f6801dff | 1803 | data = vcpu->arch.efer; |
15c4a640 | 1804 | break; |
18068523 | 1805 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 1806 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
1807 | data = vcpu->kvm->arch.wall_clock; |
1808 | break; | |
1809 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 1810 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 GOC |
1811 | data = vcpu->arch.time; |
1812 | break; | |
344d9588 GN |
1813 | case MSR_KVM_ASYNC_PF_EN: |
1814 | data = vcpu->arch.apf.msr_val; | |
1815 | break; | |
890ca9ae HY |
1816 | case MSR_IA32_P5_MC_ADDR: |
1817 | case MSR_IA32_P5_MC_TYPE: | |
1818 | case MSR_IA32_MCG_CAP: | |
1819 | case MSR_IA32_MCG_CTL: | |
1820 | case MSR_IA32_MCG_STATUS: | |
1821 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1822 | return get_msr_mce(vcpu, msr, pdata); | |
84e0cefa JS |
1823 | case MSR_K7_CLK_CTL: |
1824 | /* | |
1825 | * Provide expected ramp-up count for K7. All other | |
1826 | * are set to zero, indicating minimum divisors for | |
1827 | * every field. | |
1828 | * | |
1829 | * This prevents guest kernels on AMD host with CPU | |
1830 | * type 6, model 8 and higher from exploding due to | |
1831 | * the rdmsr failing. | |
1832 | */ | |
1833 | data = 0x20000000; | |
1834 | break; | |
55cd8e5a GN |
1835 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1836 | if (kvm_hv_msr_partition_wide(msr)) { | |
1837 | int r; | |
1838 | mutex_lock(&vcpu->kvm->lock); | |
1839 | r = get_msr_hyperv_pw(vcpu, msr, pdata); | |
1840 | mutex_unlock(&vcpu->kvm->lock); | |
1841 | return r; | |
1842 | } else | |
1843 | return get_msr_hyperv(vcpu, msr, pdata); | |
1844 | break; | |
15c4a640 | 1845 | default: |
ed85c068 AP |
1846 | if (!ignore_msrs) { |
1847 | pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); | |
1848 | return 1; | |
1849 | } else { | |
1850 | pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); | |
1851 | data = 0; | |
1852 | } | |
1853 | break; | |
15c4a640 CO |
1854 | } |
1855 | *pdata = data; | |
1856 | return 0; | |
1857 | } | |
1858 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
1859 | ||
313a3dc7 CO |
1860 | /* |
1861 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
1862 | * | |
1863 | * @return number of msrs set successfully. | |
1864 | */ | |
1865 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
1866 | struct kvm_msr_entry *entries, | |
1867 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1868 | unsigned index, u64 *data)) | |
1869 | { | |
f656ce01 | 1870 | int i, idx; |
313a3dc7 | 1871 | |
f656ce01 | 1872 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
1873 | for (i = 0; i < msrs->nmsrs; ++i) |
1874 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
1875 | break; | |
f656ce01 | 1876 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 1877 | |
313a3dc7 CO |
1878 | return i; |
1879 | } | |
1880 | ||
1881 | /* | |
1882 | * Read or write a bunch of msrs. Parameters are user addresses. | |
1883 | * | |
1884 | * @return number of msrs set successfully. | |
1885 | */ | |
1886 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
1887 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1888 | unsigned index, u64 *data), | |
1889 | int writeback) | |
1890 | { | |
1891 | struct kvm_msrs msrs; | |
1892 | struct kvm_msr_entry *entries; | |
1893 | int r, n; | |
1894 | unsigned size; | |
1895 | ||
1896 | r = -EFAULT; | |
1897 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
1898 | goto out; | |
1899 | ||
1900 | r = -E2BIG; | |
1901 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
1902 | goto out; | |
1903 | ||
1904 | r = -ENOMEM; | |
1905 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; | |
7a73c028 | 1906 | entries = kmalloc(size, GFP_KERNEL); |
313a3dc7 CO |
1907 | if (!entries) |
1908 | goto out; | |
1909 | ||
1910 | r = -EFAULT; | |
1911 | if (copy_from_user(entries, user_msrs->entries, size)) | |
1912 | goto out_free; | |
1913 | ||
1914 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
1915 | if (r < 0) | |
1916 | goto out_free; | |
1917 | ||
1918 | r = -EFAULT; | |
1919 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
1920 | goto out_free; | |
1921 | ||
1922 | r = n; | |
1923 | ||
1924 | out_free: | |
7a73c028 | 1925 | kfree(entries); |
313a3dc7 CO |
1926 | out: |
1927 | return r; | |
1928 | } | |
1929 | ||
018d00d2 ZX |
1930 | int kvm_dev_ioctl_check_extension(long ext) |
1931 | { | |
1932 | int r; | |
1933 | ||
1934 | switch (ext) { | |
1935 | case KVM_CAP_IRQCHIP: | |
1936 | case KVM_CAP_HLT: | |
1937 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 1938 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 1939 | case KVM_CAP_EXT_CPUID: |
c8076604 | 1940 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 1941 | case KVM_CAP_PIT: |
a28e4f5a | 1942 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 1943 | case KVM_CAP_MP_STATE: |
ed848624 | 1944 | case KVM_CAP_SYNC_MMU: |
52d939a0 | 1945 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 1946 | case KVM_CAP_IRQ_INJECT_STATUS: |
e56d532f | 1947 | case KVM_CAP_ASSIGN_DEV_IRQ: |
721eecbf | 1948 | case KVM_CAP_IRQFD: |
d34e6b17 | 1949 | case KVM_CAP_IOEVENTFD: |
c5ff41ce | 1950 | case KVM_CAP_PIT2: |
e9f42757 | 1951 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 1952 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 1953 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 1954 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 1955 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 1956 | case KVM_CAP_HYPERV: |
10388a07 | 1957 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 1958 | case KVM_CAP_HYPERV_SPIN: |
ab9f4ecb | 1959 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 1960 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 1961 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 1962 | case KVM_CAP_XSAVE: |
344d9588 | 1963 | case KVM_CAP_ASYNC_PF: |
018d00d2 ZX |
1964 | r = 1; |
1965 | break; | |
542472b5 LV |
1966 | case KVM_CAP_COALESCED_MMIO: |
1967 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
1968 | break; | |
774ead3a AK |
1969 | case KVM_CAP_VAPIC: |
1970 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
1971 | break; | |
f725230a AK |
1972 | case KVM_CAP_NR_VCPUS: |
1973 | r = KVM_MAX_VCPUS; | |
1974 | break; | |
a988b910 AK |
1975 | case KVM_CAP_NR_MEMSLOTS: |
1976 | r = KVM_MEMORY_SLOTS; | |
1977 | break; | |
a68a6a72 MT |
1978 | case KVM_CAP_PV_MMU: /* obsolete */ |
1979 | r = 0; | |
2f333bcb | 1980 | break; |
62c476c7 | 1981 | case KVM_CAP_IOMMU: |
19de40a8 | 1982 | r = iommu_found(); |
62c476c7 | 1983 | break; |
890ca9ae HY |
1984 | case KVM_CAP_MCE: |
1985 | r = KVM_MAX_MCE_BANKS; | |
1986 | break; | |
2d5b5a66 SY |
1987 | case KVM_CAP_XCRS: |
1988 | r = cpu_has_xsave; | |
1989 | break; | |
018d00d2 ZX |
1990 | default: |
1991 | r = 0; | |
1992 | break; | |
1993 | } | |
1994 | return r; | |
1995 | ||
1996 | } | |
1997 | ||
043405e1 CO |
1998 | long kvm_arch_dev_ioctl(struct file *filp, |
1999 | unsigned int ioctl, unsigned long arg) | |
2000 | { | |
2001 | void __user *argp = (void __user *)arg; | |
2002 | long r; | |
2003 | ||
2004 | switch (ioctl) { | |
2005 | case KVM_GET_MSR_INDEX_LIST: { | |
2006 | struct kvm_msr_list __user *user_msr_list = argp; | |
2007 | struct kvm_msr_list msr_list; | |
2008 | unsigned n; | |
2009 | ||
2010 | r = -EFAULT; | |
2011 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
2012 | goto out; | |
2013 | n = msr_list.nmsrs; | |
2014 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
2015 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
2016 | goto out; | |
2017 | r = -E2BIG; | |
e125e7b6 | 2018 | if (n < msr_list.nmsrs) |
043405e1 CO |
2019 | goto out; |
2020 | r = -EFAULT; | |
2021 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
2022 | num_msrs_to_save * sizeof(u32))) | |
2023 | goto out; | |
e125e7b6 | 2024 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 CO |
2025 | &emulated_msrs, |
2026 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
2027 | goto out; | |
2028 | r = 0; | |
2029 | break; | |
2030 | } | |
674eea0f AK |
2031 | case KVM_GET_SUPPORTED_CPUID: { |
2032 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2033 | struct kvm_cpuid2 cpuid; | |
2034 | ||
2035 | r = -EFAULT; | |
2036 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2037 | goto out; | |
2038 | r = kvm_dev_ioctl_get_supported_cpuid(&cpuid, | |
19355475 | 2039 | cpuid_arg->entries); |
674eea0f AK |
2040 | if (r) |
2041 | goto out; | |
2042 | ||
2043 | r = -EFAULT; | |
2044 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2045 | goto out; | |
2046 | r = 0; | |
2047 | break; | |
2048 | } | |
890ca9ae HY |
2049 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
2050 | u64 mce_cap; | |
2051 | ||
2052 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
2053 | r = -EFAULT; | |
2054 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
2055 | goto out; | |
2056 | r = 0; | |
2057 | break; | |
2058 | } | |
043405e1 CO |
2059 | default: |
2060 | r = -EINVAL; | |
2061 | } | |
2062 | out: | |
2063 | return r; | |
2064 | } | |
2065 | ||
f5f48ee1 SY |
2066 | static void wbinvd_ipi(void *garbage) |
2067 | { | |
2068 | wbinvd(); | |
2069 | } | |
2070 | ||
2071 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
2072 | { | |
2073 | return vcpu->kvm->arch.iommu_domain && | |
2074 | !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY); | |
2075 | } | |
2076 | ||
313a3dc7 CO |
2077 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
2078 | { | |
f5f48ee1 SY |
2079 | /* Address WBINVD may be executed by guest */ |
2080 | if (need_emulate_wbinvd(vcpu)) { | |
2081 | if (kvm_x86_ops->has_wbinvd_exit()) | |
2082 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
2083 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
2084 | smp_call_function_single(vcpu->cpu, | |
2085 | wbinvd_ipi, NULL, 1); | |
2086 | } | |
2087 | ||
313a3dc7 | 2088 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
48434c20 | 2089 | if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { |
e48672fa ZA |
2090 | /* Make sure TSC doesn't go backwards */ |
2091 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : | |
2092 | native_read_tsc() - vcpu->arch.last_host_tsc; | |
2093 | if (tsc_delta < 0) | |
2094 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
c285545f | 2095 | if (check_tsc_unstable()) { |
e48672fa | 2096 | kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta); |
c285545f ZA |
2097 | vcpu->arch.tsc_catchup = 1; |
2098 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
2099 | } | |
2100 | if (vcpu->cpu != cpu) | |
2101 | kvm_migrate_timers(vcpu); | |
e48672fa | 2102 | vcpu->cpu = cpu; |
6b7d7e76 | 2103 | } |
313a3dc7 CO |
2104 | } |
2105 | ||
2106 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
2107 | { | |
02daab21 | 2108 | kvm_x86_ops->vcpu_put(vcpu); |
1c11e713 | 2109 | kvm_put_guest_fpu(vcpu); |
e48672fa | 2110 | vcpu->arch.last_host_tsc = native_read_tsc(); |
313a3dc7 CO |
2111 | } |
2112 | ||
07716717 | 2113 | static int is_efer_nx(void) |
313a3dc7 | 2114 | { |
e286e86e | 2115 | unsigned long long efer = 0; |
313a3dc7 | 2116 | |
e286e86e | 2117 | rdmsrl_safe(MSR_EFER, &efer); |
07716717 DK |
2118 | return efer & EFER_NX; |
2119 | } | |
2120 | ||
2121 | static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) | |
2122 | { | |
2123 | int i; | |
2124 | struct kvm_cpuid_entry2 *e, *entry; | |
2125 | ||
313a3dc7 | 2126 | entry = NULL; |
ad312c7c ZX |
2127 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
2128 | e = &vcpu->arch.cpuid_entries[i]; | |
313a3dc7 CO |
2129 | if (e->function == 0x80000001) { |
2130 | entry = e; | |
2131 | break; | |
2132 | } | |
2133 | } | |
07716717 | 2134 | if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) { |
313a3dc7 CO |
2135 | entry->edx &= ~(1 << 20); |
2136 | printk(KERN_INFO "kvm: guest NX capability removed\n"); | |
2137 | } | |
2138 | } | |
2139 | ||
07716717 | 2140 | /* when an old userspace process fills a new kernel module */ |
313a3dc7 CO |
2141 | static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, |
2142 | struct kvm_cpuid *cpuid, | |
2143 | struct kvm_cpuid_entry __user *entries) | |
07716717 DK |
2144 | { |
2145 | int r, i; | |
2146 | struct kvm_cpuid_entry *cpuid_entries; | |
2147 | ||
2148 | r = -E2BIG; | |
2149 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
2150 | goto out; | |
2151 | r = -ENOMEM; | |
2152 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent); | |
2153 | if (!cpuid_entries) | |
2154 | goto out; | |
2155 | r = -EFAULT; | |
2156 | if (copy_from_user(cpuid_entries, entries, | |
2157 | cpuid->nent * sizeof(struct kvm_cpuid_entry))) | |
2158 | goto out_free; | |
2159 | for (i = 0; i < cpuid->nent; i++) { | |
ad312c7c ZX |
2160 | vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; |
2161 | vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; | |
2162 | vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx; | |
2163 | vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx; | |
2164 | vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx; | |
2165 | vcpu->arch.cpuid_entries[i].index = 0; | |
2166 | vcpu->arch.cpuid_entries[i].flags = 0; | |
2167 | vcpu->arch.cpuid_entries[i].padding[0] = 0; | |
2168 | vcpu->arch.cpuid_entries[i].padding[1] = 0; | |
2169 | vcpu->arch.cpuid_entries[i].padding[2] = 0; | |
2170 | } | |
2171 | vcpu->arch.cpuid_nent = cpuid->nent; | |
07716717 DK |
2172 | cpuid_fix_nx_cap(vcpu); |
2173 | r = 0; | |
fc61b800 | 2174 | kvm_apic_set_version(vcpu); |
0e851880 | 2175 | kvm_x86_ops->cpuid_update(vcpu); |
2acf923e | 2176 | update_cpuid(vcpu); |
07716717 DK |
2177 | |
2178 | out_free: | |
2179 | vfree(cpuid_entries); | |
2180 | out: | |
2181 | return r; | |
2182 | } | |
2183 | ||
2184 | static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, | |
19355475 AS |
2185 | struct kvm_cpuid2 *cpuid, |
2186 | struct kvm_cpuid_entry2 __user *entries) | |
313a3dc7 CO |
2187 | { |
2188 | int r; | |
2189 | ||
2190 | r = -E2BIG; | |
2191 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
2192 | goto out; | |
2193 | r = -EFAULT; | |
ad312c7c | 2194 | if (copy_from_user(&vcpu->arch.cpuid_entries, entries, |
07716717 | 2195 | cpuid->nent * sizeof(struct kvm_cpuid_entry2))) |
313a3dc7 | 2196 | goto out; |
ad312c7c | 2197 | vcpu->arch.cpuid_nent = cpuid->nent; |
fc61b800 | 2198 | kvm_apic_set_version(vcpu); |
0e851880 | 2199 | kvm_x86_ops->cpuid_update(vcpu); |
2acf923e | 2200 | update_cpuid(vcpu); |
313a3dc7 CO |
2201 | return 0; |
2202 | ||
2203 | out: | |
2204 | return r; | |
2205 | } | |
2206 | ||
07716717 | 2207 | static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, |
19355475 AS |
2208 | struct kvm_cpuid2 *cpuid, |
2209 | struct kvm_cpuid_entry2 __user *entries) | |
07716717 DK |
2210 | { |
2211 | int r; | |
2212 | ||
2213 | r = -E2BIG; | |
ad312c7c | 2214 | if (cpuid->nent < vcpu->arch.cpuid_nent) |
07716717 DK |
2215 | goto out; |
2216 | r = -EFAULT; | |
ad312c7c | 2217 | if (copy_to_user(entries, &vcpu->arch.cpuid_entries, |
19355475 | 2218 | vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
2219 | goto out; |
2220 | return 0; | |
2221 | ||
2222 | out: | |
ad312c7c | 2223 | cpuid->nent = vcpu->arch.cpuid_nent; |
07716717 DK |
2224 | return r; |
2225 | } | |
2226 | ||
07716717 | 2227 | static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
19355475 | 2228 | u32 index) |
07716717 DK |
2229 | { |
2230 | entry->function = function; | |
2231 | entry->index = index; | |
2232 | cpuid_count(entry->function, entry->index, | |
19355475 | 2233 | &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); |
07716717 DK |
2234 | entry->flags = 0; |
2235 | } | |
2236 | ||
7faa4ee1 AK |
2237 | #define F(x) bit(X86_FEATURE_##x) |
2238 | ||
07716717 DK |
2239 | static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
2240 | u32 index, int *nent, int maxnent) | |
2241 | { | |
7faa4ee1 | 2242 | unsigned f_nx = is_efer_nx() ? F(NX) : 0; |
07716717 | 2243 | #ifdef CONFIG_X86_64 |
17cc3935 SY |
2244 | unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL) |
2245 | ? F(GBPAGES) : 0; | |
7faa4ee1 AK |
2246 | unsigned f_lm = F(LM); |
2247 | #else | |
17cc3935 | 2248 | unsigned f_gbpages = 0; |
7faa4ee1 | 2249 | unsigned f_lm = 0; |
07716717 | 2250 | #endif |
4e47c7a6 | 2251 | unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0; |
7faa4ee1 AK |
2252 | |
2253 | /* cpuid 1.edx */ | |
2254 | const u32 kvm_supported_word0_x86_features = | |
2255 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
2256 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
2257 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | | |
2258 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
2259 | F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) | | |
2260 | 0 /* Reserved, DS, ACPI */ | F(MMX) | | |
2261 | F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | | |
2262 | 0 /* HTT, TM, Reserved, PBE */; | |
2263 | /* cpuid 0x80000001.edx */ | |
2264 | const u32 kvm_supported_word1_x86_features = | |
2265 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
2266 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
2267 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | | |
2268 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
2269 | F(PAT) | F(PSE36) | 0 /* Reserved */ | | |
2270 | f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | | |
4e47c7a6 | 2271 | F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp | |
7faa4ee1 AK |
2272 | 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW); |
2273 | /* cpuid 1.ecx */ | |
2274 | const u32 kvm_supported_word4_x86_features = | |
6c3f6041 | 2275 | F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | |
d149c731 AK |
2276 | 0 /* DS-CPL, VMX, SMX, EST */ | |
2277 | 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | | |
2278 | 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ | | |
2279 | 0 /* Reserved, DCA */ | F(XMM4_1) | | |
0105d1a5 | 2280 | F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | |
6d886fd0 AP |
2281 | 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | |
2282 | F(F16C); | |
7faa4ee1 | 2283 | /* cpuid 0x80000001.ecx */ |
07716717 | 2284 | const u32 kvm_supported_word6_x86_features = |
4c62a2dc | 2285 | F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | |
7faa4ee1 | 2286 | F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | |
7ef8aa72 | 2287 | F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) | |
6d886fd0 | 2288 | 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM); |
07716717 | 2289 | |
19355475 | 2290 | /* all calls to cpuid_count() should be made on the same cpu */ |
07716717 DK |
2291 | get_cpu(); |
2292 | do_cpuid_1_ent(entry, function, index); | |
2293 | ++*nent; | |
2294 | ||
2295 | switch (function) { | |
2296 | case 0: | |
2acf923e | 2297 | entry->eax = min(entry->eax, (u32)0xd); |
07716717 DK |
2298 | break; |
2299 | case 1: | |
2300 | entry->edx &= kvm_supported_word0_x86_features; | |
7faa4ee1 | 2301 | entry->ecx &= kvm_supported_word4_x86_features; |
0d1de2d9 GN |
2302 | /* we support x2apic emulation even if host does not support |
2303 | * it since we emulate x2apic in software */ | |
2304 | entry->ecx |= F(X2APIC); | |
07716717 DK |
2305 | break; |
2306 | /* function 2 entries are STATEFUL. That is, repeated cpuid commands | |
2307 | * may return different values. This forces us to get_cpu() before | |
2308 | * issuing the first command, and also to emulate this annoying behavior | |
2309 | * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */ | |
2310 | case 2: { | |
2311 | int t, times = entry->eax & 0xff; | |
2312 | ||
2313 | entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
0fdf8e59 | 2314 | entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; |
07716717 DK |
2315 | for (t = 1; t < times && *nent < maxnent; ++t) { |
2316 | do_cpuid_1_ent(&entry[t], function, 0); | |
2317 | entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
2318 | ++*nent; | |
2319 | } | |
2320 | break; | |
2321 | } | |
2322 | /* function 4 and 0xb have additional index. */ | |
2323 | case 4: { | |
14af3f3c | 2324 | int i, cache_type; |
07716717 DK |
2325 | |
2326 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2327 | /* read more entries until cache_type is zero */ | |
14af3f3c HH |
2328 | for (i = 1; *nent < maxnent; ++i) { |
2329 | cache_type = entry[i - 1].eax & 0x1f; | |
07716717 DK |
2330 | if (!cache_type) |
2331 | break; | |
14af3f3c HH |
2332 | do_cpuid_1_ent(&entry[i], function, i); |
2333 | entry[i].flags |= | |
07716717 DK |
2334 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
2335 | ++*nent; | |
2336 | } | |
2337 | break; | |
2338 | } | |
2339 | case 0xb: { | |
14af3f3c | 2340 | int i, level_type; |
07716717 DK |
2341 | |
2342 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2343 | /* read more entries until level_type is zero */ | |
14af3f3c | 2344 | for (i = 1; *nent < maxnent; ++i) { |
0853d2c1 | 2345 | level_type = entry[i - 1].ecx & 0xff00; |
07716717 DK |
2346 | if (!level_type) |
2347 | break; | |
14af3f3c HH |
2348 | do_cpuid_1_ent(&entry[i], function, i); |
2349 | entry[i].flags |= | |
07716717 DK |
2350 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
2351 | ++*nent; | |
2352 | } | |
2353 | break; | |
2354 | } | |
2acf923e DC |
2355 | case 0xd: { |
2356 | int i; | |
2357 | ||
2358 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2359 | for (i = 1; *nent < maxnent; ++i) { | |
2360 | if (entry[i - 1].eax == 0 && i != 2) | |
2361 | break; | |
2362 | do_cpuid_1_ent(&entry[i], function, i); | |
2363 | entry[i].flags |= | |
2364 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2365 | ++*nent; | |
2366 | } | |
2367 | break; | |
2368 | } | |
84478c82 GC |
2369 | case KVM_CPUID_SIGNATURE: { |
2370 | char signature[12] = "KVMKVMKVM\0\0"; | |
2371 | u32 *sigptr = (u32 *)signature; | |
2372 | entry->eax = 0; | |
2373 | entry->ebx = sigptr[0]; | |
2374 | entry->ecx = sigptr[1]; | |
2375 | entry->edx = sigptr[2]; | |
2376 | break; | |
2377 | } | |
2378 | case KVM_CPUID_FEATURES: | |
2379 | entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | | |
2380 | (1 << KVM_FEATURE_NOP_IO_DELAY) | | |
371bcf64 GC |
2381 | (1 << KVM_FEATURE_CLOCKSOURCE2) | |
2382 | (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT); | |
84478c82 GC |
2383 | entry->ebx = 0; |
2384 | entry->ecx = 0; | |
2385 | entry->edx = 0; | |
2386 | break; | |
07716717 DK |
2387 | case 0x80000000: |
2388 | entry->eax = min(entry->eax, 0x8000001a); | |
2389 | break; | |
2390 | case 0x80000001: | |
2391 | entry->edx &= kvm_supported_word1_x86_features; | |
2392 | entry->ecx &= kvm_supported_word6_x86_features; | |
2393 | break; | |
2394 | } | |
d4330ef2 JR |
2395 | |
2396 | kvm_x86_ops->set_supported_cpuid(function, entry); | |
2397 | ||
07716717 DK |
2398 | put_cpu(); |
2399 | } | |
2400 | ||
7faa4ee1 AK |
2401 | #undef F |
2402 | ||
674eea0f | 2403 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
19355475 | 2404 | struct kvm_cpuid_entry2 __user *entries) |
07716717 DK |
2405 | { |
2406 | struct kvm_cpuid_entry2 *cpuid_entries; | |
2407 | int limit, nent = 0, r = -E2BIG; | |
2408 | u32 func; | |
2409 | ||
2410 | if (cpuid->nent < 1) | |
2411 | goto out; | |
6a544355 AK |
2412 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) |
2413 | cpuid->nent = KVM_MAX_CPUID_ENTRIES; | |
07716717 DK |
2414 | r = -ENOMEM; |
2415 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent); | |
2416 | if (!cpuid_entries) | |
2417 | goto out; | |
2418 | ||
2419 | do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent); | |
2420 | limit = cpuid_entries[0].eax; | |
2421 | for (func = 1; func <= limit && nent < cpuid->nent; ++func) | |
2422 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 2423 | &nent, cpuid->nent); |
07716717 DK |
2424 | r = -E2BIG; |
2425 | if (nent >= cpuid->nent) | |
2426 | goto out_free; | |
2427 | ||
2428 | do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent); | |
2429 | limit = cpuid_entries[nent - 1].eax; | |
2430 | for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func) | |
2431 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 2432 | &nent, cpuid->nent); |
84478c82 GC |
2433 | |
2434 | ||
2435 | ||
2436 | r = -E2BIG; | |
2437 | if (nent >= cpuid->nent) | |
2438 | goto out_free; | |
2439 | ||
2440 | do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent, | |
2441 | cpuid->nent); | |
2442 | ||
2443 | r = -E2BIG; | |
2444 | if (nent >= cpuid->nent) | |
2445 | goto out_free; | |
2446 | ||
2447 | do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent, | |
2448 | cpuid->nent); | |
2449 | ||
cb007648 MM |
2450 | r = -E2BIG; |
2451 | if (nent >= cpuid->nent) | |
2452 | goto out_free; | |
2453 | ||
07716717 DK |
2454 | r = -EFAULT; |
2455 | if (copy_to_user(entries, cpuid_entries, | |
19355475 | 2456 | nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
2457 | goto out_free; |
2458 | cpuid->nent = nent; | |
2459 | r = 0; | |
2460 | ||
2461 | out_free: | |
2462 | vfree(cpuid_entries); | |
2463 | out: | |
2464 | return r; | |
2465 | } | |
2466 | ||
313a3dc7 CO |
2467 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
2468 | struct kvm_lapic_state *s) | |
2469 | { | |
ad312c7c | 2470 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
2471 | |
2472 | return 0; | |
2473 | } | |
2474 | ||
2475 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
2476 | struct kvm_lapic_state *s) | |
2477 | { | |
ad312c7c | 2478 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); |
313a3dc7 | 2479 | kvm_apic_post_state_restore(vcpu); |
cb142eb7 | 2480 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
2481 | |
2482 | return 0; | |
2483 | } | |
2484 | ||
f77bc6a4 ZX |
2485 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
2486 | struct kvm_interrupt *irq) | |
2487 | { | |
2488 | if (irq->irq < 0 || irq->irq >= 256) | |
2489 | return -EINVAL; | |
2490 | if (irqchip_in_kernel(vcpu->kvm)) | |
2491 | return -ENXIO; | |
f77bc6a4 | 2492 | |
66fd3f7f | 2493 | kvm_queue_interrupt(vcpu, irq->irq, false); |
3842d135 | 2494 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 | 2495 | |
f77bc6a4 ZX |
2496 | return 0; |
2497 | } | |
2498 | ||
c4abb7c9 JK |
2499 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
2500 | { | |
c4abb7c9 | 2501 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
2502 | |
2503 | return 0; | |
2504 | } | |
2505 | ||
b209749f AK |
2506 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
2507 | struct kvm_tpr_access_ctl *tac) | |
2508 | { | |
2509 | if (tac->flags) | |
2510 | return -EINVAL; | |
2511 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
2512 | return 0; | |
2513 | } | |
2514 | ||
890ca9ae HY |
2515 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
2516 | u64 mcg_cap) | |
2517 | { | |
2518 | int r; | |
2519 | unsigned bank_num = mcg_cap & 0xff, bank; | |
2520 | ||
2521 | r = -EINVAL; | |
a9e38c3e | 2522 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
2523 | goto out; |
2524 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
2525 | goto out; | |
2526 | r = 0; | |
2527 | vcpu->arch.mcg_cap = mcg_cap; | |
2528 | /* Init IA32_MCG_CTL to all 1s */ | |
2529 | if (mcg_cap & MCG_CTL_P) | |
2530 | vcpu->arch.mcg_ctl = ~(u64)0; | |
2531 | /* Init IA32_MCi_CTL to all 1s */ | |
2532 | for (bank = 0; bank < bank_num; bank++) | |
2533 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
2534 | out: | |
2535 | return r; | |
2536 | } | |
2537 | ||
2538 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
2539 | struct kvm_x86_mce *mce) | |
2540 | { | |
2541 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2542 | unsigned bank_num = mcg_cap & 0xff; | |
2543 | u64 *banks = vcpu->arch.mce_banks; | |
2544 | ||
2545 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
2546 | return -EINVAL; | |
2547 | /* | |
2548 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
2549 | * reporting is disabled | |
2550 | */ | |
2551 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
2552 | vcpu->arch.mcg_ctl != ~(u64)0) | |
2553 | return 0; | |
2554 | banks += 4 * mce->bank; | |
2555 | /* | |
2556 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
2557 | * reporting is disabled for the bank | |
2558 | */ | |
2559 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
2560 | return 0; | |
2561 | if (mce->status & MCI_STATUS_UC) { | |
2562 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 2563 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
890ca9ae HY |
2564 | printk(KERN_DEBUG "kvm: set_mce: " |
2565 | "injects mce exception while " | |
2566 | "previous one is in progress!\n"); | |
a8eeb04a | 2567 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
2568 | return 0; |
2569 | } | |
2570 | if (banks[1] & MCI_STATUS_VAL) | |
2571 | mce->status |= MCI_STATUS_OVER; | |
2572 | banks[2] = mce->addr; | |
2573 | banks[3] = mce->misc; | |
2574 | vcpu->arch.mcg_status = mce->mcg_status; | |
2575 | banks[1] = mce->status; | |
2576 | kvm_queue_exception(vcpu, MC_VECTOR); | |
2577 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
2578 | || !(banks[1] & MCI_STATUS_UC)) { | |
2579 | if (banks[1] & MCI_STATUS_VAL) | |
2580 | mce->status |= MCI_STATUS_OVER; | |
2581 | banks[2] = mce->addr; | |
2582 | banks[3] = mce->misc; | |
2583 | banks[1] = mce->status; | |
2584 | } else | |
2585 | banks[1] |= MCI_STATUS_OVER; | |
2586 | return 0; | |
2587 | } | |
2588 | ||
3cfc3092 JK |
2589 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
2590 | struct kvm_vcpu_events *events) | |
2591 | { | |
03b82a30 JK |
2592 | events->exception.injected = |
2593 | vcpu->arch.exception.pending && | |
2594 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
2595 | events->exception.nr = vcpu->arch.exception.nr; |
2596 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
97e69aa6 | 2597 | events->exception.pad = 0; |
3cfc3092 JK |
2598 | events->exception.error_code = vcpu->arch.exception.error_code; |
2599 | ||
03b82a30 JK |
2600 | events->interrupt.injected = |
2601 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 2602 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 2603 | events->interrupt.soft = 0; |
48005f64 JK |
2604 | events->interrupt.shadow = |
2605 | kvm_x86_ops->get_interrupt_shadow(vcpu, | |
2606 | KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI); | |
3cfc3092 JK |
2607 | |
2608 | events->nmi.injected = vcpu->arch.nmi_injected; | |
2609 | events->nmi.pending = vcpu->arch.nmi_pending; | |
2610 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); | |
97e69aa6 | 2611 | events->nmi.pad = 0; |
3cfc3092 JK |
2612 | |
2613 | events->sipi_vector = vcpu->arch.sipi_vector; | |
2614 | ||
dab4b911 | 2615 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2616 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2617 | | KVM_VCPUEVENT_VALID_SHADOW); | |
97e69aa6 | 2618 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
2619 | } |
2620 | ||
2621 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
2622 | struct kvm_vcpu_events *events) | |
2623 | { | |
dab4b911 | 2624 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2625 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2626 | | KVM_VCPUEVENT_VALID_SHADOW)) | |
3cfc3092 JK |
2627 | return -EINVAL; |
2628 | ||
3cfc3092 JK |
2629 | vcpu->arch.exception.pending = events->exception.injected; |
2630 | vcpu->arch.exception.nr = events->exception.nr; | |
2631 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
2632 | vcpu->arch.exception.error_code = events->exception.error_code; | |
2633 | ||
2634 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
2635 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
2636 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
2637 | if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm)) | |
2638 | kvm_pic_clear_isr_ack(vcpu->kvm); | |
48005f64 JK |
2639 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
2640 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
2641 | events->interrupt.shadow); | |
3cfc3092 JK |
2642 | |
2643 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
2644 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
2645 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
2646 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
2647 | ||
dab4b911 JK |
2648 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR) |
2649 | vcpu->arch.sipi_vector = events->sipi_vector; | |
3cfc3092 | 2650 | |
3842d135 AK |
2651 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2652 | ||
3cfc3092 JK |
2653 | return 0; |
2654 | } | |
2655 | ||
a1efbe77 JK |
2656 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
2657 | struct kvm_debugregs *dbgregs) | |
2658 | { | |
a1efbe77 JK |
2659 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
2660 | dbgregs->dr6 = vcpu->arch.dr6; | |
2661 | dbgregs->dr7 = vcpu->arch.dr7; | |
2662 | dbgregs->flags = 0; | |
97e69aa6 | 2663 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
2664 | } |
2665 | ||
2666 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
2667 | struct kvm_debugregs *dbgregs) | |
2668 | { | |
2669 | if (dbgregs->flags) | |
2670 | return -EINVAL; | |
2671 | ||
a1efbe77 JK |
2672 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
2673 | vcpu->arch.dr6 = dbgregs->dr6; | |
2674 | vcpu->arch.dr7 = dbgregs->dr7; | |
2675 | ||
a1efbe77 JK |
2676 | return 0; |
2677 | } | |
2678 | ||
2d5b5a66 SY |
2679 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
2680 | struct kvm_xsave *guest_xsave) | |
2681 | { | |
2682 | if (cpu_has_xsave) | |
2683 | memcpy(guest_xsave->region, | |
2684 | &vcpu->arch.guest_fpu.state->xsave, | |
f45755b8 | 2685 | xstate_size); |
2d5b5a66 SY |
2686 | else { |
2687 | memcpy(guest_xsave->region, | |
2688 | &vcpu->arch.guest_fpu.state->fxsave, | |
2689 | sizeof(struct i387_fxsave_struct)); | |
2690 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = | |
2691 | XSTATE_FPSSE; | |
2692 | } | |
2693 | } | |
2694 | ||
2695 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
2696 | struct kvm_xsave *guest_xsave) | |
2697 | { | |
2698 | u64 xstate_bv = | |
2699 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
2700 | ||
2701 | if (cpu_has_xsave) | |
2702 | memcpy(&vcpu->arch.guest_fpu.state->xsave, | |
f45755b8 | 2703 | guest_xsave->region, xstate_size); |
2d5b5a66 SY |
2704 | else { |
2705 | if (xstate_bv & ~XSTATE_FPSSE) | |
2706 | return -EINVAL; | |
2707 | memcpy(&vcpu->arch.guest_fpu.state->fxsave, | |
2708 | guest_xsave->region, sizeof(struct i387_fxsave_struct)); | |
2709 | } | |
2710 | return 0; | |
2711 | } | |
2712 | ||
2713 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
2714 | struct kvm_xcrs *guest_xcrs) | |
2715 | { | |
2716 | if (!cpu_has_xsave) { | |
2717 | guest_xcrs->nr_xcrs = 0; | |
2718 | return; | |
2719 | } | |
2720 | ||
2721 | guest_xcrs->nr_xcrs = 1; | |
2722 | guest_xcrs->flags = 0; | |
2723 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
2724 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
2725 | } | |
2726 | ||
2727 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
2728 | struct kvm_xcrs *guest_xcrs) | |
2729 | { | |
2730 | int i, r = 0; | |
2731 | ||
2732 | if (!cpu_has_xsave) | |
2733 | return -EINVAL; | |
2734 | ||
2735 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
2736 | return -EINVAL; | |
2737 | ||
2738 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
2739 | /* Only support XCR0 currently */ | |
2740 | if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) { | |
2741 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, | |
2742 | guest_xcrs->xcrs[0].value); | |
2743 | break; | |
2744 | } | |
2745 | if (r) | |
2746 | r = -EINVAL; | |
2747 | return r; | |
2748 | } | |
2749 | ||
313a3dc7 CO |
2750 | long kvm_arch_vcpu_ioctl(struct file *filp, |
2751 | unsigned int ioctl, unsigned long arg) | |
2752 | { | |
2753 | struct kvm_vcpu *vcpu = filp->private_data; | |
2754 | void __user *argp = (void __user *)arg; | |
2755 | int r; | |
d1ac91d8 AK |
2756 | union { |
2757 | struct kvm_lapic_state *lapic; | |
2758 | struct kvm_xsave *xsave; | |
2759 | struct kvm_xcrs *xcrs; | |
2760 | void *buffer; | |
2761 | } u; | |
2762 | ||
2763 | u.buffer = NULL; | |
313a3dc7 CO |
2764 | switch (ioctl) { |
2765 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
2766 | r = -EINVAL; |
2767 | if (!vcpu->arch.apic) | |
2768 | goto out; | |
d1ac91d8 | 2769 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 2770 | |
b772ff36 | 2771 | r = -ENOMEM; |
d1ac91d8 | 2772 | if (!u.lapic) |
b772ff36 | 2773 | goto out; |
d1ac91d8 | 2774 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
2775 | if (r) |
2776 | goto out; | |
2777 | r = -EFAULT; | |
d1ac91d8 | 2778 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
2779 | goto out; |
2780 | r = 0; | |
2781 | break; | |
2782 | } | |
2783 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
2784 | r = -EINVAL; |
2785 | if (!vcpu->arch.apic) | |
2786 | goto out; | |
d1ac91d8 | 2787 | u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
b772ff36 | 2788 | r = -ENOMEM; |
d1ac91d8 | 2789 | if (!u.lapic) |
b772ff36 | 2790 | goto out; |
313a3dc7 | 2791 | r = -EFAULT; |
d1ac91d8 | 2792 | if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state))) |
313a3dc7 | 2793 | goto out; |
d1ac91d8 | 2794 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
2795 | if (r) |
2796 | goto out; | |
2797 | r = 0; | |
2798 | break; | |
2799 | } | |
f77bc6a4 ZX |
2800 | case KVM_INTERRUPT: { |
2801 | struct kvm_interrupt irq; | |
2802 | ||
2803 | r = -EFAULT; | |
2804 | if (copy_from_user(&irq, argp, sizeof irq)) | |
2805 | goto out; | |
2806 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
2807 | if (r) | |
2808 | goto out; | |
2809 | r = 0; | |
2810 | break; | |
2811 | } | |
c4abb7c9 JK |
2812 | case KVM_NMI: { |
2813 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
2814 | if (r) | |
2815 | goto out; | |
2816 | r = 0; | |
2817 | break; | |
2818 | } | |
313a3dc7 CO |
2819 | case KVM_SET_CPUID: { |
2820 | struct kvm_cpuid __user *cpuid_arg = argp; | |
2821 | struct kvm_cpuid cpuid; | |
2822 | ||
2823 | r = -EFAULT; | |
2824 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2825 | goto out; | |
2826 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
2827 | if (r) | |
2828 | goto out; | |
2829 | break; | |
2830 | } | |
07716717 DK |
2831 | case KVM_SET_CPUID2: { |
2832 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2833 | struct kvm_cpuid2 cpuid; | |
2834 | ||
2835 | r = -EFAULT; | |
2836 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2837 | goto out; | |
2838 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 2839 | cpuid_arg->entries); |
07716717 DK |
2840 | if (r) |
2841 | goto out; | |
2842 | break; | |
2843 | } | |
2844 | case KVM_GET_CPUID2: { | |
2845 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2846 | struct kvm_cpuid2 cpuid; | |
2847 | ||
2848 | r = -EFAULT; | |
2849 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2850 | goto out; | |
2851 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 2852 | cpuid_arg->entries); |
07716717 DK |
2853 | if (r) |
2854 | goto out; | |
2855 | r = -EFAULT; | |
2856 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2857 | goto out; | |
2858 | r = 0; | |
2859 | break; | |
2860 | } | |
313a3dc7 CO |
2861 | case KVM_GET_MSRS: |
2862 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
2863 | break; | |
2864 | case KVM_SET_MSRS: | |
2865 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
2866 | break; | |
b209749f AK |
2867 | case KVM_TPR_ACCESS_REPORTING: { |
2868 | struct kvm_tpr_access_ctl tac; | |
2869 | ||
2870 | r = -EFAULT; | |
2871 | if (copy_from_user(&tac, argp, sizeof tac)) | |
2872 | goto out; | |
2873 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
2874 | if (r) | |
2875 | goto out; | |
2876 | r = -EFAULT; | |
2877 | if (copy_to_user(argp, &tac, sizeof tac)) | |
2878 | goto out; | |
2879 | r = 0; | |
2880 | break; | |
2881 | }; | |
b93463aa AK |
2882 | case KVM_SET_VAPIC_ADDR: { |
2883 | struct kvm_vapic_addr va; | |
2884 | ||
2885 | r = -EINVAL; | |
2886 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2887 | goto out; | |
2888 | r = -EFAULT; | |
2889 | if (copy_from_user(&va, argp, sizeof va)) | |
2890 | goto out; | |
2891 | r = 0; | |
2892 | kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); | |
2893 | break; | |
2894 | } | |
890ca9ae HY |
2895 | case KVM_X86_SETUP_MCE: { |
2896 | u64 mcg_cap; | |
2897 | ||
2898 | r = -EFAULT; | |
2899 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
2900 | goto out; | |
2901 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
2902 | break; | |
2903 | } | |
2904 | case KVM_X86_SET_MCE: { | |
2905 | struct kvm_x86_mce mce; | |
2906 | ||
2907 | r = -EFAULT; | |
2908 | if (copy_from_user(&mce, argp, sizeof mce)) | |
2909 | goto out; | |
2910 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
2911 | break; | |
2912 | } | |
3cfc3092 JK |
2913 | case KVM_GET_VCPU_EVENTS: { |
2914 | struct kvm_vcpu_events events; | |
2915 | ||
2916 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
2917 | ||
2918 | r = -EFAULT; | |
2919 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
2920 | break; | |
2921 | r = 0; | |
2922 | break; | |
2923 | } | |
2924 | case KVM_SET_VCPU_EVENTS: { | |
2925 | struct kvm_vcpu_events events; | |
2926 | ||
2927 | r = -EFAULT; | |
2928 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
2929 | break; | |
2930 | ||
2931 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
2932 | break; | |
2933 | } | |
a1efbe77 JK |
2934 | case KVM_GET_DEBUGREGS: { |
2935 | struct kvm_debugregs dbgregs; | |
2936 | ||
2937 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
2938 | ||
2939 | r = -EFAULT; | |
2940 | if (copy_to_user(argp, &dbgregs, | |
2941 | sizeof(struct kvm_debugregs))) | |
2942 | break; | |
2943 | r = 0; | |
2944 | break; | |
2945 | } | |
2946 | case KVM_SET_DEBUGREGS: { | |
2947 | struct kvm_debugregs dbgregs; | |
2948 | ||
2949 | r = -EFAULT; | |
2950 | if (copy_from_user(&dbgregs, argp, | |
2951 | sizeof(struct kvm_debugregs))) | |
2952 | break; | |
2953 | ||
2954 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
2955 | break; | |
2956 | } | |
2d5b5a66 | 2957 | case KVM_GET_XSAVE: { |
d1ac91d8 | 2958 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 2959 | r = -ENOMEM; |
d1ac91d8 | 2960 | if (!u.xsave) |
2d5b5a66 SY |
2961 | break; |
2962 | ||
d1ac91d8 | 2963 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
2964 | |
2965 | r = -EFAULT; | |
d1ac91d8 | 2966 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
2967 | break; |
2968 | r = 0; | |
2969 | break; | |
2970 | } | |
2971 | case KVM_SET_XSAVE: { | |
d1ac91d8 | 2972 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 2973 | r = -ENOMEM; |
d1ac91d8 | 2974 | if (!u.xsave) |
2d5b5a66 SY |
2975 | break; |
2976 | ||
2977 | r = -EFAULT; | |
d1ac91d8 | 2978 | if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
2979 | break; |
2980 | ||
d1ac91d8 | 2981 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
2982 | break; |
2983 | } | |
2984 | case KVM_GET_XCRS: { | |
d1ac91d8 | 2985 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 2986 | r = -ENOMEM; |
d1ac91d8 | 2987 | if (!u.xcrs) |
2d5b5a66 SY |
2988 | break; |
2989 | ||
d1ac91d8 | 2990 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
2991 | |
2992 | r = -EFAULT; | |
d1ac91d8 | 2993 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
2994 | sizeof(struct kvm_xcrs))) |
2995 | break; | |
2996 | r = 0; | |
2997 | break; | |
2998 | } | |
2999 | case KVM_SET_XCRS: { | |
d1ac91d8 | 3000 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 3001 | r = -ENOMEM; |
d1ac91d8 | 3002 | if (!u.xcrs) |
2d5b5a66 SY |
3003 | break; |
3004 | ||
3005 | r = -EFAULT; | |
d1ac91d8 | 3006 | if (copy_from_user(u.xcrs, argp, |
2d5b5a66 SY |
3007 | sizeof(struct kvm_xcrs))) |
3008 | break; | |
3009 | ||
d1ac91d8 | 3010 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3011 | break; |
3012 | } | |
313a3dc7 CO |
3013 | default: |
3014 | r = -EINVAL; | |
3015 | } | |
3016 | out: | |
d1ac91d8 | 3017 | kfree(u.buffer); |
313a3dc7 CO |
3018 | return r; |
3019 | } | |
3020 | ||
1fe779f8 CO |
3021 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
3022 | { | |
3023 | int ret; | |
3024 | ||
3025 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
3026 | return -1; | |
3027 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); | |
3028 | return ret; | |
3029 | } | |
3030 | ||
b927a3ce SY |
3031 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
3032 | u64 ident_addr) | |
3033 | { | |
3034 | kvm->arch.ept_identity_map_addr = ident_addr; | |
3035 | return 0; | |
3036 | } | |
3037 | ||
1fe779f8 CO |
3038 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
3039 | u32 kvm_nr_mmu_pages) | |
3040 | { | |
3041 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
3042 | return -EINVAL; | |
3043 | ||
79fac95e | 3044 | mutex_lock(&kvm->slots_lock); |
7c8a83b7 | 3045 | spin_lock(&kvm->mmu_lock); |
1fe779f8 CO |
3046 | |
3047 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 3048 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 3049 | |
7c8a83b7 | 3050 | spin_unlock(&kvm->mmu_lock); |
79fac95e | 3051 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
3052 | return 0; |
3053 | } | |
3054 | ||
3055 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
3056 | { | |
39de71ec | 3057 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
3058 | } |
3059 | ||
1fe779f8 CO |
3060 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
3061 | { | |
3062 | int r; | |
3063 | ||
3064 | r = 0; | |
3065 | switch (chip->chip_id) { | |
3066 | case KVM_IRQCHIP_PIC_MASTER: | |
3067 | memcpy(&chip->chip.pic, | |
3068 | &pic_irqchip(kvm)->pics[0], | |
3069 | sizeof(struct kvm_pic_state)); | |
3070 | break; | |
3071 | case KVM_IRQCHIP_PIC_SLAVE: | |
3072 | memcpy(&chip->chip.pic, | |
3073 | &pic_irqchip(kvm)->pics[1], | |
3074 | sizeof(struct kvm_pic_state)); | |
3075 | break; | |
3076 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3077 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3078 | break; |
3079 | default: | |
3080 | r = -EINVAL; | |
3081 | break; | |
3082 | } | |
3083 | return r; | |
3084 | } | |
3085 | ||
3086 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
3087 | { | |
3088 | int r; | |
3089 | ||
3090 | r = 0; | |
3091 | switch (chip->chip_id) { | |
3092 | case KVM_IRQCHIP_PIC_MASTER: | |
f4f51050 | 3093 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3094 | memcpy(&pic_irqchip(kvm)->pics[0], |
3095 | &chip->chip.pic, | |
3096 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3097 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3098 | break; |
3099 | case KVM_IRQCHIP_PIC_SLAVE: | |
f4f51050 | 3100 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3101 | memcpy(&pic_irqchip(kvm)->pics[1], |
3102 | &chip->chip.pic, | |
3103 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3104 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3105 | break; |
3106 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3107 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3108 | break; |
3109 | default: | |
3110 | r = -EINVAL; | |
3111 | break; | |
3112 | } | |
3113 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
3114 | return r; | |
3115 | } | |
3116 | ||
e0f63cb9 SY |
3117 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
3118 | { | |
3119 | int r = 0; | |
3120 | ||
894a9c55 | 3121 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3122 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 3123 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3124 | return r; |
3125 | } | |
3126 | ||
3127 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
3128 | { | |
3129 | int r = 0; | |
3130 | ||
894a9c55 | 3131 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3132 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
3133 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
3134 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3135 | return r; | |
3136 | } | |
3137 | ||
3138 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3139 | { | |
3140 | int r = 0; | |
3141 | ||
3142 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3143 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
3144 | sizeof(ps->channels)); | |
3145 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
3146 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 3147 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
e9f42757 BK |
3148 | return r; |
3149 | } | |
3150 | ||
3151 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3152 | { | |
3153 | int r = 0, start = 0; | |
3154 | u32 prev_legacy, cur_legacy; | |
3155 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3156 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3157 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3158 | if (!prev_legacy && cur_legacy) | |
3159 | start = 1; | |
3160 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
3161 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
3162 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
3163 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 3164 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3165 | return r; |
3166 | } | |
3167 | ||
52d939a0 MT |
3168 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
3169 | struct kvm_reinject_control *control) | |
3170 | { | |
3171 | if (!kvm->arch.vpit) | |
3172 | return -ENXIO; | |
894a9c55 | 3173 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 | 3174 | kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject; |
894a9c55 | 3175 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
3176 | return 0; |
3177 | } | |
3178 | ||
5bb064dc ZX |
3179 | /* |
3180 | * Get (and clear) the dirty memory log for a memory slot. | |
3181 | */ | |
3182 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, | |
3183 | struct kvm_dirty_log *log) | |
3184 | { | |
87bf6e7d | 3185 | int r, i; |
5bb064dc | 3186 | struct kvm_memory_slot *memslot; |
87bf6e7d | 3187 | unsigned long n; |
b050b015 | 3188 | unsigned long is_dirty = 0; |
5bb064dc | 3189 | |
79fac95e | 3190 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 3191 | |
b050b015 MT |
3192 | r = -EINVAL; |
3193 | if (log->slot >= KVM_MEMORY_SLOTS) | |
3194 | goto out; | |
3195 | ||
3196 | memslot = &kvm->memslots->memslots[log->slot]; | |
3197 | r = -ENOENT; | |
3198 | if (!memslot->dirty_bitmap) | |
3199 | goto out; | |
3200 | ||
87bf6e7d | 3201 | n = kvm_dirty_bitmap_bytes(memslot); |
b050b015 | 3202 | |
b050b015 MT |
3203 | for (i = 0; !is_dirty && i < n/sizeof(long); i++) |
3204 | is_dirty = memslot->dirty_bitmap[i]; | |
5bb064dc ZX |
3205 | |
3206 | /* If nothing is dirty, don't bother messing with page tables. */ | |
3207 | if (is_dirty) { | |
b050b015 | 3208 | struct kvm_memslots *slots, *old_slots; |
914ebccd | 3209 | unsigned long *dirty_bitmap; |
b050b015 | 3210 | |
515a0127 TY |
3211 | dirty_bitmap = memslot->dirty_bitmap_head; |
3212 | if (memslot->dirty_bitmap == dirty_bitmap) | |
3213 | dirty_bitmap += n / sizeof(long); | |
914ebccd | 3214 | memset(dirty_bitmap, 0, n); |
b050b015 | 3215 | |
914ebccd TY |
3216 | r = -ENOMEM; |
3217 | slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL); | |
515a0127 | 3218 | if (!slots) |
914ebccd | 3219 | goto out; |
b050b015 MT |
3220 | memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots)); |
3221 | slots->memslots[log->slot].dirty_bitmap = dirty_bitmap; | |
49c7754c | 3222 | slots->generation++; |
b050b015 MT |
3223 | |
3224 | old_slots = kvm->memslots; | |
3225 | rcu_assign_pointer(kvm->memslots, slots); | |
3226 | synchronize_srcu_expedited(&kvm->srcu); | |
3227 | dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap; | |
3228 | kfree(old_slots); | |
914ebccd | 3229 | |
edde99ce MT |
3230 | spin_lock(&kvm->mmu_lock); |
3231 | kvm_mmu_slot_remove_write_access(kvm, log->slot); | |
3232 | spin_unlock(&kvm->mmu_lock); | |
3233 | ||
914ebccd | 3234 | r = -EFAULT; |
515a0127 | 3235 | if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) |
914ebccd | 3236 | goto out; |
914ebccd TY |
3237 | } else { |
3238 | r = -EFAULT; | |
3239 | if (clear_user(log->dirty_bitmap, n)) | |
3240 | goto out; | |
5bb064dc | 3241 | } |
b050b015 | 3242 | |
5bb064dc ZX |
3243 | r = 0; |
3244 | out: | |
79fac95e | 3245 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
3246 | return r; |
3247 | } | |
3248 | ||
1fe779f8 CO |
3249 | long kvm_arch_vm_ioctl(struct file *filp, |
3250 | unsigned int ioctl, unsigned long arg) | |
3251 | { | |
3252 | struct kvm *kvm = filp->private_data; | |
3253 | void __user *argp = (void __user *)arg; | |
367e1319 | 3254 | int r = -ENOTTY; |
f0d66275 DH |
3255 | /* |
3256 | * This union makes it completely explicit to gcc-3.x | |
3257 | * that these two variables' stack usage should be | |
3258 | * combined, not added together. | |
3259 | */ | |
3260 | union { | |
3261 | struct kvm_pit_state ps; | |
e9f42757 | 3262 | struct kvm_pit_state2 ps2; |
c5ff41ce | 3263 | struct kvm_pit_config pit_config; |
f0d66275 | 3264 | } u; |
1fe779f8 CO |
3265 | |
3266 | switch (ioctl) { | |
3267 | case KVM_SET_TSS_ADDR: | |
3268 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
3269 | if (r < 0) | |
3270 | goto out; | |
3271 | break; | |
b927a3ce SY |
3272 | case KVM_SET_IDENTITY_MAP_ADDR: { |
3273 | u64 ident_addr; | |
3274 | ||
3275 | r = -EFAULT; | |
3276 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
3277 | goto out; | |
3278 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
3279 | if (r < 0) | |
3280 | goto out; | |
3281 | break; | |
3282 | } | |
1fe779f8 CO |
3283 | case KVM_SET_NR_MMU_PAGES: |
3284 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
3285 | if (r) | |
3286 | goto out; | |
3287 | break; | |
3288 | case KVM_GET_NR_MMU_PAGES: | |
3289 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
3290 | break; | |
3ddea128 MT |
3291 | case KVM_CREATE_IRQCHIP: { |
3292 | struct kvm_pic *vpic; | |
3293 | ||
3294 | mutex_lock(&kvm->lock); | |
3295 | r = -EEXIST; | |
3296 | if (kvm->arch.vpic) | |
3297 | goto create_irqchip_unlock; | |
1fe779f8 | 3298 | r = -ENOMEM; |
3ddea128 MT |
3299 | vpic = kvm_create_pic(kvm); |
3300 | if (vpic) { | |
1fe779f8 CO |
3301 | r = kvm_ioapic_init(kvm); |
3302 | if (r) { | |
72bb2fcd WY |
3303 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, |
3304 | &vpic->dev); | |
3ddea128 MT |
3305 | kfree(vpic); |
3306 | goto create_irqchip_unlock; | |
1fe779f8 CO |
3307 | } |
3308 | } else | |
3ddea128 MT |
3309 | goto create_irqchip_unlock; |
3310 | smp_wmb(); | |
3311 | kvm->arch.vpic = vpic; | |
3312 | smp_wmb(); | |
399ec807 AK |
3313 | r = kvm_setup_default_irq_routing(kvm); |
3314 | if (r) { | |
3ddea128 | 3315 | mutex_lock(&kvm->irq_lock); |
72bb2fcd WY |
3316 | kvm_ioapic_destroy(kvm); |
3317 | kvm_destroy_pic(kvm); | |
3ddea128 | 3318 | mutex_unlock(&kvm->irq_lock); |
399ec807 | 3319 | } |
3ddea128 MT |
3320 | create_irqchip_unlock: |
3321 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 3322 | break; |
3ddea128 | 3323 | } |
7837699f | 3324 | case KVM_CREATE_PIT: |
c5ff41ce JK |
3325 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
3326 | goto create_pit; | |
3327 | case KVM_CREATE_PIT2: | |
3328 | r = -EFAULT; | |
3329 | if (copy_from_user(&u.pit_config, argp, | |
3330 | sizeof(struct kvm_pit_config))) | |
3331 | goto out; | |
3332 | create_pit: | |
79fac95e | 3333 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
3334 | r = -EEXIST; |
3335 | if (kvm->arch.vpit) | |
3336 | goto create_pit_unlock; | |
7837699f | 3337 | r = -ENOMEM; |
c5ff41ce | 3338 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
3339 | if (kvm->arch.vpit) |
3340 | r = 0; | |
269e05e4 | 3341 | create_pit_unlock: |
79fac95e | 3342 | mutex_unlock(&kvm->slots_lock); |
7837699f | 3343 | break; |
4925663a | 3344 | case KVM_IRQ_LINE_STATUS: |
1fe779f8 CO |
3345 | case KVM_IRQ_LINE: { |
3346 | struct kvm_irq_level irq_event; | |
3347 | ||
3348 | r = -EFAULT; | |
3349 | if (copy_from_user(&irq_event, argp, sizeof irq_event)) | |
3350 | goto out; | |
160d2f6c | 3351 | r = -ENXIO; |
1fe779f8 | 3352 | if (irqchip_in_kernel(kvm)) { |
4925663a | 3353 | __s32 status; |
4925663a GN |
3354 | status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, |
3355 | irq_event.irq, irq_event.level); | |
4925663a | 3356 | if (ioctl == KVM_IRQ_LINE_STATUS) { |
160d2f6c | 3357 | r = -EFAULT; |
4925663a GN |
3358 | irq_event.status = status; |
3359 | if (copy_to_user(argp, &irq_event, | |
3360 | sizeof irq_event)) | |
3361 | goto out; | |
3362 | } | |
1fe779f8 CO |
3363 | r = 0; |
3364 | } | |
3365 | break; | |
3366 | } | |
3367 | case KVM_GET_IRQCHIP: { | |
3368 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 3369 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 3370 | |
f0d66275 DH |
3371 | r = -ENOMEM; |
3372 | if (!chip) | |
1fe779f8 | 3373 | goto out; |
f0d66275 DH |
3374 | r = -EFAULT; |
3375 | if (copy_from_user(chip, argp, sizeof *chip)) | |
3376 | goto get_irqchip_out; | |
1fe779f8 CO |
3377 | r = -ENXIO; |
3378 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3379 | goto get_irqchip_out; |
3380 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 3381 | if (r) |
f0d66275 | 3382 | goto get_irqchip_out; |
1fe779f8 | 3383 | r = -EFAULT; |
f0d66275 DH |
3384 | if (copy_to_user(argp, chip, sizeof *chip)) |
3385 | goto get_irqchip_out; | |
1fe779f8 | 3386 | r = 0; |
f0d66275 DH |
3387 | get_irqchip_out: |
3388 | kfree(chip); | |
3389 | if (r) | |
3390 | goto out; | |
1fe779f8 CO |
3391 | break; |
3392 | } | |
3393 | case KVM_SET_IRQCHIP: { | |
3394 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 3395 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 3396 | |
f0d66275 DH |
3397 | r = -ENOMEM; |
3398 | if (!chip) | |
1fe779f8 | 3399 | goto out; |
f0d66275 DH |
3400 | r = -EFAULT; |
3401 | if (copy_from_user(chip, argp, sizeof *chip)) | |
3402 | goto set_irqchip_out; | |
1fe779f8 CO |
3403 | r = -ENXIO; |
3404 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3405 | goto set_irqchip_out; |
3406 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 3407 | if (r) |
f0d66275 | 3408 | goto set_irqchip_out; |
1fe779f8 | 3409 | r = 0; |
f0d66275 DH |
3410 | set_irqchip_out: |
3411 | kfree(chip); | |
3412 | if (r) | |
3413 | goto out; | |
1fe779f8 CO |
3414 | break; |
3415 | } | |
e0f63cb9 | 3416 | case KVM_GET_PIT: { |
e0f63cb9 | 3417 | r = -EFAULT; |
f0d66275 | 3418 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3419 | goto out; |
3420 | r = -ENXIO; | |
3421 | if (!kvm->arch.vpit) | |
3422 | goto out; | |
f0d66275 | 3423 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
3424 | if (r) |
3425 | goto out; | |
3426 | r = -EFAULT; | |
f0d66275 | 3427 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3428 | goto out; |
3429 | r = 0; | |
3430 | break; | |
3431 | } | |
3432 | case KVM_SET_PIT: { | |
e0f63cb9 | 3433 | r = -EFAULT; |
f0d66275 | 3434 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
3435 | goto out; |
3436 | r = -ENXIO; | |
3437 | if (!kvm->arch.vpit) | |
3438 | goto out; | |
f0d66275 | 3439 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
3440 | if (r) |
3441 | goto out; | |
3442 | r = 0; | |
3443 | break; | |
3444 | } | |
e9f42757 BK |
3445 | case KVM_GET_PIT2: { |
3446 | r = -ENXIO; | |
3447 | if (!kvm->arch.vpit) | |
3448 | goto out; | |
3449 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
3450 | if (r) | |
3451 | goto out; | |
3452 | r = -EFAULT; | |
3453 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
3454 | goto out; | |
3455 | r = 0; | |
3456 | break; | |
3457 | } | |
3458 | case KVM_SET_PIT2: { | |
3459 | r = -EFAULT; | |
3460 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
3461 | goto out; | |
3462 | r = -ENXIO; | |
3463 | if (!kvm->arch.vpit) | |
3464 | goto out; | |
3465 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
3466 | if (r) | |
3467 | goto out; | |
3468 | r = 0; | |
3469 | break; | |
3470 | } | |
52d939a0 MT |
3471 | case KVM_REINJECT_CONTROL: { |
3472 | struct kvm_reinject_control control; | |
3473 | r = -EFAULT; | |
3474 | if (copy_from_user(&control, argp, sizeof(control))) | |
3475 | goto out; | |
3476 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
3477 | if (r) | |
3478 | goto out; | |
3479 | r = 0; | |
3480 | break; | |
3481 | } | |
ffde22ac ES |
3482 | case KVM_XEN_HVM_CONFIG: { |
3483 | r = -EFAULT; | |
3484 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
3485 | sizeof(struct kvm_xen_hvm_config))) | |
3486 | goto out; | |
3487 | r = -EINVAL; | |
3488 | if (kvm->arch.xen_hvm_config.flags) | |
3489 | goto out; | |
3490 | r = 0; | |
3491 | break; | |
3492 | } | |
afbcf7ab | 3493 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
3494 | struct kvm_clock_data user_ns; |
3495 | u64 now_ns; | |
3496 | s64 delta; | |
3497 | ||
3498 | r = -EFAULT; | |
3499 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
3500 | goto out; | |
3501 | ||
3502 | r = -EINVAL; | |
3503 | if (user_ns.flags) | |
3504 | goto out; | |
3505 | ||
3506 | r = 0; | |
395c6b0a | 3507 | local_irq_disable(); |
759379dd | 3508 | now_ns = get_kernel_ns(); |
afbcf7ab | 3509 | delta = user_ns.clock - now_ns; |
395c6b0a | 3510 | local_irq_enable(); |
afbcf7ab GC |
3511 | kvm->arch.kvmclock_offset = delta; |
3512 | break; | |
3513 | } | |
3514 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
3515 | struct kvm_clock_data user_ns; |
3516 | u64 now_ns; | |
3517 | ||
395c6b0a | 3518 | local_irq_disable(); |
759379dd | 3519 | now_ns = get_kernel_ns(); |
afbcf7ab | 3520 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; |
395c6b0a | 3521 | local_irq_enable(); |
afbcf7ab | 3522 | user_ns.flags = 0; |
97e69aa6 | 3523 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
3524 | |
3525 | r = -EFAULT; | |
3526 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
3527 | goto out; | |
3528 | r = 0; | |
3529 | break; | |
3530 | } | |
3531 | ||
1fe779f8 CO |
3532 | default: |
3533 | ; | |
3534 | } | |
3535 | out: | |
3536 | return r; | |
3537 | } | |
3538 | ||
a16b043c | 3539 | static void kvm_init_msr_list(void) |
043405e1 CO |
3540 | { |
3541 | u32 dummy[2]; | |
3542 | unsigned i, j; | |
3543 | ||
e3267cbb GC |
3544 | /* skip the first msrs in the list. KVM-specific */ |
3545 | for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { | |
043405e1 CO |
3546 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
3547 | continue; | |
3548 | if (j < i) | |
3549 | msrs_to_save[j] = msrs_to_save[i]; | |
3550 | j++; | |
3551 | } | |
3552 | num_msrs_to_save = j; | |
3553 | } | |
3554 | ||
bda9020e MT |
3555 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
3556 | const void *v) | |
bbd9b64e | 3557 | { |
bda9020e MT |
3558 | if (vcpu->arch.apic && |
3559 | !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v)) | |
3560 | return 0; | |
bbd9b64e | 3561 | |
e93f8a0f | 3562 | return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v); |
bbd9b64e CO |
3563 | } |
3564 | ||
bda9020e | 3565 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 3566 | { |
bda9020e MT |
3567 | if (vcpu->arch.apic && |
3568 | !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v)) | |
3569 | return 0; | |
bbd9b64e | 3570 | |
e93f8a0f | 3571 | return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v); |
bbd9b64e CO |
3572 | } |
3573 | ||
2dafc6c2 GN |
3574 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
3575 | struct kvm_segment *var, int seg) | |
3576 | { | |
3577 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
3578 | } | |
3579 | ||
3580 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
3581 | struct kvm_segment *var, int seg) | |
3582 | { | |
3583 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
3584 | } | |
3585 | ||
c30a358d JR |
3586 | static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) |
3587 | { | |
3588 | return gpa; | |
3589 | } | |
3590 | ||
02f59dc9 JR |
3591 | static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) |
3592 | { | |
3593 | gpa_t t_gpa; | |
3594 | u32 error; | |
3595 | ||
3596 | BUG_ON(!mmu_is_nested(vcpu)); | |
3597 | ||
3598 | /* NPT walks are always user-walks */ | |
3599 | access |= PFERR_USER_MASK; | |
3600 | t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error); | |
3601 | if (t_gpa == UNMAPPED_GVA) | |
0959ffac | 3602 | vcpu->arch.fault.nested = true; |
02f59dc9 JR |
3603 | |
3604 | return t_gpa; | |
3605 | } | |
3606 | ||
1871c602 GN |
3607 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) |
3608 | { | |
3609 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
14dfe855 | 3610 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error); |
1871c602 GN |
3611 | } |
3612 | ||
3613 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) | |
3614 | { | |
3615 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3616 | access |= PFERR_FETCH_MASK; | |
14dfe855 | 3617 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error); |
1871c602 GN |
3618 | } |
3619 | ||
3620 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) | |
3621 | { | |
3622 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3623 | access |= PFERR_WRITE_MASK; | |
14dfe855 | 3624 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error); |
1871c602 GN |
3625 | } |
3626 | ||
3627 | /* uses this to access any guest's mapped memory without checking CPL */ | |
3628 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) | |
3629 | { | |
14dfe855 | 3630 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error); |
1871c602 GN |
3631 | } |
3632 | ||
3633 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
3634 | struct kvm_vcpu *vcpu, u32 access, | |
3635 | u32 *error) | |
bbd9b64e CO |
3636 | { |
3637 | void *data = val; | |
10589a46 | 3638 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
3639 | |
3640 | while (bytes) { | |
14dfe855 JR |
3641 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
3642 | error); | |
bbd9b64e | 3643 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 3644 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
3645 | int ret; |
3646 | ||
10589a46 MT |
3647 | if (gpa == UNMAPPED_GVA) { |
3648 | r = X86EMUL_PROPAGATE_FAULT; | |
3649 | goto out; | |
3650 | } | |
77c2002e | 3651 | ret = kvm_read_guest(vcpu->kvm, gpa, data, toread); |
10589a46 | 3652 | if (ret < 0) { |
c3cd7ffa | 3653 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
3654 | goto out; |
3655 | } | |
bbd9b64e | 3656 | |
77c2002e IE |
3657 | bytes -= toread; |
3658 | data += toread; | |
3659 | addr += toread; | |
bbd9b64e | 3660 | } |
10589a46 | 3661 | out: |
10589a46 | 3662 | return r; |
bbd9b64e | 3663 | } |
77c2002e | 3664 | |
1871c602 GN |
3665 | /* used for instruction fetching */ |
3666 | static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes, | |
3667 | struct kvm_vcpu *vcpu, u32 *error) | |
3668 | { | |
3669 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3670 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, | |
3671 | access | PFERR_FETCH_MASK, error); | |
3672 | } | |
3673 | ||
3674 | static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes, | |
3675 | struct kvm_vcpu *vcpu, u32 *error) | |
3676 | { | |
3677 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3678 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, | |
3679 | error); | |
3680 | } | |
3681 | ||
3682 | static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes, | |
3683 | struct kvm_vcpu *vcpu, u32 *error) | |
3684 | { | |
3685 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error); | |
3686 | } | |
3687 | ||
7972995b | 3688 | static int kvm_write_guest_virt_system(gva_t addr, void *val, |
2dafc6c2 | 3689 | unsigned int bytes, |
7972995b | 3690 | struct kvm_vcpu *vcpu, |
2dafc6c2 | 3691 | u32 *error) |
77c2002e IE |
3692 | { |
3693 | void *data = val; | |
3694 | int r = X86EMUL_CONTINUE; | |
3695 | ||
3696 | while (bytes) { | |
14dfe855 JR |
3697 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
3698 | PFERR_WRITE_MASK, | |
3699 | error); | |
77c2002e IE |
3700 | unsigned offset = addr & (PAGE_SIZE-1); |
3701 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
3702 | int ret; | |
3703 | ||
3704 | if (gpa == UNMAPPED_GVA) { | |
3705 | r = X86EMUL_PROPAGATE_FAULT; | |
3706 | goto out; | |
3707 | } | |
3708 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); | |
3709 | if (ret < 0) { | |
c3cd7ffa | 3710 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
3711 | goto out; |
3712 | } | |
3713 | ||
3714 | bytes -= towrite; | |
3715 | data += towrite; | |
3716 | addr += towrite; | |
3717 | } | |
3718 | out: | |
3719 | return r; | |
3720 | } | |
3721 | ||
bbd9b64e CO |
3722 | static int emulator_read_emulated(unsigned long addr, |
3723 | void *val, | |
3724 | unsigned int bytes, | |
8fe681e9 | 3725 | unsigned int *error_code, |
bbd9b64e CO |
3726 | struct kvm_vcpu *vcpu) |
3727 | { | |
bbd9b64e CO |
3728 | gpa_t gpa; |
3729 | ||
3730 | if (vcpu->mmio_read_completed) { | |
3731 | memcpy(val, vcpu->mmio_data, bytes); | |
aec51dc4 AK |
3732 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
3733 | vcpu->mmio_phys_addr, *(u64 *)val); | |
bbd9b64e CO |
3734 | vcpu->mmio_read_completed = 0; |
3735 | return X86EMUL_CONTINUE; | |
3736 | } | |
3737 | ||
8fe681e9 | 3738 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code); |
1871c602 | 3739 | |
8fe681e9 | 3740 | if (gpa == UNMAPPED_GVA) |
1871c602 | 3741 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
3742 | |
3743 | /* For APIC access vmexit */ | |
3744 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3745 | goto mmio; | |
3746 | ||
1871c602 | 3747 | if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL) |
77c2002e | 3748 | == X86EMUL_CONTINUE) |
bbd9b64e | 3749 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
3750 | |
3751 | mmio: | |
3752 | /* | |
3753 | * Is this MMIO handled locally? | |
3754 | */ | |
aec51dc4 AK |
3755 | if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) { |
3756 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val); | |
bbd9b64e CO |
3757 | return X86EMUL_CONTINUE; |
3758 | } | |
aec51dc4 AK |
3759 | |
3760 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
bbd9b64e CO |
3761 | |
3762 | vcpu->mmio_needed = 1; | |
411c35b7 GN |
3763 | vcpu->run->exit_reason = KVM_EXIT_MMIO; |
3764 | vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa; | |
3765 | vcpu->run->mmio.len = vcpu->mmio_size = bytes; | |
3766 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0; | |
bbd9b64e | 3767 | |
c3cd7ffa | 3768 | return X86EMUL_IO_NEEDED; |
bbd9b64e CO |
3769 | } |
3770 | ||
3200f405 | 3771 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 3772 | const void *val, int bytes) |
bbd9b64e CO |
3773 | { |
3774 | int ret; | |
3775 | ||
3776 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 3777 | if (ret < 0) |
bbd9b64e | 3778 | return 0; |
ad218f85 | 3779 | kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1); |
bbd9b64e CO |
3780 | return 1; |
3781 | } | |
3782 | ||
3783 | static int emulator_write_emulated_onepage(unsigned long addr, | |
3784 | const void *val, | |
3785 | unsigned int bytes, | |
8fe681e9 | 3786 | unsigned int *error_code, |
bbd9b64e CO |
3787 | struct kvm_vcpu *vcpu) |
3788 | { | |
10589a46 MT |
3789 | gpa_t gpa; |
3790 | ||
8fe681e9 | 3791 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code); |
bbd9b64e | 3792 | |
8fe681e9 | 3793 | if (gpa == UNMAPPED_GVA) |
bbd9b64e | 3794 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
3795 | |
3796 | /* For APIC access vmexit */ | |
3797 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3798 | goto mmio; | |
3799 | ||
3800 | if (emulator_write_phys(vcpu, gpa, val, bytes)) | |
3801 | return X86EMUL_CONTINUE; | |
3802 | ||
3803 | mmio: | |
aec51dc4 | 3804 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); |
bbd9b64e CO |
3805 | /* |
3806 | * Is this MMIO handled locally? | |
3807 | */ | |
bda9020e | 3808 | if (!vcpu_mmio_write(vcpu, gpa, bytes, val)) |
bbd9b64e | 3809 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
3810 | |
3811 | vcpu->mmio_needed = 1; | |
411c35b7 GN |
3812 | vcpu->run->exit_reason = KVM_EXIT_MMIO; |
3813 | vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa; | |
3814 | vcpu->run->mmio.len = vcpu->mmio_size = bytes; | |
3815 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1; | |
3816 | memcpy(vcpu->run->mmio.data, val, bytes); | |
bbd9b64e CO |
3817 | |
3818 | return X86EMUL_CONTINUE; | |
3819 | } | |
3820 | ||
3821 | int emulator_write_emulated(unsigned long addr, | |
8f6abd06 GN |
3822 | const void *val, |
3823 | unsigned int bytes, | |
8fe681e9 | 3824 | unsigned int *error_code, |
8f6abd06 | 3825 | struct kvm_vcpu *vcpu) |
bbd9b64e CO |
3826 | { |
3827 | /* Crossing a page boundary? */ | |
3828 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
3829 | int rc, now; | |
3830 | ||
3831 | now = -addr & ~PAGE_MASK; | |
8fe681e9 GN |
3832 | rc = emulator_write_emulated_onepage(addr, val, now, error_code, |
3833 | vcpu); | |
bbd9b64e CO |
3834 | if (rc != X86EMUL_CONTINUE) |
3835 | return rc; | |
3836 | addr += now; | |
3837 | val += now; | |
3838 | bytes -= now; | |
3839 | } | |
8fe681e9 GN |
3840 | return emulator_write_emulated_onepage(addr, val, bytes, error_code, |
3841 | vcpu); | |
bbd9b64e | 3842 | } |
bbd9b64e | 3843 | |
daea3e73 AK |
3844 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
3845 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
3846 | ||
3847 | #ifdef CONFIG_X86_64 | |
3848 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
3849 | #else | |
3850 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 3851 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
3852 | #endif |
3853 | ||
bbd9b64e CO |
3854 | static int emulator_cmpxchg_emulated(unsigned long addr, |
3855 | const void *old, | |
3856 | const void *new, | |
3857 | unsigned int bytes, | |
8fe681e9 | 3858 | unsigned int *error_code, |
bbd9b64e CO |
3859 | struct kvm_vcpu *vcpu) |
3860 | { | |
daea3e73 AK |
3861 | gpa_t gpa; |
3862 | struct page *page; | |
3863 | char *kaddr; | |
3864 | bool exchanged; | |
2bacc55c | 3865 | |
daea3e73 AK |
3866 | /* guests cmpxchg8b have to be emulated atomically */ |
3867 | if (bytes > 8 || (bytes & (bytes - 1))) | |
3868 | goto emul_write; | |
10589a46 | 3869 | |
daea3e73 | 3870 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 3871 | |
daea3e73 AK |
3872 | if (gpa == UNMAPPED_GVA || |
3873 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3874 | goto emul_write; | |
2bacc55c | 3875 | |
daea3e73 AK |
3876 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
3877 | goto emul_write; | |
72dc67a6 | 3878 | |
daea3e73 | 3879 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
c19b8bd6 WY |
3880 | if (is_error_page(page)) { |
3881 | kvm_release_page_clean(page); | |
3882 | goto emul_write; | |
3883 | } | |
72dc67a6 | 3884 | |
daea3e73 AK |
3885 | kaddr = kmap_atomic(page, KM_USER0); |
3886 | kaddr += offset_in_page(gpa); | |
3887 | switch (bytes) { | |
3888 | case 1: | |
3889 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
3890 | break; | |
3891 | case 2: | |
3892 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
3893 | break; | |
3894 | case 4: | |
3895 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
3896 | break; | |
3897 | case 8: | |
3898 | exchanged = CMPXCHG64(kaddr, old, new); | |
3899 | break; | |
3900 | default: | |
3901 | BUG(); | |
2bacc55c | 3902 | } |
daea3e73 AK |
3903 | kunmap_atomic(kaddr, KM_USER0); |
3904 | kvm_release_page_dirty(page); | |
3905 | ||
3906 | if (!exchanged) | |
3907 | return X86EMUL_CMPXCHG_FAILED; | |
3908 | ||
8f6abd06 GN |
3909 | kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1); |
3910 | ||
3911 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 3912 | |
3200f405 | 3913 | emul_write: |
daea3e73 | 3914 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 3915 | |
8fe681e9 | 3916 | return emulator_write_emulated(addr, new, bytes, error_code, vcpu); |
bbd9b64e CO |
3917 | } |
3918 | ||
cf8f70bf GN |
3919 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
3920 | { | |
3921 | /* TODO: String I/O for in kernel device */ | |
3922 | int r; | |
3923 | ||
3924 | if (vcpu->arch.pio.in) | |
3925 | r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, | |
3926 | vcpu->arch.pio.size, pd); | |
3927 | else | |
3928 | r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, | |
3929 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
3930 | pd); | |
3931 | return r; | |
3932 | } | |
3933 | ||
3934 | ||
3935 | static int emulator_pio_in_emulated(int size, unsigned short port, void *val, | |
3936 | unsigned int count, struct kvm_vcpu *vcpu) | |
3937 | { | |
7972995b | 3938 | if (vcpu->arch.pio.count) |
cf8f70bf GN |
3939 | goto data_avail; |
3940 | ||
c41a15dd | 3941 | trace_kvm_pio(0, port, size, 1); |
cf8f70bf GN |
3942 | |
3943 | vcpu->arch.pio.port = port; | |
3944 | vcpu->arch.pio.in = 1; | |
7972995b | 3945 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
3946 | vcpu->arch.pio.size = size; |
3947 | ||
3948 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
3949 | data_avail: | |
3950 | memcpy(val, vcpu->arch.pio_data, size * count); | |
7972995b | 3951 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
3952 | return 1; |
3953 | } | |
3954 | ||
3955 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
3956 | vcpu->run->io.direction = KVM_EXIT_IO_IN; | |
3957 | vcpu->run->io.size = size; | |
3958 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
3959 | vcpu->run->io.count = count; | |
3960 | vcpu->run->io.port = port; | |
3961 | ||
3962 | return 0; | |
3963 | } | |
3964 | ||
3965 | static int emulator_pio_out_emulated(int size, unsigned short port, | |
3966 | const void *val, unsigned int count, | |
3967 | struct kvm_vcpu *vcpu) | |
3968 | { | |
c41a15dd | 3969 | trace_kvm_pio(1, port, size, 1); |
cf8f70bf GN |
3970 | |
3971 | vcpu->arch.pio.port = port; | |
3972 | vcpu->arch.pio.in = 0; | |
7972995b | 3973 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
3974 | vcpu->arch.pio.size = size; |
3975 | ||
3976 | memcpy(vcpu->arch.pio_data, val, size * count); | |
3977 | ||
3978 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 3979 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
3980 | return 1; |
3981 | } | |
3982 | ||
3983 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
3984 | vcpu->run->io.direction = KVM_EXIT_IO_OUT; | |
3985 | vcpu->run->io.size = size; | |
3986 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
3987 | vcpu->run->io.count = count; | |
3988 | vcpu->run->io.port = port; | |
3989 | ||
3990 | return 0; | |
3991 | } | |
3992 | ||
bbd9b64e CO |
3993 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
3994 | { | |
3995 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
3996 | } | |
3997 | ||
3998 | int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address) | |
3999 | { | |
a7052897 | 4000 | kvm_mmu_invlpg(vcpu, address); |
bbd9b64e CO |
4001 | return X86EMUL_CONTINUE; |
4002 | } | |
4003 | ||
f5f48ee1 SY |
4004 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) |
4005 | { | |
4006 | if (!need_emulate_wbinvd(vcpu)) | |
4007 | return X86EMUL_CONTINUE; | |
4008 | ||
4009 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
4010 | int cpu = get_cpu(); |
4011 | ||
4012 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
4013 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
4014 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 4015 | put_cpu(); |
f5f48ee1 | 4016 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
4017 | } else |
4018 | wbinvd(); | |
f5f48ee1 SY |
4019 | return X86EMUL_CONTINUE; |
4020 | } | |
4021 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); | |
4022 | ||
bbd9b64e CO |
4023 | int emulate_clts(struct kvm_vcpu *vcpu) |
4024 | { | |
4d4ec087 | 4025 | kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); |
6b52d186 | 4026 | kvm_x86_ops->fpu_activate(vcpu); |
bbd9b64e CO |
4027 | return X86EMUL_CONTINUE; |
4028 | } | |
4029 | ||
35aa5375 | 4030 | int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu) |
bbd9b64e | 4031 | { |
338dbc97 | 4032 | return _kvm_get_dr(vcpu, dr, dest); |
bbd9b64e CO |
4033 | } |
4034 | ||
35aa5375 | 4035 | int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu) |
bbd9b64e | 4036 | { |
338dbc97 GN |
4037 | |
4038 | return __kvm_set_dr(vcpu, dr, value); | |
bbd9b64e CO |
4039 | } |
4040 | ||
52a46617 | 4041 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 4042 | { |
52a46617 | 4043 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
4044 | } |
4045 | ||
52a46617 | 4046 | static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu) |
bbd9b64e | 4047 | { |
52a46617 GN |
4048 | unsigned long value; |
4049 | ||
4050 | switch (cr) { | |
4051 | case 0: | |
4052 | value = kvm_read_cr0(vcpu); | |
4053 | break; | |
4054 | case 2: | |
4055 | value = vcpu->arch.cr2; | |
4056 | break; | |
4057 | case 3: | |
4058 | value = vcpu->arch.cr3; | |
4059 | break; | |
4060 | case 4: | |
4061 | value = kvm_read_cr4(vcpu); | |
4062 | break; | |
4063 | case 8: | |
4064 | value = kvm_get_cr8(vcpu); | |
4065 | break; | |
4066 | default: | |
4067 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); | |
4068 | return 0; | |
4069 | } | |
4070 | ||
4071 | return value; | |
4072 | } | |
4073 | ||
0f12244f | 4074 | static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu) |
52a46617 | 4075 | { |
0f12244f GN |
4076 | int res = 0; |
4077 | ||
52a46617 GN |
4078 | switch (cr) { |
4079 | case 0: | |
49a9b07e | 4080 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
4081 | break; |
4082 | case 2: | |
4083 | vcpu->arch.cr2 = val; | |
4084 | break; | |
4085 | case 3: | |
2390218b | 4086 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
4087 | break; |
4088 | case 4: | |
a83b29c6 | 4089 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
4090 | break; |
4091 | case 8: | |
0f12244f | 4092 | res = __kvm_set_cr8(vcpu, val & 0xfUL); |
52a46617 GN |
4093 | break; |
4094 | default: | |
4095 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); | |
0f12244f | 4096 | res = -1; |
52a46617 | 4097 | } |
0f12244f GN |
4098 | |
4099 | return res; | |
52a46617 GN |
4100 | } |
4101 | ||
9c537244 GN |
4102 | static int emulator_get_cpl(struct kvm_vcpu *vcpu) |
4103 | { | |
4104 | return kvm_x86_ops->get_cpl(vcpu); | |
4105 | } | |
4106 | ||
2dafc6c2 GN |
4107 | static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu) |
4108 | { | |
4109 | kvm_x86_ops->get_gdt(vcpu, dt); | |
4110 | } | |
4111 | ||
160ce1f1 MG |
4112 | static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu) |
4113 | { | |
4114 | kvm_x86_ops->get_idt(vcpu, dt); | |
4115 | } | |
4116 | ||
5951c442 GN |
4117 | static unsigned long emulator_get_cached_segment_base(int seg, |
4118 | struct kvm_vcpu *vcpu) | |
4119 | { | |
4120 | return get_segment_base(vcpu, seg); | |
4121 | } | |
4122 | ||
2dafc6c2 GN |
4123 | static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg, |
4124 | struct kvm_vcpu *vcpu) | |
4125 | { | |
4126 | struct kvm_segment var; | |
4127 | ||
4128 | kvm_get_segment(vcpu, &var, seg); | |
4129 | ||
4130 | if (var.unusable) | |
4131 | return false; | |
4132 | ||
4133 | if (var.g) | |
4134 | var.limit >>= 12; | |
4135 | set_desc_limit(desc, var.limit); | |
4136 | set_desc_base(desc, (unsigned long)var.base); | |
4137 | desc->type = var.type; | |
4138 | desc->s = var.s; | |
4139 | desc->dpl = var.dpl; | |
4140 | desc->p = var.present; | |
4141 | desc->avl = var.avl; | |
4142 | desc->l = var.l; | |
4143 | desc->d = var.db; | |
4144 | desc->g = var.g; | |
4145 | ||
4146 | return true; | |
4147 | } | |
4148 | ||
4149 | static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg, | |
4150 | struct kvm_vcpu *vcpu) | |
4151 | { | |
4152 | struct kvm_segment var; | |
4153 | ||
4154 | /* needed to preserve selector */ | |
4155 | kvm_get_segment(vcpu, &var, seg); | |
4156 | ||
4157 | var.base = get_desc_base(desc); | |
4158 | var.limit = get_desc_limit(desc); | |
4159 | if (desc->g) | |
4160 | var.limit = (var.limit << 12) | 0xfff; | |
4161 | var.type = desc->type; | |
4162 | var.present = desc->p; | |
4163 | var.dpl = desc->dpl; | |
4164 | var.db = desc->d; | |
4165 | var.s = desc->s; | |
4166 | var.l = desc->l; | |
4167 | var.g = desc->g; | |
4168 | var.avl = desc->avl; | |
4169 | var.present = desc->p; | |
4170 | var.unusable = !var.present; | |
4171 | var.padding = 0; | |
4172 | ||
4173 | kvm_set_segment(vcpu, &var, seg); | |
4174 | return; | |
4175 | } | |
4176 | ||
4177 | static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu) | |
4178 | { | |
4179 | struct kvm_segment kvm_seg; | |
4180 | ||
4181 | kvm_get_segment(vcpu, &kvm_seg, seg); | |
4182 | return kvm_seg.selector; | |
4183 | } | |
4184 | ||
4185 | static void emulator_set_segment_selector(u16 sel, int seg, | |
4186 | struct kvm_vcpu *vcpu) | |
4187 | { | |
4188 | struct kvm_segment kvm_seg; | |
4189 | ||
4190 | kvm_get_segment(vcpu, &kvm_seg, seg); | |
4191 | kvm_seg.selector = sel; | |
4192 | kvm_set_segment(vcpu, &kvm_seg, seg); | |
4193 | } | |
4194 | ||
14af3f3c | 4195 | static struct x86_emulate_ops emulate_ops = { |
1871c602 | 4196 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 4197 | .write_std = kvm_write_guest_virt_system, |
1871c602 | 4198 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
4199 | .read_emulated = emulator_read_emulated, |
4200 | .write_emulated = emulator_write_emulated, | |
4201 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
cf8f70bf GN |
4202 | .pio_in_emulated = emulator_pio_in_emulated, |
4203 | .pio_out_emulated = emulator_pio_out_emulated, | |
2dafc6c2 GN |
4204 | .get_cached_descriptor = emulator_get_cached_descriptor, |
4205 | .set_cached_descriptor = emulator_set_cached_descriptor, | |
4206 | .get_segment_selector = emulator_get_segment_selector, | |
4207 | .set_segment_selector = emulator_set_segment_selector, | |
5951c442 | 4208 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 4209 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 4210 | .get_idt = emulator_get_idt, |
52a46617 GN |
4211 | .get_cr = emulator_get_cr, |
4212 | .set_cr = emulator_set_cr, | |
9c537244 | 4213 | .cpl = emulator_get_cpl, |
35aa5375 GN |
4214 | .get_dr = emulator_get_dr, |
4215 | .set_dr = emulator_set_dr, | |
3fb1b5db GN |
4216 | .set_msr = kvm_set_msr, |
4217 | .get_msr = kvm_get_msr, | |
bbd9b64e CO |
4218 | }; |
4219 | ||
5fdbf976 MT |
4220 | static void cache_all_regs(struct kvm_vcpu *vcpu) |
4221 | { | |
4222 | kvm_register_read(vcpu, VCPU_REGS_RAX); | |
4223 | kvm_register_read(vcpu, VCPU_REGS_RSP); | |
4224 | kvm_register_read(vcpu, VCPU_REGS_RIP); | |
4225 | vcpu->arch.regs_dirty = ~0; | |
4226 | } | |
4227 | ||
95cb2295 GN |
4228 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
4229 | { | |
4230 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask); | |
4231 | /* | |
4232 | * an sti; sti; sequence only disable interrupts for the first | |
4233 | * instruction. So, if the last instruction, be it emulated or | |
4234 | * not, left the system with the INT_STI flag enabled, it | |
4235 | * means that the last instruction is an sti. We should not | |
4236 | * leave the flag on in this case. The same goes for mov ss | |
4237 | */ | |
4238 | if (!(int_shadow & mask)) | |
4239 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); | |
4240 | } | |
4241 | ||
54b8486f GN |
4242 | static void inject_emulated_exception(struct kvm_vcpu *vcpu) |
4243 | { | |
4244 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
4245 | if (ctxt->exception == PF_VECTOR) | |
d4f8cf66 | 4246 | kvm_propagate_fault(vcpu); |
54b8486f GN |
4247 | else if (ctxt->error_code_valid) |
4248 | kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code); | |
4249 | else | |
4250 | kvm_queue_exception(vcpu, ctxt->exception); | |
4251 | } | |
4252 | ||
8ec4722d MG |
4253 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
4254 | { | |
4255 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; | |
4256 | int cs_db, cs_l; | |
4257 | ||
4258 | cache_all_regs(vcpu); | |
4259 | ||
4260 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
4261 | ||
4262 | vcpu->arch.emulate_ctxt.vcpu = vcpu; | |
4263 | vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu); | |
4264 | vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu); | |
4265 | vcpu->arch.emulate_ctxt.mode = | |
4266 | (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
4267 | (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM) | |
4268 | ? X86EMUL_MODE_VM86 : cs_l | |
4269 | ? X86EMUL_MODE_PROT64 : cs_db | |
4270 | ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; | |
4271 | memset(c, 0, sizeof(struct decode_cache)); | |
4272 | memcpy(c->regs, vcpu->arch.regs, sizeof c->regs); | |
4273 | } | |
4274 | ||
63995653 MG |
4275 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq) |
4276 | { | |
4277 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; | |
4278 | int ret; | |
4279 | ||
4280 | init_emulate_ctxt(vcpu); | |
4281 | ||
4282 | vcpu->arch.emulate_ctxt.decode.op_bytes = 2; | |
4283 | vcpu->arch.emulate_ctxt.decode.ad_bytes = 2; | |
4284 | vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip; | |
4285 | ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq); | |
4286 | ||
4287 | if (ret != X86EMUL_CONTINUE) | |
4288 | return EMULATE_FAIL; | |
4289 | ||
4290 | vcpu->arch.emulate_ctxt.eip = c->eip; | |
4291 | memcpy(vcpu->arch.regs, c->regs, sizeof c->regs); | |
4292 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip); | |
4293 | kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); | |
4294 | ||
4295 | if (irq == NMI_VECTOR) | |
4296 | vcpu->arch.nmi_pending = false; | |
4297 | else | |
4298 | vcpu->arch.interrupt.pending = false; | |
4299 | ||
4300 | return EMULATE_DONE; | |
4301 | } | |
4302 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
4303 | ||
6d77dbfc GN |
4304 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) |
4305 | { | |
6d77dbfc GN |
4306 | ++vcpu->stat.insn_emulation_fail; |
4307 | trace_kvm_emulate_insn_failed(vcpu); | |
4308 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
4309 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
4310 | vcpu->run->internal.ndata = 0; | |
4311 | kvm_queue_exception(vcpu, UD_VECTOR); | |
4312 | return EMULATE_FAIL; | |
4313 | } | |
4314 | ||
a6f177ef GN |
4315 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva) |
4316 | { | |
4317 | gpa_t gpa; | |
4318 | ||
68be0803 GN |
4319 | if (tdp_enabled) |
4320 | return false; | |
4321 | ||
a6f177ef GN |
4322 | /* |
4323 | * if emulation was due to access to shadowed page table | |
4324 | * and it failed try to unshadow page and re-entetr the | |
4325 | * guest to let CPU execute the instruction. | |
4326 | */ | |
4327 | if (kvm_mmu_unprotect_page_virt(vcpu, gva)) | |
4328 | return true; | |
4329 | ||
4330 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL); | |
4331 | ||
4332 | if (gpa == UNMAPPED_GVA) | |
4333 | return true; /* let cpu generate fault */ | |
4334 | ||
4335 | if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT))) | |
4336 | return true; | |
4337 | ||
4338 | return false; | |
4339 | } | |
4340 | ||
bbd9b64e | 4341 | int emulate_instruction(struct kvm_vcpu *vcpu, |
bbd9b64e CO |
4342 | unsigned long cr2, |
4343 | u16 error_code, | |
571008da | 4344 | int emulation_type) |
bbd9b64e | 4345 | { |
95cb2295 | 4346 | int r; |
4d2179e1 | 4347 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; |
bbd9b64e | 4348 | |
26eef70c | 4349 | kvm_clear_exception_queue(vcpu); |
ad312c7c | 4350 | vcpu->arch.mmio_fault_cr2 = cr2; |
5fdbf976 | 4351 | /* |
56e82318 | 4352 | * TODO: fix emulate.c to use guest_read/write_register |
5fdbf976 MT |
4353 | * instead of direct ->regs accesses, can save hundred cycles |
4354 | * on Intel for instructions that don't read/change RSP, for | |
4355 | * for example. | |
4356 | */ | |
4357 | cache_all_regs(vcpu); | |
bbd9b64e | 4358 | |
571008da | 4359 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 4360 | init_emulate_ctxt(vcpu); |
95cb2295 | 4361 | vcpu->arch.emulate_ctxt.interruptibility = 0; |
54b8486f | 4362 | vcpu->arch.emulate_ctxt.exception = -1; |
4fc40f07 | 4363 | vcpu->arch.emulate_ctxt.perm_ok = false; |
bbd9b64e | 4364 | |
9aabc88f | 4365 | r = x86_decode_insn(&vcpu->arch.emulate_ctxt); |
d47f00a6 JR |
4366 | if (r == X86EMUL_PROPAGATE_FAULT) |
4367 | goto done; | |
bbd9b64e | 4368 | |
e46479f8 | 4369 | trace_kvm_emulate_insn_start(vcpu); |
571008da | 4370 | |
0cb5762e AP |
4371 | /* Only allow emulation of specific instructions on #UD |
4372 | * (namely VMMCALL, sysenter, sysexit, syscall)*/ | |
0cb5762e AP |
4373 | if (emulation_type & EMULTYPE_TRAP_UD) { |
4374 | if (!c->twobyte) | |
4375 | return EMULATE_FAIL; | |
4376 | switch (c->b) { | |
4377 | case 0x01: /* VMMCALL */ | |
4378 | if (c->modrm_mod != 3 || c->modrm_rm != 1) | |
4379 | return EMULATE_FAIL; | |
4380 | break; | |
4381 | case 0x34: /* sysenter */ | |
4382 | case 0x35: /* sysexit */ | |
4383 | if (c->modrm_mod != 0 || c->modrm_rm != 0) | |
4384 | return EMULATE_FAIL; | |
4385 | break; | |
4386 | case 0x05: /* syscall */ | |
4387 | if (c->modrm_mod != 0 || c->modrm_rm != 0) | |
4388 | return EMULATE_FAIL; | |
4389 | break; | |
4390 | default: | |
4391 | return EMULATE_FAIL; | |
4392 | } | |
4393 | ||
4394 | if (!(c->modrm_reg == 0 || c->modrm_reg == 3)) | |
4395 | return EMULATE_FAIL; | |
4396 | } | |
571008da | 4397 | |
f2b5756b | 4398 | ++vcpu->stat.insn_emulation; |
bbd9b64e | 4399 | if (r) { |
a6f177ef | 4400 | if (reexecute_instruction(vcpu, cr2)) |
bbd9b64e | 4401 | return EMULATE_DONE; |
6d77dbfc GN |
4402 | if (emulation_type & EMULTYPE_SKIP) |
4403 | return EMULATE_FAIL; | |
4404 | return handle_emulation_failure(vcpu); | |
bbd9b64e CO |
4405 | } |
4406 | } | |
4407 | ||
ba8afb6b GN |
4408 | if (emulation_type & EMULTYPE_SKIP) { |
4409 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip); | |
4410 | return EMULATE_DONE; | |
4411 | } | |
4412 | ||
4d2179e1 GN |
4413 | /* this is needed for vmware backdor interface to work since it |
4414 | changes registers values during IO operation */ | |
4415 | memcpy(c->regs, vcpu->arch.regs, sizeof c->regs); | |
4416 | ||
5cd21917 | 4417 | restart: |
9aabc88f | 4418 | r = x86_emulate_insn(&vcpu->arch.emulate_ctxt); |
bbd9b64e | 4419 | |
d2ddd1c4 | 4420 | if (r == EMULATION_FAILED) { |
a6f177ef | 4421 | if (reexecute_instruction(vcpu, cr2)) |
c3cd7ffa GN |
4422 | return EMULATE_DONE; |
4423 | ||
6d77dbfc | 4424 | return handle_emulation_failure(vcpu); |
bbd9b64e CO |
4425 | } |
4426 | ||
d47f00a6 | 4427 | done: |
54b8486f GN |
4428 | if (vcpu->arch.emulate_ctxt.exception >= 0) { |
4429 | inject_emulated_exception(vcpu); | |
d2ddd1c4 GN |
4430 | r = EMULATE_DONE; |
4431 | } else if (vcpu->arch.pio.count) { | |
3457e419 GN |
4432 | if (!vcpu->arch.pio.in) |
4433 | vcpu->arch.pio.count = 0; | |
e85d28f8 GN |
4434 | r = EMULATE_DO_MMIO; |
4435 | } else if (vcpu->mmio_needed) { | |
3457e419 GN |
4436 | if (vcpu->mmio_is_write) |
4437 | vcpu->mmio_needed = 0; | |
e85d28f8 | 4438 | r = EMULATE_DO_MMIO; |
d2ddd1c4 | 4439 | } else if (r == EMULATION_RESTART) |
5cd21917 | 4440 | goto restart; |
d2ddd1c4 GN |
4441 | else |
4442 | r = EMULATE_DONE; | |
f850e2e6 | 4443 | |
e85d28f8 GN |
4444 | toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility); |
4445 | kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); | |
3842d135 | 4446 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e85d28f8 GN |
4447 | memcpy(vcpu->arch.regs, c->regs, sizeof c->regs); |
4448 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip); | |
4449 | ||
4450 | return r; | |
de7d789a | 4451 | } |
bbd9b64e | 4452 | EXPORT_SYMBOL_GPL(emulate_instruction); |
de7d789a | 4453 | |
cf8f70bf | 4454 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) |
de7d789a | 4455 | { |
cf8f70bf GN |
4456 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4457 | int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu); | |
4458 | /* do not return to emulator after return from userspace */ | |
7972995b | 4459 | vcpu->arch.pio.count = 0; |
de7d789a CO |
4460 | return ret; |
4461 | } | |
cf8f70bf | 4462 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); |
de7d789a | 4463 | |
8cfdc000 ZA |
4464 | static void tsc_bad(void *info) |
4465 | { | |
4466 | __get_cpu_var(cpu_tsc_khz) = 0; | |
4467 | } | |
4468 | ||
4469 | static void tsc_khz_changed(void *data) | |
c8076604 | 4470 | { |
8cfdc000 ZA |
4471 | struct cpufreq_freqs *freq = data; |
4472 | unsigned long khz = 0; | |
4473 | ||
4474 | if (data) | |
4475 | khz = freq->new; | |
4476 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
4477 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
4478 | if (!khz) | |
4479 | khz = tsc_khz; | |
4480 | __get_cpu_var(cpu_tsc_khz) = khz; | |
c8076604 GH |
4481 | } |
4482 | ||
c8076604 GH |
4483 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
4484 | void *data) | |
4485 | { | |
4486 | struct cpufreq_freqs *freq = data; | |
4487 | struct kvm *kvm; | |
4488 | struct kvm_vcpu *vcpu; | |
4489 | int i, send_ipi = 0; | |
4490 | ||
8cfdc000 ZA |
4491 | /* |
4492 | * We allow guests to temporarily run on slowing clocks, | |
4493 | * provided we notify them after, or to run on accelerating | |
4494 | * clocks, provided we notify them before. Thus time never | |
4495 | * goes backwards. | |
4496 | * | |
4497 | * However, we have a problem. We can't atomically update | |
4498 | * the frequency of a given CPU from this function; it is | |
4499 | * merely a notifier, which can be called from any CPU. | |
4500 | * Changing the TSC frequency at arbitrary points in time | |
4501 | * requires a recomputation of local variables related to | |
4502 | * the TSC for each VCPU. We must flag these local variables | |
4503 | * to be updated and be sure the update takes place with the | |
4504 | * new frequency before any guests proceed. | |
4505 | * | |
4506 | * Unfortunately, the combination of hotplug CPU and frequency | |
4507 | * change creates an intractable locking scenario; the order | |
4508 | * of when these callouts happen is undefined with respect to | |
4509 | * CPU hotplug, and they can race with each other. As such, | |
4510 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
4511 | * undefined; you can actually have a CPU frequency change take | |
4512 | * place in between the computation of X and the setting of the | |
4513 | * variable. To protect against this problem, all updates of | |
4514 | * the per_cpu tsc_khz variable are done in an interrupt | |
4515 | * protected IPI, and all callers wishing to update the value | |
4516 | * must wait for a synchronous IPI to complete (which is trivial | |
4517 | * if the caller is on the CPU already). This establishes the | |
4518 | * necessary total order on variable updates. | |
4519 | * | |
4520 | * Note that because a guest time update may take place | |
4521 | * anytime after the setting of the VCPU's request bit, the | |
4522 | * correct TSC value must be set before the request. However, | |
4523 | * to ensure the update actually makes it to any guest which | |
4524 | * starts running in hardware virtualization between the set | |
4525 | * and the acquisition of the spinlock, we must also ping the | |
4526 | * CPU after setting the request bit. | |
4527 | * | |
4528 | */ | |
4529 | ||
c8076604 GH |
4530 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
4531 | return 0; | |
4532 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
4533 | return 0; | |
8cfdc000 ZA |
4534 | |
4535 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
c8076604 GH |
4536 | |
4537 | spin_lock(&kvm_lock); | |
4538 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
988a2cae | 4539 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
4540 | if (vcpu->cpu != freq->cpu) |
4541 | continue; | |
c285545f | 4542 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c8076604 | 4543 | if (vcpu->cpu != smp_processor_id()) |
8cfdc000 | 4544 | send_ipi = 1; |
c8076604 GH |
4545 | } |
4546 | } | |
4547 | spin_unlock(&kvm_lock); | |
4548 | ||
4549 | if (freq->old < freq->new && send_ipi) { | |
4550 | /* | |
4551 | * We upscale the frequency. Must make the guest | |
4552 | * doesn't see old kvmclock values while running with | |
4553 | * the new frequency, otherwise we risk the guest sees | |
4554 | * time go backwards. | |
4555 | * | |
4556 | * In case we update the frequency for another cpu | |
4557 | * (which might be in guest context) send an interrupt | |
4558 | * to kick the cpu out of guest context. Next time | |
4559 | * guest context is entered kvmclock will be updated, | |
4560 | * so the guest will not see stale values. | |
4561 | */ | |
8cfdc000 | 4562 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); |
c8076604 GH |
4563 | } |
4564 | return 0; | |
4565 | } | |
4566 | ||
4567 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
4568 | .notifier_call = kvmclock_cpufreq_notifier |
4569 | }; | |
4570 | ||
4571 | static int kvmclock_cpu_notifier(struct notifier_block *nfb, | |
4572 | unsigned long action, void *hcpu) | |
4573 | { | |
4574 | unsigned int cpu = (unsigned long)hcpu; | |
4575 | ||
4576 | switch (action) { | |
4577 | case CPU_ONLINE: | |
4578 | case CPU_DOWN_FAILED: | |
4579 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
4580 | break; | |
4581 | case CPU_DOWN_PREPARE: | |
4582 | smp_call_function_single(cpu, tsc_bad, NULL, 1); | |
4583 | break; | |
4584 | } | |
4585 | return NOTIFY_OK; | |
4586 | } | |
4587 | ||
4588 | static struct notifier_block kvmclock_cpu_notifier_block = { | |
4589 | .notifier_call = kvmclock_cpu_notifier, | |
4590 | .priority = -INT_MAX | |
c8076604 GH |
4591 | }; |
4592 | ||
b820cc0c ZA |
4593 | static void kvm_timer_init(void) |
4594 | { | |
4595 | int cpu; | |
4596 | ||
c285545f | 4597 | max_tsc_khz = tsc_khz; |
8cfdc000 | 4598 | register_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
b820cc0c | 4599 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
4600 | #ifdef CONFIG_CPU_FREQ |
4601 | struct cpufreq_policy policy; | |
4602 | memset(&policy, 0, sizeof(policy)); | |
3e26f230 AK |
4603 | cpu = get_cpu(); |
4604 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
4605 | if (policy.cpuinfo.max_freq) |
4606 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 4607 | put_cpu(); |
c285545f | 4608 | #endif |
b820cc0c ZA |
4609 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
4610 | CPUFREQ_TRANSITION_NOTIFIER); | |
4611 | } | |
c285545f | 4612 | pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); |
8cfdc000 ZA |
4613 | for_each_online_cpu(cpu) |
4614 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
b820cc0c ZA |
4615 | } |
4616 | ||
ff9d07a0 ZY |
4617 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
4618 | ||
4619 | static int kvm_is_in_guest(void) | |
4620 | { | |
4621 | return percpu_read(current_vcpu) != NULL; | |
4622 | } | |
4623 | ||
4624 | static int kvm_is_user_mode(void) | |
4625 | { | |
4626 | int user_mode = 3; | |
dcf46b94 | 4627 | |
ff9d07a0 ZY |
4628 | if (percpu_read(current_vcpu)) |
4629 | user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu)); | |
dcf46b94 | 4630 | |
ff9d07a0 ZY |
4631 | return user_mode != 0; |
4632 | } | |
4633 | ||
4634 | static unsigned long kvm_get_guest_ip(void) | |
4635 | { | |
4636 | unsigned long ip = 0; | |
dcf46b94 | 4637 | |
ff9d07a0 ZY |
4638 | if (percpu_read(current_vcpu)) |
4639 | ip = kvm_rip_read(percpu_read(current_vcpu)); | |
dcf46b94 | 4640 | |
ff9d07a0 ZY |
4641 | return ip; |
4642 | } | |
4643 | ||
4644 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
4645 | .is_in_guest = kvm_is_in_guest, | |
4646 | .is_user_mode = kvm_is_user_mode, | |
4647 | .get_guest_ip = kvm_get_guest_ip, | |
4648 | }; | |
4649 | ||
4650 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
4651 | { | |
4652 | percpu_write(current_vcpu, vcpu); | |
4653 | } | |
4654 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
4655 | ||
4656 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
4657 | { | |
4658 | percpu_write(current_vcpu, NULL); | |
4659 | } | |
4660 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
4661 | ||
f8c16bba | 4662 | int kvm_arch_init(void *opaque) |
043405e1 | 4663 | { |
b820cc0c | 4664 | int r; |
f8c16bba ZX |
4665 | struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque; |
4666 | ||
f8c16bba ZX |
4667 | if (kvm_x86_ops) { |
4668 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
4669 | r = -EEXIST; |
4670 | goto out; | |
f8c16bba ZX |
4671 | } |
4672 | ||
4673 | if (!ops->cpu_has_kvm_support()) { | |
4674 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
4675 | r = -EOPNOTSUPP; |
4676 | goto out; | |
f8c16bba ZX |
4677 | } |
4678 | if (ops->disabled_by_bios()) { | |
4679 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
4680 | r = -EOPNOTSUPP; |
4681 | goto out; | |
f8c16bba ZX |
4682 | } |
4683 | ||
97db56ce AK |
4684 | r = kvm_mmu_module_init(); |
4685 | if (r) | |
4686 | goto out; | |
4687 | ||
4688 | kvm_init_msr_list(); | |
4689 | ||
f8c16bba | 4690 | kvm_x86_ops = ops; |
56c6d28a | 4691 | kvm_mmu_set_nonpresent_ptes(0ull, 0ull); |
7b52345e | 4692 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
4b12f0de | 4693 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 4694 | |
b820cc0c | 4695 | kvm_timer_init(); |
c8076604 | 4696 | |
ff9d07a0 ZY |
4697 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
4698 | ||
2acf923e DC |
4699 | if (cpu_has_xsave) |
4700 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); | |
4701 | ||
f8c16bba | 4702 | return 0; |
56c6d28a ZX |
4703 | |
4704 | out: | |
56c6d28a | 4705 | return r; |
043405e1 | 4706 | } |
8776e519 | 4707 | |
f8c16bba ZX |
4708 | void kvm_arch_exit(void) |
4709 | { | |
ff9d07a0 ZY |
4710 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
4711 | ||
888d256e JK |
4712 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
4713 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
4714 | CPUFREQ_TRANSITION_NOTIFIER); | |
8cfdc000 | 4715 | unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
f8c16bba | 4716 | kvm_x86_ops = NULL; |
56c6d28a ZX |
4717 | kvm_mmu_module_exit(); |
4718 | } | |
f8c16bba | 4719 | |
8776e519 HB |
4720 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) |
4721 | { | |
4722 | ++vcpu->stat.halt_exits; | |
4723 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 4724 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
4725 | return 1; |
4726 | } else { | |
4727 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
4728 | return 0; | |
4729 | } | |
4730 | } | |
4731 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
4732 | ||
2f333bcb MT |
4733 | static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0, |
4734 | unsigned long a1) | |
4735 | { | |
4736 | if (is_long_mode(vcpu)) | |
4737 | return a0; | |
4738 | else | |
4739 | return a0 | ((gpa_t)a1 << 32); | |
4740 | } | |
4741 | ||
55cd8e5a GN |
4742 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
4743 | { | |
4744 | u64 param, ingpa, outgpa, ret; | |
4745 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
4746 | bool fast, longmode; | |
4747 | int cs_db, cs_l; | |
4748 | ||
4749 | /* | |
4750 | * hypercall generates UD from non zero cpl and real mode | |
4751 | * per HYPER-V spec | |
4752 | */ | |
3eeb3288 | 4753 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { |
55cd8e5a GN |
4754 | kvm_queue_exception(vcpu, UD_VECTOR); |
4755 | return 0; | |
4756 | } | |
4757 | ||
4758 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
4759 | longmode = is_long_mode(vcpu) && cs_l == 1; | |
4760 | ||
4761 | if (!longmode) { | |
ccd46936 GN |
4762 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | |
4763 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
4764 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
4765 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
4766 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
4767 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
55cd8e5a GN |
4768 | } |
4769 | #ifdef CONFIG_X86_64 | |
4770 | else { | |
4771 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4772 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4773 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
4774 | } | |
4775 | #endif | |
4776 | ||
4777 | code = param & 0xffff; | |
4778 | fast = (param >> 16) & 0x1; | |
4779 | rep_cnt = (param >> 32) & 0xfff; | |
4780 | rep_idx = (param >> 48) & 0xfff; | |
4781 | ||
4782 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
4783 | ||
c25bc163 GN |
4784 | switch (code) { |
4785 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
4786 | kvm_vcpu_on_spin(vcpu); | |
4787 | break; | |
4788 | default: | |
4789 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
4790 | break; | |
4791 | } | |
55cd8e5a GN |
4792 | |
4793 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
4794 | if (longmode) { | |
4795 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
4796 | } else { | |
4797 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
4798 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
4799 | } | |
4800 | ||
4801 | return 1; | |
4802 | } | |
4803 | ||
8776e519 HB |
4804 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
4805 | { | |
4806 | unsigned long nr, a0, a1, a2, a3, ret; | |
2f333bcb | 4807 | int r = 1; |
8776e519 | 4808 | |
55cd8e5a GN |
4809 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
4810 | return kvm_hv_hypercall(vcpu); | |
4811 | ||
5fdbf976 MT |
4812 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4813 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
4814 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4815 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4816 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 4817 | |
229456fc | 4818 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 4819 | |
8776e519 HB |
4820 | if (!is_long_mode(vcpu)) { |
4821 | nr &= 0xFFFFFFFF; | |
4822 | a0 &= 0xFFFFFFFF; | |
4823 | a1 &= 0xFFFFFFFF; | |
4824 | a2 &= 0xFFFFFFFF; | |
4825 | a3 &= 0xFFFFFFFF; | |
4826 | } | |
4827 | ||
07708c4a JK |
4828 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
4829 | ret = -KVM_EPERM; | |
4830 | goto out; | |
4831 | } | |
4832 | ||
8776e519 | 4833 | switch (nr) { |
b93463aa AK |
4834 | case KVM_HC_VAPIC_POLL_IRQ: |
4835 | ret = 0; | |
4836 | break; | |
2f333bcb MT |
4837 | case KVM_HC_MMU_OP: |
4838 | r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret); | |
4839 | break; | |
8776e519 HB |
4840 | default: |
4841 | ret = -KVM_ENOSYS; | |
4842 | break; | |
4843 | } | |
07708c4a | 4844 | out: |
5fdbf976 | 4845 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 4846 | ++vcpu->stat.hypercalls; |
2f333bcb | 4847 | return r; |
8776e519 HB |
4848 | } |
4849 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
4850 | ||
4851 | int kvm_fix_hypercall(struct kvm_vcpu *vcpu) | |
4852 | { | |
4853 | char instruction[3]; | |
5fdbf976 | 4854 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 4855 | |
8776e519 HB |
4856 | /* |
4857 | * Blow out the MMU to ensure that no other VCPU has an active mapping | |
4858 | * to ensure that the updated hypercall appears atomically across all | |
4859 | * VCPUs. | |
4860 | */ | |
4861 | kvm_mmu_zap_all(vcpu->kvm); | |
4862 | ||
8776e519 | 4863 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 4864 | |
8fe681e9 | 4865 | return emulator_write_emulated(rip, instruction, 3, NULL, vcpu); |
8776e519 HB |
4866 | } |
4867 | ||
8776e519 HB |
4868 | void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) |
4869 | { | |
89a27f4d | 4870 | struct desc_ptr dt = { limit, base }; |
8776e519 HB |
4871 | |
4872 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
4873 | } | |
4874 | ||
4875 | void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
4876 | { | |
89a27f4d | 4877 | struct desc_ptr dt = { limit, base }; |
8776e519 HB |
4878 | |
4879 | kvm_x86_ops->set_idt(vcpu, &dt); | |
4880 | } | |
4881 | ||
07716717 DK |
4882 | static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i) |
4883 | { | |
ad312c7c ZX |
4884 | struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i]; |
4885 | int j, nent = vcpu->arch.cpuid_nent; | |
07716717 DK |
4886 | |
4887 | e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT; | |
4888 | /* when no next entry is found, the current entry[i] is reselected */ | |
0fdf8e59 | 4889 | for (j = i + 1; ; j = (j + 1) % nent) { |
ad312c7c | 4890 | struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j]; |
07716717 DK |
4891 | if (ej->function == e->function) { |
4892 | ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; | |
4893 | return j; | |
4894 | } | |
4895 | } | |
4896 | return 0; /* silence gcc, even though control never reaches here */ | |
4897 | } | |
4898 | ||
4899 | /* find an entry with matching function, matching index (if needed), and that | |
4900 | * should be read next (if it's stateful) */ | |
4901 | static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e, | |
4902 | u32 function, u32 index) | |
4903 | { | |
4904 | if (e->function != function) | |
4905 | return 0; | |
4906 | if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index) | |
4907 | return 0; | |
4908 | if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) && | |
19355475 | 4909 | !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT)) |
07716717 DK |
4910 | return 0; |
4911 | return 1; | |
4912 | } | |
4913 | ||
d8017474 AG |
4914 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, |
4915 | u32 function, u32 index) | |
8776e519 HB |
4916 | { |
4917 | int i; | |
d8017474 | 4918 | struct kvm_cpuid_entry2 *best = NULL; |
8776e519 | 4919 | |
ad312c7c | 4920 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
d8017474 AG |
4921 | struct kvm_cpuid_entry2 *e; |
4922 | ||
ad312c7c | 4923 | e = &vcpu->arch.cpuid_entries[i]; |
07716717 DK |
4924 | if (is_matching_cpuid_entry(e, function, index)) { |
4925 | if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) | |
4926 | move_to_next_stateful_cpuid_entry(vcpu, i); | |
8776e519 HB |
4927 | best = e; |
4928 | break; | |
4929 | } | |
4930 | /* | |
4931 | * Both basic or both extended? | |
4932 | */ | |
4933 | if (((e->function ^ function) & 0x80000000) == 0) | |
4934 | if (!best || e->function > best->function) | |
4935 | best = e; | |
4936 | } | |
d8017474 AG |
4937 | return best; |
4938 | } | |
0e851880 | 4939 | EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); |
d8017474 | 4940 | |
82725b20 DE |
4941 | int cpuid_maxphyaddr(struct kvm_vcpu *vcpu) |
4942 | { | |
4943 | struct kvm_cpuid_entry2 *best; | |
4944 | ||
f7a71197 AK |
4945 | best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); |
4946 | if (!best || best->eax < 0x80000008) | |
4947 | goto not_found; | |
82725b20 DE |
4948 | best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); |
4949 | if (best) | |
4950 | return best->eax & 0xff; | |
f7a71197 | 4951 | not_found: |
82725b20 DE |
4952 | return 36; |
4953 | } | |
4954 | ||
d8017474 AG |
4955 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu) |
4956 | { | |
4957 | u32 function, index; | |
4958 | struct kvm_cpuid_entry2 *best; | |
4959 | ||
4960 | function = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
4961 | index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4962 | kvm_register_write(vcpu, VCPU_REGS_RAX, 0); | |
4963 | kvm_register_write(vcpu, VCPU_REGS_RBX, 0); | |
4964 | kvm_register_write(vcpu, VCPU_REGS_RCX, 0); | |
4965 | kvm_register_write(vcpu, VCPU_REGS_RDX, 0); | |
4966 | best = kvm_find_cpuid_entry(vcpu, function, index); | |
8776e519 | 4967 | if (best) { |
5fdbf976 MT |
4968 | kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax); |
4969 | kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx); | |
4970 | kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx); | |
4971 | kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx); | |
8776e519 | 4972 | } |
8776e519 | 4973 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
229456fc MT |
4974 | trace_kvm_cpuid(function, |
4975 | kvm_register_read(vcpu, VCPU_REGS_RAX), | |
4976 | kvm_register_read(vcpu, VCPU_REGS_RBX), | |
4977 | kvm_register_read(vcpu, VCPU_REGS_RCX), | |
4978 | kvm_register_read(vcpu, VCPU_REGS_RDX)); | |
8776e519 HB |
4979 | } |
4980 | EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); | |
d0752060 | 4981 | |
b6c7a5dc HB |
4982 | /* |
4983 | * Check if userspace requested an interrupt window, and that the | |
4984 | * interrupt window is open. | |
4985 | * | |
4986 | * No need to exit to userspace if we already have an interrupt queued. | |
4987 | */ | |
851ba692 | 4988 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 4989 | { |
8061823a | 4990 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 4991 | vcpu->run->request_interrupt_window && |
5df56646 | 4992 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
4993 | } |
4994 | ||
851ba692 | 4995 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 4996 | { |
851ba692 AK |
4997 | struct kvm_run *kvm_run = vcpu->run; |
4998 | ||
91586a3b | 4999 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
2d3ad1f4 | 5000 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 5001 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 5002 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 5003 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 5004 | else |
b6c7a5dc | 5005 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
5006 | kvm_arch_interrupt_allowed(vcpu) && |
5007 | !kvm_cpu_has_interrupt(vcpu) && | |
5008 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
5009 | } |
5010 | ||
b93463aa AK |
5011 | static void vapic_enter(struct kvm_vcpu *vcpu) |
5012 | { | |
5013 | struct kvm_lapic *apic = vcpu->arch.apic; | |
5014 | struct page *page; | |
5015 | ||
5016 | if (!apic || !apic->vapic_addr) | |
5017 | return; | |
5018 | ||
5019 | page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
72dc67a6 IE |
5020 | |
5021 | vcpu->arch.apic->vapic_page = page; | |
b93463aa AK |
5022 | } |
5023 | ||
5024 | static void vapic_exit(struct kvm_vcpu *vcpu) | |
5025 | { | |
5026 | struct kvm_lapic *apic = vcpu->arch.apic; | |
f656ce01 | 5027 | int idx; |
b93463aa AK |
5028 | |
5029 | if (!apic || !apic->vapic_addr) | |
5030 | return; | |
5031 | ||
f656ce01 | 5032 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
b93463aa AK |
5033 | kvm_release_page_dirty(apic->vapic_page); |
5034 | mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
f656ce01 | 5035 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
5036 | } |
5037 | ||
95ba8273 GN |
5038 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
5039 | { | |
5040 | int max_irr, tpr; | |
5041 | ||
5042 | if (!kvm_x86_ops->update_cr8_intercept) | |
5043 | return; | |
5044 | ||
88c808fd AK |
5045 | if (!vcpu->arch.apic) |
5046 | return; | |
5047 | ||
8db3baa2 GN |
5048 | if (!vcpu->arch.apic->vapic_addr) |
5049 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
5050 | else | |
5051 | max_irr = -1; | |
95ba8273 GN |
5052 | |
5053 | if (max_irr != -1) | |
5054 | max_irr >>= 4; | |
5055 | ||
5056 | tpr = kvm_lapic_get_cr8(vcpu); | |
5057 | ||
5058 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
5059 | } | |
5060 | ||
851ba692 | 5061 | static void inject_pending_event(struct kvm_vcpu *vcpu) |
95ba8273 GN |
5062 | { |
5063 | /* try to reinject previous events if any */ | |
b59bb7bd | 5064 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
5065 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
5066 | vcpu->arch.exception.has_error_code, | |
5067 | vcpu->arch.exception.error_code); | |
b59bb7bd GN |
5068 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
5069 | vcpu->arch.exception.has_error_code, | |
ce7ddec4 JR |
5070 | vcpu->arch.exception.error_code, |
5071 | vcpu->arch.exception.reinject); | |
b59bb7bd GN |
5072 | return; |
5073 | } | |
5074 | ||
95ba8273 GN |
5075 | if (vcpu->arch.nmi_injected) { |
5076 | kvm_x86_ops->set_nmi(vcpu); | |
5077 | return; | |
5078 | } | |
5079 | ||
5080 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 5081 | kvm_x86_ops->set_irq(vcpu); |
95ba8273 GN |
5082 | return; |
5083 | } | |
5084 | ||
5085 | /* try to inject new event if pending */ | |
5086 | if (vcpu->arch.nmi_pending) { | |
5087 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
5088 | vcpu->arch.nmi_pending = false; | |
5089 | vcpu->arch.nmi_injected = true; | |
5090 | kvm_x86_ops->set_nmi(vcpu); | |
5091 | } | |
5092 | } else if (kvm_cpu_has_interrupt(vcpu)) { | |
5093 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { | |
66fd3f7f GN |
5094 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
5095 | false); | |
5096 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
5097 | } |
5098 | } | |
5099 | } | |
5100 | ||
2acf923e DC |
5101 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
5102 | { | |
5103 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
5104 | !vcpu->guest_xcr0_loaded) { | |
5105 | /* kvm_set_xcr() also depends on this */ | |
5106 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
5107 | vcpu->guest_xcr0_loaded = 1; | |
5108 | } | |
5109 | } | |
5110 | ||
5111 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
5112 | { | |
5113 | if (vcpu->guest_xcr0_loaded) { | |
5114 | if (vcpu->arch.xcr0 != host_xcr0) | |
5115 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
5116 | vcpu->guest_xcr0_loaded = 0; | |
5117 | } | |
5118 | } | |
5119 | ||
851ba692 | 5120 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
5121 | { |
5122 | int r; | |
6a8b1d13 | 5123 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 5124 | vcpu->run->request_interrupt_window; |
b6c7a5dc | 5125 | |
3e007509 | 5126 | if (vcpu->requests) { |
a8eeb04a | 5127 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 5128 | kvm_mmu_unload(vcpu); |
a8eeb04a | 5129 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 5130 | __kvm_migrate_timers(vcpu); |
34c238a1 ZA |
5131 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
5132 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
5133 | if (unlikely(r)) |
5134 | goto out; | |
5135 | } | |
a8eeb04a | 5136 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 5137 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 5138 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
d4acf7e7 | 5139 | kvm_x86_ops->tlb_flush(vcpu); |
a8eeb04a | 5140 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 5141 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
5142 | r = 0; |
5143 | goto out; | |
5144 | } | |
a8eeb04a | 5145 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 5146 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
5147 | r = 0; |
5148 | goto out; | |
5149 | } | |
a8eeb04a | 5150 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { |
02daab21 AK |
5151 | vcpu->fpu_active = 0; |
5152 | kvm_x86_ops->fpu_deactivate(vcpu); | |
5153 | } | |
af585b92 GN |
5154 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
5155 | /* Page is swapped out. Do synthetic halt */ | |
5156 | vcpu->arch.apf.halted = true; | |
5157 | r = 1; | |
5158 | goto out; | |
5159 | } | |
2f52d58c | 5160 | } |
b93463aa | 5161 | |
3e007509 AK |
5162 | r = kvm_mmu_reload(vcpu); |
5163 | if (unlikely(r)) | |
5164 | goto out; | |
5165 | ||
b463a6f7 AK |
5166 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
5167 | inject_pending_event(vcpu); | |
5168 | ||
5169 | /* enable NMI/IRQ window open exits if needed */ | |
5170 | if (vcpu->arch.nmi_pending) | |
5171 | kvm_x86_ops->enable_nmi_window(vcpu); | |
5172 | else if (kvm_cpu_has_interrupt(vcpu) || req_int_win) | |
5173 | kvm_x86_ops->enable_irq_window(vcpu); | |
5174 | ||
5175 | if (kvm_lapic_enabled(vcpu)) { | |
5176 | update_cr8_intercept(vcpu); | |
5177 | kvm_lapic_sync_to_vapic(vcpu); | |
5178 | } | |
5179 | } | |
5180 | ||
b6c7a5dc HB |
5181 | preempt_disable(); |
5182 | ||
5183 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
5184 | if (vcpu->fpu_active) |
5185 | kvm_load_guest_fpu(vcpu); | |
2acf923e | 5186 | kvm_load_guest_xcr0(vcpu); |
b6c7a5dc | 5187 | |
d94e1dc9 AK |
5188 | atomic_set(&vcpu->guest_mode, 1); |
5189 | smp_wmb(); | |
b6c7a5dc | 5190 | |
d94e1dc9 | 5191 | local_irq_disable(); |
32f88400 | 5192 | |
d94e1dc9 AK |
5193 | if (!atomic_read(&vcpu->guest_mode) || vcpu->requests |
5194 | || need_resched() || signal_pending(current)) { | |
5195 | atomic_set(&vcpu->guest_mode, 0); | |
5196 | smp_wmb(); | |
6c142801 AK |
5197 | local_irq_enable(); |
5198 | preempt_enable(); | |
b463a6f7 | 5199 | kvm_x86_ops->cancel_injection(vcpu); |
6c142801 AK |
5200 | r = 1; |
5201 | goto out; | |
5202 | } | |
5203 | ||
f656ce01 | 5204 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
3200f405 | 5205 | |
b6c7a5dc HB |
5206 | kvm_guest_enter(); |
5207 | ||
42dbaa5a | 5208 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
5209 | set_debugreg(0, 7); |
5210 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
5211 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
5212 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
5213 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
5214 | } | |
b6c7a5dc | 5215 | |
229456fc | 5216 | trace_kvm_entry(vcpu->vcpu_id); |
851ba692 | 5217 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 5218 | |
24f1e32c FW |
5219 | /* |
5220 | * If the guest has used debug registers, at least dr7 | |
5221 | * will be disabled while returning to the host. | |
5222 | * If we don't have active breakpoints in the host, we don't | |
5223 | * care about the messed up debug address registers. But if | |
5224 | * we have some of them active, restore the old state. | |
5225 | */ | |
59d8eb53 | 5226 | if (hw_breakpoint_active()) |
24f1e32c | 5227 | hw_breakpoint_restore(); |
42dbaa5a | 5228 | |
1d5f066e ZA |
5229 | kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc); |
5230 | ||
d94e1dc9 AK |
5231 | atomic_set(&vcpu->guest_mode, 0); |
5232 | smp_wmb(); | |
b6c7a5dc HB |
5233 | local_irq_enable(); |
5234 | ||
5235 | ++vcpu->stat.exits; | |
5236 | ||
5237 | /* | |
5238 | * We must have an instruction between local_irq_enable() and | |
5239 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
5240 | * the interrupt shadow. The stat.exits increment will do nicely. | |
5241 | * But we need to prevent reordering, hence this barrier(): | |
5242 | */ | |
5243 | barrier(); | |
5244 | ||
5245 | kvm_guest_exit(); | |
5246 | ||
5247 | preempt_enable(); | |
5248 | ||
f656ce01 | 5249 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 5250 | |
b6c7a5dc HB |
5251 | /* |
5252 | * Profile KVM exit RIPs: | |
5253 | */ | |
5254 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
5255 | unsigned long rip = kvm_rip_read(vcpu); |
5256 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
5257 | } |
5258 | ||
298101da | 5259 | |
b93463aa AK |
5260 | kvm_lapic_sync_from_vapic(vcpu); |
5261 | ||
851ba692 | 5262 | r = kvm_x86_ops->handle_exit(vcpu); |
d7690175 MT |
5263 | out: |
5264 | return r; | |
5265 | } | |
b6c7a5dc | 5266 | |
09cec754 | 5267 | |
851ba692 | 5268 | static int __vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
5269 | { |
5270 | int r; | |
f656ce01 | 5271 | struct kvm *kvm = vcpu->kvm; |
d7690175 MT |
5272 | |
5273 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) { | |
1b10bf31 JK |
5274 | pr_debug("vcpu %d received sipi with vector # %x\n", |
5275 | vcpu->vcpu_id, vcpu->arch.sipi_vector); | |
d7690175 | 5276 | kvm_lapic_reset(vcpu); |
5f179287 | 5277 | r = kvm_arch_vcpu_reset(vcpu); |
d7690175 MT |
5278 | if (r) |
5279 | return r; | |
5280 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
b6c7a5dc HB |
5281 | } |
5282 | ||
f656ce01 | 5283 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 MT |
5284 | vapic_enter(vcpu); |
5285 | ||
5286 | r = 1; | |
5287 | while (r > 0) { | |
af585b92 GN |
5288 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
5289 | !vcpu->arch.apf.halted) | |
851ba692 | 5290 | r = vcpu_enter_guest(vcpu); |
d7690175 | 5291 | else { |
f656ce01 | 5292 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
d7690175 | 5293 | kvm_vcpu_block(vcpu); |
f656ce01 | 5294 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
a8eeb04a | 5295 | if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
09cec754 GN |
5296 | { |
5297 | switch(vcpu->arch.mp_state) { | |
5298 | case KVM_MP_STATE_HALTED: | |
d7690175 | 5299 | vcpu->arch.mp_state = |
09cec754 GN |
5300 | KVM_MP_STATE_RUNNABLE; |
5301 | case KVM_MP_STATE_RUNNABLE: | |
af585b92 | 5302 | vcpu->arch.apf.halted = false; |
09cec754 GN |
5303 | break; |
5304 | case KVM_MP_STATE_SIPI_RECEIVED: | |
5305 | default: | |
5306 | r = -EINTR; | |
5307 | break; | |
5308 | } | |
5309 | } | |
d7690175 MT |
5310 | } |
5311 | ||
09cec754 GN |
5312 | if (r <= 0) |
5313 | break; | |
5314 | ||
5315 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
5316 | if (kvm_cpu_has_pending_timer(vcpu)) | |
5317 | kvm_inject_pending_timer_irqs(vcpu); | |
5318 | ||
851ba692 | 5319 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 5320 | r = -EINTR; |
851ba692 | 5321 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
5322 | ++vcpu->stat.request_irq_exits; |
5323 | } | |
af585b92 GN |
5324 | |
5325 | kvm_check_async_pf_completion(vcpu); | |
5326 | ||
09cec754 GN |
5327 | if (signal_pending(current)) { |
5328 | r = -EINTR; | |
851ba692 | 5329 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
5330 | ++vcpu->stat.signal_exits; |
5331 | } | |
5332 | if (need_resched()) { | |
f656ce01 | 5333 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
09cec754 | 5334 | kvm_resched(vcpu); |
f656ce01 | 5335 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 5336 | } |
b6c7a5dc HB |
5337 | } |
5338 | ||
f656ce01 | 5339 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc | 5340 | |
b93463aa AK |
5341 | vapic_exit(vcpu); |
5342 | ||
b6c7a5dc HB |
5343 | return r; |
5344 | } | |
5345 | ||
5346 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
5347 | { | |
5348 | int r; | |
5349 | sigset_t sigsaved; | |
5350 | ||
ac9f6dc0 AK |
5351 | if (vcpu->sigset_active) |
5352 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
5353 | ||
a4535290 | 5354 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 5355 | kvm_vcpu_block(vcpu); |
d7690175 | 5356 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
5357 | r = -EAGAIN; |
5358 | goto out; | |
b6c7a5dc HB |
5359 | } |
5360 | ||
b6c7a5dc HB |
5361 | /* re-sync apic's tpr */ |
5362 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2d3ad1f4 | 5363 | kvm_set_cr8(vcpu, kvm_run->cr8); |
b6c7a5dc | 5364 | |
d2ddd1c4 | 5365 | if (vcpu->arch.pio.count || vcpu->mmio_needed) { |
92bf9748 GN |
5366 | if (vcpu->mmio_needed) { |
5367 | memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8); | |
5368 | vcpu->mmio_read_completed = 1; | |
5369 | vcpu->mmio_needed = 0; | |
b6c7a5dc | 5370 | } |
f656ce01 | 5371 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
5cd21917 | 5372 | r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE); |
f656ce01 | 5373 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
6d77dbfc | 5374 | if (r != EMULATE_DONE) { |
b6c7a5dc HB |
5375 | r = 0; |
5376 | goto out; | |
5377 | } | |
5378 | } | |
5fdbf976 MT |
5379 | if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) |
5380 | kvm_register_write(vcpu, VCPU_REGS_RAX, | |
5381 | kvm_run->hypercall.ret); | |
b6c7a5dc | 5382 | |
851ba692 | 5383 | r = __vcpu_run(vcpu); |
b6c7a5dc HB |
5384 | |
5385 | out: | |
f1d86e46 | 5386 | post_kvm_run_save(vcpu); |
b6c7a5dc HB |
5387 | if (vcpu->sigset_active) |
5388 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
5389 | ||
b6c7a5dc HB |
5390 | return r; |
5391 | } | |
5392 | ||
5393 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
5394 | { | |
5fdbf976 MT |
5395 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
5396 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5397 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5398 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5399 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
5400 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
5401 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
5402 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 5403 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
5404 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
5405 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
5406 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
5407 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
5408 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
5409 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
5410 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
5411 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
5412 | #endif |
5413 | ||
5fdbf976 | 5414 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 5415 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc | 5416 | |
b6c7a5dc HB |
5417 | return 0; |
5418 | } | |
5419 | ||
5420 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
5421 | { | |
5fdbf976 MT |
5422 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
5423 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
5424 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
5425 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
5426 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
5427 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
5428 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
5429 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 5430 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
5431 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
5432 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
5433 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
5434 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
5435 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
5436 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
5437 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
5438 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
5439 | #endif |
5440 | ||
5fdbf976 | 5441 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 5442 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 5443 | |
b4f14abd JK |
5444 | vcpu->arch.exception.pending = false; |
5445 | ||
3842d135 AK |
5446 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5447 | ||
b6c7a5dc HB |
5448 | return 0; |
5449 | } | |
5450 | ||
b6c7a5dc HB |
5451 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
5452 | { | |
5453 | struct kvm_segment cs; | |
5454 | ||
3e6e0aab | 5455 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
5456 | *db = cs.db; |
5457 | *l = cs.l; | |
5458 | } | |
5459 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
5460 | ||
5461 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
5462 | struct kvm_sregs *sregs) | |
5463 | { | |
89a27f4d | 5464 | struct desc_ptr dt; |
b6c7a5dc | 5465 | |
3e6e0aab GT |
5466 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
5467 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
5468 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
5469 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
5470 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
5471 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 5472 | |
3e6e0aab GT |
5473 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5474 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
5475 | |
5476 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
5477 | sregs->idt.limit = dt.size; |
5478 | sregs->idt.base = dt.address; | |
b6c7a5dc | 5479 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
5480 | sregs->gdt.limit = dt.size; |
5481 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 5482 | |
4d4ec087 | 5483 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c ZX |
5484 | sregs->cr2 = vcpu->arch.cr2; |
5485 | sregs->cr3 = vcpu->arch.cr3; | |
fc78f519 | 5486 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 5487 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 5488 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
5489 | sregs->apic_base = kvm_get_apic_base(vcpu); |
5490 | ||
923c61bb | 5491 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 5492 | |
36752c9b | 5493 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
5494 | set_bit(vcpu->arch.interrupt.nr, |
5495 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 5496 | |
b6c7a5dc HB |
5497 | return 0; |
5498 | } | |
5499 | ||
62d9f0db MT |
5500 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
5501 | struct kvm_mp_state *mp_state) | |
5502 | { | |
62d9f0db | 5503 | mp_state->mp_state = vcpu->arch.mp_state; |
62d9f0db MT |
5504 | return 0; |
5505 | } | |
5506 | ||
5507 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
5508 | struct kvm_mp_state *mp_state) | |
5509 | { | |
62d9f0db | 5510 | vcpu->arch.mp_state = mp_state->mp_state; |
3842d135 | 5511 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
62d9f0db MT |
5512 | return 0; |
5513 | } | |
5514 | ||
e269fb21 JK |
5515 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason, |
5516 | bool has_error_code, u32 error_code) | |
b6c7a5dc | 5517 | { |
4d2179e1 | 5518 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; |
8ec4722d | 5519 | int ret; |
e01c2426 | 5520 | |
8ec4722d | 5521 | init_emulate_ctxt(vcpu); |
c697518a | 5522 | |
9aabc88f | 5523 | ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, |
e269fb21 JK |
5524 | tss_selector, reason, has_error_code, |
5525 | error_code); | |
c697518a | 5526 | |
c697518a | 5527 | if (ret) |
19d04437 | 5528 | return EMULATE_FAIL; |
37817f29 | 5529 | |
4d2179e1 | 5530 | memcpy(vcpu->arch.regs, c->regs, sizeof c->regs); |
95c55886 | 5531 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip); |
19d04437 | 5532 | kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); |
3842d135 | 5533 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 5534 | return EMULATE_DONE; |
37817f29 IE |
5535 | } |
5536 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
5537 | ||
b6c7a5dc HB |
5538 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
5539 | struct kvm_sregs *sregs) | |
5540 | { | |
5541 | int mmu_reset_needed = 0; | |
923c61bb | 5542 | int pending_vec, max_bits; |
89a27f4d | 5543 | struct desc_ptr dt; |
b6c7a5dc | 5544 | |
89a27f4d GN |
5545 | dt.size = sregs->idt.limit; |
5546 | dt.address = sregs->idt.base; | |
b6c7a5dc | 5547 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
5548 | dt.size = sregs->gdt.limit; |
5549 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
5550 | kvm_x86_ops->set_gdt(vcpu, &dt); |
5551 | ||
ad312c7c ZX |
5552 | vcpu->arch.cr2 = sregs->cr2; |
5553 | mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3; | |
dc7e795e | 5554 | vcpu->arch.cr3 = sregs->cr3; |
b6c7a5dc | 5555 | |
2d3ad1f4 | 5556 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 5557 | |
f6801dff | 5558 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 5559 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc HB |
5560 | kvm_set_apic_base(vcpu, sregs->apic_base); |
5561 | ||
4d4ec087 | 5562 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 5563 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 5564 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 5565 | |
fc78f519 | 5566 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 5567 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
3ea3aa8c SY |
5568 | if (sregs->cr4 & X86_CR4_OSXSAVE) |
5569 | update_cpuid(vcpu); | |
7c93be44 | 5570 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
ff03a073 | 5571 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3); |
7c93be44 MT |
5572 | mmu_reset_needed = 1; |
5573 | } | |
b6c7a5dc HB |
5574 | |
5575 | if (mmu_reset_needed) | |
5576 | kvm_mmu_reset_context(vcpu); | |
5577 | ||
923c61bb GN |
5578 | max_bits = (sizeof sregs->interrupt_bitmap) << 3; |
5579 | pending_vec = find_first_bit( | |
5580 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
5581 | if (pending_vec < max_bits) { | |
66fd3f7f | 5582 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb GN |
5583 | pr_debug("Set back pending irq %d\n", pending_vec); |
5584 | if (irqchip_in_kernel(vcpu->kvm)) | |
5585 | kvm_pic_clear_isr_ack(vcpu->kvm); | |
b6c7a5dc HB |
5586 | } |
5587 | ||
3e6e0aab GT |
5588 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
5589 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
5590 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
5591 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
5592 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
5593 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 5594 | |
3e6e0aab GT |
5595 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5596 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 5597 | |
5f0269f5 ME |
5598 | update_cr8_intercept(vcpu); |
5599 | ||
9c3e4aab | 5600 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 5601 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 5602 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 5603 | !is_protmode(vcpu)) |
9c3e4aab MT |
5604 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
5605 | ||
3842d135 AK |
5606 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5607 | ||
b6c7a5dc HB |
5608 | return 0; |
5609 | } | |
5610 | ||
d0bfb940 JK |
5611 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
5612 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 5613 | { |
355be0b9 | 5614 | unsigned long rflags; |
ae675ef0 | 5615 | int i, r; |
b6c7a5dc | 5616 | |
4f926bf2 JK |
5617 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
5618 | r = -EBUSY; | |
5619 | if (vcpu->arch.exception.pending) | |
2122ff5e | 5620 | goto out; |
4f926bf2 JK |
5621 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
5622 | kvm_queue_exception(vcpu, DB_VECTOR); | |
5623 | else | |
5624 | kvm_queue_exception(vcpu, BP_VECTOR); | |
5625 | } | |
5626 | ||
91586a3b JK |
5627 | /* |
5628 | * Read rflags as long as potentially injected trace flags are still | |
5629 | * filtered out. | |
5630 | */ | |
5631 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
5632 | |
5633 | vcpu->guest_debug = dbg->control; | |
5634 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
5635 | vcpu->guest_debug = 0; | |
5636 | ||
5637 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
5638 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
5639 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
5640 | vcpu->arch.switch_db_regs = | |
5641 | (dbg->arch.debugreg[7] & DR7_BP_EN_MASK); | |
5642 | } else { | |
5643 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
5644 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
5645 | vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK); | |
5646 | } | |
5647 | ||
f92653ee JK |
5648 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
5649 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
5650 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 5651 | |
91586a3b JK |
5652 | /* |
5653 | * Trigger an rflags update that will inject or remove the trace | |
5654 | * flags. | |
5655 | */ | |
5656 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 5657 | |
355be0b9 | 5658 | kvm_x86_ops->set_guest_debug(vcpu, dbg); |
b6c7a5dc | 5659 | |
4f926bf2 | 5660 | r = 0; |
d0bfb940 | 5661 | |
2122ff5e | 5662 | out: |
b6c7a5dc HB |
5663 | |
5664 | return r; | |
5665 | } | |
5666 | ||
8b006791 ZX |
5667 | /* |
5668 | * Translate a guest virtual address to a guest physical address. | |
5669 | */ | |
5670 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
5671 | struct kvm_translation *tr) | |
5672 | { | |
5673 | unsigned long vaddr = tr->linear_address; | |
5674 | gpa_t gpa; | |
f656ce01 | 5675 | int idx; |
8b006791 | 5676 | |
f656ce01 | 5677 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 5678 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 5679 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
5680 | tr->physical_address = gpa; |
5681 | tr->valid = gpa != UNMAPPED_GVA; | |
5682 | tr->writeable = 1; | |
5683 | tr->usermode = 0; | |
8b006791 ZX |
5684 | |
5685 | return 0; | |
5686 | } | |
5687 | ||
d0752060 HB |
5688 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
5689 | { | |
98918833 SY |
5690 | struct i387_fxsave_struct *fxsave = |
5691 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 5692 | |
d0752060 HB |
5693 | memcpy(fpu->fpr, fxsave->st_space, 128); |
5694 | fpu->fcw = fxsave->cwd; | |
5695 | fpu->fsw = fxsave->swd; | |
5696 | fpu->ftwx = fxsave->twd; | |
5697 | fpu->last_opcode = fxsave->fop; | |
5698 | fpu->last_ip = fxsave->rip; | |
5699 | fpu->last_dp = fxsave->rdp; | |
5700 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
5701 | ||
d0752060 HB |
5702 | return 0; |
5703 | } | |
5704 | ||
5705 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
5706 | { | |
98918833 SY |
5707 | struct i387_fxsave_struct *fxsave = |
5708 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 5709 | |
d0752060 HB |
5710 | memcpy(fxsave->st_space, fpu->fpr, 128); |
5711 | fxsave->cwd = fpu->fcw; | |
5712 | fxsave->swd = fpu->fsw; | |
5713 | fxsave->twd = fpu->ftwx; | |
5714 | fxsave->fop = fpu->last_opcode; | |
5715 | fxsave->rip = fpu->last_ip; | |
5716 | fxsave->rdp = fpu->last_dp; | |
5717 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
5718 | ||
d0752060 HB |
5719 | return 0; |
5720 | } | |
5721 | ||
10ab25cd | 5722 | int fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 5723 | { |
10ab25cd JK |
5724 | int err; |
5725 | ||
5726 | err = fpu_alloc(&vcpu->arch.guest_fpu); | |
5727 | if (err) | |
5728 | return err; | |
5729 | ||
98918833 | 5730 | fpu_finit(&vcpu->arch.guest_fpu); |
d0752060 | 5731 | |
2acf923e DC |
5732 | /* |
5733 | * Ensure guest xcr0 is valid for loading | |
5734 | */ | |
5735 | vcpu->arch.xcr0 = XSTATE_FP; | |
5736 | ||
ad312c7c | 5737 | vcpu->arch.cr0 |= X86_CR0_ET; |
10ab25cd JK |
5738 | |
5739 | return 0; | |
d0752060 HB |
5740 | } |
5741 | EXPORT_SYMBOL_GPL(fx_init); | |
5742 | ||
98918833 SY |
5743 | static void fx_free(struct kvm_vcpu *vcpu) |
5744 | { | |
5745 | fpu_free(&vcpu->arch.guest_fpu); | |
5746 | } | |
5747 | ||
d0752060 HB |
5748 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) |
5749 | { | |
2608d7a1 | 5750 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
5751 | return; |
5752 | ||
2acf923e DC |
5753 | /* |
5754 | * Restore all possible states in the guest, | |
5755 | * and assume host would use all available bits. | |
5756 | * Guest xcr0 would be loaded later. | |
5757 | */ | |
5758 | kvm_put_guest_xcr0(vcpu); | |
d0752060 | 5759 | vcpu->guest_fpu_loaded = 1; |
7cf30855 | 5760 | unlazy_fpu(current); |
98918833 | 5761 | fpu_restore_checking(&vcpu->arch.guest_fpu); |
0c04851c | 5762 | trace_kvm_fpu(1); |
d0752060 | 5763 | } |
d0752060 HB |
5764 | |
5765 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
5766 | { | |
2acf923e DC |
5767 | kvm_put_guest_xcr0(vcpu); |
5768 | ||
d0752060 HB |
5769 | if (!vcpu->guest_fpu_loaded) |
5770 | return; | |
5771 | ||
5772 | vcpu->guest_fpu_loaded = 0; | |
98918833 | 5773 | fpu_save_init(&vcpu->arch.guest_fpu); |
f096ed85 | 5774 | ++vcpu->stat.fpu_reload; |
a8eeb04a | 5775 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); |
0c04851c | 5776 | trace_kvm_fpu(0); |
d0752060 | 5777 | } |
e9b11c17 ZX |
5778 | |
5779 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
5780 | { | |
7f1ea208 JR |
5781 | if (vcpu->arch.time_page) { |
5782 | kvm_release_page_dirty(vcpu->arch.time_page); | |
5783 | vcpu->arch.time_page = NULL; | |
5784 | } | |
5785 | ||
f5f48ee1 | 5786 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
98918833 | 5787 | fx_free(vcpu); |
e9b11c17 ZX |
5788 | kvm_x86_ops->vcpu_free(vcpu); |
5789 | } | |
5790 | ||
5791 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
5792 | unsigned int id) | |
5793 | { | |
6755bae8 ZA |
5794 | if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
5795 | printk_once(KERN_WARNING | |
5796 | "kvm: SMP vm created on host with unstable TSC; " | |
5797 | "guest TSC will not be reliable\n"); | |
26e5215f AK |
5798 | return kvm_x86_ops->vcpu_create(kvm, id); |
5799 | } | |
e9b11c17 | 5800 | |
26e5215f AK |
5801 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
5802 | { | |
5803 | int r; | |
e9b11c17 | 5804 | |
0bed3b56 | 5805 | vcpu->arch.mtrr_state.have_fixed = 1; |
e9b11c17 ZX |
5806 | vcpu_load(vcpu); |
5807 | r = kvm_arch_vcpu_reset(vcpu); | |
5808 | if (r == 0) | |
5809 | r = kvm_mmu_setup(vcpu); | |
5810 | vcpu_put(vcpu); | |
5811 | if (r < 0) | |
5812 | goto free_vcpu; | |
5813 | ||
26e5215f | 5814 | return 0; |
e9b11c17 ZX |
5815 | free_vcpu: |
5816 | kvm_x86_ops->vcpu_free(vcpu); | |
26e5215f | 5817 | return r; |
e9b11c17 ZX |
5818 | } |
5819 | ||
d40ccc62 | 5820 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 5821 | { |
344d9588 GN |
5822 | vcpu->arch.apf.msr_val = 0; |
5823 | ||
e9b11c17 ZX |
5824 | vcpu_load(vcpu); |
5825 | kvm_mmu_unload(vcpu); | |
5826 | vcpu_put(vcpu); | |
5827 | ||
98918833 | 5828 | fx_free(vcpu); |
e9b11c17 ZX |
5829 | kvm_x86_ops->vcpu_free(vcpu); |
5830 | } | |
5831 | ||
5832 | int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu) | |
5833 | { | |
448fa4a9 JK |
5834 | vcpu->arch.nmi_pending = false; |
5835 | vcpu->arch.nmi_injected = false; | |
5836 | ||
42dbaa5a JK |
5837 | vcpu->arch.switch_db_regs = 0; |
5838 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); | |
5839 | vcpu->arch.dr6 = DR6_FIXED_1; | |
5840 | vcpu->arch.dr7 = DR7_FIXED_1; | |
5841 | ||
3842d135 | 5842 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 5843 | vcpu->arch.apf.msr_val = 0; |
3842d135 | 5844 | |
af585b92 GN |
5845 | kvm_clear_async_pf_completion_queue(vcpu); |
5846 | kvm_async_pf_hash_reset(vcpu); | |
5847 | vcpu->arch.apf.halted = false; | |
5848 | ||
e9b11c17 ZX |
5849 | return kvm_x86_ops->vcpu_reset(vcpu); |
5850 | } | |
5851 | ||
10474ae8 | 5852 | int kvm_arch_hardware_enable(void *garbage) |
e9b11c17 | 5853 | { |
ca84d1a2 ZA |
5854 | struct kvm *kvm; |
5855 | struct kvm_vcpu *vcpu; | |
5856 | int i; | |
18863bdd AK |
5857 | |
5858 | kvm_shared_msr_cpu_online(); | |
ca84d1a2 ZA |
5859 | list_for_each_entry(kvm, &vm_list, vm_list) |
5860 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5861 | if (vcpu->cpu == smp_processor_id()) | |
c285545f | 5862 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
10474ae8 | 5863 | return kvm_x86_ops->hardware_enable(garbage); |
e9b11c17 ZX |
5864 | } |
5865 | ||
5866 | void kvm_arch_hardware_disable(void *garbage) | |
5867 | { | |
5868 | kvm_x86_ops->hardware_disable(garbage); | |
3548bab5 | 5869 | drop_user_return_notifiers(garbage); |
e9b11c17 ZX |
5870 | } |
5871 | ||
5872 | int kvm_arch_hardware_setup(void) | |
5873 | { | |
5874 | return kvm_x86_ops->hardware_setup(); | |
5875 | } | |
5876 | ||
5877 | void kvm_arch_hardware_unsetup(void) | |
5878 | { | |
5879 | kvm_x86_ops->hardware_unsetup(); | |
5880 | } | |
5881 | ||
5882 | void kvm_arch_check_processor_compat(void *rtn) | |
5883 | { | |
5884 | kvm_x86_ops->check_processor_compatibility(rtn); | |
5885 | } | |
5886 | ||
5887 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) | |
5888 | { | |
5889 | struct page *page; | |
5890 | struct kvm *kvm; | |
5891 | int r; | |
5892 | ||
5893 | BUG_ON(vcpu->kvm == NULL); | |
5894 | kvm = vcpu->kvm; | |
5895 | ||
9aabc88f | 5896 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
14dfe855 | 5897 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; |
ad312c7c | 5898 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
c30a358d | 5899 | vcpu->arch.mmu.translate_gpa = translate_gpa; |
02f59dc9 | 5900 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; |
c5af89b6 | 5901 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) |
a4535290 | 5902 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 5903 | else |
a4535290 | 5904 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
5905 | |
5906 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
5907 | if (!page) { | |
5908 | r = -ENOMEM; | |
5909 | goto fail; | |
5910 | } | |
ad312c7c | 5911 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 5912 | |
c285545f ZA |
5913 | if (!kvm->arch.virtual_tsc_khz) |
5914 | kvm_arch_set_tsc_khz(kvm, max_tsc_khz); | |
5915 | ||
e9b11c17 ZX |
5916 | r = kvm_mmu_create(vcpu); |
5917 | if (r < 0) | |
5918 | goto fail_free_pio_data; | |
5919 | ||
5920 | if (irqchip_in_kernel(kvm)) { | |
5921 | r = kvm_create_lapic(vcpu); | |
5922 | if (r < 0) | |
5923 | goto fail_mmu_destroy; | |
5924 | } | |
5925 | ||
890ca9ae HY |
5926 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
5927 | GFP_KERNEL); | |
5928 | if (!vcpu->arch.mce_banks) { | |
5929 | r = -ENOMEM; | |
443c39bc | 5930 | goto fail_free_lapic; |
890ca9ae HY |
5931 | } |
5932 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
5933 | ||
f5f48ee1 SY |
5934 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) |
5935 | goto fail_free_mce_banks; | |
5936 | ||
af585b92 GN |
5937 | kvm_async_pf_hash_reset(vcpu); |
5938 | ||
e9b11c17 | 5939 | return 0; |
f5f48ee1 SY |
5940 | fail_free_mce_banks: |
5941 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
5942 | fail_free_lapic: |
5943 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
5944 | fail_mmu_destroy: |
5945 | kvm_mmu_destroy(vcpu); | |
5946 | fail_free_pio_data: | |
ad312c7c | 5947 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
5948 | fail: |
5949 | return r; | |
5950 | } | |
5951 | ||
5952 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
5953 | { | |
f656ce01 MT |
5954 | int idx; |
5955 | ||
36cb93fd | 5956 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 5957 | kvm_free_lapic(vcpu); |
f656ce01 | 5958 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 5959 | kvm_mmu_destroy(vcpu); |
f656ce01 | 5960 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 5961 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 | 5962 | } |
d19a9cd2 ZX |
5963 | |
5964 | struct kvm *kvm_arch_create_vm(void) | |
5965 | { | |
5966 | struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL); | |
5967 | ||
5968 | if (!kvm) | |
5969 | return ERR_PTR(-ENOMEM); | |
5970 | ||
f05e70ac | 5971 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
4d5c5d0f | 5972 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
d19a9cd2 | 5973 | |
5550af4d SY |
5974 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
5975 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
5976 | ||
99e3e30a | 5977 | spin_lock_init(&kvm->arch.tsc_write_lock); |
53f658b3 | 5978 | |
d19a9cd2 ZX |
5979 | return kvm; |
5980 | } | |
5981 | ||
5982 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
5983 | { | |
5984 | vcpu_load(vcpu); | |
5985 | kvm_mmu_unload(vcpu); | |
5986 | vcpu_put(vcpu); | |
5987 | } | |
5988 | ||
5989 | static void kvm_free_vcpus(struct kvm *kvm) | |
5990 | { | |
5991 | unsigned int i; | |
988a2cae | 5992 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
5993 | |
5994 | /* | |
5995 | * Unpin any mmu pages first. | |
5996 | */ | |
af585b92 GN |
5997 | kvm_for_each_vcpu(i, vcpu, kvm) { |
5998 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 5999 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 6000 | } |
988a2cae GN |
6001 | kvm_for_each_vcpu(i, vcpu, kvm) |
6002 | kvm_arch_vcpu_free(vcpu); | |
6003 | ||
6004 | mutex_lock(&kvm->lock); | |
6005 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
6006 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 6007 | |
988a2cae GN |
6008 | atomic_set(&kvm->online_vcpus, 0); |
6009 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
6010 | } |
6011 | ||
ad8ba2cd SY |
6012 | void kvm_arch_sync_events(struct kvm *kvm) |
6013 | { | |
ba4cef31 | 6014 | kvm_free_all_assigned_devices(kvm); |
aea924f6 | 6015 | kvm_free_pit(kvm); |
ad8ba2cd SY |
6016 | } |
6017 | ||
d19a9cd2 ZX |
6018 | void kvm_arch_destroy_vm(struct kvm *kvm) |
6019 | { | |
6eb55818 | 6020 | kvm_iommu_unmap_guest(kvm); |
d7deeeb0 ZX |
6021 | kfree(kvm->arch.vpic); |
6022 | kfree(kvm->arch.vioapic); | |
d19a9cd2 ZX |
6023 | kvm_free_vcpus(kvm); |
6024 | kvm_free_physmem(kvm); | |
3d45830c AK |
6025 | if (kvm->arch.apic_access_page) |
6026 | put_page(kvm->arch.apic_access_page); | |
b7ebfb05 SY |
6027 | if (kvm->arch.ept_identity_pagetable) |
6028 | put_page(kvm->arch.ept_identity_pagetable); | |
64749204 | 6029 | cleanup_srcu_struct(&kvm->srcu); |
d19a9cd2 ZX |
6030 | kfree(kvm); |
6031 | } | |
0de10343 | 6032 | |
f7784b8e MT |
6033 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
6034 | struct kvm_memory_slot *memslot, | |
0de10343 | 6035 | struct kvm_memory_slot old, |
f7784b8e | 6036 | struct kvm_userspace_memory_region *mem, |
0de10343 ZX |
6037 | int user_alloc) |
6038 | { | |
f7784b8e | 6039 | int npages = memslot->npages; |
7ac77099 AK |
6040 | int map_flags = MAP_PRIVATE | MAP_ANONYMOUS; |
6041 | ||
6042 | /* Prevent internal slot pages from being moved by fork()/COW. */ | |
6043 | if (memslot->id >= KVM_MEMORY_SLOTS) | |
6044 | map_flags = MAP_SHARED | MAP_ANONYMOUS; | |
0de10343 ZX |
6045 | |
6046 | /*To keep backward compatibility with older userspace, | |
6047 | *x86 needs to hanlde !user_alloc case. | |
6048 | */ | |
6049 | if (!user_alloc) { | |
6050 | if (npages && !old.rmap) { | |
604b38ac AA |
6051 | unsigned long userspace_addr; |
6052 | ||
72dc67a6 | 6053 | down_write(¤t->mm->mmap_sem); |
604b38ac AA |
6054 | userspace_addr = do_mmap(NULL, 0, |
6055 | npages * PAGE_SIZE, | |
6056 | PROT_READ | PROT_WRITE, | |
7ac77099 | 6057 | map_flags, |
604b38ac | 6058 | 0); |
72dc67a6 | 6059 | up_write(¤t->mm->mmap_sem); |
0de10343 | 6060 | |
604b38ac AA |
6061 | if (IS_ERR((void *)userspace_addr)) |
6062 | return PTR_ERR((void *)userspace_addr); | |
6063 | ||
604b38ac | 6064 | memslot->userspace_addr = userspace_addr; |
0de10343 ZX |
6065 | } |
6066 | } | |
6067 | ||
f7784b8e MT |
6068 | |
6069 | return 0; | |
6070 | } | |
6071 | ||
6072 | void kvm_arch_commit_memory_region(struct kvm *kvm, | |
6073 | struct kvm_userspace_memory_region *mem, | |
6074 | struct kvm_memory_slot old, | |
6075 | int user_alloc) | |
6076 | { | |
6077 | ||
6078 | int npages = mem->memory_size >> PAGE_SHIFT; | |
6079 | ||
6080 | if (!user_alloc && !old.user_alloc && old.rmap && !npages) { | |
6081 | int ret; | |
6082 | ||
6083 | down_write(¤t->mm->mmap_sem); | |
6084 | ret = do_munmap(current->mm, old.userspace_addr, | |
6085 | old.npages * PAGE_SIZE); | |
6086 | up_write(¤t->mm->mmap_sem); | |
6087 | if (ret < 0) | |
6088 | printk(KERN_WARNING | |
6089 | "kvm_vm_ioctl_set_memory_region: " | |
6090 | "failed to munmap memory\n"); | |
6091 | } | |
6092 | ||
7c8a83b7 | 6093 | spin_lock(&kvm->mmu_lock); |
f05e70ac | 6094 | if (!kvm->arch.n_requested_mmu_pages) { |
0de10343 ZX |
6095 | unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); |
6096 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); | |
6097 | } | |
6098 | ||
6099 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); | |
7c8a83b7 | 6100 | spin_unlock(&kvm->mmu_lock); |
0de10343 | 6101 | } |
1d737c8a | 6102 | |
34d4cb8f MT |
6103 | void kvm_arch_flush_shadow(struct kvm *kvm) |
6104 | { | |
6105 | kvm_mmu_zap_all(kvm); | |
8986ecc0 | 6106 | kvm_reload_remote_mmus(kvm); |
34d4cb8f MT |
6107 | } |
6108 | ||
1d737c8a ZX |
6109 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
6110 | { | |
af585b92 GN |
6111 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
6112 | !vcpu->arch.apf.halted) | |
6113 | || !list_empty_careful(&vcpu->async_pf.done) | |
a1b37100 GN |
6114 | || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED |
6115 | || vcpu->arch.nmi_pending || | |
6116 | (kvm_arch_interrupt_allowed(vcpu) && | |
6117 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 6118 | } |
5736199a | 6119 | |
5736199a ZX |
6120 | void kvm_vcpu_kick(struct kvm_vcpu *vcpu) |
6121 | { | |
32f88400 MT |
6122 | int me; |
6123 | int cpu = vcpu->cpu; | |
5736199a ZX |
6124 | |
6125 | if (waitqueue_active(&vcpu->wq)) { | |
6126 | wake_up_interruptible(&vcpu->wq); | |
6127 | ++vcpu->stat.halt_wakeup; | |
6128 | } | |
32f88400 MT |
6129 | |
6130 | me = get_cpu(); | |
6131 | if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu)) | |
d94e1dc9 | 6132 | if (atomic_xchg(&vcpu->guest_mode, 0)) |
32f88400 | 6133 | smp_send_reschedule(cpu); |
e9571ed5 | 6134 | put_cpu(); |
5736199a | 6135 | } |
78646121 GN |
6136 | |
6137 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
6138 | { | |
6139 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
6140 | } | |
229456fc | 6141 | |
f92653ee JK |
6142 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
6143 | { | |
6144 | unsigned long current_rip = kvm_rip_read(vcpu) + | |
6145 | get_segment_base(vcpu, VCPU_SREG_CS); | |
6146 | ||
6147 | return current_rip == linear_rip; | |
6148 | } | |
6149 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
6150 | ||
94fe45da JK |
6151 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
6152 | { | |
6153 | unsigned long rflags; | |
6154 | ||
6155 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
6156 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 6157 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
6158 | return rflags; |
6159 | } | |
6160 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
6161 | ||
6162 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
6163 | { | |
6164 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 6165 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 6166 | rflags |= X86_EFLAGS_TF; |
94fe45da | 6167 | kvm_x86_ops->set_rflags(vcpu, rflags); |
3842d135 | 6168 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
6169 | } |
6170 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
6171 | ||
56028d08 GN |
6172 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
6173 | { | |
6174 | int r; | |
6175 | ||
6176 | if (!vcpu->arch.mmu.direct_map || is_error_page(work->page)) | |
6177 | return; | |
6178 | ||
6179 | r = kvm_mmu_reload(vcpu); | |
6180 | if (unlikely(r)) | |
6181 | return; | |
6182 | ||
6183 | vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); | |
6184 | } | |
6185 | ||
af585b92 GN |
6186 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
6187 | { | |
6188 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
6189 | } | |
6190 | ||
6191 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
6192 | { | |
6193 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
6194 | } | |
6195 | ||
6196 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6197 | { | |
6198 | u32 key = kvm_async_pf_hash_fn(gfn); | |
6199 | ||
6200 | while (vcpu->arch.apf.gfns[key] != ~0) | |
6201 | key = kvm_async_pf_next_probe(key); | |
6202 | ||
6203 | vcpu->arch.apf.gfns[key] = gfn; | |
6204 | } | |
6205 | ||
6206 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6207 | { | |
6208 | int i; | |
6209 | u32 key = kvm_async_pf_hash_fn(gfn); | |
6210 | ||
6211 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
6212 | (vcpu->arch.apf.gfns[key] != gfn || | |
6213 | vcpu->arch.apf.gfns[key] == ~0); i++) | |
6214 | key = kvm_async_pf_next_probe(key); | |
6215 | ||
6216 | return key; | |
6217 | } | |
6218 | ||
6219 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6220 | { | |
6221 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
6222 | } | |
6223 | ||
6224 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6225 | { | |
6226 | u32 i, j, k; | |
6227 | ||
6228 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
6229 | while (true) { | |
6230 | vcpu->arch.apf.gfns[i] = ~0; | |
6231 | do { | |
6232 | j = kvm_async_pf_next_probe(j); | |
6233 | if (vcpu->arch.apf.gfns[j] == ~0) | |
6234 | return; | |
6235 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
6236 | /* | |
6237 | * k lies cyclically in ]i,j] | |
6238 | * | i.k.j | | |
6239 | * |....j i.k.| or |.k..j i...| | |
6240 | */ | |
6241 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
6242 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
6243 | i = j; | |
6244 | } | |
6245 | } | |
6246 | ||
7c90705b GN |
6247 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
6248 | { | |
6249 | ||
6250 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
6251 | sizeof(val)); | |
6252 | } | |
6253 | ||
af585b92 GN |
6254 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
6255 | struct kvm_async_pf *work) | |
6256 | { | |
7c90705b | 6257 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 6258 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b GN |
6259 | |
6260 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
fc5f06fa GN |
6261 | (vcpu->arch.apf.send_user_only && |
6262 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
7c90705b GN |
6263 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
6264 | else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6265 | vcpu->arch.fault.error_code = 0; | |
6266 | vcpu->arch.fault.address = work->arch.token; | |
6267 | kvm_inject_page_fault(vcpu); | |
6268 | } | |
af585b92 GN |
6269 | } |
6270 | ||
6271 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
6272 | struct kvm_async_pf *work) | |
6273 | { | |
7c90705b GN |
6274 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
6275 | if (is_error_page(work->page)) | |
6276 | work->arch.token = ~0; /* broadcast wakeup */ | |
6277 | else | |
6278 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
6279 | ||
6280 | if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && | |
6281 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { | |
6282 | vcpu->arch.fault.error_code = 0; | |
6283 | vcpu->arch.fault.address = work->arch.token; | |
6284 | kvm_inject_page_fault(vcpu); | |
6285 | } | |
6286 | } | |
6287 | ||
6288 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
6289 | { | |
6290 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
6291 | return true; | |
6292 | else | |
6293 | return !kvm_event_needs_reinjection(vcpu) && | |
6294 | kvm_x86_ops->interrupt_allowed(vcpu); | |
af585b92 GN |
6295 | } |
6296 | ||
229456fc MT |
6297 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
6298 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
6299 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
6300 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
6301 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 6302 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 6303 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 6304 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 6305 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 6306 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 6307 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 6308 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |