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KVM: x86: fix check legal type of Variable Range MTRRs
[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
92a1f12d
JR		 101bool kvm_has_tsc_control;
102EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103u32 kvm_max_guest_tsc_khz;
104EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105
cc578287
ZA		 106/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107static u32 tsc_tolerance_ppm = 250;
108module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109
16a96021
MT		 110static bool backwards_tsc_observed = false;
111
18863bdd
AK		 112#define KVM_NR_SHARED_MSRS 16
113
114struct kvm_shared_msrs_global {
115 int nr;
2bf78fa7 116 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 117};
118
119struct kvm_shared_msrs {
120 struct user_return_notifier urn;
121 bool registered;
2bf78fa7
SY		 122 struct kvm_shared_msr_values {
123 u64 host;
124 u64 curr;
125 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 126};
127
128static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 129static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 130
417bc304 131struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 132 { "pf_fixed", VCPU_STAT(pf_fixed) },
133 { "pf_guest", VCPU_STAT(pf_guest) },
134 { "tlb_flush", VCPU_STAT(tlb_flush) },
135 { "invlpg", VCPU_STAT(invlpg) },
136 { "exits", VCPU_STAT(exits) },
137 { "io_exits", VCPU_STAT(io_exits) },
138 { "mmio_exits", VCPU_STAT(mmio_exits) },
139 { "signal_exits", VCPU_STAT(signal_exits) },
140 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 141 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 142 { "halt_exits", VCPU_STAT(halt_exits) },
143 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 144 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 145 { "request_irq", VCPU_STAT(request_irq_exits) },
146 { "irq_exits", VCPU_STAT(irq_exits) },
147 { "host_state_reload", VCPU_STAT(host_state_reload) },
148 { "efer_reload", VCPU_STAT(efer_reload) },
149 { "fpu_reload", VCPU_STAT(fpu_reload) },
150 { "insn_emulation", VCPU_STAT(insn_emulation) },
151 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 152 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 153 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 154 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
155 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
156 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
157 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
158 { "mmu_flooded", VM_STAT(mmu_flooded) },
159 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 160 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 161 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 162 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 163 { "largepages", VM_STAT(lpages) },
417bc304
HB		 164 { NULL }
165};
166
2acf923e
DC		 167u64 __read_mostly host_xcr0;
168
b6785def 169static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 170
af585b92
GN		 171static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
172{
173 int i;
174 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
175 vcpu->arch.apf.gfns[i] = ~0;
176}
177
18863bdd
AK		 178static void kvm_on_user_return(struct user_return_notifier *urn)
179{
180 unsigned slot;
18863bdd
AK		 181 struct kvm_shared_msrs *locals
182 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 183 struct kvm_shared_msr_values *values;
18863bdd
AK		 184
185 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 186 values = &locals->values[slot];
187 if (values->host != values->curr) {
188 wrmsrl(shared_msrs_global.msrs[slot], values->host);
189 values->curr = values->host;
18863bdd
AK		 190 }
191 }
192 locals->registered = false;
193 user_return_notifier_unregister(urn);
194}
195
2bf78fa7 196static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 197{
18863bdd 198 u64 value;
013f6a5d
MT		 199 unsigned int cpu = smp_processor_id();
200 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 201
2bf78fa7
SY		 202 /* only read, and nobody should modify it at this time,
203 * so don't need lock */
204 if (slot >= shared_msrs_global.nr) {
205 printk(KERN_ERR "kvm: invalid MSR slot!");
206 return;
207 }
208 rdmsrl_safe(msr, &value);
209 smsr->values[slot].host = value;
210 smsr->values[slot].curr = value;
211}
212
213void kvm_define_shared_msr(unsigned slot, u32 msr)
214{
0123be42 215 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 216 if (slot >= shared_msrs_global.nr)
217 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 218 shared_msrs_global.msrs[slot] = msr;
219 /* we need ensured the shared_msr_global have been updated */
220 smp_wmb();
18863bdd
AK		 221}
222EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
223
224static void kvm_shared_msr_cpu_online(void)
225{
226 unsigned i;
18863bdd
AK		 227
228 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 229 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 230}
231
d5696725 232void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 233{
013f6a5d
MT		 234 unsigned int cpu = smp_processor_id();
235 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 236
2bf78fa7 237 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 238 return;
2bf78fa7
SY		 239 smsr->values[slot].curr = value;
240 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 241 if (!smsr->registered) {
242 smsr->urn.on_user_return = kvm_on_user_return;
243 user_return_notifier_register(&smsr->urn);
244 smsr->registered = true;
245 }
246}
247EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
248
3548bab5
AK		 249static void drop_user_return_notifiers(void *ignore)
250{
013f6a5d
MT		 251 unsigned int cpu = smp_processor_id();
252 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 253
254 if (smsr->registered)
255 kvm_on_user_return(&smsr->urn);
256}
257
6866b83e
CO		 258u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
259{
8a5a87d9 260 return vcpu->arch.apic_base;
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_get_apic_base);
263
58cb628d
JK		 264int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
265{
266 u64 old_state = vcpu->arch.apic_base &
267 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
268 u64 new_state = msr_info->data &
269 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
270 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
271 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
272
273 if (!msr_info->host_initiated &&
274 ((msr_info->data & reserved_bits) != 0 ||
275 new_state == X2APIC_ENABLE ||
276 (new_state == MSR_IA32_APICBASE_ENABLE &&
277 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
278 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
279 old_state == 0)))
280 return 1;
281
282 kvm_lapic_set_base(vcpu, msr_info->data);
283 return 0;
6866b83e
CO		 284}
285EXPORT_SYMBOL_GPL(kvm_set_apic_base);
286
2605fc21 287asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 288{
289 /* Fault while not rebooting. We want the trace. */
290 BUG();
291}
292EXPORT_SYMBOL_GPL(kvm_spurious_fault);
293
3fd28fce
ED		 294#define EXCPT_BENIGN 0
295#define EXCPT_CONTRIBUTORY 1
296#define EXCPT_PF 2
297
298static int exception_class(int vector)
299{
300 switch (vector) {
301 case PF_VECTOR:
302 return EXCPT_PF;
303 case DE_VECTOR:
304 case TS_VECTOR:
305 case NP_VECTOR:
306 case SS_VECTOR:
307 case GP_VECTOR:
308 return EXCPT_CONTRIBUTORY;
309 default:
310 break;
311 }
312 return EXCPT_BENIGN;
313}
314
d6e8c854
NA		 315#define EXCPT_FAULT 0
316#define EXCPT_TRAP 1
317#define EXCPT_ABORT 2
318#define EXCPT_INTERRUPT 3
319
320static int exception_type(int vector)
321{
322 unsigned int mask;
323
324 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
325 return EXCPT_INTERRUPT;
326
327 mask = 1 << vector;
328
329 /* #DB is trap, as instruction watchpoints are handled elsewhere */
330 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
331 return EXCPT_TRAP;
332
333 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
334 return EXCPT_ABORT;
335
336 /* Reserved exceptions will result in fault */
337 return EXCPT_FAULT;
338}
339
3fd28fce 340static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 341 unsigned nr, bool has_error, u32 error_code,
342 bool reinject)
3fd28fce
ED		 343{
344 u32 prev_nr;
345 int class1, class2;
346
3842d135
AK		 347 kvm_make_request(KVM_REQ_EVENT, vcpu);
348
3fd28fce
ED		 349 if (!vcpu->arch.exception.pending) {
350 queue:
351 vcpu->arch.exception.pending = true;
352 vcpu->arch.exception.has_error_code = has_error;
353 vcpu->arch.exception.nr = nr;
354 vcpu->arch.exception.error_code = error_code;
3f0fd292 355 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 356 return;
357 }
358
359 /* to check exception */
360 prev_nr = vcpu->arch.exception.nr;
361 if (prev_nr == DF_VECTOR) {
362 /* triple fault -> shutdown */
a8eeb04a 363 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 364 return;
365 }
366 class1 = exception_class(prev_nr);
367 class2 = exception_class(nr);
368 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
369 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
370 /* generate double fault per SDM Table 5-5 */
371 vcpu->arch.exception.pending = true;
372 vcpu->arch.exception.has_error_code = true;
373 vcpu->arch.exception.nr = DF_VECTOR;
374 vcpu->arch.exception.error_code = 0;
375 } else
376 /* replace previous exception with a new one in a hope
377 that instruction re-execution will regenerate lost
378 exception */
379 goto queue;
380}
381
298101da
AK		 382void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
383{
ce7ddec4 384 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 385}
386EXPORT_SYMBOL_GPL(kvm_queue_exception);
387
ce7ddec4
JR		 388void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
389{
390 kvm_multiple_exception(vcpu, nr, false, 0, true);
391}
392EXPORT_SYMBOL_GPL(kvm_requeue_exception);
393
db8fcefa 394void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 395{
db8fcefa
AP		 396 if (err)
397 kvm_inject_gp(vcpu, 0);
398 else
399 kvm_x86_ops->skip_emulated_instruction(vcpu);
400}
401EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 402
6389ee94 403void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 404{
405 ++vcpu->stat.pf_guest;
6389ee94
AK		 406 vcpu->arch.cr2 = fault->address;
407 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 408}
27d6c865 409EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 410
6389ee94 411void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 412{
6389ee94
AK		 413 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
414 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 415 else
6389ee94 416 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 417}
418
3419ffc8
SY		 419void kvm_inject_nmi(struct kvm_vcpu *vcpu)
420{
7460fb4a
AK		 421 atomic_inc(&vcpu->arch.nmi_queued);
422 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 423}
424EXPORT_SYMBOL_GPL(kvm_inject_nmi);
425
298101da
AK		 426void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
427{
ce7ddec4 428 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 429}
430EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
431
ce7ddec4
JR		 432void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
433{
434 kvm_multiple_exception(vcpu, nr, true, error_code, true);
435}
436EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
437
0a79b009
AK		 438/*
439 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
440 * a #GP and return false.
441 */
442bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 443{
0a79b009
AK		 444 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
445 return true;
446 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
447 return false;
298101da 448}
0a79b009 449EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 450
ec92fe44
JR		 451/*
452 * This function will be used to read from the physical memory of the currently
453 * running guest. The difference to kvm_read_guest_page is that this function
454 * can read from guest physical or from the guest's guest physical memory.
455 */
456int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
457 gfn_t ngfn, void *data, int offset, int len,
458 u32 access)
459{
460 gfn_t real_gfn;
461 gpa_t ngpa;
462
463 ngpa = gfn_to_gpa(ngfn);
464 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
465 if (real_gfn == UNMAPPED_GVA)
466 return -EFAULT;
467
468 real_gfn = gpa_to_gfn(real_gfn);
469
470 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
471}
472EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
473
3d06b8bf
JR		 474int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
475 void *data, int offset, int len, u32 access)
476{
477 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
478 data, offset, len, access);
479}
480
a03490ed
CO		 481/*
482 * Load the pae pdptrs. Return true is they are all valid.
483 */
ff03a073 484int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 485{
486 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
487 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
488 int i;
489 int ret;
ff03a073 490 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 491
ff03a073
JR		 492 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
493 offset * sizeof(u64), sizeof(pdpte),
494 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 495 if (ret < 0) {
496 ret = 0;
497 goto out;
498 }
499 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 500 if (is_present_gpte(pdpte[i]) &&
20c466b5 501 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 502 ret = 0;
503 goto out;
504 }
505 }
506 ret = 1;
507
ff03a073 508 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 509 __set_bit(VCPU_EXREG_PDPTR,
510 (unsigned long *)&vcpu->arch.regs_avail);
511 __set_bit(VCPU_EXREG_PDPTR,
512 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 513out:
a03490ed
CO		 514
515 return ret;
516}
cc4b6871 517EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 518
d835dfec
AK		 519static bool pdptrs_changed(struct kvm_vcpu *vcpu)
520{
ff03a073 521 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 522 bool changed = true;
3d06b8bf
JR		 523 int offset;
524 gfn_t gfn;
d835dfec
AK		 525 int r;
526
527 if (is_long_mode(vcpu) || !is_pae(vcpu))
528 return false;
529
6de4f3ad
AK		 530 if (!test_bit(VCPU_EXREG_PDPTR,
531 (unsigned long *)&vcpu->arch.regs_avail))
532 return true;
533
9f8fe504
AK		 534 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
535 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 536 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
537 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 538 if (r < 0)
539 goto out;
ff03a073 540 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 541out:
d835dfec
AK		 542
543 return changed;
544}
545
49a9b07e 546int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 547{
aad82703
SY		 548 unsigned long old_cr0 = kvm_read_cr0(vcpu);
549 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
550 X86_CR0_CD | X86_CR0_NW;
551
f9a48e6a
AK		 552 cr0 |= X86_CR0_ET;
553
ab344828 554#ifdef CONFIG_X86_64
0f12244f
GN		 555 if (cr0 & 0xffffffff00000000UL)
556 return 1;
ab344828
GN		 557#endif
558
559 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 560
0f12244f
GN		 561 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
562 return 1;
a03490ed 563
0f12244f
GN		 564 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
565 return 1;
a03490ed
CO		 566
567 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
568#ifdef CONFIG_X86_64
f6801dff 569 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 570 int cs_db, cs_l;
571
0f12244f
GN		 572 if (!is_pae(vcpu))
573 return 1;
a03490ed 574 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 575 if (cs_l)
576 return 1;
a03490ed
CO		 577 } else
578#endif
ff03a073 579 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 580 kvm_read_cr3(vcpu)))
0f12244f 581 return 1;
a03490ed
CO		 582 }
583
ad756a16
MJ		 584 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
585 return 1;
586
a03490ed 587 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 588
d170c419 589 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 590 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 591 kvm_async_pf_hash_reset(vcpu);
592 }
e5f3f027 593
aad82703
SY		 594 if ((cr0 ^ old_cr0) & update_bits)
595 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 596 return 0;
597}
2d3ad1f4 598EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 599
2d3ad1f4 600void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 601{
49a9b07e 602 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 603}
2d3ad1f4 604EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 605
42bdf991
MT		 606static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
607{
608 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
609 !vcpu->guest_xcr0_loaded) {
610 /* kvm_set_xcr() also depends on this */
611 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
612 vcpu->guest_xcr0_loaded = 1;
613 }
614}
615
616static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
617{
618 if (vcpu->guest_xcr0_loaded) {
619 if (vcpu->arch.xcr0 != host_xcr0)
620 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
621 vcpu->guest_xcr0_loaded = 0;
622 }
623}
624
2acf923e
DC		 625int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
626{
56c103ec
LJ		 627 u64 xcr0 = xcr;
628 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 629 u64 valid_bits;
2acf923e
DC		 630
631 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
632 if (index != XCR_XFEATURE_ENABLED_MASK)
633 return 1;
2acf923e
DC		 634 if (!(xcr0 & XSTATE_FP))
635 return 1;
636 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
637 return 1;
46c34cb0
PB		 638
639 /*
640 * Do not allow the guest to set bits that we do not support
641 * saving. However, xcr0 bit 0 is always set, even if the
642 * emulated CPU does not support XSAVE (see fx_init).
643 */
644 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
645 if (xcr0 & ~valid_bits)
2acf923e 646 return 1;
46c34cb0 647
390bd528
LJ		 648 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
649 return 1;
650
42bdf991 651 kvm_put_guest_xcr0(vcpu);
2acf923e 652 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 653
654 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
655 kvm_update_cpuid(vcpu);
2acf923e
DC		 656 return 0;
657}
658
659int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
660{
764bcbc5
Z		 661 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
662 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 663 kvm_inject_gp(vcpu, 0);
664 return 1;
665 }
666 return 0;
667}
668EXPORT_SYMBOL_GPL(kvm_set_xcr);
669
a83b29c6 670int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 671{
fc78f519 672 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 673 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
674 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 675 if (cr4 & CR4_RESERVED_BITS)
676 return 1;
a03490ed 677
2acf923e
DC		 678 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
679 return 1;
680
c68b734f
YW		 681 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
682 return 1;
683
97ec8c06
FW		 684 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
685 return 1;
686
afcbf13f 687 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 688 return 1;
689
a03490ed 690 if (is_long_mode(vcpu)) {
0f12244f
GN		 691 if (!(cr4 & X86_CR4_PAE))
692 return 1;
a2edf57f
AK		 693 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
694 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 695 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
696 kvm_read_cr3(vcpu)))
0f12244f
GN		 697 return 1;
698
ad756a16
MJ		 699 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
700 if (!guest_cpuid_has_pcid(vcpu))
701 return 1;
702
703 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
704 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
705 return 1;
706 }
707
5e1746d6 708 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 709 return 1;
a03490ed 710
ad756a16
MJ		 711 if (((cr4 ^ old_cr4) & pdptr_bits) ||
712 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 713 kvm_mmu_reset_context(vcpu);
0f12244f 714
97ec8c06
FW		 715 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
716 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
717
2acf923e 718 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 719 kvm_update_cpuid(vcpu);
2acf923e 720
0f12244f
GN		 721 return 0;
722}
2d3ad1f4 723EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 724
2390218b 725int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 726{
9f8fe504 727 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 728 kvm_mmu_sync_roots(vcpu);
d835dfec 729 kvm_mmu_flush_tlb(vcpu);
0f12244f 730 return 0;
d835dfec
AK		 731 }
732
a03490ed 733 if (is_long_mode(vcpu)) {
d9f89b88
JK		 734 if (cr3 & CR3_L_MODE_RESERVED_BITS)
735 return 1;
736 } else if (is_pae(vcpu) && is_paging(vcpu) &&
737 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 738 return 1;
a03490ed 739
0f12244f 740 vcpu->arch.cr3 = cr3;
aff48baa 741 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 742 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 743 return 0;
744}
2d3ad1f4 745EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 746
eea1cff9 747int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 748{
0f12244f
GN		 749 if (cr8 & CR8_RESERVED_BITS)
750 return 1;
a03490ed
CO		 751 if (irqchip_in_kernel(vcpu->kvm))
752 kvm_lapic_set_tpr(vcpu, cr8);
753 else
ad312c7c 754 vcpu->arch.cr8 = cr8;
0f12244f
GN		 755 return 0;
756}
2d3ad1f4 757EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 758
2d3ad1f4 759unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 760{
761 if (irqchip_in_kernel(vcpu->kvm))
762 return kvm_lapic_get_cr8(vcpu);
763 else
ad312c7c 764 return vcpu->arch.cr8;
a03490ed 765}
2d3ad1f4 766EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 767
73aaf249
JK		 768static void kvm_update_dr6(struct kvm_vcpu *vcpu)
769{
770 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
771 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
772}
773
c8639010
JK		 774static void kvm_update_dr7(struct kvm_vcpu *vcpu)
775{
776 unsigned long dr7;
777
778 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
779 dr7 = vcpu->arch.guest_debug_dr7;
780 else
781 dr7 = vcpu->arch.dr7;
782 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 783 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
784 if (dr7 & DR7_BP_EN_MASK)
785 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 786}
787
6f43ed01
NA		 788static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
789{
790 u64 fixed = DR6_FIXED_1;
791
792 if (!guest_cpuid_has_rtm(vcpu))
793 fixed |= DR6_RTM;
794 return fixed;
795}
796
338dbc97 797static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 798{
799 switch (dr) {
800 case 0 ... 3:
801 vcpu->arch.db[dr] = val;
802 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
803 vcpu->arch.eff_db[dr] = val;
804 break;
805 case 4:
338dbc97
GN		 806 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
807 return 1; /* #UD */
020df079
GN		 808 /* fall through */
809 case 6:
338dbc97
GN		 810 if (val & 0xffffffff00000000ULL)
811 return -1; /* #GP */
6f43ed01 812 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 813 kvm_update_dr6(vcpu);
020df079
GN		 814 break;
815 case 5:
338dbc97
GN		 816 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
817 return 1; /* #UD */
020df079
GN		 818 /* fall through */
819 default: /* 7 */
338dbc97
GN		 820 if (val & 0xffffffff00000000ULL)
821 return -1; /* #GP */
020df079 822 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 823 kvm_update_dr7(vcpu);
020df079
GN		 824 break;
825 }
826
827 return 0;
828}
338dbc97
GN		 829
830int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
831{
832 int res;
833
834 res = __kvm_set_dr(vcpu, dr, val);
835 if (res > 0)
836 kvm_queue_exception(vcpu, UD_VECTOR);
837 else if (res < 0)
838 kvm_inject_gp(vcpu, 0);
839
840 return res;
841}
020df079
GN		 842EXPORT_SYMBOL_GPL(kvm_set_dr);
843
338dbc97 844static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 845{
846 switch (dr) {
847 case 0 ... 3:
848 *val = vcpu->arch.db[dr];
849 break;
850 case 4:
338dbc97 851 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 852 return 1;
020df079
GN		 853 /* fall through */
854 case 6:
73aaf249
JK		 855 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
856 *val = vcpu->arch.dr6;
857 else
858 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 859 break;
860 case 5:
338dbc97 861 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 862 return 1;
020df079
GN		 863 /* fall through */
864 default: /* 7 */
865 *val = vcpu->arch.dr7;
866 break;
867 }
868
869 return 0;
870}
338dbc97
GN		 871
872int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
873{
874 if (_kvm_get_dr(vcpu, dr, val)) {
875 kvm_queue_exception(vcpu, UD_VECTOR);
876 return 1;
877 }
878 return 0;
879}
020df079
GN		 880EXPORT_SYMBOL_GPL(kvm_get_dr);
881
022cd0e8
AK		 882bool kvm_rdpmc(struct kvm_vcpu *vcpu)
883{
884 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
885 u64 data;
886 int err;
887
888 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
889 if (err)
890 return err;
891 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
892 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
893 return err;
894}
895EXPORT_SYMBOL_GPL(kvm_rdpmc);
896
043405e1
CO		 897/*
898 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
899 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
900 *
901 * This list is modified at module load time to reflect the
e3267cbb
GC		 902 * capabilities of the host cpu. This capabilities test skips MSRs that are
903 * kvm-specific. Those are put in the beginning of the list.
043405e1 904 */
e3267cbb 905
e984097b 906#define KVM_SAVE_MSRS_BEGIN 12
043405e1 907static u32 msrs_to_save[] = {
e3267cbb 908 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 909 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 910 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 911 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 912 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 913 MSR_KVM_PV_EOI_EN,
043405e1 914 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 915 MSR_STAR,
043405e1
CO		 916#ifdef CONFIG_X86_64
917 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
918#endif
b3897a49 919 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 920 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 921};
922
923static unsigned num_msrs_to_save;
924
f1d24831 925static const u32 emulated_msrs[] = {
ba904635 926 MSR_IA32_TSC_ADJUST,
a3e06bbe 927 MSR_IA32_TSCDEADLINE,
043405e1 928 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 929 MSR_IA32_MCG_STATUS,
930 MSR_IA32_MCG_CTL,
043405e1
CO		 931};
932
384bb783 933bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 934{
b69e8cae 935 if (efer & efer_reserved_bits)
384bb783 936 return false;
15c4a640 937
1b2fd70c
AG		 938 if (efer & EFER_FFXSR) {
939 struct kvm_cpuid_entry2 *feat;
940
941 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 942 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 943 return false;
1b2fd70c
AG		 944 }
945
d8017474
AG		 946 if (efer & EFER_SVME) {
947 struct kvm_cpuid_entry2 *feat;
948
949 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 950 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 951 return false;
d8017474
AG		 952 }
953
384bb783
JK		 954 return true;
955}
956EXPORT_SYMBOL_GPL(kvm_valid_efer);
957
958static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
959{
960 u64 old_efer = vcpu->arch.efer;
961
962 if (!kvm_valid_efer(vcpu, efer))
963 return 1;
964
965 if (is_paging(vcpu)
966 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
967 return 1;
968
15c4a640 969 efer &= ~EFER_LMA;
f6801dff 970 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 971
a3d204e2
SY		 972 kvm_x86_ops->set_efer(vcpu, efer);
973
aad82703
SY		 974 /* Update reserved bits */
975 if ((efer ^ old_efer) & EFER_NX)
976 kvm_mmu_reset_context(vcpu);
977
b69e8cae 978 return 0;
15c4a640
CO		 979}
980
f2b4b7dd
JR		 981void kvm_enable_efer_bits(u64 mask)
982{
983 efer_reserved_bits &= ~mask;
984}
985EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
986
987
15c4a640
CO		 988/*
989 * Writes msr value into into the appropriate "register".
990 * Returns 0 on success, non-0 otherwise.
991 * Assumes vcpu_load() was already called.
992 */
8fe8ab46 993int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 994{
8fe8ab46 995 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 996}
997
313a3dc7
CO		 998/*
999 * Adapt set_msr() to msr_io()'s calling convention
1000 */
1001static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1002{
8fe8ab46
WA		 1003 struct msr_data msr;
1004
1005 msr.data = *data;
1006 msr.index = index;
1007 msr.host_initiated = true;
1008 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1009}
1010
16e8d74d
MT		 1011#ifdef CONFIG_X86_64
1012struct pvclock_gtod_data {
1013 seqcount_t seq;
1014
1015 struct { /* extract of a clocksource struct */
1016 int vclock_mode;
1017 cycle_t cycle_last;
1018 cycle_t mask;
1019 u32 mult;
1020 u32 shift;
1021 } clock;
1022
cbcf2dd3
TG		 1023 u64 boot_ns;
1024 u64 nsec_base;
16e8d74d
MT		 1025};
1026
1027static struct pvclock_gtod_data pvclock_gtod_data;
1028
1029static void update_pvclock_gtod(struct timekeeper *tk)
1030{
1031 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1032 u64 boot_ns;
1033
d28ede83 1034 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
16e8d74d
MT		 1035
1036 write_seqcount_begin(&vdata->seq);
1037
1038 /* copy pvclock gtod data */
d28ede83
TG		 1039 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1040 vdata->clock.cycle_last = tk->tkr.cycle_last;
1041 vdata->clock.mask = tk->tkr.mask;
1042 vdata->clock.mult = tk->tkr.mult;
1043 vdata->clock.shift = tk->tkr.shift;
16e8d74d 1044
cbcf2dd3 1045 vdata->boot_ns = boot_ns;
d28ede83 1046 vdata->nsec_base = tk->tkr.xtime_nsec;
16e8d74d
MT		 1047
1048 write_seqcount_end(&vdata->seq);
1049}
1050#endif
1051
1052
18068523
GOC		 1053static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1054{
9ed3c444
AK		 1055 int version;
1056 int r;
50d0a0f9 1057 struct pvclock_wall_clock wc;
923de3cf 1058 struct timespec boot;
18068523
GOC		 1059
1060 if (!wall_clock)
1061 return;
1062
9ed3c444
AK		 1063 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1064 if (r)
1065 return;
1066
1067 if (version & 1)
1068 ++version; /* first time write, random junk */
1069
1070 ++version;
18068523 1071
18068523
GOC		 1072 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1073
50d0a0f9
GH		 1074 /*
1075 * The guest calculates current wall clock time by adding
34c238a1 1076 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1077 * wall clock specified here. guest system time equals host
1078 * system time for us, thus we must fill in host boot time here.
1079 */
923de3cf 1080 getboottime(&boot);
50d0a0f9 1081
4b648665
BR		 1082 if (kvm->arch.kvmclock_offset) {
1083 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1084 boot = timespec_sub(boot, ts);
1085 }
50d0a0f9
GH		 1086 wc.sec = boot.tv_sec;
1087 wc.nsec = boot.tv_nsec;
1088 wc.version = version;
18068523
GOC		 1089
1090 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1091
1092 version++;
1093 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1094}
1095
50d0a0f9
GH		 1096static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1097{
1098 uint32_t quotient, remainder;
1099
1100 /* Don't try to replace with do_div(), this one calculates
1101 * "(dividend << 32) / divisor" */
1102 __asm__ ( "divl %4"
1103 : "=a" (quotient), "=d" (remainder)
1104 : "0" (0), "1" (dividend), "r" (divisor) );
1105 return quotient;
1106}
1107
5f4e3f88
ZA		 1108static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1109 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1110{
5f4e3f88 1111 uint64_t scaled64;
50d0a0f9
GH		 1112 int32_t shift = 0;
1113 uint64_t tps64;
1114 uint32_t tps32;
1115
5f4e3f88
ZA		 1116 tps64 = base_khz * 1000LL;
1117 scaled64 = scaled_khz * 1000LL;
50933623 1118 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1119 tps64 >>= 1;
1120 shift--;
1121 }
1122
1123 tps32 = (uint32_t)tps64;
50933623
JK		 1124 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1125 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1126 scaled64 >>= 1;
1127 else
1128 tps32 <<= 1;
50d0a0f9
GH		 1129 shift++;
1130 }
1131
5f4e3f88
ZA		 1132 *pshift = shift;
1133 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1134
5f4e3f88
ZA		 1135 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1136 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1137}
1138
759379dd
ZA		 1139static inline u64 get_kernel_ns(void)
1140{
bb0b5812 1141 return ktime_get_boot_ns();
50d0a0f9
GH		 1142}
1143
d828199e 1144#ifdef CONFIG_X86_64
16e8d74d 1145static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1146#endif
16e8d74d 1147
c8076604 1148static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1149unsigned long max_tsc_khz;
c8076604 1150
cc578287 1151static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1152{
cc578287
ZA		 1153 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1154 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1155}
1156
cc578287 1157static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1158{
cc578287
ZA		 1159 u64 v = (u64)khz * (1000000 + ppm);
1160 do_div(v, 1000000);
1161 return v;
1e993611
JR		 1162}
1163
cc578287 1164static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1165{
cc578287
ZA		 1166 u32 thresh_lo, thresh_hi;
1167 int use_scaling = 0;
217fc9cf 1168
03ba32ca
MT		 1169 /* tsc_khz can be zero if TSC calibration fails */
1170 if (this_tsc_khz == 0)
1171 return;
1172
c285545f
ZA		 1173 /* Compute a scale to convert nanoseconds in TSC cycles */
1174 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1175 &vcpu->arch.virtual_tsc_shift,
1176 &vcpu->arch.virtual_tsc_mult);
1177 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1178
1179 /*
1180 * Compute the variation in TSC rate which is acceptable
1181 * within the range of tolerance and decide if the
1182 * rate being applied is within that bounds of the hardware
1183 * rate. If so, no scaling or compensation need be done.
1184 */
1185 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1186 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1187 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1188 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1189 use_scaling = 1;
1190 }
1191 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1192}
1193
1194static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1195{
e26101b1 1196 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1197 vcpu->arch.virtual_tsc_mult,
1198 vcpu->arch.virtual_tsc_shift);
e26101b1 1199 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1200 return tsc;
1201}
1202
b48aa97e
MT		 1203void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1204{
1205#ifdef CONFIG_X86_64
1206 bool vcpus_matched;
1207 bool do_request = false;
1208 struct kvm_arch *ka = &vcpu->kvm->arch;
1209 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1210
1211 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1212 atomic_read(&vcpu->kvm->online_vcpus));
1213
1214 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1215 if (!ka->use_master_clock)
1216 do_request = 1;
1217
1218 if (!vcpus_matched && ka->use_master_clock)
1219 do_request = 1;
1220
1221 if (do_request)
1222 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1223
1224 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1225 atomic_read(&vcpu->kvm->online_vcpus),
1226 ka->use_master_clock, gtod->clock.vclock_mode);
1227#endif
1228}
1229
ba904635
WA		 1230static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1231{
1232 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1233 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1234}
1235
8fe8ab46 1236void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1237{
1238 struct kvm *kvm = vcpu->kvm;
f38e098f 1239 u64 offset, ns, elapsed;
99e3e30a 1240 unsigned long flags;
02626b6a 1241 s64 usdiff;
b48aa97e 1242 bool matched;
0d3da0d2 1243 bool already_matched;
8fe8ab46 1244 u64 data = msr->data;
99e3e30a 1245
038f8c11 1246 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1247 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1248 ns = get_kernel_ns();
f38e098f 1249 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1250
03ba32ca 1251 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1252 int faulted = 0;
1253
03ba32ca
MT		 1254 /* n.b - signed multiplication and division required */
1255 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1256#ifdef CONFIG_X86_64
03ba32ca 1257 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1258#else
03ba32ca 1259 /* do_div() only does unsigned */
8915aa27
MT		 1260 asm("1: idivl %[divisor]\n"
1261 "2: xor %%edx, %%edx\n"
1262 " movl $0, %[faulted]\n"
1263 "3:\n"
1264 ".section .fixup,\"ax\"\n"
1265 "4: movl $1, %[faulted]\n"
1266 " jmp 3b\n"
1267 ".previous\n"
1268
1269 _ASM_EXTABLE(1b, 4b)
1270
1271 : "=A"(usdiff), [faulted] "=r" (faulted)
1272 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1273
5d3cb0f6 1274#endif
03ba32ca
MT		 1275 do_div(elapsed, 1000);
1276 usdiff -= elapsed;
1277 if (usdiff < 0)
1278 usdiff = -usdiff;
8915aa27
MT		 1279
1280 /* idivl overflow => difference is larger than USEC_PER_SEC */
1281 if (faulted)
1282 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1283 } else
1284 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1285
1286 /*
5d3cb0f6
ZA		 1287 * Special case: TSC write with a small delta (1 second) of virtual
1288 * cycle time against real time is interpreted as an attempt to
1289 * synchronize the CPU.
1290 *
1291 * For a reliable TSC, we can match TSC offsets, and for an unstable
1292 * TSC, we add elapsed time in this computation. We could let the
1293 * compensation code attempt to catch up if we fall behind, but
1294 * it's better to try to match offsets from the beginning.
1295 */
02626b6a 1296 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1297 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1298 if (!check_tsc_unstable()) {
e26101b1 1299 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1300 pr_debug("kvm: matched tsc offset for %llu\n", data);
1301 } else {
857e4099 1302 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1303 data += delta;
1304 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1305 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1306 }
b48aa97e 1307 matched = true;
0d3da0d2 1308 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1309 } else {
1310 /*
1311 * We split periods of matched TSC writes into generations.
1312 * For each generation, we track the original measured
1313 * nanosecond time, offset, and write, so if TSCs are in
1314 * sync, we can match exact offset, and if not, we can match
4a969980 1315 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1316 *
1317 * These values are tracked in kvm->arch.cur_xxx variables.
1318 */
1319 kvm->arch.cur_tsc_generation++;
1320 kvm->arch.cur_tsc_nsec = ns;
1321 kvm->arch.cur_tsc_write = data;
1322 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1323 matched = false;
0d3da0d2 1324 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1325 kvm->arch.cur_tsc_generation, data);
f38e098f 1326 }
e26101b1
ZA		 1327
1328 /*
1329 * We also track th most recent recorded KHZ, write and time to
1330 * allow the matching interval to be extended at each write.
1331 */
f38e098f
ZA		 1332 kvm->arch.last_tsc_nsec = ns;
1333 kvm->arch.last_tsc_write = data;
5d3cb0f6 1334 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1335
b183aa58 1336 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1337
1338 /* Keep track of which generation this VCPU has synchronized to */
1339 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1340 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1341 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1342
ba904635
WA		 1343 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1344 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1345 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1346 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1347
1348 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1349 if (!matched) {
b48aa97e 1350 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1351 } else if (!already_matched) {
1352 kvm->arch.nr_vcpus_matched_tsc++;
1353 }
b48aa97e
MT		 1354
1355 kvm_track_tsc_matching(vcpu);
1356 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1357}
e26101b1 1358
99e3e30a
ZA		 1359EXPORT_SYMBOL_GPL(kvm_write_tsc);
1360
d828199e
MT		 1361#ifdef CONFIG_X86_64
1362
1363static cycle_t read_tsc(void)
1364{
1365 cycle_t ret;
1366 u64 last;
1367
1368 /*
1369 * Empirically, a fence (of type that depends on the CPU)
1370 * before rdtsc is enough to ensure that rdtsc is ordered
1371 * with respect to loads. The various CPU manuals are unclear
1372 * as to whether rdtsc can be reordered with later loads,
1373 * but no one has ever seen it happen.
1374 */
1375 rdtsc_barrier();
1376 ret = (cycle_t)vget_cycles();
1377
1378 last = pvclock_gtod_data.clock.cycle_last;
1379
1380 if (likely(ret >= last))
1381 return ret;
1382
1383 /*
1384 * GCC likes to generate cmov here, but this branch is extremely
1385 * predictable (it's just a funciton of time and the likely is
1386 * very likely) and there's a data dependence, so force GCC
1387 * to generate a branch instead. I don't barrier() because
1388 * we don't actually need a barrier, and if this function
1389 * ever gets inlined it will generate worse code.
1390 */
1391 asm volatile ("");
1392 return last;
1393}
1394
1395static inline u64 vgettsc(cycle_t *cycle_now)
1396{
1397 long v;
1398 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1399
1400 *cycle_now = read_tsc();
1401
1402 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1403 return v * gtod->clock.mult;
1404}
1405
cbcf2dd3 1406static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1407{
cbcf2dd3 1408 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1409 unsigned long seq;
d828199e 1410 int mode;
cbcf2dd3 1411 u64 ns;
d828199e 1412
d828199e
MT		 1413 do {
1414 seq = read_seqcount_begin(&gtod->seq);
1415 mode = gtod->clock.vclock_mode;
cbcf2dd3 1416 ns = gtod->nsec_base;
d828199e
MT		 1417 ns += vgettsc(cycle_now);
1418 ns >>= gtod->clock.shift;
cbcf2dd3 1419 ns += gtod->boot_ns;
d828199e 1420 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1421 *t = ns;
d828199e
MT		 1422
1423 return mode;
1424}
1425
1426/* returns true if host is using tsc clocksource */
1427static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1428{
d828199e
MT		 1429 /* checked again under seqlock below */
1430 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1431 return false;
1432
cbcf2dd3 1433 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1434}
1435#endif
1436
1437/*
1438 *
b48aa97e
MT		 1439 * Assuming a stable TSC across physical CPUS, and a stable TSC
1440 * across virtual CPUs, the following condition is possible.
1441 * Each numbered line represents an event visible to both
d828199e
MT		 1442 * CPUs at the next numbered event.
1443 *
1444 * "timespecX" represents host monotonic time. "tscX" represents
1445 * RDTSC value.
1446 *
1447 * VCPU0 on CPU0 | VCPU1 on CPU1
1448 *
1449 * 1. read timespec0,tsc0
1450 * 2. | timespec1 = timespec0 + N
1451 * | tsc1 = tsc0 + M
1452 * 3. transition to guest | transition to guest
1453 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1454 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1455 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1456 *
1457 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1458 *
1459 * - ret0 < ret1
1460 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1461 * ...
1462 * - 0 < N - M => M < N
1463 *
1464 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1465 * always the case (the difference between two distinct xtime instances
1466 * might be smaller then the difference between corresponding TSC reads,
1467 * when updating guest vcpus pvclock areas).
1468 *
1469 * To avoid that problem, do not allow visibility of distinct
1470 * system_timestamp/tsc_timestamp values simultaneously: use a master
1471 * copy of host monotonic time values. Update that master copy
1472 * in lockstep.
1473 *
b48aa97e 1474 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1475 *
1476 */
1477
1478static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1479{
1480#ifdef CONFIG_X86_64
1481 struct kvm_arch *ka = &kvm->arch;
1482 int vclock_mode;
b48aa97e
MT		 1483 bool host_tsc_clocksource, vcpus_matched;
1484
1485 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1486 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1487
1488 /*
1489 * If the host uses TSC clock, then passthrough TSC as stable
1490 * to the guest.
1491 */
b48aa97e 1492 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1493 &ka->master_kernel_ns,
1494 &ka->master_cycle_now);
1495
16a96021
MT		 1496 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1497 && !backwards_tsc_observed;
b48aa97e 1498
d828199e
MT		 1499 if (ka->use_master_clock)
1500 atomic_set(&kvm_guest_has_master_clock, 1);
1501
1502 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1503 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1504 vcpus_matched);
d828199e
MT		 1505#endif
1506}
1507
2e762ff7
MT		 1508static void kvm_gen_update_masterclock(struct kvm *kvm)
1509{
1510#ifdef CONFIG_X86_64
1511 int i;
1512 struct kvm_vcpu *vcpu;
1513 struct kvm_arch *ka = &kvm->arch;
1514
1515 spin_lock(&ka->pvclock_gtod_sync_lock);
1516 kvm_make_mclock_inprogress_request(kvm);
1517 /* no guest entries from this point */
1518 pvclock_update_vm_gtod_copy(kvm);
1519
1520 kvm_for_each_vcpu(i, vcpu, kvm)
1521 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1522
1523 /* guest entries allowed */
1524 kvm_for_each_vcpu(i, vcpu, kvm)
1525 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1526
1527 spin_unlock(&ka->pvclock_gtod_sync_lock);
1528#endif
1529}
1530
34c238a1 1531static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1532{
d828199e 1533 unsigned long flags, this_tsc_khz;
18068523 1534 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1535 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1536 s64 kernel_ns;
d828199e 1537 u64 tsc_timestamp, host_tsc;
0b79459b 1538 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1539 u8 pvclock_flags;
d828199e
MT		 1540 bool use_master_clock;
1541
1542 kernel_ns = 0;
1543 host_tsc = 0;
18068523 1544
d828199e
MT		 1545 /*
1546 * If the host uses TSC clock, then passthrough TSC as stable
1547 * to the guest.
1548 */
1549 spin_lock(&ka->pvclock_gtod_sync_lock);
1550 use_master_clock = ka->use_master_clock;
1551 if (use_master_clock) {
1552 host_tsc = ka->master_cycle_now;
1553 kernel_ns = ka->master_kernel_ns;
1554 }
1555 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1556
1557 /* Keep irq disabled to prevent changes to the clock */
1558 local_irq_save(flags);
1559 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1560 if (unlikely(this_tsc_khz == 0)) {
1561 local_irq_restore(flags);
1562 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1563 return 1;
1564 }
d828199e
MT		 1565 if (!use_master_clock) {
1566 host_tsc = native_read_tsc();
1567 kernel_ns = get_kernel_ns();
1568 }
1569
1570 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1571
c285545f
ZA		 1572 /*
1573 * We may have to catch up the TSC to match elapsed wall clock
1574 * time for two reasons, even if kvmclock is used.
1575 * 1) CPU could have been running below the maximum TSC rate
1576 * 2) Broken TSC compensation resets the base at each VCPU
1577 * entry to avoid unknown leaps of TSC even when running
1578 * again on the same CPU. This may cause apparent elapsed
1579 * time to disappear, and the guest to stand still or run
1580 * very slowly.
1581 */
1582 if (vcpu->tsc_catchup) {
1583 u64 tsc = compute_guest_tsc(v, kernel_ns);
1584 if (tsc > tsc_timestamp) {
f1e2b260 1585 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1586 tsc_timestamp = tsc;
1587 }
50d0a0f9
GH		 1588 }
1589
18068523
GOC		 1590 local_irq_restore(flags);
1591
0b79459b 1592 if (!vcpu->pv_time_enabled)
c285545f 1593 return 0;
18068523 1594
e48672fa 1595 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1596 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1597 &vcpu->hv_clock.tsc_shift,
1598 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1599 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1600 }
1601
1602 /* With all the info we got, fill in the values */
1d5f066e 1603 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1604 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1605 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1606
18068523
GOC		 1607 /*
1608 * The interface expects us to write an even number signaling that the
1609 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1610 * state, we just increase by 2 at the end.
18068523 1611 */
50d0a0f9 1612 vcpu->hv_clock.version += 2;
18068523 1613
0b79459b
AH		 1614 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1615 &guest_hv_clock, sizeof(guest_hv_clock))))
1616 return 0;
78c0337a
MT		 1617
1618 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1619 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1620
1621 if (vcpu->pvclock_set_guest_stopped_request) {
1622 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1623 vcpu->pvclock_set_guest_stopped_request = false;
1624 }
1625
d828199e
MT		 1626 /* If the host uses TSC clocksource, then it is stable */
1627 if (use_master_clock)
1628 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1629
78c0337a
MT		 1630 vcpu->hv_clock.flags = pvclock_flags;
1631
0b79459b
AH		 1632 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1633 &vcpu->hv_clock,
1634 sizeof(vcpu->hv_clock));
8cfdc000 1635 return 0;
c8076604
GH		 1636}
1637
0061d53d
MT		 1638/*
1639 * kvmclock updates which are isolated to a given vcpu, such as
1640 * vcpu->cpu migration, should not allow system_timestamp from
1641 * the rest of the vcpus to remain static. Otherwise ntp frequency
1642 * correction applies to one vcpu's system_timestamp but not
1643 * the others.
1644 *
1645 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1646 * We need to rate-limit these requests though, as they can
1647 * considerably slow guests that have a large number of vcpus.
1648 * The time for a remote vcpu to update its kvmclock is bound
1649 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1650 */
1651
7e44e449
AJ		 1652#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1653
1654static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1655{
1656 int i;
7e44e449
AJ		 1657 struct delayed_work *dwork = to_delayed_work(work);
1658 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1659 kvmclock_update_work);
1660 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1661 struct kvm_vcpu *vcpu;
1662
1663 kvm_for_each_vcpu(i, vcpu, kvm) {
1664 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1665 kvm_vcpu_kick(vcpu);
1666 }
1667}
1668
7e44e449
AJ		 1669static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1670{
1671 struct kvm *kvm = v->kvm;
1672
1673 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1674 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1675 KVMCLOCK_UPDATE_DELAY);
1676}
1677
332967a3
AJ		 1678#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1679
1680static void kvmclock_sync_fn(struct work_struct *work)
1681{
1682 struct delayed_work *dwork = to_delayed_work(work);
1683 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1684 kvmclock_sync_work);
1685 struct kvm *kvm = container_of(ka, struct kvm, arch);
1686
1687 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1688 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1689 KVMCLOCK_SYNC_PERIOD);
1690}
1691
9ba075a6
AK		 1692static bool msr_mtrr_valid(unsigned msr)
1693{
1694 switch (msr) {
1695 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1696 case MSR_MTRRfix64K_00000:
1697 case MSR_MTRRfix16K_80000:
1698 case MSR_MTRRfix16K_A0000:
1699 case MSR_MTRRfix4K_C0000:
1700 case MSR_MTRRfix4K_C8000:
1701 case MSR_MTRRfix4K_D0000:
1702 case MSR_MTRRfix4K_D8000:
1703 case MSR_MTRRfix4K_E0000:
1704 case MSR_MTRRfix4K_E8000:
1705 case MSR_MTRRfix4K_F0000:
1706 case MSR_MTRRfix4K_F8000:
1707 case MSR_MTRRdefType:
1708 case MSR_IA32_CR_PAT:
1709 return true;
1710 case 0x2f8:
1711 return true;
1712 }
1713 return false;
1714}
1715
d6289b93
MT		 1716static bool valid_pat_type(unsigned t)
1717{
1718 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1719}
1720
1721static bool valid_mtrr_type(unsigned t)
1722{
1723 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1724}
1725
1726static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1727{
1728 int i;
1729
1730 if (!msr_mtrr_valid(msr))
1731 return false;
1732
1733 if (msr == MSR_IA32_CR_PAT) {
1734 for (i = 0; i < 8; i++)
1735 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1736 return false;
1737 return true;
1738 } else if (msr == MSR_MTRRdefType) {
1739 if (data & ~0xcff)
1740 return false;
1741 return valid_mtrr_type(data & 0xff);
1742 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1743 for (i = 0; i < 8 ; i++)
1744 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1745 return false;
1746 return true;
1747 }
1748
1749 /* variable MTRRs */
adfb5d27
WL		 1750 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1751
1752 if ((msr & 1) == 0)
1753 /* MTRR base */
1754 return valid_mtrr_type(data & 0xff);
1755 /* MTRR mask */
1756 return true;
d6289b93
MT		 1757}
1758
9ba075a6
AK		 1759static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1760{
0bed3b56
SY		 1761 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1762
d6289b93 1763 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1764 return 1;
1765
0bed3b56
SY		 1766 if (msr == MSR_MTRRdefType) {
1767 vcpu->arch.mtrr_state.def_type = data;
1768 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1769 } else if (msr == MSR_MTRRfix64K_00000)
1770 p[0] = data;
1771 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1772 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1773 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1774 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1775 else if (msr == MSR_IA32_CR_PAT)
1776 vcpu->arch.pat = data;
1777 else { /* Variable MTRRs */
1778 int idx, is_mtrr_mask;
1779 u64 *pt;
1780
1781 idx = (msr - 0x200) / 2;
1782 is_mtrr_mask = msr - 0x200 - 2 * idx;
1783 if (!is_mtrr_mask)
1784 pt =
1785 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1786 else
1787 pt =
1788 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1789 *pt = data;
1790 }
1791
1792 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1793 return 0;
1794}
15c4a640 1795
890ca9ae 1796static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1797{
890ca9ae
HY		 1798 u64 mcg_cap = vcpu->arch.mcg_cap;
1799 unsigned bank_num = mcg_cap & 0xff;
1800
15c4a640 1801 switch (msr) {
15c4a640 1802 case MSR_IA32_MCG_STATUS:
890ca9ae 1803 vcpu->arch.mcg_status = data;
15c4a640 1804 break;
c7ac679c 1805 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1806 if (!(mcg_cap & MCG_CTL_P))
1807 return 1;
1808 if (data != 0 && data != ~(u64)0)
1809 return -1;
1810 vcpu->arch.mcg_ctl = data;
1811 break;
1812 default:
1813 if (msr >= MSR_IA32_MC0_CTL &&
1814 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1815 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1816 /* only 0 or all 1s can be written to IA32_MCi_CTL
1817 * some Linux kernels though clear bit 10 in bank 4 to
1818 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1819 * this to avoid an uncatched #GP in the guest
1820 */
890ca9ae 1821 if ((offset & 0x3) == 0 &&
114be429 1822 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1823 return -1;
1824 vcpu->arch.mce_banks[offset] = data;
1825 break;
1826 }
1827 return 1;
1828 }
1829 return 0;
1830}
1831
ffde22ac
ES		 1832static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1833{
1834 struct kvm *kvm = vcpu->kvm;
1835 int lm = is_long_mode(vcpu);
1836 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1837 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1838 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1839 : kvm->arch.xen_hvm_config.blob_size_32;
1840 u32 page_num = data & ~PAGE_MASK;
1841 u64 page_addr = data & PAGE_MASK;
1842 u8 *page;
1843 int r;
1844
1845 r = -E2BIG;
1846 if (page_num >= blob_size)
1847 goto out;
1848 r = -ENOMEM;
ff5c2c03
SL		 1849 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1850 if (IS_ERR(page)) {
1851 r = PTR_ERR(page);
ffde22ac 1852 goto out;
ff5c2c03 1853 }
ffde22ac
ES		 1854 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1855 goto out_free;
1856 r = 0;
1857out_free:
1858 kfree(page);
1859out:
1860 return r;
1861}
1862
55cd8e5a
GN		 1863static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1864{
1865 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1866}
1867
1868static bool kvm_hv_msr_partition_wide(u32 msr)
1869{
1870 bool r = false;
1871 switch (msr) {
1872 case HV_X64_MSR_GUEST_OS_ID:
1873 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1874 case HV_X64_MSR_REFERENCE_TSC:
1875 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1876 r = true;
1877 break;
1878 }
1879
1880 return r;
1881}
1882
1883static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1884{
1885 struct kvm *kvm = vcpu->kvm;
1886
1887 switch (msr) {
1888 case HV_X64_MSR_GUEST_OS_ID:
1889 kvm->arch.hv_guest_os_id = data;
1890 /* setting guest os id to zero disables hypercall page */
1891 if (!kvm->arch.hv_guest_os_id)
1892 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1893 break;
1894 case HV_X64_MSR_HYPERCALL: {
1895 u64 gfn;
1896 unsigned long addr;
1897 u8 instructions[4];
1898
1899 /* if guest os id is not set hypercall should remain disabled */
1900 if (!kvm->arch.hv_guest_os_id)
1901 break;
1902 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1903 kvm->arch.hv_hypercall = data;
1904 break;
1905 }
1906 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1907 addr = gfn_to_hva(kvm, gfn);
1908 if (kvm_is_error_hva(addr))
1909 return 1;
1910 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1911 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1912 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1913 return 1;
1914 kvm->arch.hv_hypercall = data;
b94b64c9 1915 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1916 break;
1917 }
e984097b
VR		 1918 case HV_X64_MSR_REFERENCE_TSC: {
1919 u64 gfn;
1920 HV_REFERENCE_TSC_PAGE tsc_ref;
1921 memset(&tsc_ref, 0, sizeof(tsc_ref));
1922 kvm->arch.hv_tsc_page = data;
1923 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1924 break;
1925 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1926 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1927 &tsc_ref, sizeof(tsc_ref)))
1928 return 1;
1929 mark_page_dirty(kvm, gfn);
1930 break;
1931 }
55cd8e5a 1932 default:
a737f256
CD		 1933 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1934 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1935 return 1;
1936 }
1937 return 0;
1938}
1939
1940static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1941{
10388a07
GN		 1942 switch (msr) {
1943 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1944 u64 gfn;
10388a07 1945 unsigned long addr;
55cd8e5a 1946
10388a07
GN		 1947 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1948 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1949 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1950 return 1;
10388a07
GN		 1951 break;
1952 }
b3af1e88
VR		 1953 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1954 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1955 if (kvm_is_error_hva(addr))
1956 return 1;
8b0cedff 1957 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1958 return 1;
1959 vcpu->arch.hv_vapic = data;
b3af1e88 1960 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 1961 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1962 return 1;
10388a07
GN		 1963 break;
1964 }
1965 case HV_X64_MSR_EOI:
1966 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1967 case HV_X64_MSR_ICR:
1968 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1969 case HV_X64_MSR_TPR:
1970 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1971 default:
a737f256
CD		 1972 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1973 "data 0x%llx\n", msr, data);
10388a07
GN		 1974 return 1;
1975 }
1976
1977 return 0;
55cd8e5a
GN		 1978}
1979
344d9588
GN		 1980static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1981{
1982 gpa_t gpa = data & ~0x3f;
1983
4a969980 1984 /* Bits 2:5 are reserved, Should be zero */
6adba527 1985 if (data & 0x3c)
344d9588
GN		 1986 return 1;
1987
1988 vcpu->arch.apf.msr_val = data;
1989
1990 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1991 kvm_clear_async_pf_completion_queue(vcpu);
1992 kvm_async_pf_hash_reset(vcpu);
1993 return 0;
1994 }
1995
8f964525
AH		 1996 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1997 sizeof(u32)))
344d9588
GN		 1998 return 1;
1999
6adba527 2000 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2001 kvm_async_pf_wakeup_all(vcpu);
2002 return 0;
2003}
2004
12f9a48f
GC		 2005static void kvmclock_reset(struct kvm_vcpu *vcpu)
2006{
0b79459b 2007 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2008}
2009
c9aaa895
GC		 2010static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2011{
2012 u64 delta;
2013
2014 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2015 return;
2016
2017 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2018 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2019 vcpu->arch.st.accum_steal = delta;
2020}
2021
2022static void record_steal_time(struct kvm_vcpu *vcpu)
2023{
2024 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2025 return;
2026
2027 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2028 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2029 return;
2030
2031 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2032 vcpu->arch.st.steal.version += 2;
2033 vcpu->arch.st.accum_steal = 0;
2034
2035 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2036 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2037}
2038
8fe8ab46 2039int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2040{
5753785f 2041 bool pr = false;
8fe8ab46
WA		 2042 u32 msr = msr_info->index;
2043 u64 data = msr_info->data;
5753785f 2044
15c4a640 2045 switch (msr) {
2e32b719
BP		 2046 case MSR_AMD64_NB_CFG:
2047 case MSR_IA32_UCODE_REV:
2048 case MSR_IA32_UCODE_WRITE:
2049 case MSR_VM_HSAVE_PA:
2050 case MSR_AMD64_PATCH_LOADER:
2051 case MSR_AMD64_BU_CFG2:
2052 break;
2053
15c4a640 2054 case MSR_EFER:
b69e8cae 2055 return set_efer(vcpu, data);
8f1589d9
AP		 2056 case MSR_K7_HWCR:
2057 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2058 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2059 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2060 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2061 if (data != 0) {
a737f256
CD		 2062 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2063 data);
8f1589d9
AP		 2064 return 1;
2065 }
15c4a640 2066 break;
f7c6d140
AP		 2067 case MSR_FAM10H_MMIO_CONF_BASE:
2068 if (data != 0) {
a737f256
CD		 2069 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2070 "0x%llx\n", data);
f7c6d140
AP		 2071 return 1;
2072 }
15c4a640 2073 break;
b5e2fec0
AG		 2074 case MSR_IA32_DEBUGCTLMSR:
2075 if (!data) {
2076 /* We support the non-activated case already */
2077 break;
2078 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2079 /* Values other than LBR and BTF are vendor-specific,
2080 thus reserved and should throw a #GP */
2081 return 1;
2082 }
a737f256
CD		 2083 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2084 __func__, data);
b5e2fec0 2085 break;
9ba075a6
AK		 2086 case 0x200 ... 0x2ff:
2087 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2088 case MSR_IA32_APICBASE:
58cb628d 2089 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2090 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2091 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2092 case MSR_IA32_TSCDEADLINE:
2093 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2094 break;
ba904635
WA		 2095 case MSR_IA32_TSC_ADJUST:
2096 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2097 if (!msr_info->host_initiated) {
2098 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2099 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2100 }
2101 vcpu->arch.ia32_tsc_adjust_msr = data;
2102 }
2103 break;
15c4a640 2104 case MSR_IA32_MISC_ENABLE:
ad312c7c 2105 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2106 break;
11c6bffa 2107 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2108 case MSR_KVM_WALL_CLOCK:
2109 vcpu->kvm->arch.wall_clock = data;
2110 kvm_write_wall_clock(vcpu->kvm, data);
2111 break;
11c6bffa 2112 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2113 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2114 u64 gpa_offset;
12f9a48f 2115 kvmclock_reset(vcpu);
18068523
GOC		 2116
2117 vcpu->arch.time = data;
0061d53d 2118 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2119
2120 /* we verify if the enable bit is set... */
2121 if (!(data & 1))
2122 break;
2123
0b79459b 2124 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2125
0b79459b 2126 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2127 &vcpu->arch.pv_time, data & ~1ULL,
2128 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2129 vcpu->arch.pv_time_enabled = false;
2130 else
2131 vcpu->arch.pv_time_enabled = true;
32cad84f 2132
18068523
GOC		 2133 break;
2134 }
344d9588
GN		 2135 case MSR_KVM_ASYNC_PF_EN:
2136 if (kvm_pv_enable_async_pf(vcpu, data))
2137 return 1;
2138 break;
c9aaa895
GC		 2139 case MSR_KVM_STEAL_TIME:
2140
2141 if (unlikely(!sched_info_on()))
2142 return 1;
2143
2144 if (data & KVM_STEAL_RESERVED_MASK)
2145 return 1;
2146
2147 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2148 data & KVM_STEAL_VALID_BITS,
2149 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2150 return 1;
2151
2152 vcpu->arch.st.msr_val = data;
2153
2154 if (!(data & KVM_MSR_ENABLED))
2155 break;
2156
2157 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2158
2159 preempt_disable();
2160 accumulate_steal_time(vcpu);
2161 preempt_enable();
2162
2163 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2164
2165 break;
ae7a2a3f
MT		 2166 case MSR_KVM_PV_EOI_EN:
2167 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2168 return 1;
2169 break;
c9aaa895 2170
890ca9ae
HY		 2171 case MSR_IA32_MCG_CTL:
2172 case MSR_IA32_MCG_STATUS:
2173 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2174 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2175
2176 /* Performance counters are not protected by a CPUID bit,
2177 * so we should check all of them in the generic path for the sake of
2178 * cross vendor migration.
2179 * Writing a zero into the event select MSRs disables them,
2180 * which we perfectly emulate ;-). Any other value should be at least
2181 * reported, some guests depend on them.
2182 */
71db6023
AP		 2183 case MSR_K7_EVNTSEL0:
2184 case MSR_K7_EVNTSEL1:
2185 case MSR_K7_EVNTSEL2:
2186 case MSR_K7_EVNTSEL3:
2187 if (data != 0)
a737f256
CD		 2188 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2189 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2190 break;
2191 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2192 * so we ignore writes to make it happy.
2193 */
71db6023
AP		 2194 case MSR_K7_PERFCTR0:
2195 case MSR_K7_PERFCTR1:
2196 case MSR_K7_PERFCTR2:
2197 case MSR_K7_PERFCTR3:
a737f256
CD		 2198 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2199 "0x%x data 0x%llx\n", msr, data);
71db6023 2200 break;
5753785f
GN		 2201 case MSR_P6_PERFCTR0:
2202 case MSR_P6_PERFCTR1:
2203 pr = true;
2204 case MSR_P6_EVNTSEL0:
2205 case MSR_P6_EVNTSEL1:
2206 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2207 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2208
2209 if (pr || data != 0)
a737f256
CD		 2210 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2211 "0x%x data 0x%llx\n", msr, data);
5753785f 2212 break;
84e0cefa
JS		 2213 case MSR_K7_CLK_CTL:
2214 /*
2215 * Ignore all writes to this no longer documented MSR.
2216 * Writes are only relevant for old K7 processors,
2217 * all pre-dating SVM, but a recommended workaround from
4a969980 2218 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2219 * affected processor models on the command line, hence
2220 * the need to ignore the workaround.
2221 */
2222 break;
55cd8e5a
GN		 2223 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2224 if (kvm_hv_msr_partition_wide(msr)) {
2225 int r;
2226 mutex_lock(&vcpu->kvm->lock);
2227 r = set_msr_hyperv_pw(vcpu, msr, data);
2228 mutex_unlock(&vcpu->kvm->lock);
2229 return r;
2230 } else
2231 return set_msr_hyperv(vcpu, msr, data);
2232 break;
91c9c3ed 2233 case MSR_IA32_BBL_CR_CTL3:
2234 /* Drop writes to this legacy MSR -- see rdmsr
2235 * counterpart for further detail.
2236 */
a737f256 2237 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2238 break;
2b036c6b
BO		 2239 case MSR_AMD64_OSVW_ID_LENGTH:
2240 if (!guest_cpuid_has_osvw(vcpu))
2241 return 1;
2242 vcpu->arch.osvw.length = data;
2243 break;
2244 case MSR_AMD64_OSVW_STATUS:
2245 if (!guest_cpuid_has_osvw(vcpu))
2246 return 1;
2247 vcpu->arch.osvw.status = data;
2248 break;
15c4a640 2249 default:
ffde22ac
ES		 2250 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2251 return xen_hvm_config(vcpu, data);
f5132b01 2252 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2253 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2254 if (!ignore_msrs) {
a737f256
CD		 2255 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2256 msr, data);
ed85c068
AP		 2257 return 1;
2258 } else {
a737f256
CD		 2259 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2260 msr, data);
ed85c068
AP		 2261 break;
2262 }
15c4a640
CO		 2263 }
2264 return 0;
2265}
2266EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2267
2268
2269/*
2270 * Reads an msr value (of 'msr_index') into 'pdata'.
2271 * Returns 0 on success, non-0 otherwise.
2272 * Assumes vcpu_load() was already called.
2273 */
2274int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2275{
2276 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2277}
2278
9ba075a6
AK		 2279static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2280{
0bed3b56
SY		 2281 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2282
9ba075a6
AK		 2283 if (!msr_mtrr_valid(msr))
2284 return 1;
2285
0bed3b56
SY		 2286 if (msr == MSR_MTRRdefType)
2287 *pdata = vcpu->arch.mtrr_state.def_type +
2288 (vcpu->arch.mtrr_state.enabled << 10);
2289 else if (msr == MSR_MTRRfix64K_00000)
2290 *pdata = p[0];
2291 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2292 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2293 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2294 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2295 else if (msr == MSR_IA32_CR_PAT)
2296 *pdata = vcpu->arch.pat;
2297 else { /* Variable MTRRs */
2298 int idx, is_mtrr_mask;
2299 u64 *pt;
2300
2301 idx = (msr - 0x200) / 2;
2302 is_mtrr_mask = msr - 0x200 - 2 * idx;
2303 if (!is_mtrr_mask)
2304 pt =
2305 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2306 else
2307 pt =
2308 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2309 *pdata = *pt;
2310 }
2311
9ba075a6
AK		 2312 return 0;
2313}
2314
890ca9ae 2315static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2316{
2317 u64 data;
890ca9ae
HY		 2318 u64 mcg_cap = vcpu->arch.mcg_cap;
2319 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2320
2321 switch (msr) {
15c4a640
CO		 2322 case MSR_IA32_P5_MC_ADDR:
2323 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2324 data = 0;
2325 break;
15c4a640 2326 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2327 data = vcpu->arch.mcg_cap;
2328 break;
c7ac679c 2329 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2330 if (!(mcg_cap & MCG_CTL_P))
2331 return 1;
2332 data = vcpu->arch.mcg_ctl;
2333 break;
2334 case MSR_IA32_MCG_STATUS:
2335 data = vcpu->arch.mcg_status;
2336 break;
2337 default:
2338 if (msr >= MSR_IA32_MC0_CTL &&
2339 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2340 u32 offset = msr - MSR_IA32_MC0_CTL;
2341 data = vcpu->arch.mce_banks[offset];
2342 break;
2343 }
2344 return 1;
2345 }
2346 *pdata = data;
2347 return 0;
2348}
2349
55cd8e5a
GN		 2350static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2351{
2352 u64 data = 0;
2353 struct kvm *kvm = vcpu->kvm;
2354
2355 switch (msr) {
2356 case HV_X64_MSR_GUEST_OS_ID:
2357 data = kvm->arch.hv_guest_os_id;
2358 break;
2359 case HV_X64_MSR_HYPERCALL:
2360 data = kvm->arch.hv_hypercall;
2361 break;
e984097b
VR		 2362 case HV_X64_MSR_TIME_REF_COUNT: {
2363 data =
2364 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2365 break;
2366 }
2367 case HV_X64_MSR_REFERENCE_TSC:
2368 data = kvm->arch.hv_tsc_page;
2369 break;
55cd8e5a 2370 default:
a737f256 2371 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2372 return 1;
2373 }
2374
2375 *pdata = data;
2376 return 0;
2377}
2378
2379static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2380{
2381 u64 data = 0;
2382
2383 switch (msr) {
2384 case HV_X64_MSR_VP_INDEX: {
2385 int r;
2386 struct kvm_vcpu *v;
684851a1
TY		 2387 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2388 if (v == vcpu) {
55cd8e5a 2389 data = r;
684851a1
TY		 2390 break;
2391 }
2392 }
55cd8e5a
GN		 2393 break;
2394 }
10388a07
GN		 2395 case HV_X64_MSR_EOI:
2396 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2397 case HV_X64_MSR_ICR:
2398 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2399 case HV_X64_MSR_TPR:
2400 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2401 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2402 data = vcpu->arch.hv_vapic;
2403 break;
55cd8e5a 2404 default:
a737f256 2405 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2406 return 1;
2407 }
2408 *pdata = data;
2409 return 0;
2410}
2411
890ca9ae
HY		 2412int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2413{
2414 u64 data;
2415
2416 switch (msr) {
890ca9ae 2417 case MSR_IA32_PLATFORM_ID:
15c4a640 2418 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2419 case MSR_IA32_DEBUGCTLMSR:
2420 case MSR_IA32_LASTBRANCHFROMIP:
2421 case MSR_IA32_LASTBRANCHTOIP:
2422 case MSR_IA32_LASTINTFROMIP:
2423 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2424 case MSR_K8_SYSCFG:
2425 case MSR_K7_HWCR:
61a6bd67 2426 case MSR_VM_HSAVE_PA:
9e699624 2427 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2428 case MSR_K7_EVNTSEL1:
2429 case MSR_K7_EVNTSEL2:
2430 case MSR_K7_EVNTSEL3:
1f3ee616 2431 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2432 case MSR_K7_PERFCTR1:
2433 case MSR_K7_PERFCTR2:
2434 case MSR_K7_PERFCTR3:
1fdbd48c 2435 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2436 case MSR_AMD64_NB_CFG:
f7c6d140 2437 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2438 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2439 data = 0;
2440 break;
5753785f
GN		 2441 case MSR_P6_PERFCTR0:
2442 case MSR_P6_PERFCTR1:
2443 case MSR_P6_EVNTSEL0:
2444 case MSR_P6_EVNTSEL1:
2445 if (kvm_pmu_msr(vcpu, msr))
2446 return kvm_pmu_get_msr(vcpu, msr, pdata);
2447 data = 0;
2448 break;
742bc670
MT		 2449 case MSR_IA32_UCODE_REV:
2450 data = 0x100000000ULL;
2451 break;
9ba075a6
AK		 2452 case MSR_MTRRcap:
2453 data = 0x500 | KVM_NR_VAR_MTRR;
2454 break;
2455 case 0x200 ... 0x2ff:
2456 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2457 case 0xcd: /* fsb frequency */
2458 data = 3;
2459 break;
7b914098
JS		 2460 /*
2461 * MSR_EBC_FREQUENCY_ID
2462 * Conservative value valid for even the basic CPU models.
2463 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2464 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2465 * and 266MHz for model 3, or 4. Set Core Clock
2466 * Frequency to System Bus Frequency Ratio to 1 (bits
2467 * 31:24) even though these are only valid for CPU
2468 * models > 2, however guests may end up dividing or
2469 * multiplying by zero otherwise.
2470 */
2471 case MSR_EBC_FREQUENCY_ID:
2472 data = 1 << 24;
2473 break;
15c4a640
CO		 2474 case MSR_IA32_APICBASE:
2475 data = kvm_get_apic_base(vcpu);
2476 break;
0105d1a5
GN		 2477 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2478 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2479 break;
a3e06bbe
LJ		 2480 case MSR_IA32_TSCDEADLINE:
2481 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2482 break;
ba904635
WA		 2483 case MSR_IA32_TSC_ADJUST:
2484 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2485 break;
15c4a640 2486 case MSR_IA32_MISC_ENABLE:
ad312c7c 2487 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2488 break;
847f0ad8
AG		 2489 case MSR_IA32_PERF_STATUS:
2490 /* TSC increment by tick */
2491 data = 1000ULL;
2492 /* CPU multiplier */
2493 data |= (((uint64_t)4ULL) << 40);
2494 break;
15c4a640 2495 case MSR_EFER:
f6801dff 2496 data = vcpu->arch.efer;
15c4a640 2497 break;
18068523 2498 case MSR_KVM_WALL_CLOCK:
11c6bffa 2499 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2500 data = vcpu->kvm->arch.wall_clock;
2501 break;
2502 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2503 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2504 data = vcpu->arch.time;
2505 break;
344d9588
GN		 2506 case MSR_KVM_ASYNC_PF_EN:
2507 data = vcpu->arch.apf.msr_val;
2508 break;
c9aaa895
GC		 2509 case MSR_KVM_STEAL_TIME:
2510 data = vcpu->arch.st.msr_val;
2511 break;
1d92128f
MT		 2512 case MSR_KVM_PV_EOI_EN:
2513 data = vcpu->arch.pv_eoi.msr_val;
2514 break;
890ca9ae
HY		 2515 case MSR_IA32_P5_MC_ADDR:
2516 case MSR_IA32_P5_MC_TYPE:
2517 case MSR_IA32_MCG_CAP:
2518 case MSR_IA32_MCG_CTL:
2519 case MSR_IA32_MCG_STATUS:
2520 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2521 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2522 case MSR_K7_CLK_CTL:
2523 /*
2524 * Provide expected ramp-up count for K7. All other
2525 * are set to zero, indicating minimum divisors for
2526 * every field.
2527 *
2528 * This prevents guest kernels on AMD host with CPU
2529 * type 6, model 8 and higher from exploding due to
2530 * the rdmsr failing.
2531 */
2532 data = 0x20000000;
2533 break;
55cd8e5a
GN		 2534 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2535 if (kvm_hv_msr_partition_wide(msr)) {
2536 int r;
2537 mutex_lock(&vcpu->kvm->lock);
2538 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2539 mutex_unlock(&vcpu->kvm->lock);
2540 return r;
2541 } else
2542 return get_msr_hyperv(vcpu, msr, pdata);
2543 break;
91c9c3ed 2544 case MSR_IA32_BBL_CR_CTL3:
2545 /* This legacy MSR exists but isn't fully documented in current
2546 * silicon. It is however accessed by winxp in very narrow
2547 * scenarios where it sets bit #19, itself documented as
2548 * a "reserved" bit. Best effort attempt to source coherent
2549 * read data here should the balance of the register be
2550 * interpreted by the guest:
2551 *
2552 * L2 cache control register 3: 64GB range, 256KB size,
2553 * enabled, latency 0x1, configured
2554 */
2555 data = 0xbe702111;
2556 break;
2b036c6b
BO		 2557 case MSR_AMD64_OSVW_ID_LENGTH:
2558 if (!guest_cpuid_has_osvw(vcpu))
2559 return 1;
2560 data = vcpu->arch.osvw.length;
2561 break;
2562 case MSR_AMD64_OSVW_STATUS:
2563 if (!guest_cpuid_has_osvw(vcpu))
2564 return 1;
2565 data = vcpu->arch.osvw.status;
2566 break;
15c4a640 2567 default:
f5132b01
GN		 2568 if (kvm_pmu_msr(vcpu, msr))
2569 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2570 if (!ignore_msrs) {
a737f256 2571 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2572 return 1;
2573 } else {
a737f256 2574 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2575 data = 0;
2576 }
2577 break;
15c4a640
CO		 2578 }
2579 *pdata = data;
2580 return 0;
2581}
2582EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2583
313a3dc7
CO		 2584/*
2585 * Read or write a bunch of msrs. All parameters are kernel addresses.
2586 *
2587 * @return number of msrs set successfully.
2588 */
2589static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2590 struct kvm_msr_entry *entries,
2591 int (*do_msr)(struct kvm_vcpu *vcpu,
2592 unsigned index, u64 *data))
2593{
f656ce01 2594 int i, idx;
313a3dc7 2595
f656ce01 2596 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2597 for (i = 0; i < msrs->nmsrs; ++i)
2598 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2599 break;
f656ce01 2600 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2601
313a3dc7
CO		 2602 return i;
2603}
2604
2605/*
2606 * Read or write a bunch of msrs. Parameters are user addresses.
2607 *
2608 * @return number of msrs set successfully.
2609 */
2610static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2611 int (*do_msr)(struct kvm_vcpu *vcpu,
2612 unsigned index, u64 *data),
2613 int writeback)
2614{
2615 struct kvm_msrs msrs;
2616 struct kvm_msr_entry *entries;
2617 int r, n;
2618 unsigned size;
2619
2620 r = -EFAULT;
2621 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2622 goto out;
2623
2624 r = -E2BIG;
2625 if (msrs.nmsrs >= MAX_IO_MSRS)
2626 goto out;
2627
313a3dc7 2628 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2629 entries = memdup_user(user_msrs->entries, size);
2630 if (IS_ERR(entries)) {
2631 r = PTR_ERR(entries);
313a3dc7 2632 goto out;
ff5c2c03 2633 }
313a3dc7
CO		 2634
2635 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2636 if (r < 0)
2637 goto out_free;
2638
2639 r = -EFAULT;
2640 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2641 goto out_free;
2642
2643 r = n;
2644
2645out_free:
7a73c028 2646 kfree(entries);
313a3dc7
CO		 2647out:
2648 return r;
2649}
2650
784aa3d7 2651int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2652{
2653 int r;
2654
2655 switch (ext) {
2656 case KVM_CAP_IRQCHIP:
2657 case KVM_CAP_HLT:
2658 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2659 case KVM_CAP_SET_TSS_ADDR:
07716717 2660 case KVM_CAP_EXT_CPUID:
9c15bb1d 2661 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2662 case KVM_CAP_CLOCKSOURCE:
7837699f 2663 case KVM_CAP_PIT:
a28e4f5a 2664 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2665 case KVM_CAP_MP_STATE:
ed848624 2666 case KVM_CAP_SYNC_MMU:
a355c85c 2667 case KVM_CAP_USER_NMI:
52d939a0 2668 case KVM_CAP_REINJECT_CONTROL:
4925663a 2669 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2670 case KVM_CAP_IRQFD:
d34e6b17 2671 case KVM_CAP_IOEVENTFD:
f848a5a8 2672 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2673 case KVM_CAP_PIT2:
e9f42757 2674 case KVM_CAP_PIT_STATE2:
b927a3ce 2675 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2676 case KVM_CAP_XEN_HVM:
afbcf7ab 2677 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2678 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2679 case KVM_CAP_HYPERV:
10388a07 2680 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2681 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2682 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2683 case KVM_CAP_DEBUGREGS:
d2be1651 2684 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2685 case KVM_CAP_XSAVE:
344d9588 2686 case KVM_CAP_ASYNC_PF:
92a1f12d 2687 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2688 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2689 case KVM_CAP_READONLY_MEM:
5f66b620 2690 case KVM_CAP_HYPERV_TIME:
100943c5 2691 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2692#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2693 case KVM_CAP_ASSIGN_DEV_IRQ:
2694 case KVM_CAP_PCI_2_3:
2695#endif
018d00d2
ZX		 2696 r = 1;
2697 break;
542472b5
LV		 2698 case KVM_CAP_COALESCED_MMIO:
2699 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2700 break;
774ead3a
AK		 2701 case KVM_CAP_VAPIC:
2702 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2703 break;
f725230a 2704 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2705 r = KVM_SOFT_MAX_VCPUS;
2706 break;
2707 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2708 r = KVM_MAX_VCPUS;
2709 break;
a988b910 2710 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2711 r = KVM_USER_MEM_SLOTS;
a988b910 2712 break;
a68a6a72
MT		 2713 case KVM_CAP_PV_MMU: /* obsolete */
2714 r = 0;
2f333bcb 2715 break;
4cee4b72 2716#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2717 case KVM_CAP_IOMMU:
a1b60c1c 2718 r = iommu_present(&pci_bus_type);
62c476c7 2719 break;
4cee4b72 2720#endif
890ca9ae
HY		 2721 case KVM_CAP_MCE:
2722 r = KVM_MAX_MCE_BANKS;
2723 break;
2d5b5a66
SY		 2724 case KVM_CAP_XCRS:
2725 r = cpu_has_xsave;
2726 break;
92a1f12d
JR		 2727 case KVM_CAP_TSC_CONTROL:
2728 r = kvm_has_tsc_control;
2729 break;
4d25a066
JK		 2730 case KVM_CAP_TSC_DEADLINE_TIMER:
2731 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2732 break;
018d00d2
ZX		 2733 default:
2734 r = 0;
2735 break;
2736 }
2737 return r;
2738
2739}
2740
043405e1
CO		 2741long kvm_arch_dev_ioctl(struct file *filp,
2742 unsigned int ioctl, unsigned long arg)
2743{
2744 void __user *argp = (void __user *)arg;
2745 long r;
2746
2747 switch (ioctl) {
2748 case KVM_GET_MSR_INDEX_LIST: {
2749 struct kvm_msr_list __user *user_msr_list = argp;
2750 struct kvm_msr_list msr_list;
2751 unsigned n;
2752
2753 r = -EFAULT;
2754 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2755 goto out;
2756 n = msr_list.nmsrs;
2757 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2758 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2759 goto out;
2760 r = -E2BIG;
e125e7b6 2761 if (n < msr_list.nmsrs)
043405e1
CO		 2762 goto out;
2763 r = -EFAULT;
2764 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2765 num_msrs_to_save * sizeof(u32)))
2766 goto out;
e125e7b6 2767 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2768 &emulated_msrs,
2769 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2770 goto out;
2771 r = 0;
2772 break;
2773 }
9c15bb1d
BP		 2774 case KVM_GET_SUPPORTED_CPUID:
2775 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2776 struct kvm_cpuid2 __user *cpuid_arg = argp;
2777 struct kvm_cpuid2 cpuid;
2778
2779 r = -EFAULT;
2780 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2781 goto out;
9c15bb1d
BP		 2782
2783 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2784 ioctl);
674eea0f
AK		 2785 if (r)
2786 goto out;
2787
2788 r = -EFAULT;
2789 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2790 goto out;
2791 r = 0;
2792 break;
2793 }
890ca9ae
HY		 2794 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2795 u64 mce_cap;
2796
2797 mce_cap = KVM_MCE_CAP_SUPPORTED;
2798 r = -EFAULT;
2799 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2800 goto out;
2801 r = 0;
2802 break;
2803 }
043405e1
CO		 2804 default:
2805 r = -EINVAL;
2806 }
2807out:
2808 return r;
2809}
2810
f5f48ee1
SY		 2811static void wbinvd_ipi(void *garbage)
2812{
2813 wbinvd();
2814}
2815
2816static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2817{
e0f0bbc5 2818 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2819}
2820
313a3dc7
CO		 2821void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2822{
f5f48ee1
SY		 2823 /* Address WBINVD may be executed by guest */
2824 if (need_emulate_wbinvd(vcpu)) {
2825 if (kvm_x86_ops->has_wbinvd_exit())
2826 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2827 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2828 smp_call_function_single(vcpu->cpu,
2829 wbinvd_ipi, NULL, 1);
2830 }
2831
313a3dc7 2832 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2833
0dd6a6ed
ZA		 2834 /* Apply any externally detected TSC adjustments (due to suspend) */
2835 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2836 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2837 vcpu->arch.tsc_offset_adjustment = 0;
2838 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2839 }
8f6055cb 2840
48434c20 2841 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2842 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2843 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2844 if (tsc_delta < 0)
2845 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2846 if (check_tsc_unstable()) {
b183aa58
ZA		 2847 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2848 vcpu->arch.last_guest_tsc);
2849 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2850 vcpu->arch.tsc_catchup = 1;
c285545f 2851 }
d98d07ca
MT		 2852 /*
2853 * On a host with synchronized TSC, there is no need to update
2854 * kvmclock on vcpu->cpu migration
2855 */
2856 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2857 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2858 if (vcpu->cpu != cpu)
2859 kvm_migrate_timers(vcpu);
e48672fa 2860 vcpu->cpu = cpu;
6b7d7e76 2861 }
c9aaa895
GC		 2862
2863 accumulate_steal_time(vcpu);
2864 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2865}
2866
2867void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2868{
02daab21 2869 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2870 kvm_put_guest_fpu(vcpu);
6f526ec5 2871 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2872}
2873
313a3dc7
CO		 2874static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2875 struct kvm_lapic_state *s)
2876{
5a71785d 2877 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2878 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2879
2880 return 0;
2881}
2882
2883static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2884 struct kvm_lapic_state *s)
2885{
64eb0620 2886 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2887 update_cr8_intercept(vcpu);
313a3dc7
CO		 2888
2889 return 0;
2890}
2891
f77bc6a4
ZX		 2892static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2893 struct kvm_interrupt *irq)
2894{
02cdb50f 2895 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2896 return -EINVAL;
2897 if (irqchip_in_kernel(vcpu->kvm))
2898 return -ENXIO;
f77bc6a4 2899
66fd3f7f 2900 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2901 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2902
f77bc6a4
ZX		 2903 return 0;
2904}
2905
c4abb7c9
JK		 2906static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2907{
c4abb7c9 2908 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2909
2910 return 0;
2911}
2912
b209749f
AK		 2913static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2914 struct kvm_tpr_access_ctl *tac)
2915{
2916 if (tac->flags)
2917 return -EINVAL;
2918 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2919 return 0;
2920}
2921
890ca9ae
HY		 2922static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2923 u64 mcg_cap)
2924{
2925 int r;
2926 unsigned bank_num = mcg_cap & 0xff, bank;
2927
2928 r = -EINVAL;
a9e38c3e 2929 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2930 goto out;
2931 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2932 goto out;
2933 r = 0;
2934 vcpu->arch.mcg_cap = mcg_cap;
2935 /* Init IA32_MCG_CTL to all 1s */
2936 if (mcg_cap & MCG_CTL_P)
2937 vcpu->arch.mcg_ctl = ~(u64)0;
2938 /* Init IA32_MCi_CTL to all 1s */
2939 for (bank = 0; bank < bank_num; bank++)
2940 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2941out:
2942 return r;
2943}
2944
2945static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2946 struct kvm_x86_mce *mce)
2947{
2948 u64 mcg_cap = vcpu->arch.mcg_cap;
2949 unsigned bank_num = mcg_cap & 0xff;
2950 u64 *banks = vcpu->arch.mce_banks;
2951
2952 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2953 return -EINVAL;
2954 /*
2955 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2956 * reporting is disabled
2957 */
2958 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2959 vcpu->arch.mcg_ctl != ~(u64)0)
2960 return 0;
2961 banks += 4 * mce->bank;
2962 /*
2963 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2964 * reporting is disabled for the bank
2965 */
2966 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2967 return 0;
2968 if (mce->status & MCI_STATUS_UC) {
2969 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2970 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2971 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2972 return 0;
2973 }
2974 if (banks[1] & MCI_STATUS_VAL)
2975 mce->status |= MCI_STATUS_OVER;
2976 banks[2] = mce->addr;
2977 banks[3] = mce->misc;
2978 vcpu->arch.mcg_status = mce->mcg_status;
2979 banks[1] = mce->status;
2980 kvm_queue_exception(vcpu, MC_VECTOR);
2981 } else if (!(banks[1] & MCI_STATUS_VAL)
2982 || !(banks[1] & MCI_STATUS_UC)) {
2983 if (banks[1] & MCI_STATUS_VAL)
2984 mce->status |= MCI_STATUS_OVER;
2985 banks[2] = mce->addr;
2986 banks[3] = mce->misc;
2987 banks[1] = mce->status;
2988 } else
2989 banks[1] |= MCI_STATUS_OVER;
2990 return 0;
2991}
2992
3cfc3092
JK		 2993static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2994 struct kvm_vcpu_events *events)
2995{
7460fb4a 2996 process_nmi(vcpu);
03b82a30
JK		 2997 events->exception.injected =
2998 vcpu->arch.exception.pending &&
2999 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3000 events->exception.nr = vcpu->arch.exception.nr;
3001 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3002 events->exception.pad = 0;
3cfc3092
JK		 3003 events->exception.error_code = vcpu->arch.exception.error_code;
3004
03b82a30
JK		 3005 events->interrupt.injected =
3006 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3007 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3008 events->interrupt.soft = 0;
37ccdcbe 3009 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3010
3011 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3012 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3013 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3014 events->nmi.pad = 0;
3cfc3092 3015
66450a21 3016 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3017
dab4b911 3018 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3019 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3020 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3021}
3022
3023static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3024 struct kvm_vcpu_events *events)
3025{
dab4b911 3026 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3027 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3028 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3029 return -EINVAL;
3030
7460fb4a 3031 process_nmi(vcpu);
3cfc3092
JK		 3032 vcpu->arch.exception.pending = events->exception.injected;
3033 vcpu->arch.exception.nr = events->exception.nr;
3034 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3035 vcpu->arch.exception.error_code = events->exception.error_code;
3036
3037 vcpu->arch.interrupt.pending = events->interrupt.injected;
3038 vcpu->arch.interrupt.nr = events->interrupt.nr;
3039 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3040 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3041 kvm_x86_ops->set_interrupt_shadow(vcpu,
3042 events->interrupt.shadow);
3cfc3092
JK		 3043
3044 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3045 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3046 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3047 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3048
66450a21
JK		 3049 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3050 kvm_vcpu_has_lapic(vcpu))
3051 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3052
3842d135
AK		 3053 kvm_make_request(KVM_REQ_EVENT, vcpu);
3054
3cfc3092
JK		 3055 return 0;
3056}
3057
a1efbe77
JK		 3058static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3059 struct kvm_debugregs *dbgregs)
3060{
73aaf249
JK		 3061 unsigned long val;
3062
a1efbe77 3063 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3064 _kvm_get_dr(vcpu, 6, &val);
3065 dbgregs->dr6 = val;
a1efbe77
JK		 3066 dbgregs->dr7 = vcpu->arch.dr7;
3067 dbgregs->flags = 0;
97e69aa6 3068 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3069}
3070
3071static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3072 struct kvm_debugregs *dbgregs)
3073{
3074 if (dbgregs->flags)
3075 return -EINVAL;
3076
a1efbe77
JK		 3077 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3078 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3079 kvm_update_dr6(vcpu);
a1efbe77 3080 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3081 kvm_update_dr7(vcpu);
a1efbe77 3082
a1efbe77
JK		 3083 return 0;
3084}
3085
2d5b5a66
SY		 3086static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3087 struct kvm_xsave *guest_xsave)
3088{
4344ee98 3089 if (cpu_has_xsave) {
2d5b5a66
SY		 3090 memcpy(guest_xsave->region,
3091 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3092 vcpu->arch.guest_xstate_size);
3093 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3094 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3095 } else {
2d5b5a66
SY		 3096 memcpy(guest_xsave->region,
3097 &vcpu->arch.guest_fpu.state->fxsave,
3098 sizeof(struct i387_fxsave_struct));
3099 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3100 XSTATE_FPSSE;
3101 }
3102}
3103
3104static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3105 struct kvm_xsave *guest_xsave)
3106{
3107 u64 xstate_bv =
3108 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3109
d7876f1b
PB		 3110 if (cpu_has_xsave) {
3111 /*
3112 * Here we allow setting states that are not present in
3113 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3114 * with old userspace.
3115 */
4ff41732 3116 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3117 return -EINVAL;
2d5b5a66 3118 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3119 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3120 } else {
2d5b5a66
SY		 3121 if (xstate_bv & ~XSTATE_FPSSE)
3122 return -EINVAL;
3123 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3124 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3125 }
3126 return 0;
3127}
3128
3129static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3130 struct kvm_xcrs *guest_xcrs)
3131{
3132 if (!cpu_has_xsave) {
3133 guest_xcrs->nr_xcrs = 0;
3134 return;
3135 }
3136
3137 guest_xcrs->nr_xcrs = 1;
3138 guest_xcrs->flags = 0;
3139 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3140 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3141}
3142
3143static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3144 struct kvm_xcrs *guest_xcrs)
3145{
3146 int i, r = 0;
3147
3148 if (!cpu_has_xsave)
3149 return -EINVAL;
3150
3151 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3152 return -EINVAL;
3153
3154 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3155 /* Only support XCR0 currently */
c67a04cb 3156 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3157 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3158 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3159 break;
3160 }
3161 if (r)
3162 r = -EINVAL;
3163 return r;
3164}
3165
1c0b28c2
EM		 3166/*
3167 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3168 * stopped by the hypervisor. This function will be called from the host only.
3169 * EINVAL is returned when the host attempts to set the flag for a guest that
3170 * does not support pv clocks.
3171 */
3172static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3173{
0b79459b 3174 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3175 return -EINVAL;
51d59c6b 3176 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3177 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3178 return 0;
3179}
3180
313a3dc7
CO		 3181long kvm_arch_vcpu_ioctl(struct file *filp,
3182 unsigned int ioctl, unsigned long arg)
3183{
3184 struct kvm_vcpu *vcpu = filp->private_data;
3185 void __user *argp = (void __user *)arg;
3186 int r;
d1ac91d8
AK		 3187 union {
3188 struct kvm_lapic_state *lapic;
3189 struct kvm_xsave *xsave;
3190 struct kvm_xcrs *xcrs;
3191 void *buffer;
3192 } u;
3193
3194 u.buffer = NULL;
313a3dc7
CO		 3195 switch (ioctl) {
3196 case KVM_GET_LAPIC: {
2204ae3c
MT		 3197 r = -EINVAL;
3198 if (!vcpu->arch.apic)
3199 goto out;
d1ac91d8 3200 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3201
b772ff36 3202 r = -ENOMEM;
d1ac91d8 3203 if (!u.lapic)
b772ff36 3204 goto out;
d1ac91d8 3205 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3206 if (r)
3207 goto out;
3208 r = -EFAULT;
d1ac91d8 3209 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3210 goto out;
3211 r = 0;
3212 break;
3213 }
3214 case KVM_SET_LAPIC: {
2204ae3c
MT		 3215 r = -EINVAL;
3216 if (!vcpu->arch.apic)
3217 goto out;
ff5c2c03 3218 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3219 if (IS_ERR(u.lapic))
3220 return PTR_ERR(u.lapic);
ff5c2c03 3221
d1ac91d8 3222 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3223 break;
3224 }
f77bc6a4
ZX		 3225 case KVM_INTERRUPT: {
3226 struct kvm_interrupt irq;
3227
3228 r = -EFAULT;
3229 if (copy_from_user(&irq, argp, sizeof irq))
3230 goto out;
3231 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3232 break;
3233 }
c4abb7c9
JK		 3234 case KVM_NMI: {
3235 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3236 break;
3237 }
313a3dc7
CO		 3238 case KVM_SET_CPUID: {
3239 struct kvm_cpuid __user *cpuid_arg = argp;
3240 struct kvm_cpuid cpuid;
3241
3242 r = -EFAULT;
3243 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3244 goto out;
3245 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3246 break;
3247 }
07716717
DK		 3248 case KVM_SET_CPUID2: {
3249 struct kvm_cpuid2 __user *cpuid_arg = argp;
3250 struct kvm_cpuid2 cpuid;
3251
3252 r = -EFAULT;
3253 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3254 goto out;
3255 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3256 cpuid_arg->entries);
07716717
DK		 3257 break;
3258 }
3259 case KVM_GET_CPUID2: {
3260 struct kvm_cpuid2 __user *cpuid_arg = argp;
3261 struct kvm_cpuid2 cpuid;
3262
3263 r = -EFAULT;
3264 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3265 goto out;
3266 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3267 cpuid_arg->entries);
07716717
DK		 3268 if (r)
3269 goto out;
3270 r = -EFAULT;
3271 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3272 goto out;
3273 r = 0;
3274 break;
3275 }
313a3dc7
CO		 3276 case KVM_GET_MSRS:
3277 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3278 break;
3279 case KVM_SET_MSRS:
3280 r = msr_io(vcpu, argp, do_set_msr, 0);
3281 break;
b209749f
AK		 3282 case KVM_TPR_ACCESS_REPORTING: {
3283 struct kvm_tpr_access_ctl tac;
3284
3285 r = -EFAULT;
3286 if (copy_from_user(&tac, argp, sizeof tac))
3287 goto out;
3288 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3289 if (r)
3290 goto out;
3291 r = -EFAULT;
3292 if (copy_to_user(argp, &tac, sizeof tac))
3293 goto out;
3294 r = 0;
3295 break;
3296 };
b93463aa
AK		 3297 case KVM_SET_VAPIC_ADDR: {
3298 struct kvm_vapic_addr va;
3299
3300 r = -EINVAL;
3301 if (!irqchip_in_kernel(vcpu->kvm))
3302 goto out;
3303 r = -EFAULT;
3304 if (copy_from_user(&va, argp, sizeof va))
3305 goto out;
fda4e2e8 3306 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3307 break;
3308 }
890ca9ae
HY		 3309 case KVM_X86_SETUP_MCE: {
3310 u64 mcg_cap;
3311
3312 r = -EFAULT;
3313 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3314 goto out;
3315 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3316 break;
3317 }
3318 case KVM_X86_SET_MCE: {
3319 struct kvm_x86_mce mce;
3320
3321 r = -EFAULT;
3322 if (copy_from_user(&mce, argp, sizeof mce))
3323 goto out;
3324 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3325 break;
3326 }
3cfc3092
JK		 3327 case KVM_GET_VCPU_EVENTS: {
3328 struct kvm_vcpu_events events;
3329
3330 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3331
3332 r = -EFAULT;
3333 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3334 break;
3335 r = 0;
3336 break;
3337 }
3338 case KVM_SET_VCPU_EVENTS: {
3339 struct kvm_vcpu_events events;
3340
3341 r = -EFAULT;
3342 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3343 break;
3344
3345 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3346 break;
3347 }
a1efbe77
JK		 3348 case KVM_GET_DEBUGREGS: {
3349 struct kvm_debugregs dbgregs;
3350
3351 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3352
3353 r = -EFAULT;
3354 if (copy_to_user(argp, &dbgregs,
3355 sizeof(struct kvm_debugregs)))
3356 break;
3357 r = 0;
3358 break;
3359 }
3360 case KVM_SET_DEBUGREGS: {
3361 struct kvm_debugregs dbgregs;
3362
3363 r = -EFAULT;
3364 if (copy_from_user(&dbgregs, argp,
3365 sizeof(struct kvm_debugregs)))
3366 break;
3367
3368 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3369 break;
3370 }
2d5b5a66 3371 case KVM_GET_XSAVE: {
d1ac91d8 3372 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3373 r = -ENOMEM;
d1ac91d8 3374 if (!u.xsave)
2d5b5a66
SY		 3375 break;
3376
d1ac91d8 3377 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3378
3379 r = -EFAULT;
d1ac91d8 3380 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3381 break;
3382 r = 0;
3383 break;
3384 }
3385 case KVM_SET_XSAVE: {
ff5c2c03 3386 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3387 if (IS_ERR(u.xsave))
3388 return PTR_ERR(u.xsave);
2d5b5a66 3389
d1ac91d8 3390 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3391 break;
3392 }
3393 case KVM_GET_XCRS: {
d1ac91d8 3394 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3395 r = -ENOMEM;
d1ac91d8 3396 if (!u.xcrs)
2d5b5a66
SY		 3397 break;
3398
d1ac91d8 3399 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3400
3401 r = -EFAULT;
d1ac91d8 3402 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3403 sizeof(struct kvm_xcrs)))
3404 break;
3405 r = 0;
3406 break;
3407 }
3408 case KVM_SET_XCRS: {
ff5c2c03 3409 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3410 if (IS_ERR(u.xcrs))
3411 return PTR_ERR(u.xcrs);
2d5b5a66 3412
d1ac91d8 3413 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3414 break;
3415 }
92a1f12d
JR		 3416 case KVM_SET_TSC_KHZ: {
3417 u32 user_tsc_khz;
3418
3419 r = -EINVAL;
92a1f12d
JR		 3420 user_tsc_khz = (u32)arg;
3421
3422 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3423 goto out;
3424
cc578287
ZA		 3425 if (user_tsc_khz == 0)
3426 user_tsc_khz = tsc_khz;
3427
3428 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3429
3430 r = 0;
3431 goto out;
3432 }
3433 case KVM_GET_TSC_KHZ: {
cc578287 3434 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3435 goto out;
3436 }
1c0b28c2
EM		 3437 case KVM_KVMCLOCK_CTRL: {
3438 r = kvm_set_guest_paused(vcpu);
3439 goto out;
3440 }
313a3dc7
CO		 3441 default:
3442 r = -EINVAL;
3443 }
3444out:
d1ac91d8 3445 kfree(u.buffer);
313a3dc7
CO		 3446 return r;
3447}
3448
5b1c1493
CO		 3449int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3450{
3451 return VM_FAULT_SIGBUS;
3452}
3453
1fe779f8
CO		 3454static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3455{
3456 int ret;
3457
3458 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3459 return -EINVAL;
1fe779f8
CO		 3460 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3461 return ret;
3462}
3463
b927a3ce
SY		 3464static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3465 u64 ident_addr)
3466{
3467 kvm->arch.ept_identity_map_addr = ident_addr;
3468 return 0;
3469}
3470
1fe779f8
CO		 3471static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3472 u32 kvm_nr_mmu_pages)
3473{
3474 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3475 return -EINVAL;
3476
79fac95e 3477 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3478
3479 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3480 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3481
79fac95e 3482 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3483 return 0;
3484}
3485
3486static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3487{
39de71ec 3488 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3489}
3490
1fe779f8
CO		 3491static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3492{
3493 int r;
3494
3495 r = 0;
3496 switch (chip->chip_id) {
3497 case KVM_IRQCHIP_PIC_MASTER:
3498 memcpy(&chip->chip.pic,
3499 &pic_irqchip(kvm)->pics[0],
3500 sizeof(struct kvm_pic_state));
3501 break;
3502 case KVM_IRQCHIP_PIC_SLAVE:
3503 memcpy(&chip->chip.pic,
3504 &pic_irqchip(kvm)->pics[1],
3505 sizeof(struct kvm_pic_state));
3506 break;
3507 case KVM_IRQCHIP_IOAPIC:
eba0226b 3508 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3509 break;
3510 default:
3511 r = -EINVAL;
3512 break;
3513 }
3514 return r;
3515}
3516
3517static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3518{
3519 int r;
3520
3521 r = 0;
3522 switch (chip->chip_id) {
3523 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3524 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3525 memcpy(&pic_irqchip(kvm)->pics[0],
3526 &chip->chip.pic,
3527 sizeof(struct kvm_pic_state));
f4f51050 3528 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3529 break;
3530 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3531 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3532 memcpy(&pic_irqchip(kvm)->pics[1],
3533 &chip->chip.pic,
3534 sizeof(struct kvm_pic_state));
f4f51050 3535 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3536 break;
3537 case KVM_IRQCHIP_IOAPIC:
eba0226b 3538 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3539 break;
3540 default:
3541 r = -EINVAL;
3542 break;
3543 }
3544 kvm_pic_update_irq(pic_irqchip(kvm));
3545 return r;
3546}
3547
e0f63cb9
SY		 3548static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3549{
3550 int r = 0;
3551
894a9c55 3552 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3553 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3554 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3555 return r;
3556}
3557
3558static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3559{
3560 int r = 0;
3561
894a9c55 3562 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3563 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3564 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3565 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3566 return r;
3567}
3568
3569static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3570{
3571 int r = 0;
3572
3573 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3574 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3575 sizeof(ps->channels));
3576 ps->flags = kvm->arch.vpit->pit_state.flags;
3577 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3578 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3579 return r;
3580}
3581
3582static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3583{
3584 int r = 0, start = 0;
3585 u32 prev_legacy, cur_legacy;
3586 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3587 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3588 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3589 if (!prev_legacy && cur_legacy)
3590 start = 1;
3591 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3592 sizeof(kvm->arch.vpit->pit_state.channels));
3593 kvm->arch.vpit->pit_state.flags = ps->flags;
3594 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3595 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3596 return r;
3597}
3598
52d939a0
MT		 3599static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3600 struct kvm_reinject_control *control)
3601{
3602 if (!kvm->arch.vpit)
3603 return -ENXIO;
894a9c55 3604 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3605 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3606 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3607 return 0;
3608}
3609
95d4c16c 3610/**
60c34612
TY		 3611 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3612 * @kvm: kvm instance
3613 * @log: slot id and address to which we copy the log
95d4c16c 3614 *
60c34612
TY		 3615 * We need to keep it in mind that VCPU threads can write to the bitmap
3616 * concurrently. So, to avoid losing data, we keep the following order for
3617 * each bit:
95d4c16c 3618 *
60c34612
TY		 3619 * 1. Take a snapshot of the bit and clear it if needed.
3620 * 2. Write protect the corresponding page.
3621 * 3. Flush TLB's if needed.
3622 * 4. Copy the snapshot to the userspace.
95d4c16c 3623 *
60c34612
TY		 3624 * Between 2 and 3, the guest may write to the page using the remaining TLB
3625 * entry. This is not a problem because the page will be reported dirty at
3626 * step 4 using the snapshot taken before and step 3 ensures that successive
3627 * writes will be logged for the next call.
5bb064dc 3628 */
60c34612 3629int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3630{
7850ac54 3631 int r;
5bb064dc 3632 struct kvm_memory_slot *memslot;
60c34612
TY		 3633 unsigned long n, i;
3634 unsigned long *dirty_bitmap;
3635 unsigned long *dirty_bitmap_buffer;
3636 bool is_dirty = false;
5bb064dc 3637
79fac95e 3638 mutex_lock(&kvm->slots_lock);
5bb064dc 3639
b050b015 3640 r = -EINVAL;
bbacc0c1 3641 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3642 goto out;
3643
28a37544 3644 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3645
3646 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3647 r = -ENOENT;
60c34612 3648 if (!dirty_bitmap)
b050b015
MT		 3649 goto out;
3650
87bf6e7d 3651 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3652
60c34612
TY		 3653 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3654 memset(dirty_bitmap_buffer, 0, n);
b050b015 3655
60c34612 3656 spin_lock(&kvm->mmu_lock);
b050b015 3657
60c34612
TY		 3658 for (i = 0; i < n / sizeof(long); i++) {
3659 unsigned long mask;
3660 gfn_t offset;
cdfca7b3 3661
60c34612
TY		 3662 if (!dirty_bitmap[i])
3663 continue;
b050b015 3664
60c34612 3665 is_dirty = true;
914ebccd 3666
60c34612
TY		 3667 mask = xchg(&dirty_bitmap[i], 0);
3668 dirty_bitmap_buffer[i] = mask;
edde99ce 3669
60c34612
TY		 3670 offset = i * BITS_PER_LONG;
3671 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3672 }
60c34612
TY		 3673
3674 spin_unlock(&kvm->mmu_lock);
3675
198c74f4
XG		 3676 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3677 lockdep_assert_held(&kvm->slots_lock);
3678
3679 /*
3680 * All the TLBs can be flushed out of mmu lock, see the comments in
3681 * kvm_mmu_slot_remove_write_access().
3682 */
3683 if (is_dirty)
3684 kvm_flush_remote_tlbs(kvm);
3685
60c34612
TY		 3686 r = -EFAULT;
3687 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3688 goto out;
b050b015 3689
5bb064dc
ZX		 3690 r = 0;
3691out:
79fac95e 3692 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3693 return r;
3694}
3695
aa2fbe6d
YZ		 3696int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3697 bool line_status)
23d43cf9
CD		 3698{
3699 if (!irqchip_in_kernel(kvm))
3700 return -ENXIO;
3701
3702 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3703 irq_event->irq, irq_event->level,
3704 line_status);
23d43cf9
CD		 3705 return 0;
3706}
3707
1fe779f8
CO		 3708long kvm_arch_vm_ioctl(struct file *filp,
3709 unsigned int ioctl, unsigned long arg)
3710{
3711 struct kvm *kvm = filp->private_data;
3712 void __user *argp = (void __user *)arg;
367e1319 3713 int r = -ENOTTY;
f0d66275
DH		 3714 /*
3715 * This union makes it completely explicit to gcc-3.x
3716 * that these two variables' stack usage should be
3717 * combined, not added together.
3718 */
3719 union {
3720 struct kvm_pit_state ps;
e9f42757 3721 struct kvm_pit_state2 ps2;
c5ff41ce 3722 struct kvm_pit_config pit_config;
f0d66275 3723 } u;
1fe779f8
CO		 3724
3725 switch (ioctl) {
3726 case KVM_SET_TSS_ADDR:
3727 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3728 break;
b927a3ce
SY		 3729 case KVM_SET_IDENTITY_MAP_ADDR: {
3730 u64 ident_addr;
3731
3732 r = -EFAULT;
3733 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3734 goto out;
3735 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3736 break;
3737 }
1fe779f8
CO		 3738 case KVM_SET_NR_MMU_PAGES:
3739 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3740 break;
3741 case KVM_GET_NR_MMU_PAGES:
3742 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3743 break;
3ddea128
MT		 3744 case KVM_CREATE_IRQCHIP: {
3745 struct kvm_pic *vpic;
3746
3747 mutex_lock(&kvm->lock);
3748 r = -EEXIST;
3749 if (kvm->arch.vpic)
3750 goto create_irqchip_unlock;
3e515705
AK		 3751 r = -EINVAL;
3752 if (atomic_read(&kvm->online_vcpus))
3753 goto create_irqchip_unlock;
1fe779f8 3754 r = -ENOMEM;
3ddea128
MT		 3755 vpic = kvm_create_pic(kvm);
3756 if (vpic) {
1fe779f8
CO		 3757 r = kvm_ioapic_init(kvm);
3758 if (r) {
175504cd 3759 mutex_lock(&kvm->slots_lock);
72bb2fcd 3760 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3761 &vpic->dev_master);
3762 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3763 &vpic->dev_slave);
3764 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3765 &vpic->dev_eclr);
175504cd 3766 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3767 kfree(vpic);
3768 goto create_irqchip_unlock;
1fe779f8
CO		 3769 }
3770 } else
3ddea128
MT		 3771 goto create_irqchip_unlock;
3772 smp_wmb();
3773 kvm->arch.vpic = vpic;
3774 smp_wmb();
399ec807
AK		 3775 r = kvm_setup_default_irq_routing(kvm);
3776 if (r) {
175504cd 3777 mutex_lock(&kvm->slots_lock);
3ddea128 3778 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3779 kvm_ioapic_destroy(kvm);
3780 kvm_destroy_pic(kvm);
3ddea128 3781 mutex_unlock(&kvm->irq_lock);
175504cd 3782 mutex_unlock(&kvm->slots_lock);
399ec807 3783 }
3ddea128
MT		 3784 create_irqchip_unlock:
3785 mutex_unlock(&kvm->lock);
1fe779f8 3786 break;
3ddea128 3787 }
7837699f 3788 case KVM_CREATE_PIT:
c5ff41ce
JK		 3789 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3790 goto create_pit;
3791 case KVM_CREATE_PIT2:
3792 r = -EFAULT;
3793 if (copy_from_user(&u.pit_config, argp,
3794 sizeof(struct kvm_pit_config)))
3795 goto out;
3796 create_pit:
79fac95e 3797 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3798 r = -EEXIST;
3799 if (kvm->arch.vpit)
3800 goto create_pit_unlock;
7837699f 3801 r = -ENOMEM;
c5ff41ce 3802 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3803 if (kvm->arch.vpit)
3804 r = 0;
269e05e4 3805 create_pit_unlock:
79fac95e 3806 mutex_unlock(&kvm->slots_lock);
7837699f 3807 break;
1fe779f8
CO		 3808 case KVM_GET_IRQCHIP: {
3809 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3810 struct kvm_irqchip *chip;
1fe779f8 3811
ff5c2c03
SL		 3812 chip = memdup_user(argp, sizeof(*chip));
3813 if (IS_ERR(chip)) {
3814 r = PTR_ERR(chip);
1fe779f8 3815 goto out;
ff5c2c03
SL		 3816 }
3817
1fe779f8
CO		 3818 r = -ENXIO;
3819 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3820 goto get_irqchip_out;
3821 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3822 if (r)
f0d66275 3823 goto get_irqchip_out;
1fe779f8 3824 r = -EFAULT;
f0d66275
DH		 3825 if (copy_to_user(argp, chip, sizeof *chip))
3826 goto get_irqchip_out;
1fe779f8 3827 r = 0;
f0d66275
DH		 3828 get_irqchip_out:
3829 kfree(chip);
1fe779f8
CO		 3830 break;
3831 }
3832 case KVM_SET_IRQCHIP: {
3833 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3834 struct kvm_irqchip *chip;
1fe779f8 3835
ff5c2c03
SL		 3836 chip = memdup_user(argp, sizeof(*chip));
3837 if (IS_ERR(chip)) {
3838 r = PTR_ERR(chip);
1fe779f8 3839 goto out;
ff5c2c03
SL		 3840 }
3841
1fe779f8
CO		 3842 r = -ENXIO;
3843 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3844 goto set_irqchip_out;
3845 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3846 if (r)
f0d66275 3847 goto set_irqchip_out;
1fe779f8 3848 r = 0;
f0d66275
DH		 3849 set_irqchip_out:
3850 kfree(chip);
1fe779f8
CO		 3851 break;
3852 }
e0f63cb9 3853 case KVM_GET_PIT: {
e0f63cb9 3854 r = -EFAULT;
f0d66275 3855 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3856 goto out;
3857 r = -ENXIO;
3858 if (!kvm->arch.vpit)
3859 goto out;
f0d66275 3860 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3861 if (r)
3862 goto out;
3863 r = -EFAULT;
f0d66275 3864 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3865 goto out;
3866 r = 0;
3867 break;
3868 }
3869 case KVM_SET_PIT: {
e0f63cb9 3870 r = -EFAULT;
f0d66275 3871 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3872 goto out;
3873 r = -ENXIO;
3874 if (!kvm->arch.vpit)
3875 goto out;
f0d66275 3876 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3877 break;
3878 }
e9f42757
BK		 3879 case KVM_GET_PIT2: {
3880 r = -ENXIO;
3881 if (!kvm->arch.vpit)
3882 goto out;
3883 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3884 if (r)
3885 goto out;
3886 r = -EFAULT;
3887 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3888 goto out;
3889 r = 0;
3890 break;
3891 }
3892 case KVM_SET_PIT2: {
3893 r = -EFAULT;
3894 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3895 goto out;
3896 r = -ENXIO;
3897 if (!kvm->arch.vpit)
3898 goto out;
3899 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3900 break;
3901 }
52d939a0
MT		 3902 case KVM_REINJECT_CONTROL: {
3903 struct kvm_reinject_control control;
3904 r = -EFAULT;
3905 if (copy_from_user(&control, argp, sizeof(control)))
3906 goto out;
3907 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3908 break;
3909 }
ffde22ac
ES		 3910 case KVM_XEN_HVM_CONFIG: {
3911 r = -EFAULT;
3912 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3913 sizeof(struct kvm_xen_hvm_config)))
3914 goto out;
3915 r = -EINVAL;
3916 if (kvm->arch.xen_hvm_config.flags)
3917 goto out;
3918 r = 0;
3919 break;
3920 }
afbcf7ab 3921 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3922 struct kvm_clock_data user_ns;
3923 u64 now_ns;
3924 s64 delta;
3925
3926 r = -EFAULT;
3927 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3928 goto out;
3929
3930 r = -EINVAL;
3931 if (user_ns.flags)
3932 goto out;
3933
3934 r = 0;
395c6b0a 3935 local_irq_disable();
759379dd 3936 now_ns = get_kernel_ns();
afbcf7ab 3937 delta = user_ns.clock - now_ns;
395c6b0a 3938 local_irq_enable();
afbcf7ab 3939 kvm->arch.kvmclock_offset = delta;
2e762ff7 3940 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3941 break;
3942 }
3943 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3944 struct kvm_clock_data user_ns;
3945 u64 now_ns;
3946
395c6b0a 3947 local_irq_disable();
759379dd 3948 now_ns = get_kernel_ns();
afbcf7ab 3949 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3950 local_irq_enable();
afbcf7ab 3951 user_ns.flags = 0;
97e69aa6 3952 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3953
3954 r = -EFAULT;
3955 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3956 goto out;
3957 r = 0;
3958 break;
3959 }
3960
1fe779f8
CO		 3961 default:
3962 ;
3963 }
3964out:
3965 return r;
3966}
3967
a16b043c 3968static void kvm_init_msr_list(void)
043405e1
CO		 3969{
3970 u32 dummy[2];
3971 unsigned i, j;
3972
e3267cbb
GC		 3973 /* skip the first msrs in the list. KVM-specific */
3974 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3975 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3976 continue;
93c4adc7
PB		 3977
3978 /*
3979 * Even MSRs that are valid in the host may not be exposed
3980 * to the guests in some cases. We could work around this
3981 * in VMX with the generic MSR save/load machinery, but it
3982 * is not really worthwhile since it will really only
3983 * happen with nested virtualization.
3984 */
3985 switch (msrs_to_save[i]) {
3986 case MSR_IA32_BNDCFGS:
3987 if (!kvm_x86_ops->mpx_supported())
3988 continue;
3989 break;
3990 default:
3991 break;
3992 }
3993
043405e1
CO		 3994 if (j < i)
3995 msrs_to_save[j] = msrs_to_save[i];
3996 j++;
3997 }
3998 num_msrs_to_save = j;
3999}
4000
bda9020e
MT		 4001static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4002 const void *v)
bbd9b64e 4003{
70252a10
AK		 4004 int handled = 0;
4005 int n;
4006
4007 do {
4008 n = min(len, 8);
4009 if (!(vcpu->arch.apic &&
4010 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4011 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4012 break;
4013 handled += n;
4014 addr += n;
4015 len -= n;
4016 v += n;
4017 } while (len);
bbd9b64e 4018
70252a10 4019 return handled;
bbd9b64e
CO		 4020}
4021
bda9020e 4022static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4023{
70252a10
AK		 4024 int handled = 0;
4025 int n;
4026
4027 do {
4028 n = min(len, 8);
4029 if (!(vcpu->arch.apic &&
4030 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4031 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4032 break;
4033 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4034 handled += n;
4035 addr += n;
4036 len -= n;
4037 v += n;
4038 } while (len);
bbd9b64e 4039
70252a10 4040 return handled;
bbd9b64e
CO		 4041}
4042
2dafc6c2
GN		 4043static void kvm_set_segment(struct kvm_vcpu *vcpu,
4044 struct kvm_segment *var, int seg)
4045{
4046 kvm_x86_ops->set_segment(vcpu, var, seg);
4047}
4048
4049void kvm_get_segment(struct kvm_vcpu *vcpu,
4050 struct kvm_segment *var, int seg)
4051{
4052 kvm_x86_ops->get_segment(vcpu, var, seg);
4053}
4054
e459e322 4055gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 4056{
4057 gpa_t t_gpa;
ab9ae313 4058 struct x86_exception exception;
02f59dc9
JR		 4059
4060 BUG_ON(!mmu_is_nested(vcpu));
4061
4062 /* NPT walks are always user-walks */
4063 access |= PFERR_USER_MASK;
ab9ae313 4064 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 4065
4066 return t_gpa;
4067}
4068
ab9ae313
AK		 4069gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4070 struct x86_exception *exception)
1871c602
GN		 4071{
4072 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4073 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4074}
4075
ab9ae313
AK		 4076 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4077 struct x86_exception *exception)
1871c602
GN		 4078{
4079 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4080 access |= PFERR_FETCH_MASK;
ab9ae313 4081 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4082}
4083
ab9ae313
AK		 4084gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4085 struct x86_exception *exception)
1871c602
GN		 4086{
4087 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4088 access |= PFERR_WRITE_MASK;
ab9ae313 4089 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4090}
4091
4092/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4093gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4094 struct x86_exception *exception)
1871c602 4095{
ab9ae313 4096 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4097}
4098
4099static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4100 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4101 struct x86_exception *exception)
bbd9b64e
CO		 4102{
4103 void *data = val;
10589a46 4104 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4105
4106 while (bytes) {
14dfe855 4107 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4108 exception);
bbd9b64e 4109 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4110 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4111 int ret;
4112
bcc55cba 4113 if (gpa == UNMAPPED_GVA)
ab9ae313 4114 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4115 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4116 offset, toread);
10589a46 4117 if (ret < 0) {
c3cd7ffa 4118 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4119 goto out;
4120 }
bbd9b64e 4121
77c2002e
IE		 4122 bytes -= toread;
4123 data += toread;
4124 addr += toread;
bbd9b64e 4125 }
10589a46 4126out:
10589a46 4127 return r;
bbd9b64e 4128}
77c2002e 4129
1871c602 4130/* used for instruction fetching */
0f65dd70
AK		 4131static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4132 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4133 struct x86_exception *exception)
1871c602 4134{
0f65dd70 4135 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4136 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4137 unsigned offset;
4138 int ret;
0f65dd70 4139
44583cba
PB		 4140 /* Inline kvm_read_guest_virt_helper for speed. */
4141 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4142 exception);
4143 if (unlikely(gpa == UNMAPPED_GVA))
4144 return X86EMUL_PROPAGATE_FAULT;
4145
4146 offset = addr & (PAGE_SIZE-1);
4147 if (WARN_ON(offset + bytes > PAGE_SIZE))
4148 bytes = (unsigned)PAGE_SIZE - offset;
4149 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4150 offset, bytes);
4151 if (unlikely(ret < 0))
4152 return X86EMUL_IO_NEEDED;
4153
4154 return X86EMUL_CONTINUE;
1871c602
GN		 4155}
4156
064aea77 4157int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4158 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4159 struct x86_exception *exception)
1871c602 4160{
0f65dd70 4161 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4162 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4163
1871c602 4164 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4165 exception);
1871c602 4166}
064aea77 4167EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4168
0f65dd70
AK		 4169static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4170 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4171 struct x86_exception *exception)
1871c602 4172{
0f65dd70 4173 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4174 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4175}
4176
6a4d7550 4177int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4178 gva_t addr, void *val,
2dafc6c2 4179 unsigned int bytes,
bcc55cba 4180 struct x86_exception *exception)
77c2002e 4181{
0f65dd70 4182 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4183 void *data = val;
4184 int r = X86EMUL_CONTINUE;
4185
4186 while (bytes) {
14dfe855
JR		 4187 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4188 PFERR_WRITE_MASK,
ab9ae313 4189 exception);
77c2002e
IE		 4190 unsigned offset = addr & (PAGE_SIZE-1);
4191 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4192 int ret;
4193
bcc55cba 4194 if (gpa == UNMAPPED_GVA)
ab9ae313 4195 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4196 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4197 if (ret < 0) {
c3cd7ffa 4198 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4199 goto out;
4200 }
4201
4202 bytes -= towrite;
4203 data += towrite;
4204 addr += towrite;
4205 }
4206out:
4207 return r;
4208}
6a4d7550 4209EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4210
af7cc7d1
XG		 4211static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4212 gpa_t *gpa, struct x86_exception *exception,
4213 bool write)
4214{
97d64b78
AK		 4215 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4216 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4217
97d64b78 4218 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4219 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4220 vcpu->arch.access, access)) {
bebb106a
XG		 4221 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4222 (gva & (PAGE_SIZE - 1));
4f022648 4223 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4224 return 1;
4225 }
4226
af7cc7d1
XG		 4227 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4228
4229 if (*gpa == UNMAPPED_GVA)
4230 return -1;
4231
4232 /* For APIC access vmexit */
4233 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4234 return 1;
4235
4f022648
XG		 4236 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4237 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4238 return 1;
4f022648 4239 }
bebb106a 4240
af7cc7d1
XG		 4241 return 0;
4242}
4243
3200f405 4244int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4245 const void *val, int bytes)
bbd9b64e
CO		 4246{
4247 int ret;
4248
4249 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4250 if (ret < 0)
bbd9b64e 4251 return 0;
f57f2ef5 4252 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4253 return 1;
4254}
4255
77d197b2
XG		 4256struct read_write_emulator_ops {
4257 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4258 int bytes);
4259 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4260 void *val, int bytes);
4261 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4262 int bytes, void *val);
4263 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4264 void *val, int bytes);
4265 bool write;
4266};
4267
4268static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4269{
4270 if (vcpu->mmio_read_completed) {
77d197b2 4271 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4272 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4273 vcpu->mmio_read_completed = 0;
4274 return 1;
4275 }
4276
4277 return 0;
4278}
4279
4280static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4281 void *val, int bytes)
4282{
4283 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4284}
4285
4286static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4287 void *val, int bytes)
4288{
4289 return emulator_write_phys(vcpu, gpa, val, bytes);
4290}
4291
4292static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4293{
4294 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4295 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4296}
4297
4298static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4299 void *val, int bytes)
4300{
4301 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4302 return X86EMUL_IO_NEEDED;
4303}
4304
4305static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4306 void *val, int bytes)
4307{
f78146b0
AK		 4308 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4309
87da7e66 4310 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4311 return X86EMUL_CONTINUE;
4312}
4313
0fbe9b0b 4314static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4315 .read_write_prepare = read_prepare,
4316 .read_write_emulate = read_emulate,
4317 .read_write_mmio = vcpu_mmio_read,
4318 .read_write_exit_mmio = read_exit_mmio,
4319};
4320
0fbe9b0b 4321static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4322 .read_write_emulate = write_emulate,
4323 .read_write_mmio = write_mmio,
4324 .read_write_exit_mmio = write_exit_mmio,
4325 .write = true,
4326};
4327
22388a3c
XG		 4328static int emulator_read_write_onepage(unsigned long addr, void *val,
4329 unsigned int bytes,
4330 struct x86_exception *exception,
4331 struct kvm_vcpu *vcpu,
0fbe9b0b 4332 const struct read_write_emulator_ops *ops)
bbd9b64e 4333{
af7cc7d1
XG		 4334 gpa_t gpa;
4335 int handled, ret;
22388a3c 4336 bool write = ops->write;
f78146b0 4337 struct kvm_mmio_fragment *frag;
10589a46 4338
22388a3c 4339 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4340
af7cc7d1 4341 if (ret < 0)
bbd9b64e 4342 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4343
4344 /* For APIC access vmexit */
af7cc7d1 4345 if (ret)
bbd9b64e
CO		 4346 goto mmio;
4347
22388a3c 4348 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4349 return X86EMUL_CONTINUE;
4350
4351mmio:
4352 /*
4353 * Is this MMIO handled locally?
4354 */
22388a3c 4355 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4356 if (handled == bytes)
bbd9b64e 4357 return X86EMUL_CONTINUE;
bbd9b64e 4358
70252a10
AK		 4359 gpa += handled;
4360 bytes -= handled;
4361 val += handled;
4362
87da7e66
XG		 4363 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4364 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4365 frag->gpa = gpa;
4366 frag->data = val;
4367 frag->len = bytes;
f78146b0 4368 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4369}
4370
22388a3c
XG		 4371int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4372 void *val, unsigned int bytes,
4373 struct x86_exception *exception,
0fbe9b0b 4374 const struct read_write_emulator_ops *ops)
bbd9b64e 4375{
0f65dd70 4376 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4377 gpa_t gpa;
4378 int rc;
4379
4380 if (ops->read_write_prepare &&
4381 ops->read_write_prepare(vcpu, val, bytes))
4382 return X86EMUL_CONTINUE;
4383
4384 vcpu->mmio_nr_fragments = 0;
0f65dd70 4385
bbd9b64e
CO		 4386 /* Crossing a page boundary? */
4387 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4388 int now;
bbd9b64e
CO		 4389
4390 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4391 rc = emulator_read_write_onepage(addr, val, now, exception,
4392 vcpu, ops);
4393
bbd9b64e
CO		 4394 if (rc != X86EMUL_CONTINUE)
4395 return rc;
4396 addr += now;
4397 val += now;
4398 bytes -= now;
4399 }
22388a3c 4400
f78146b0
AK		 4401 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4402 vcpu, ops);
4403 if (rc != X86EMUL_CONTINUE)
4404 return rc;
4405
4406 if (!vcpu->mmio_nr_fragments)
4407 return rc;
4408
4409 gpa = vcpu->mmio_fragments[0].gpa;
4410
4411 vcpu->mmio_needed = 1;
4412 vcpu->mmio_cur_fragment = 0;
4413
87da7e66 4414 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4415 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4416 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4417 vcpu->run->mmio.phys_addr = gpa;
4418
4419 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4420}
4421
4422static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4423 unsigned long addr,
4424 void *val,
4425 unsigned int bytes,
4426 struct x86_exception *exception)
4427{
4428 return emulator_read_write(ctxt, addr, val, bytes,
4429 exception, &read_emultor);
4430}
4431
4432int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4433 unsigned long addr,
4434 const void *val,
4435 unsigned int bytes,
4436 struct x86_exception *exception)
4437{
4438 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4439 exception, &write_emultor);
bbd9b64e 4440}
bbd9b64e 4441
daea3e73
AK		 4442#define CMPXCHG_TYPE(t, ptr, old, new) \
4443 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4444
4445#ifdef CONFIG_X86_64
4446# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4447#else
4448# define CMPXCHG64(ptr, old, new) \
9749a6c0 4449 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4450#endif
4451
0f65dd70
AK		 4452static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4453 unsigned long addr,
bbd9b64e
CO		 4454 const void *old,
4455 const void *new,
4456 unsigned int bytes,
0f65dd70 4457 struct x86_exception *exception)
bbd9b64e 4458{
0f65dd70 4459 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4460 gpa_t gpa;
4461 struct page *page;
4462 char *kaddr;
4463 bool exchanged;
2bacc55c 4464
daea3e73
AK		 4465 /* guests cmpxchg8b have to be emulated atomically */
4466 if (bytes > 8 || (bytes & (bytes - 1)))
4467 goto emul_write;
10589a46 4468
daea3e73 4469 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4470
daea3e73
AK		 4471 if (gpa == UNMAPPED_GVA ||
4472 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4473 goto emul_write;
2bacc55c 4474
daea3e73
AK		 4475 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4476 goto emul_write;
72dc67a6 4477
daea3e73 4478 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4479 if (is_error_page(page))
c19b8bd6 4480 goto emul_write;
72dc67a6 4481
8fd75e12 4482 kaddr = kmap_atomic(page);
daea3e73
AK		 4483 kaddr += offset_in_page(gpa);
4484 switch (bytes) {
4485 case 1:
4486 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4487 break;
4488 case 2:
4489 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4490 break;
4491 case 4:
4492 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4493 break;
4494 case 8:
4495 exchanged = CMPXCHG64(kaddr, old, new);
4496 break;
4497 default:
4498 BUG();
2bacc55c 4499 }
8fd75e12 4500 kunmap_atomic(kaddr);
daea3e73
AK		 4501 kvm_release_page_dirty(page);
4502
4503 if (!exchanged)
4504 return X86EMUL_CMPXCHG_FAILED;
4505
d3714010 4506 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4507 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4508
4509 return X86EMUL_CONTINUE;
4a5f48f6 4510
3200f405 4511emul_write:
daea3e73 4512 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4513
0f65dd70 4514 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4515}
4516
cf8f70bf
GN		 4517static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4518{
4519 /* TODO: String I/O for in kernel device */
4520 int r;
4521
4522 if (vcpu->arch.pio.in)
4523 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4524 vcpu->arch.pio.size, pd);
4525 else
4526 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4527 vcpu->arch.pio.port, vcpu->arch.pio.size,
4528 pd);
4529 return r;
4530}
4531
6f6fbe98
XG		 4532static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4533 unsigned short port, void *val,
4534 unsigned int count, bool in)
cf8f70bf 4535{
cf8f70bf 4536 vcpu->arch.pio.port = port;
6f6fbe98 4537 vcpu->arch.pio.in = in;
7972995b 4538 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4539 vcpu->arch.pio.size = size;
4540
4541 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4542 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4543 return 1;
4544 }
4545
4546 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4547 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4548 vcpu->run->io.size = size;
4549 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4550 vcpu->run->io.count = count;
4551 vcpu->run->io.port = port;
4552
4553 return 0;
4554}
4555
6f6fbe98
XG		 4556static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4557 int size, unsigned short port, void *val,
4558 unsigned int count)
cf8f70bf 4559{
ca1d4a9e 4560 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4561 int ret;
ca1d4a9e 4562
6f6fbe98
XG		 4563 if (vcpu->arch.pio.count)
4564 goto data_avail;
cf8f70bf 4565
6f6fbe98
XG		 4566 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4567 if (ret) {
4568data_avail:
4569 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4570 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4571 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4572 return 1;
4573 }
4574
cf8f70bf
GN		 4575 return 0;
4576}
4577
6f6fbe98
XG		 4578static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4579 int size, unsigned short port,
4580 const void *val, unsigned int count)
4581{
4582 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4583
4584 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4585 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4586 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4587}
4588
bbd9b64e
CO		 4589static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4590{
4591 return kvm_x86_ops->get_segment_base(vcpu, seg);
4592}
4593
3cb16fe7 4594static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4595{
3cb16fe7 4596 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4597}
4598
f5f48ee1
SY		 4599int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4600{
4601 if (!need_emulate_wbinvd(vcpu))
4602 return X86EMUL_CONTINUE;
4603
4604 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4605 int cpu = get_cpu();
4606
4607 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4608 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4609 wbinvd_ipi, NULL, 1);
2eec7343 4610 put_cpu();
f5f48ee1 4611 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4612 } else
4613 wbinvd();
f5f48ee1
SY		 4614 return X86EMUL_CONTINUE;
4615}
4616EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4617
bcaf5cc5
AK		 4618static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4619{
4620 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4621}
4622
717746e3 4623int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4624{
717746e3 4625 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4626}
4627
717746e3 4628int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4629{
338dbc97 4630
717746e3 4631 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4632}
4633
52a46617 4634static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4635{
52a46617 4636 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4637}
4638
717746e3 4639static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4640{
717746e3 4641 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4642 unsigned long value;
4643
4644 switch (cr) {
4645 case 0:
4646 value = kvm_read_cr0(vcpu);
4647 break;
4648 case 2:
4649 value = vcpu->arch.cr2;
4650 break;
4651 case 3:
9f8fe504 4652 value = kvm_read_cr3(vcpu);
52a46617
GN		 4653 break;
4654 case 4:
4655 value = kvm_read_cr4(vcpu);
4656 break;
4657 case 8:
4658 value = kvm_get_cr8(vcpu);
4659 break;
4660 default:
a737f256 4661 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4662 return 0;
4663 }
4664
4665 return value;
4666}
4667
717746e3 4668static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4669{
717746e3 4670 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4671 int res = 0;
4672
52a46617
GN		 4673 switch (cr) {
4674 case 0:
49a9b07e 4675 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4676 break;
4677 case 2:
4678 vcpu->arch.cr2 = val;
4679 break;
4680 case 3:
2390218b 4681 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4682 break;
4683 case 4:
a83b29c6 4684 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4685 break;
4686 case 8:
eea1cff9 4687 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4688 break;
4689 default:
a737f256 4690 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4691 res = -1;
52a46617 4692 }
0f12244f
GN		 4693
4694 return res;
52a46617
GN		 4695}
4696
717746e3 4697static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4698{
717746e3 4699 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4700}
4701
4bff1e86 4702static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4703{
4bff1e86 4704 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4705}
4706
4bff1e86 4707static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4708{
4bff1e86 4709 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4710}
4711
1ac9d0cf
AK		 4712static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4713{
4714 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4715}
4716
4717static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4718{
4719 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4720}
4721
4bff1e86
AK		 4722static unsigned long emulator_get_cached_segment_base(
4723 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4724{
4bff1e86 4725 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4726}
4727
1aa36616
AK		 4728static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4729 struct desc_struct *desc, u32 *base3,
4730 int seg)
2dafc6c2
GN		 4731{
4732 struct kvm_segment var;
4733
4bff1e86 4734 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4735 *selector = var.selector;
2dafc6c2 4736
378a8b09
GN		 4737 if (var.unusable) {
4738 memset(desc, 0, sizeof(*desc));
2dafc6c2 4739 return false;
378a8b09 4740 }
2dafc6c2
GN		 4741
4742 if (var.g)
4743 var.limit >>= 12;
4744 set_desc_limit(desc, var.limit);
4745 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4746#ifdef CONFIG_X86_64
4747 if (base3)
4748 *base3 = var.base >> 32;
4749#endif
2dafc6c2
GN		 4750 desc->type = var.type;
4751 desc->s = var.s;
4752 desc->dpl = var.dpl;
4753 desc->p = var.present;
4754 desc->avl = var.avl;
4755 desc->l = var.l;
4756 desc->d = var.db;
4757 desc->g = var.g;
4758
4759 return true;
4760}
4761
1aa36616
AK		 4762static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4763 struct desc_struct *desc, u32 base3,
4764 int seg)
2dafc6c2 4765{
4bff1e86 4766 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4767 struct kvm_segment var;
4768
1aa36616 4769 var.selector = selector;
2dafc6c2 4770 var.base = get_desc_base(desc);
5601d05b
GN		 4771#ifdef CONFIG_X86_64
4772 var.base |= ((u64)base3) << 32;
4773#endif
2dafc6c2
GN		 4774 var.limit = get_desc_limit(desc);
4775 if (desc->g)
4776 var.limit = (var.limit << 12) | 0xfff;
4777 var.type = desc->type;
2dafc6c2
GN		 4778 var.dpl = desc->dpl;
4779 var.db = desc->d;
4780 var.s = desc->s;
4781 var.l = desc->l;
4782 var.g = desc->g;
4783 var.avl = desc->avl;
4784 var.present = desc->p;
4785 var.unusable = !var.present;
4786 var.padding = 0;
4787
4788 kvm_set_segment(vcpu, &var, seg);
4789 return;
4790}
4791
717746e3
AK		 4792static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4793 u32 msr_index, u64 *pdata)
4794{
4795 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4796}
4797
4798static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4799 u32 msr_index, u64 data)
4800{
8fe8ab46
WA		 4801 struct msr_data msr;
4802
4803 msr.data = data;
4804 msr.index = msr_index;
4805 msr.host_initiated = false;
4806 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4807}
4808
67f4d428
NA		 4809static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4810 u32 pmc)
4811{
4812 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4813}
4814
222d21aa
AK		 4815static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4816 u32 pmc, u64 *pdata)
4817{
4818 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4819}
4820
6c3287f7
AK		 4821static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4822{
4823 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4824}
4825
5037f6f3
AK		 4826static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4827{
4828 preempt_disable();
5197b808 4829 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4830 /*
4831 * CR0.TS may reference the host fpu state, not the guest fpu state,
4832 * so it may be clear at this point.
4833 */
4834 clts();
4835}
4836
4837static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4838{
4839 preempt_enable();
4840}
4841
2953538e 4842static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4843 struct x86_instruction_info *info,
c4f035c6
AK		 4844 enum x86_intercept_stage stage)
4845{
2953538e 4846 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4847}
4848
0017f93a 4849static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4850 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4851{
0017f93a 4852 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4853}
4854
dd856efa
AK		 4855static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4856{
4857 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4858}
4859
4860static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4861{
4862 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4863}
4864
0225fb50 4865static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4866 .read_gpr = emulator_read_gpr,
4867 .write_gpr = emulator_write_gpr,
1871c602 4868 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4869 .write_std = kvm_write_guest_virt_system,
1871c602 4870 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4871 .read_emulated = emulator_read_emulated,
4872 .write_emulated = emulator_write_emulated,
4873 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4874 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4875 .pio_in_emulated = emulator_pio_in_emulated,
4876 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4877 .get_segment = emulator_get_segment,
4878 .set_segment = emulator_set_segment,
5951c442 4879 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4880 .get_gdt = emulator_get_gdt,
160ce1f1 4881 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4882 .set_gdt = emulator_set_gdt,
4883 .set_idt = emulator_set_idt,
52a46617
GN		 4884 .get_cr = emulator_get_cr,
4885 .set_cr = emulator_set_cr,
9c537244 4886 .cpl = emulator_get_cpl,
35aa5375
GN		 4887 .get_dr = emulator_get_dr,
4888 .set_dr = emulator_set_dr,
717746e3
AK		 4889 .set_msr = emulator_set_msr,
4890 .get_msr = emulator_get_msr,
67f4d428 4891 .check_pmc = emulator_check_pmc,
222d21aa 4892 .read_pmc = emulator_read_pmc,
6c3287f7 4893 .halt = emulator_halt,
bcaf5cc5 4894 .wbinvd = emulator_wbinvd,
d6aa1000 4895 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4896 .get_fpu = emulator_get_fpu,
4897 .put_fpu = emulator_put_fpu,
c4f035c6 4898 .intercept = emulator_intercept,
bdb42f5a 4899 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4900};
4901
95cb2295
GN		 4902static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4903{
37ccdcbe 4904 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4905 /*
4906 * an sti; sti; sequence only disable interrupts for the first
4907 * instruction. So, if the last instruction, be it emulated or
4908 * not, left the system with the INT_STI flag enabled, it
4909 * means that the last instruction is an sti. We should not
4910 * leave the flag on in this case. The same goes for mov ss
4911 */
37ccdcbe
PB		 4912 if (int_shadow & mask)
4913 mask = 0;
6addfc42 4914 if (unlikely(int_shadow || mask)) {
95cb2295 4915 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4916 if (!mask)
4917 kvm_make_request(KVM_REQ_EVENT, vcpu);
4918 }
95cb2295
GN		 4919}
4920
54b8486f
GN		 4921static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4922{
4923 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4924 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4925 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4926 else if (ctxt->exception.error_code_valid)
4927 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4928 ctxt->exception.error_code);
54b8486f 4929 else
da9cb575 4930 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4931}
4932
8ec4722d
MG		 4933static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4934{
adf52235 4935 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4936 int cs_db, cs_l;
4937
8ec4722d
MG		 4938 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4939
adf52235
TY		 4940 ctxt->eflags = kvm_get_rflags(vcpu);
4941 ctxt->eip = kvm_rip_read(vcpu);
4942 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4943 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4944 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4945 cs_db ? X86EMUL_MODE_PROT32 :
4946 X86EMUL_MODE_PROT16;
4947 ctxt->guest_mode = is_guest_mode(vcpu);
4948
dd856efa 4949 init_decode_cache(ctxt);
7ae441ea 4950 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4951}
4952
71f9833b 4953int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4954{
9d74191a 4955 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4956 int ret;
4957
4958 init_emulate_ctxt(vcpu);
4959
9dac77fa
AK		 4960 ctxt->op_bytes = 2;
4961 ctxt->ad_bytes = 2;
4962 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4963 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4964
4965 if (ret != X86EMUL_CONTINUE)
4966 return EMULATE_FAIL;
4967
9dac77fa 4968 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4969 kvm_rip_write(vcpu, ctxt->eip);
4970 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4971
4972 if (irq == NMI_VECTOR)
7460fb4a 4973 vcpu->arch.nmi_pending = 0;
63995653
MG		 4974 else
4975 vcpu->arch.interrupt.pending = false;
4976
4977 return EMULATE_DONE;
4978}
4979EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4980
6d77dbfc
GN		 4981static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4982{
fc3a9157
JR		 4983 int r = EMULATE_DONE;
4984
6d77dbfc
GN		 4985 ++vcpu->stat.insn_emulation_fail;
4986 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4987 if (!is_guest_mode(vcpu)) {
4988 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4989 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4990 vcpu->run->internal.ndata = 0;
4991 r = EMULATE_FAIL;
4992 }
6d77dbfc 4993 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4994
4995 return r;
6d77dbfc
GN		 4996}
4997
93c05d3e 4998static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4999 bool write_fault_to_shadow_pgtable,
5000 int emulation_type)
a6f177ef 5001{
95b3cf69 5002 gpa_t gpa = cr2;
8e3d9d06 5003 pfn_t pfn;
a6f177ef 5004
991eebf9
GN		 5005 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5006 return false;
5007
95b3cf69
XG		 5008 if (!vcpu->arch.mmu.direct_map) {
5009 /*
5010 * Write permission should be allowed since only
5011 * write access need to be emulated.
5012 */
5013 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5014
95b3cf69
XG		 5015 /*
5016 * If the mapping is invalid in guest, let cpu retry
5017 * it to generate fault.
5018 */
5019 if (gpa == UNMAPPED_GVA)
5020 return true;
5021 }
a6f177ef 5022
8e3d9d06
XG		 5023 /*
5024 * Do not retry the unhandleable instruction if it faults on the
5025 * readonly host memory, otherwise it will goto a infinite loop:
5026 * retry instruction -> write #PF -> emulation fail -> retry
5027 * instruction -> ...
5028 */
5029 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5030
5031 /*
5032 * If the instruction failed on the error pfn, it can not be fixed,
5033 * report the error to userspace.
5034 */
5035 if (is_error_noslot_pfn(pfn))
5036 return false;
5037
5038 kvm_release_pfn_clean(pfn);
5039
5040 /* The instructions are well-emulated on direct mmu. */
5041 if (vcpu->arch.mmu.direct_map) {
5042 unsigned int indirect_shadow_pages;
5043
5044 spin_lock(&vcpu->kvm->mmu_lock);
5045 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5046 spin_unlock(&vcpu->kvm->mmu_lock);
5047
5048 if (indirect_shadow_pages)
5049 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5050
a6f177ef 5051 return true;
8e3d9d06 5052 }
a6f177ef 5053
95b3cf69
XG		 5054 /*
5055 * if emulation was due to access to shadowed page table
5056 * and it failed try to unshadow page and re-enter the
5057 * guest to let CPU execute the instruction.
5058 */
5059 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5060
5061 /*
5062 * If the access faults on its page table, it can not
5063 * be fixed by unprotecting shadow page and it should
5064 * be reported to userspace.
5065 */
5066 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5067}
5068
1cb3f3ae
XG		 5069static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5070 unsigned long cr2, int emulation_type)
5071{
5072 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5073 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5074
5075 last_retry_eip = vcpu->arch.last_retry_eip;
5076 last_retry_addr = vcpu->arch.last_retry_addr;
5077
5078 /*
5079 * If the emulation is caused by #PF and it is non-page_table
5080 * writing instruction, it means the VM-EXIT is caused by shadow
5081 * page protected, we can zap the shadow page and retry this
5082 * instruction directly.
5083 *
5084 * Note: if the guest uses a non-page-table modifying instruction
5085 * on the PDE that points to the instruction, then we will unmap
5086 * the instruction and go to an infinite loop. So, we cache the
5087 * last retried eip and the last fault address, if we meet the eip
5088 * and the address again, we can break out of the potential infinite
5089 * loop.
5090 */
5091 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5092
5093 if (!(emulation_type & EMULTYPE_RETRY))
5094 return false;
5095
5096 if (x86_page_table_writing_insn(ctxt))
5097 return false;
5098
5099 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5100 return false;
5101
5102 vcpu->arch.last_retry_eip = ctxt->eip;
5103 vcpu->arch.last_retry_addr = cr2;
5104
5105 if (!vcpu->arch.mmu.direct_map)
5106 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5107
22368028 5108 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5109
5110 return true;
5111}
5112
716d51ab
GN		 5113static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5114static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5115
4a1e10d5
PB		 5116static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5117 unsigned long *db)
5118{
5119 u32 dr6 = 0;
5120 int i;
5121 u32 enable, rwlen;
5122
5123 enable = dr7;
5124 rwlen = dr7 >> 16;
5125 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5126 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5127 dr6 |= (1 << i);
5128 return dr6;
5129}
5130
6addfc42 5131static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5132{
5133 struct kvm_run *kvm_run = vcpu->run;
5134
5135 /*
6addfc42
PB		 5136 * rflags is the old, "raw" value of the flags. The new value has
5137 * not been saved yet.
663f4c61
PB		 5138 *
5139 * This is correct even for TF set by the guest, because "the
5140 * processor will not generate this exception after the instruction
5141 * that sets the TF flag".
5142 */
663f4c61
PB		 5143 if (unlikely(rflags & X86_EFLAGS_TF)) {
5144 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5145 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5146 DR6_RTM;
663f4c61
PB		 5147 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5148 kvm_run->debug.arch.exception = DB_VECTOR;
5149 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5150 *r = EMULATE_USER_EXIT;
5151 } else {
5152 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5153 /*
5154 * "Certain debug exceptions may clear bit 0-3. The
5155 * remaining contents of the DR6 register are never
5156 * cleared by the processor".
5157 */
5158 vcpu->arch.dr6 &= ~15;
6f43ed01 5159 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5160 kvm_queue_exception(vcpu, DB_VECTOR);
5161 }
5162 }
5163}
5164
4a1e10d5
PB		 5165static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5166{
5167 struct kvm_run *kvm_run = vcpu->run;
5168 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5169 u32 dr6 = 0;
5170
5171 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5172 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5173 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5174 vcpu->arch.guest_debug_dr7,
5175 vcpu->arch.eff_db);
5176
5177 if (dr6 != 0) {
6f43ed01 5178 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
4a1e10d5
PB		 5179 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5180 get_segment_base(vcpu, VCPU_SREG_CS);
5181
5182 kvm_run->debug.arch.exception = DB_VECTOR;
5183 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5184 *r = EMULATE_USER_EXIT;
5185 return true;
5186 }
5187 }
5188
4161a569
NA		 5189 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5190 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
4a1e10d5
PB		 5191 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5192 vcpu->arch.dr7,
5193 vcpu->arch.db);
5194
5195 if (dr6 != 0) {
5196 vcpu->arch.dr6 &= ~15;
6f43ed01 5197 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5198 kvm_queue_exception(vcpu, DB_VECTOR);
5199 *r = EMULATE_DONE;
5200 return true;
5201 }
5202 }
5203
5204 return false;
5205}
5206
51d8b661
AP		 5207int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5208 unsigned long cr2,
dc25e89e
AP		 5209 int emulation_type,
5210 void *insn,
5211 int insn_len)
bbd9b64e 5212{
95cb2295 5213 int r;
9d74191a 5214 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5215 bool writeback = true;
93c05d3e 5216 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5217
93c05d3e
XG		 5218 /*
5219 * Clear write_fault_to_shadow_pgtable here to ensure it is
5220 * never reused.
5221 */
5222 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5223 kvm_clear_exception_queue(vcpu);
8d7d8102 5224
571008da 5225 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5226 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5227
5228 /*
5229 * We will reenter on the same instruction since
5230 * we do not set complete_userspace_io. This does not
5231 * handle watchpoints yet, those would be handled in
5232 * the emulate_ops.
5233 */
5234 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5235 return r;
5236
9d74191a
TY		 5237 ctxt->interruptibility = 0;
5238 ctxt->have_exception = false;
5239 ctxt->perm_ok = false;
bbd9b64e 5240
b51e974f 5241 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5242
9d74191a 5243 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5244
e46479f8 5245 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5246 ++vcpu->stat.insn_emulation;
1d2887e2 5247 if (r != EMULATION_OK) {
4005996e
AK		 5248 if (emulation_type & EMULTYPE_TRAP_UD)
5249 return EMULATE_FAIL;
991eebf9
GN		 5250 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5251 emulation_type))
bbd9b64e 5252 return EMULATE_DONE;
6d77dbfc
GN		 5253 if (emulation_type & EMULTYPE_SKIP)
5254 return EMULATE_FAIL;
5255 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5256 }
5257 }
5258
ba8afb6b 5259 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5260 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5261 if (ctxt->eflags & X86_EFLAGS_RF)
5262 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5263 return EMULATE_DONE;
5264 }
5265
1cb3f3ae
XG		 5266 if (retry_instruction(ctxt, cr2, emulation_type))
5267 return EMULATE_DONE;
5268
7ae441ea 5269 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5270 changes registers values during IO operation */
7ae441ea
GN		 5271 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5272 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5273 emulator_invalidate_register_cache(ctxt);
7ae441ea 5274 }
4d2179e1 5275
5cd21917 5276restart:
9d74191a 5277 r = x86_emulate_insn(ctxt);
bbd9b64e 5278
775fde86
JR		 5279 if (r == EMULATION_INTERCEPTED)
5280 return EMULATE_DONE;
5281
d2ddd1c4 5282 if (r == EMULATION_FAILED) {
991eebf9
GN		 5283 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5284 emulation_type))
c3cd7ffa
GN		 5285 return EMULATE_DONE;
5286
6d77dbfc 5287 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5288 }
5289
9d74191a 5290 if (ctxt->have_exception) {
54b8486f 5291 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5292 r = EMULATE_DONE;
5293 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5294 if (!vcpu->arch.pio.in) {
5295 /* FIXME: return into emulator if single-stepping. */
3457e419 5296 vcpu->arch.pio.count = 0;
0912c977 5297 } else {
7ae441ea 5298 writeback = false;
716d51ab
GN		 5299 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5300 }
ac0a48c3 5301 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5302 } else if (vcpu->mmio_needed) {
5303 if (!vcpu->mmio_is_write)
5304 writeback = false;
ac0a48c3 5305 r = EMULATE_USER_EXIT;
716d51ab 5306 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5307 } else if (r == EMULATION_RESTART)
5cd21917 5308 goto restart;
d2ddd1c4
GN		 5309 else
5310 r = EMULATE_DONE;
f850e2e6 5311
7ae441ea 5312 if (writeback) {
6addfc42 5313 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5314 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5315 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5316 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5317 if (r == EMULATE_DONE)
6addfc42
PB		 5318 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5319 __kvm_set_rflags(vcpu, ctxt->eflags);
5320
5321 /*
5322 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5323 * do nothing, and it will be requested again as soon as
5324 * the shadow expires. But we still need to check here,
5325 * because POPF has no interrupt shadow.
5326 */
5327 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5328 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5329 } else
5330 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5331
5332 return r;
de7d789a 5333}
51d8b661 5334EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5335
cf8f70bf 5336int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5337{
cf8f70bf 5338 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5339 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5340 size, port, &val, 1);
cf8f70bf 5341 /* do not return to emulator after return from userspace */
7972995b 5342 vcpu->arch.pio.count = 0;
de7d789a
CO		 5343 return ret;
5344}
cf8f70bf 5345EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5346
8cfdc000
ZA		 5347static void tsc_bad(void *info)
5348{
0a3aee0d 5349 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5350}
5351
5352static void tsc_khz_changed(void *data)
c8076604 5353{
8cfdc000
ZA		 5354 struct cpufreq_freqs *freq = data;
5355 unsigned long khz = 0;
5356
5357 if (data)
5358 khz = freq->new;
5359 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5360 khz = cpufreq_quick_get(raw_smp_processor_id());
5361 if (!khz)
5362 khz = tsc_khz;
0a3aee0d 5363 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5364}
5365
c8076604
GH		 5366static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5367 void *data)
5368{
5369 struct cpufreq_freqs *freq = data;
5370 struct kvm *kvm;
5371 struct kvm_vcpu *vcpu;
5372 int i, send_ipi = 0;
5373
8cfdc000
ZA		 5374 /*
5375 * We allow guests to temporarily run on slowing clocks,
5376 * provided we notify them after, or to run on accelerating
5377 * clocks, provided we notify them before. Thus time never
5378 * goes backwards.
5379 *
5380 * However, we have a problem. We can't atomically update
5381 * the frequency of a given CPU from this function; it is
5382 * merely a notifier, which can be called from any CPU.
5383 * Changing the TSC frequency at arbitrary points in time
5384 * requires a recomputation of local variables related to
5385 * the TSC for each VCPU. We must flag these local variables
5386 * to be updated and be sure the update takes place with the
5387 * new frequency before any guests proceed.
5388 *
5389 * Unfortunately, the combination of hotplug CPU and frequency
5390 * change creates an intractable locking scenario; the order
5391 * of when these callouts happen is undefined with respect to
5392 * CPU hotplug, and they can race with each other. As such,
5393 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5394 * undefined; you can actually have a CPU frequency change take
5395 * place in between the computation of X and the setting of the
5396 * variable. To protect against this problem, all updates of
5397 * the per_cpu tsc_khz variable are done in an interrupt
5398 * protected IPI, and all callers wishing to update the value
5399 * must wait for a synchronous IPI to complete (which is trivial
5400 * if the caller is on the CPU already). This establishes the
5401 * necessary total order on variable updates.
5402 *
5403 * Note that because a guest time update may take place
5404 * anytime after the setting of the VCPU's request bit, the
5405 * correct TSC value must be set before the request. However,
5406 * to ensure the update actually makes it to any guest which
5407 * starts running in hardware virtualization between the set
5408 * and the acquisition of the spinlock, we must also ping the
5409 * CPU after setting the request bit.
5410 *
5411 */
5412
c8076604
GH		 5413 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5414 return 0;
5415 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5416 return 0;
8cfdc000
ZA		 5417
5418 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5419
2f303b74 5420 spin_lock(&kvm_lock);
c8076604 5421 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5422 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5423 if (vcpu->cpu != freq->cpu)
5424 continue;
c285545f 5425 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5426 if (vcpu->cpu != smp_processor_id())
8cfdc000 5427 send_ipi = 1;
c8076604
GH		 5428 }
5429 }
2f303b74 5430 spin_unlock(&kvm_lock);
c8076604
GH		 5431
5432 if (freq->old < freq->new && send_ipi) {
5433 /*
5434 * We upscale the frequency. Must make the guest
5435 * doesn't see old kvmclock values while running with
5436 * the new frequency, otherwise we risk the guest sees
5437 * time go backwards.
5438 *
5439 * In case we update the frequency for another cpu
5440 * (which might be in guest context) send an interrupt
5441 * to kick the cpu out of guest context. Next time
5442 * guest context is entered kvmclock will be updated,
5443 * so the guest will not see stale values.
5444 */
8cfdc000 5445 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5446 }
5447 return 0;
5448}
5449
5450static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5451 .notifier_call = kvmclock_cpufreq_notifier
5452};
5453
5454static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5455 unsigned long action, void *hcpu)
5456{
5457 unsigned int cpu = (unsigned long)hcpu;
5458
5459 switch (action) {
5460 case CPU_ONLINE:
5461 case CPU_DOWN_FAILED:
5462 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5463 break;
5464 case CPU_DOWN_PREPARE:
5465 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5466 break;
5467 }
5468 return NOTIFY_OK;
5469}
5470
5471static struct notifier_block kvmclock_cpu_notifier_block = {
5472 .notifier_call = kvmclock_cpu_notifier,
5473 .priority = -INT_MAX
c8076604
GH		 5474};
5475
b820cc0c
ZA		 5476static void kvm_timer_init(void)
5477{
5478 int cpu;
5479
c285545f 5480 max_tsc_khz = tsc_khz;
460dd42e
SB		 5481
5482 cpu_notifier_register_begin();
b820cc0c 5483 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5484#ifdef CONFIG_CPU_FREQ
5485 struct cpufreq_policy policy;
5486 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5487 cpu = get_cpu();
5488 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5489 if (policy.cpuinfo.max_freq)
5490 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5491 put_cpu();
c285545f 5492#endif
b820cc0c
ZA		 5493 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5494 CPUFREQ_TRANSITION_NOTIFIER);
5495 }
c285545f 5496 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5497 for_each_online_cpu(cpu)
5498 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5499
5500 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5501 cpu_notifier_register_done();
5502
b820cc0c
ZA		 5503}
5504
ff9d07a0
ZY		 5505static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5506
f5132b01 5507int kvm_is_in_guest(void)
ff9d07a0 5508{
086c9855 5509 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5510}
5511
5512static int kvm_is_user_mode(void)
5513{
5514 int user_mode = 3;
dcf46b94 5515
086c9855
AS		 5516 if (__this_cpu_read(current_vcpu))
5517 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5518
ff9d07a0
ZY		 5519 return user_mode != 0;
5520}
5521
5522static unsigned long kvm_get_guest_ip(void)
5523{
5524 unsigned long ip = 0;
dcf46b94 5525
086c9855
AS		 5526 if (__this_cpu_read(current_vcpu))
5527 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5528
ff9d07a0
ZY		 5529 return ip;
5530}
5531
5532static struct perf_guest_info_callbacks kvm_guest_cbs = {
5533 .is_in_guest = kvm_is_in_guest,
5534 .is_user_mode = kvm_is_user_mode,
5535 .get_guest_ip = kvm_get_guest_ip,
5536};
5537
5538void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5539{
086c9855 5540 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5541}
5542EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5543
5544void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5545{
086c9855 5546 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5547}
5548EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5549
ce88decf
XG		 5550static void kvm_set_mmio_spte_mask(void)
5551{
5552 u64 mask;
5553 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5554
5555 /*
5556 * Set the reserved bits and the present bit of an paging-structure
5557 * entry to generate page fault with PFER.RSV = 1.
5558 */
885032b9
XG		 5559 /* Mask the reserved physical address bits. */
5560 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5561
5562 /* Bit 62 is always reserved for 32bit host. */
5563 mask |= 0x3ull << 62;
5564
5565 /* Set the present bit. */
ce88decf
XG		 5566 mask |= 1ull;
5567
5568#ifdef CONFIG_X86_64
5569 /*
5570 * If reserved bit is not supported, clear the present bit to disable
5571 * mmio page fault.
5572 */
5573 if (maxphyaddr == 52)
5574 mask &= ~1ull;
5575#endif
5576
5577 kvm_mmu_set_mmio_spte_mask(mask);
5578}
5579
16e8d74d
MT		 5580#ifdef CONFIG_X86_64
5581static void pvclock_gtod_update_fn(struct work_struct *work)
5582{
d828199e
MT		 5583 struct kvm *kvm;
5584
5585 struct kvm_vcpu *vcpu;
5586 int i;
5587
2f303b74 5588 spin_lock(&kvm_lock);
d828199e
MT		 5589 list_for_each_entry(kvm, &vm_list, vm_list)
5590 kvm_for_each_vcpu(i, vcpu, kvm)
5591 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5592 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5593 spin_unlock(&kvm_lock);
16e8d74d
MT		 5594}
5595
5596static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5597
5598/*
5599 * Notification about pvclock gtod data update.
5600 */
5601static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5602 void *priv)
5603{
5604 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5605 struct timekeeper *tk = priv;
5606
5607 update_pvclock_gtod(tk);
5608
5609 /* disable master clock if host does not trust, or does not
5610 * use, TSC clocksource
5611 */
5612 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5613 atomic_read(&kvm_guest_has_master_clock) != 0)
5614 queue_work(system_long_wq, &pvclock_gtod_work);
5615
5616 return 0;
5617}
5618
5619static struct notifier_block pvclock_gtod_notifier = {
5620 .notifier_call = pvclock_gtod_notify,
5621};
5622#endif
5623
f8c16bba 5624int kvm_arch_init(void *opaque)
043405e1 5625{
b820cc0c 5626 int r;
6b61edf7 5627 struct kvm_x86_ops *ops = opaque;
f8c16bba 5628
f8c16bba
ZX		 5629 if (kvm_x86_ops) {
5630 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5631 r = -EEXIST;
5632 goto out;
f8c16bba
ZX		 5633 }
5634
5635 if (!ops->cpu_has_kvm_support()) {
5636 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5637 r = -EOPNOTSUPP;
5638 goto out;
f8c16bba
ZX		 5639 }
5640 if (ops->disabled_by_bios()) {
5641 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5642 r = -EOPNOTSUPP;
5643 goto out;
f8c16bba
ZX		 5644 }
5645
013f6a5d
MT		 5646 r = -ENOMEM;
5647 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5648 if (!shared_msrs) {
5649 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5650 goto out;
5651 }
5652
97db56ce
AK		 5653 r = kvm_mmu_module_init();
5654 if (r)
013f6a5d 5655 goto out_free_percpu;
97db56ce 5656
ce88decf 5657 kvm_set_mmio_spte_mask();
97db56ce 5658
f8c16bba 5659 kvm_x86_ops = ops;
920c8377
PB		 5660 kvm_init_msr_list();
5661
7b52345e 5662 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5663 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5664
b820cc0c 5665 kvm_timer_init();
c8076604 5666
ff9d07a0
ZY		 5667 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5668
2acf923e
DC		 5669 if (cpu_has_xsave)
5670 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5671
c5cc421b 5672 kvm_lapic_init();
16e8d74d
MT		 5673#ifdef CONFIG_X86_64
5674 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5675#endif
5676
f8c16bba 5677 return 0;
56c6d28a 5678
013f6a5d
MT		 5679out_free_percpu:
5680 free_percpu(shared_msrs);
56c6d28a 5681out:
56c6d28a 5682 return r;
043405e1 5683}
8776e519 5684
f8c16bba
ZX		 5685void kvm_arch_exit(void)
5686{
ff9d07a0
ZY		 5687 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5688
888d256e
JK		 5689 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5690 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5691 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5692 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5693#ifdef CONFIG_X86_64
5694 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5695#endif
f8c16bba 5696 kvm_x86_ops = NULL;
56c6d28a 5697 kvm_mmu_module_exit();
013f6a5d 5698 free_percpu(shared_msrs);
56c6d28a 5699}
f8c16bba 5700
8776e519
HB		 5701int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5702{
5703 ++vcpu->stat.halt_exits;
5704 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5705 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5706 return 1;
5707 } else {
5708 vcpu->run->exit_reason = KVM_EXIT_HLT;
5709 return 0;
5710 }
5711}
5712EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5713
55cd8e5a
GN		 5714int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5715{
5716 u64 param, ingpa, outgpa, ret;
5717 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5718 bool fast, longmode;
55cd8e5a
GN		 5719
5720 /*
5721 * hypercall generates UD from non zero cpl and real mode
5722 * per HYPER-V spec
5723 */
3eeb3288 5724 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5725 kvm_queue_exception(vcpu, UD_VECTOR);
5726 return 0;
5727 }
5728
a449c7aa 5729 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5730
5731 if (!longmode) {
ccd46936
GN		 5732 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5733 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5734 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5735 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5736 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5737 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5738 }
5739#ifdef CONFIG_X86_64
5740 else {
5741 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5742 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5743 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5744 }
5745#endif
5746
5747 code = param & 0xffff;
5748 fast = (param >> 16) & 0x1;
5749 rep_cnt = (param >> 32) & 0xfff;
5750 rep_idx = (param >> 48) & 0xfff;
5751
5752 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5753
c25bc163
GN		 5754 switch (code) {
5755 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5756 kvm_vcpu_on_spin(vcpu);
5757 break;
5758 default:
5759 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5760 break;
5761 }
55cd8e5a
GN		 5762
5763 ret = res | (((u64)rep_done & 0xfff) << 32);
5764 if (longmode) {
5765 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5766 } else {
5767 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5768 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5769 }
5770
5771 return 1;
5772}
5773
6aef266c
SV		 5774/*
5775 * kvm_pv_kick_cpu_op: Kick a vcpu.
5776 *
5777 * @apicid - apicid of vcpu to be kicked.
5778 */
5779static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5780{
24d2166b 5781 struct kvm_lapic_irq lapic_irq;
6aef266c 5782
24d2166b
R		 5783 lapic_irq.shorthand = 0;
5784 lapic_irq.dest_mode = 0;
5785 lapic_irq.dest_id = apicid;
6aef266c 5786
24d2166b
R		 5787 lapic_irq.delivery_mode = APIC_DM_REMRD;
5788 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5789}
5790
8776e519
HB		 5791int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5792{
5793 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5794 int op_64_bit, r = 1;
8776e519 5795
55cd8e5a
GN		 5796 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5797 return kvm_hv_hypercall(vcpu);
5798
5fdbf976
MT		 5799 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5800 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5801 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5802 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5803 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5804
229456fc 5805 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5806
a449c7aa
NA		 5807 op_64_bit = is_64_bit_mode(vcpu);
5808 if (!op_64_bit) {
8776e519
HB		 5809 nr &= 0xFFFFFFFF;
5810 a0 &= 0xFFFFFFFF;
5811 a1 &= 0xFFFFFFFF;
5812 a2 &= 0xFFFFFFFF;
5813 a3 &= 0xFFFFFFFF;
5814 }
5815
07708c4a
JK		 5816 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5817 ret = -KVM_EPERM;
5818 goto out;
5819 }
5820
8776e519 5821 switch (nr) {
b93463aa
AK		 5822 case KVM_HC_VAPIC_POLL_IRQ:
5823 ret = 0;
5824 break;
6aef266c
SV		 5825 case KVM_HC_KICK_CPU:
5826 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5827 ret = 0;
5828 break;
8776e519
HB		 5829 default:
5830 ret = -KVM_ENOSYS;
5831 break;
5832 }
07708c4a 5833out:
a449c7aa
NA		 5834 if (!op_64_bit)
5835 ret = (u32)ret;
5fdbf976 5836 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5837 ++vcpu->stat.hypercalls;
2f333bcb 5838 return r;
8776e519
HB		 5839}
5840EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5841
b6785def 5842static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5843{
d6aa1000 5844 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5845 char instruction[3];
5fdbf976 5846 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5847
8776e519 5848 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5849
9d74191a 5850 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5851}
5852
b6c7a5dc
HB		 5853/*
5854 * Check if userspace requested an interrupt window, and that the
5855 * interrupt window is open.
5856 *
5857 * No need to exit to userspace if we already have an interrupt queued.
5858 */
851ba692 5859static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5860{
8061823a 5861 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5862 vcpu->run->request_interrupt_window &&
5df56646 5863 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5864}
5865
851ba692 5866static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5867{
851ba692
AK		 5868 struct kvm_run *kvm_run = vcpu->run;
5869
91586a3b 5870 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5871 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5872 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5873 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5874 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5875 else
b6c7a5dc 5876 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5877 kvm_arch_interrupt_allowed(vcpu) &&
5878 !kvm_cpu_has_interrupt(vcpu) &&
5879 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5880}
5881
95ba8273
GN		 5882static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5883{
5884 int max_irr, tpr;
5885
5886 if (!kvm_x86_ops->update_cr8_intercept)
5887 return;
5888
88c808fd
AK		 5889 if (!vcpu->arch.apic)
5890 return;
5891
8db3baa2
GN		 5892 if (!vcpu->arch.apic->vapic_addr)
5893 max_irr = kvm_lapic_find_highest_irr(vcpu);
5894 else
5895 max_irr = -1;
95ba8273
GN		 5896
5897 if (max_irr != -1)
5898 max_irr >>= 4;
5899
5900 tpr = kvm_lapic_get_cr8(vcpu);
5901
5902 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5903}
5904
b6b8a145 5905static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5906{
b6b8a145
JK		 5907 int r;
5908
95ba8273 5909 /* try to reinject previous events if any */
b59bb7bd 5910 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5911 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5912 vcpu->arch.exception.has_error_code,
5913 vcpu->arch.exception.error_code);
d6e8c854
NA		 5914
5915 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5916 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5917 X86_EFLAGS_RF);
5918
b59bb7bd
GN		 5919 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5920 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5921 vcpu->arch.exception.error_code,
5922 vcpu->arch.exception.reinject);
b6b8a145 5923 return 0;
b59bb7bd
GN		 5924 }
5925
95ba8273
GN		 5926 if (vcpu->arch.nmi_injected) {
5927 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5928 return 0;
95ba8273
GN		 5929 }
5930
5931 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5932 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5933 return 0;
5934 }
5935
5936 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5937 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5938 if (r != 0)
5939 return r;
95ba8273
GN		 5940 }
5941
5942 /* try to inject new event if pending */
5943 if (vcpu->arch.nmi_pending) {
5944 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5945 --vcpu->arch.nmi_pending;
95ba8273
GN		 5946 vcpu->arch.nmi_injected = true;
5947 kvm_x86_ops->set_nmi(vcpu);
5948 }
c7c9c56c 5949 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5950 /*
5951 * Because interrupts can be injected asynchronously, we are
5952 * calling check_nested_events again here to avoid a race condition.
5953 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5954 * proposal and current concerns. Perhaps we should be setting
5955 * KVM_REQ_EVENT only on certain events and not unconditionally?
5956 */
5957 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5958 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5959 if (r != 0)
5960 return r;
5961 }
95ba8273 5962 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5963 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5964 false);
5965 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5966 }
5967 }
b6b8a145 5968 return 0;
95ba8273
GN		 5969}
5970
7460fb4a
AK		 5971static void process_nmi(struct kvm_vcpu *vcpu)
5972{
5973 unsigned limit = 2;
5974
5975 /*
5976 * x86 is limited to one NMI running, and one NMI pending after it.
5977 * If an NMI is already in progress, limit further NMIs to just one.
5978 * Otherwise, allow two (and we'll inject the first one immediately).
5979 */
5980 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5981 limit = 1;
5982
5983 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5984 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5985 kvm_make_request(KVM_REQ_EVENT, vcpu);
5986}
5987
3d81bc7e 5988static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5989{
5990 u64 eoi_exit_bitmap[4];
cf9e65b7 5991 u32 tmr[8];
c7c9c56c 5992
3d81bc7e
YZ		 5993 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5994 return;
c7c9c56c
YZ		 5995
5996 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5997 memset(tmr, 0, 32);
c7c9c56c 5998
cf9e65b7 5999 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6000 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6001 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6002}
6003
9357d939
TY		 6004/*
6005 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6006 * exiting to the userspace. Otherwise, the value will be returned to the
6007 * userspace.
6008 */
851ba692 6009static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6010{
6011 int r;
6a8b1d13 6012 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6013 vcpu->run->request_interrupt_window;
730dca42 6014 bool req_immediate_exit = false;
b6c7a5dc 6015
3e007509 6016 if (vcpu->requests) {
a8eeb04a 6017 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6018 kvm_mmu_unload(vcpu);
a8eeb04a 6019 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6020 __kvm_migrate_timers(vcpu);
d828199e
MT		 6021 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6022 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6023 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6024 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6025 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6026 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6027 if (unlikely(r))
6028 goto out;
6029 }
a8eeb04a 6030 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6031 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6032 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 6033 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 6034 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6035 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6036 r = 0;
6037 goto out;
6038 }
a8eeb04a 6039 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6040 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6041 r = 0;
6042 goto out;
6043 }
a8eeb04a 6044 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6045 vcpu->fpu_active = 0;
6046 kvm_x86_ops->fpu_deactivate(vcpu);
6047 }
af585b92
GN		 6048 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6049 /* Page is swapped out. Do synthetic halt */
6050 vcpu->arch.apf.halted = true;
6051 r = 1;
6052 goto out;
6053 }
c9aaa895
GC		 6054 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6055 record_steal_time(vcpu);
7460fb4a
AK		 6056 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6057 process_nmi(vcpu);
f5132b01
GN		 6058 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6059 kvm_handle_pmu_event(vcpu);
6060 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6061 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6062 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6063 vcpu_scan_ioapic(vcpu);
2f52d58c 6064 }
b93463aa 6065
b463a6f7 6066 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6067 kvm_apic_accept_events(vcpu);
6068 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6069 r = 1;
6070 goto out;
6071 }
6072
b6b8a145
JK		 6073 if (inject_pending_event(vcpu, req_int_win) != 0)
6074 req_immediate_exit = true;
b463a6f7 6075 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6076 else if (vcpu->arch.nmi_pending)
c9a7953f 6077 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6078 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6079 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6080
6081 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6082 /*
6083 * Update architecture specific hints for APIC
6084 * virtual interrupt delivery.
6085 */
6086 if (kvm_x86_ops->hwapic_irr_update)
6087 kvm_x86_ops->hwapic_irr_update(vcpu,
6088 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6089 update_cr8_intercept(vcpu);
6090 kvm_lapic_sync_to_vapic(vcpu);
6091 }
6092 }
6093
d8368af8
AK		 6094 r = kvm_mmu_reload(vcpu);
6095 if (unlikely(r)) {
d905c069 6096 goto cancel_injection;
d8368af8
AK		 6097 }
6098
b6c7a5dc
HB		 6099 preempt_disable();
6100
6101 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6102 if (vcpu->fpu_active)
6103 kvm_load_guest_fpu(vcpu);
2acf923e 6104 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6105
6b7e2d09
XG		 6106 vcpu->mode = IN_GUEST_MODE;
6107
01b71917
MT		 6108 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6109
6b7e2d09
XG		 6110 /* We should set ->mode before check ->requests,
6111 * see the comment in make_all_cpus_request.
6112 */
01b71917 6113 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6114
d94e1dc9 6115 local_irq_disable();
32f88400 6116
6b7e2d09 6117 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6118 || need_resched() || signal_pending(current)) {
6b7e2d09 6119 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6120 smp_wmb();
6c142801
AK		 6121 local_irq_enable();
6122 preempt_enable();
01b71917 6123 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6124 r = 1;
d905c069 6125 goto cancel_injection;
6c142801
AK		 6126 }
6127
d6185f20
NHE		 6128 if (req_immediate_exit)
6129 smp_send_reschedule(vcpu->cpu);
6130
b6c7a5dc
HB		 6131 kvm_guest_enter();
6132
42dbaa5a 6133 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6134 set_debugreg(0, 7);
6135 set_debugreg(vcpu->arch.eff_db[0], 0);
6136 set_debugreg(vcpu->arch.eff_db[1], 1);
6137 set_debugreg(vcpu->arch.eff_db[2], 2);
6138 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6139 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6140 }
b6c7a5dc 6141
229456fc 6142 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6143 kvm_x86_ops->run(vcpu);
b6c7a5dc 6144
c77fb5fe
PB		 6145 /*
6146 * Do this here before restoring debug registers on the host. And
6147 * since we do this before handling the vmexit, a DR access vmexit
6148 * can (a) read the correct value of the debug registers, (b) set
6149 * KVM_DEBUGREG_WONT_EXIT again.
6150 */
6151 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6152 int i;
6153
6154 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6155 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6156 for (i = 0; i < KVM_NR_DB_REGS; i++)
6157 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6158 }
6159
24f1e32c
FW		 6160 /*
6161 * If the guest has used debug registers, at least dr7
6162 * will be disabled while returning to the host.
6163 * If we don't have active breakpoints in the host, we don't
6164 * care about the messed up debug address registers. But if
6165 * we have some of them active, restore the old state.
6166 */
59d8eb53 6167 if (hw_breakpoint_active())
24f1e32c 6168 hw_breakpoint_restore();
42dbaa5a 6169
886b470c
MT		 6170 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6171 native_read_tsc());
1d5f066e 6172
6b7e2d09 6173 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6174 smp_wmb();
a547c6db
YZ		 6175
6176 /* Interrupt is enabled by handle_external_intr() */
6177 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6178
6179 ++vcpu->stat.exits;
6180
6181 /*
6182 * We must have an instruction between local_irq_enable() and
6183 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6184 * the interrupt shadow. The stat.exits increment will do nicely.
6185 * But we need to prevent reordering, hence this barrier():
6186 */
6187 barrier();
6188
6189 kvm_guest_exit();
6190
6191 preempt_enable();
6192
f656ce01 6193 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6194
b6c7a5dc
HB		 6195 /*
6196 * Profile KVM exit RIPs:
6197 */
6198 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6199 unsigned long rip = kvm_rip_read(vcpu);
6200 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6201 }
6202
cc578287
ZA		 6203 if (unlikely(vcpu->arch.tsc_always_catchup))
6204 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6205
5cfb1d5a
MT		 6206 if (vcpu->arch.apic_attention)
6207 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6208
851ba692 6209 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6210 return r;
6211
6212cancel_injection:
6213 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6214 if (unlikely(vcpu->arch.apic_attention))
6215 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6216out:
6217 return r;
6218}
b6c7a5dc 6219
09cec754 6220
851ba692 6221static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6222{
6223 int r;
f656ce01 6224 struct kvm *kvm = vcpu->kvm;
d7690175 6225
f656ce01 6226 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6227
6228 r = 1;
6229 while (r > 0) {
af585b92
GN		 6230 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6231 !vcpu->arch.apf.halted)
851ba692 6232 r = vcpu_enter_guest(vcpu);
d7690175 6233 else {
f656ce01 6234 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6235 kvm_vcpu_block(vcpu);
f656ce01 6236 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6237 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6238 kvm_apic_accept_events(vcpu);
09cec754
GN		 6239 switch(vcpu->arch.mp_state) {
6240 case KVM_MP_STATE_HALTED:
6aef266c 6241 vcpu->arch.pv.pv_unhalted = false;
d7690175 6242 vcpu->arch.mp_state =
09cec754
GN		 6243 KVM_MP_STATE_RUNNABLE;
6244 case KVM_MP_STATE_RUNNABLE:
af585b92 6245 vcpu->arch.apf.halted = false;
09cec754 6246 break;
66450a21
JK		 6247 case KVM_MP_STATE_INIT_RECEIVED:
6248 break;
09cec754
GN		 6249 default:
6250 r = -EINTR;
6251 break;
6252 }
6253 }
d7690175
MT		 6254 }
6255
09cec754
GN		 6256 if (r <= 0)
6257 break;
6258
6259 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6260 if (kvm_cpu_has_pending_timer(vcpu))
6261 kvm_inject_pending_timer_irqs(vcpu);
6262
851ba692 6263 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6264 r = -EINTR;
851ba692 6265 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6266 ++vcpu->stat.request_irq_exits;
6267 }
af585b92
GN		 6268
6269 kvm_check_async_pf_completion(vcpu);
6270
09cec754
GN		 6271 if (signal_pending(current)) {
6272 r = -EINTR;
851ba692 6273 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6274 ++vcpu->stat.signal_exits;
6275 }
6276 if (need_resched()) {
f656ce01 6277 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6278 cond_resched();
f656ce01 6279 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6280 }
b6c7a5dc
HB		 6281 }
6282
f656ce01 6283 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6284
6285 return r;
6286}
6287
716d51ab
GN		 6288static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6289{
6290 int r;
6291 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6292 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6293 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6294 if (r != EMULATE_DONE)
6295 return 0;
6296 return 1;
6297}
6298
6299static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6300{
6301 BUG_ON(!vcpu->arch.pio.count);
6302
6303 return complete_emulated_io(vcpu);
6304}
6305
f78146b0
AK		 6306/*
6307 * Implements the following, as a state machine:
6308 *
6309 * read:
6310 * for each fragment
87da7e66
XG		 6311 * for each mmio piece in the fragment
6312 * write gpa, len
6313 * exit
6314 * copy data
f78146b0
AK		 6315 * execute insn
6316 *
6317 * write:
6318 * for each fragment
87da7e66
XG		 6319 * for each mmio piece in the fragment
6320 * write gpa, len
6321 * copy data
6322 * exit
f78146b0 6323 */
716d51ab 6324static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6325{
6326 struct kvm_run *run = vcpu->run;
f78146b0 6327 struct kvm_mmio_fragment *frag;
87da7e66 6328 unsigned len;
5287f194 6329
716d51ab 6330 BUG_ON(!vcpu->mmio_needed);
5287f194 6331
716d51ab 6332 /* Complete previous fragment */
87da7e66
XG		 6333 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6334 len = min(8u, frag->len);
716d51ab 6335 if (!vcpu->mmio_is_write)
87da7e66
XG		 6336 memcpy(frag->data, run->mmio.data, len);
6337
6338 if (frag->len <= 8) {
6339 /* Switch to the next fragment. */
6340 frag++;
6341 vcpu->mmio_cur_fragment++;
6342 } else {
6343 /* Go forward to the next mmio piece. */
6344 frag->data += len;
6345 frag->gpa += len;
6346 frag->len -= len;
6347 }
6348
a08d3b3b 6349 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6350 vcpu->mmio_needed = 0;
0912c977
PB		 6351
6352 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6353 if (vcpu->mmio_is_write)
716d51ab
GN		 6354 return 1;
6355 vcpu->mmio_read_completed = 1;
6356 return complete_emulated_io(vcpu);
6357 }
87da7e66 6358
716d51ab
GN		 6359 run->exit_reason = KVM_EXIT_MMIO;
6360 run->mmio.phys_addr = frag->gpa;
6361 if (vcpu->mmio_is_write)
87da7e66
XG		 6362 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6363 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6364 run->mmio.is_write = vcpu->mmio_is_write;
6365 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6366 return 0;
5287f194
AK		 6367}
6368
716d51ab 6369
b6c7a5dc
HB		 6370int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6371{
6372 int r;
6373 sigset_t sigsaved;
6374
e5c30142
AK		 6375 if (!tsk_used_math(current) && init_fpu(current))
6376 return -ENOMEM;
6377
ac9f6dc0
AK		 6378 if (vcpu->sigset_active)
6379 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6380
a4535290 6381 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6382 kvm_vcpu_block(vcpu);
66450a21 6383 kvm_apic_accept_events(vcpu);
d7690175 6384 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6385 r = -EAGAIN;
6386 goto out;
b6c7a5dc
HB		 6387 }
6388
b6c7a5dc 6389 /* re-sync apic's tpr */
eea1cff9
AP		 6390 if (!irqchip_in_kernel(vcpu->kvm)) {
6391 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6392 r = -EINVAL;
6393 goto out;
6394 }
6395 }
b6c7a5dc 6396
716d51ab
GN		 6397 if (unlikely(vcpu->arch.complete_userspace_io)) {
6398 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6399 vcpu->arch.complete_userspace_io = NULL;
6400 r = cui(vcpu);
6401 if (r <= 0)
6402 goto out;
6403 } else
6404 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6405
851ba692 6406 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6407
6408out:
f1d86e46 6409 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6410 if (vcpu->sigset_active)
6411 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6412
b6c7a5dc
HB		 6413 return r;
6414}
6415
6416int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6417{
7ae441ea
GN		 6418 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6419 /*
6420 * We are here if userspace calls get_regs() in the middle of
6421 * instruction emulation. Registers state needs to be copied
4a969980 6422 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6423 * that usually, but some bad designed PV devices (vmware
6424 * backdoor interface) need this to work
6425 */
dd856efa 6426 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6427 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6428 }
5fdbf976
MT		 6429 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6430 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6431 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6432 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6433 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6434 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6435 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6436 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6437#ifdef CONFIG_X86_64
5fdbf976
MT		 6438 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6439 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6440 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6441 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6442 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6443 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6444 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6445 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6446#endif
6447
5fdbf976 6448 regs->rip = kvm_rip_read(vcpu);
91586a3b 6449 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6450
b6c7a5dc
HB		 6451 return 0;
6452}
6453
6454int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6455{
7ae441ea
GN		 6456 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6457 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6458
5fdbf976
MT		 6459 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6460 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6461 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6462 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6463 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6464 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6465 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6466 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6467#ifdef CONFIG_X86_64
5fdbf976
MT		 6468 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6469 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6470 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6471 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6472 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6473 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6474 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6475 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6476#endif
6477
5fdbf976 6478 kvm_rip_write(vcpu, regs->rip);
91586a3b 6479 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6480
b4f14abd
JK		 6481 vcpu->arch.exception.pending = false;
6482
3842d135
AK		 6483 kvm_make_request(KVM_REQ_EVENT, vcpu);
6484
b6c7a5dc
HB		 6485 return 0;
6486}
6487
b6c7a5dc
HB		 6488void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6489{
6490 struct kvm_segment cs;
6491
3e6e0aab 6492 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6493 *db = cs.db;
6494 *l = cs.l;
6495}
6496EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6497
6498int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6499 struct kvm_sregs *sregs)
6500{
89a27f4d 6501 struct desc_ptr dt;
b6c7a5dc 6502
3e6e0aab
GT		 6503 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6504 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6505 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6506 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6507 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6508 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6509
3e6e0aab
GT		 6510 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6511 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6512
6513 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6514 sregs->idt.limit = dt.size;
6515 sregs->idt.base = dt.address;
b6c7a5dc 6516 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6517 sregs->gdt.limit = dt.size;
6518 sregs->gdt.base = dt.address;
b6c7a5dc 6519
4d4ec087 6520 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6521 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6522 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6523 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6524 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6525 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6526 sregs->apic_base = kvm_get_apic_base(vcpu);
6527
923c61bb 6528 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6529
36752c9b 6530 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6531 set_bit(vcpu->arch.interrupt.nr,
6532 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6533
b6c7a5dc
HB		 6534 return 0;
6535}
6536
62d9f0db
MT		 6537int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6538 struct kvm_mp_state *mp_state)
6539{
66450a21 6540 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6541 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6542 vcpu->arch.pv.pv_unhalted)
6543 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6544 else
6545 mp_state->mp_state = vcpu->arch.mp_state;
6546
62d9f0db
MT		 6547 return 0;
6548}
6549
6550int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6551 struct kvm_mp_state *mp_state)
6552{
66450a21
JK		 6553 if (!kvm_vcpu_has_lapic(vcpu) &&
6554 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6555 return -EINVAL;
6556
6557 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6558 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6559 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6560 } else
6561 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6562 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6563 return 0;
6564}
6565
7f3d35fd
KW		 6566int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6567 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6568{
9d74191a 6569 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6570 int ret;
e01c2426 6571
8ec4722d 6572 init_emulate_ctxt(vcpu);
c697518a 6573
7f3d35fd 6574 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6575 has_error_code, error_code);
c697518a 6576
c697518a 6577 if (ret)
19d04437 6578 return EMULATE_FAIL;
37817f29 6579
9d74191a
TY		 6580 kvm_rip_write(vcpu, ctxt->eip);
6581 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6582 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6583 return EMULATE_DONE;
37817f29
IE		 6584}
6585EXPORT_SYMBOL_GPL(kvm_task_switch);
6586
b6c7a5dc
HB		 6587int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6588 struct kvm_sregs *sregs)
6589{
58cb628d 6590 struct msr_data apic_base_msr;
b6c7a5dc 6591 int mmu_reset_needed = 0;
63f42e02 6592 int pending_vec, max_bits, idx;
89a27f4d 6593 struct desc_ptr dt;
b6c7a5dc 6594
6d1068b3
PM		 6595 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6596 return -EINVAL;
6597
89a27f4d
GN		 6598 dt.size = sregs->idt.limit;
6599 dt.address = sregs->idt.base;
b6c7a5dc 6600 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6601 dt.size = sregs->gdt.limit;
6602 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6603 kvm_x86_ops->set_gdt(vcpu, &dt);
6604
ad312c7c 6605 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6606 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6607 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6608 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6609
2d3ad1f4 6610 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6611
f6801dff 6612 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6613 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6614 apic_base_msr.data = sregs->apic_base;
6615 apic_base_msr.host_initiated = true;
6616 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6617
4d4ec087 6618 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6619 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6620 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6621
fc78f519 6622 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6623 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6624 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6625 kvm_update_cpuid(vcpu);
63f42e02
XG		 6626
6627 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6628 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6629 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6630 mmu_reset_needed = 1;
6631 }
63f42e02 6632 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6633
6634 if (mmu_reset_needed)
6635 kvm_mmu_reset_context(vcpu);
6636
a50abc3b 6637 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6638 pending_vec = find_first_bit(
6639 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6640 if (pending_vec < max_bits) {
66fd3f7f 6641 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6642 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6643 }
6644
3e6e0aab
GT		 6645 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6646 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6647 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6648 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6649 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6650 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6651
3e6e0aab
GT		 6652 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6653 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6654
5f0269f5
ME		 6655 update_cr8_intercept(vcpu);
6656
9c3e4aab 6657 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6658 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6659 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6660 !is_protmode(vcpu))
9c3e4aab
MT		 6661 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6662
3842d135
AK		 6663 kvm_make_request(KVM_REQ_EVENT, vcpu);
6664
b6c7a5dc
HB		 6665 return 0;
6666}
6667
d0bfb940
JK		 6668int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6669 struct kvm_guest_debug *dbg)
b6c7a5dc 6670{
355be0b9 6671 unsigned long rflags;
ae675ef0 6672 int i, r;
b6c7a5dc 6673
4f926bf2
JK		 6674 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6675 r = -EBUSY;
6676 if (vcpu->arch.exception.pending)
2122ff5e 6677 goto out;
4f926bf2
JK		 6678 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6679 kvm_queue_exception(vcpu, DB_VECTOR);
6680 else
6681 kvm_queue_exception(vcpu, BP_VECTOR);
6682 }
6683
91586a3b
JK		 6684 /*
6685 * Read rflags as long as potentially injected trace flags are still
6686 * filtered out.
6687 */
6688 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6689
6690 vcpu->guest_debug = dbg->control;
6691 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6692 vcpu->guest_debug = 0;
6693
6694 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6695 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6696 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6697 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6698 } else {
6699 for (i = 0; i < KVM_NR_DB_REGS; i++)
6700 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6701 }
c8639010 6702 kvm_update_dr7(vcpu);
ae675ef0 6703
f92653ee
JK		 6704 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6705 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6706 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6707
91586a3b
JK		 6708 /*
6709 * Trigger an rflags update that will inject or remove the trace
6710 * flags.
6711 */
6712 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6713
c8639010 6714 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6715
4f926bf2 6716 r = 0;
d0bfb940 6717
2122ff5e 6718out:
b6c7a5dc
HB		 6719
6720 return r;
6721}
6722
8b006791
ZX		 6723/*
6724 * Translate a guest virtual address to a guest physical address.
6725 */
6726int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6727 struct kvm_translation *tr)
6728{
6729 unsigned long vaddr = tr->linear_address;
6730 gpa_t gpa;
f656ce01 6731 int idx;
8b006791 6732
f656ce01 6733 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6734 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6735 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6736 tr->physical_address = gpa;
6737 tr->valid = gpa != UNMAPPED_GVA;
6738 tr->writeable = 1;
6739 tr->usermode = 0;
8b006791
ZX		 6740
6741 return 0;
6742}
6743
d0752060
HB		 6744int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6745{
98918833
SY		 6746 struct i387_fxsave_struct *fxsave =
6747 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6748
d0752060
HB		 6749 memcpy(fpu->fpr, fxsave->st_space, 128);
6750 fpu->fcw = fxsave->cwd;
6751 fpu->fsw = fxsave->swd;
6752 fpu->ftwx = fxsave->twd;
6753 fpu->last_opcode = fxsave->fop;
6754 fpu->last_ip = fxsave->rip;
6755 fpu->last_dp = fxsave->rdp;
6756 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6757
d0752060
HB		 6758 return 0;
6759}
6760
6761int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6762{
98918833
SY		 6763 struct i387_fxsave_struct *fxsave =
6764 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6765
d0752060
HB		 6766 memcpy(fxsave->st_space, fpu->fpr, 128);
6767 fxsave->cwd = fpu->fcw;
6768 fxsave->swd = fpu->fsw;
6769 fxsave->twd = fpu->ftwx;
6770 fxsave->fop = fpu->last_opcode;
6771 fxsave->rip = fpu->last_ip;
6772 fxsave->rdp = fpu->last_dp;
6773 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6774
d0752060
HB		 6775 return 0;
6776}
6777
10ab25cd 6778int fx_init(struct kvm_vcpu *vcpu)
d0752060 6779{
10ab25cd
JK		 6780 int err;
6781
6782 err = fpu_alloc(&vcpu->arch.guest_fpu);
6783 if (err)
6784 return err;
6785
98918833 6786 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6787
2acf923e
DC		 6788 /*
6789 * Ensure guest xcr0 is valid for loading
6790 */
6791 vcpu->arch.xcr0 = XSTATE_FP;
6792
ad312c7c 6793 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6794
6795 return 0;
d0752060
HB		 6796}
6797EXPORT_SYMBOL_GPL(fx_init);
6798
98918833
SY		 6799static void fx_free(struct kvm_vcpu *vcpu)
6800{
6801 fpu_free(&vcpu->arch.guest_fpu);
6802}
6803
d0752060
HB		 6804void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6805{
2608d7a1 6806 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6807 return;
6808
2acf923e
DC		 6809 /*
6810 * Restore all possible states in the guest,
6811 * and assume host would use all available bits.
6812 * Guest xcr0 would be loaded later.
6813 */
6814 kvm_put_guest_xcr0(vcpu);
d0752060 6815 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6816 __kernel_fpu_begin();
98918833 6817 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6818 trace_kvm_fpu(1);
d0752060 6819}
d0752060
HB		 6820
6821void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6822{
2acf923e
DC		 6823 kvm_put_guest_xcr0(vcpu);
6824
d0752060
HB		 6825 if (!vcpu->guest_fpu_loaded)
6826 return;
6827
6828 vcpu->guest_fpu_loaded = 0;
98918833 6829 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6830 __kernel_fpu_end();
f096ed85 6831 ++vcpu->stat.fpu_reload;
a8eeb04a 6832 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6833 trace_kvm_fpu(0);
d0752060 6834}
e9b11c17
ZX		 6835
6836void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6837{
12f9a48f 6838 kvmclock_reset(vcpu);
7f1ea208 6839
f5f48ee1 6840 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6841 fx_free(vcpu);
e9b11c17
ZX		 6842 kvm_x86_ops->vcpu_free(vcpu);
6843}
6844
6845struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6846 unsigned int id)
6847{
6755bae8
ZA		 6848 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6849 printk_once(KERN_WARNING
6850 "kvm: SMP vm created on host with unstable TSC; "
6851 "guest TSC will not be reliable\n");
26e5215f
AK		 6852 return kvm_x86_ops->vcpu_create(kvm, id);
6853}
e9b11c17 6854
26e5215f
AK		 6855int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6856{
6857 int r;
e9b11c17 6858
0bed3b56 6859 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6860 r = vcpu_load(vcpu);
6861 if (r)
6862 return r;
57f252f2 6863 kvm_vcpu_reset(vcpu);
8a3c1a33 6864 kvm_mmu_setup(vcpu);
e9b11c17 6865 vcpu_put(vcpu);
e9b11c17 6866
26e5215f 6867 return r;
e9b11c17
ZX		 6868}
6869
42897d86
MT		 6870int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6871{
6872 int r;
8fe8ab46 6873 struct msr_data msr;
332967a3 6874 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6875
6876 r = vcpu_load(vcpu);
6877 if (r)
6878 return r;
8fe8ab46
WA		 6879 msr.data = 0x0;
6880 msr.index = MSR_IA32_TSC;
6881 msr.host_initiated = true;
6882 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6883 vcpu_put(vcpu);
6884
332967a3
AJ		 6885 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6886 KVMCLOCK_SYNC_PERIOD);
6887
42897d86
MT		 6888 return r;
6889}
6890
d40ccc62 6891void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6892{
9fc77441 6893 int r;
344d9588
GN		 6894 vcpu->arch.apf.msr_val = 0;
6895
9fc77441
MT		 6896 r = vcpu_load(vcpu);
6897 BUG_ON(r);
e9b11c17
ZX		 6898 kvm_mmu_unload(vcpu);
6899 vcpu_put(vcpu);
6900
98918833 6901 fx_free(vcpu);
e9b11c17
ZX		 6902 kvm_x86_ops->vcpu_free(vcpu);
6903}
6904
66450a21 6905void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6906{
7460fb4a
AK		 6907 atomic_set(&vcpu->arch.nmi_queued, 0);
6908 vcpu->arch.nmi_pending = 0;
448fa4a9 6909 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 6910 kvm_clear_interrupt_queue(vcpu);
6911 kvm_clear_exception_queue(vcpu);
448fa4a9 6912
42dbaa5a 6913 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6f43ed01 6914 vcpu->arch.dr6 = DR6_INIT;
73aaf249 6915 kvm_update_dr6(vcpu);
42dbaa5a 6916 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6917 kvm_update_dr7(vcpu);
42dbaa5a 6918
3842d135 6919 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6920 vcpu->arch.apf.msr_val = 0;
c9aaa895 6921 vcpu->arch.st.msr_val = 0;
3842d135 6922
12f9a48f
GC		 6923 kvmclock_reset(vcpu);
6924
af585b92
GN		 6925 kvm_clear_async_pf_completion_queue(vcpu);
6926 kvm_async_pf_hash_reset(vcpu);
6927 vcpu->arch.apf.halted = false;
3842d135 6928
f5132b01
GN		 6929 kvm_pmu_reset(vcpu);
6930
66f7b72e
JS		 6931 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6932 vcpu->arch.regs_avail = ~0;
6933 vcpu->arch.regs_dirty = ~0;
6934
57f252f2 6935 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6936}
6937
66450a21
JK		 6938void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6939{
6940 struct kvm_segment cs;
6941
6942 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6943 cs.selector = vector << 8;
6944 cs.base = vector << 12;
6945 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6946 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6947}
6948
10474ae8 6949int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6950{
ca84d1a2
ZA		 6951 struct kvm *kvm;
6952 struct kvm_vcpu *vcpu;
6953 int i;
0dd6a6ed
ZA		 6954 int ret;
6955 u64 local_tsc;
6956 u64 max_tsc = 0;
6957 bool stable, backwards_tsc = false;
18863bdd
AK		 6958
6959 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6960 ret = kvm_x86_ops->hardware_enable(garbage);
6961 if (ret != 0)
6962 return ret;
6963
6964 local_tsc = native_read_tsc();
6965 stable = !check_tsc_unstable();
6966 list_for_each_entry(kvm, &vm_list, vm_list) {
6967 kvm_for_each_vcpu(i, vcpu, kvm) {
6968 if (!stable && vcpu->cpu == smp_processor_id())
6969 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6970 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6971 backwards_tsc = true;
6972 if (vcpu->arch.last_host_tsc > max_tsc)
6973 max_tsc = vcpu->arch.last_host_tsc;
6974 }
6975 }
6976 }
6977
6978 /*
6979 * Sometimes, even reliable TSCs go backwards. This happens on
6980 * platforms that reset TSC during suspend or hibernate actions, but
6981 * maintain synchronization. We must compensate. Fortunately, we can
6982 * detect that condition here, which happens early in CPU bringup,
6983 * before any KVM threads can be running. Unfortunately, we can't
6984 * bring the TSCs fully up to date with real time, as we aren't yet far
6985 * enough into CPU bringup that we know how much real time has actually
6986 * elapsed; our helper function, get_kernel_ns() will be using boot
6987 * variables that haven't been updated yet.
6988 *
6989 * So we simply find the maximum observed TSC above, then record the
6990 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6991 * the adjustment will be applied. Note that we accumulate
6992 * adjustments, in case multiple suspend cycles happen before some VCPU
6993 * gets a chance to run again. In the event that no KVM threads get a
6994 * chance to run, we will miss the entire elapsed period, as we'll have
6995 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6996 * loose cycle time. This isn't too big a deal, since the loss will be
6997 * uniform across all VCPUs (not to mention the scenario is extremely
6998 * unlikely). It is possible that a second hibernate recovery happens
6999 * much faster than a first, causing the observed TSC here to be
7000 * smaller; this would require additional padding adjustment, which is
7001 * why we set last_host_tsc to the local tsc observed here.
7002 *
7003 * N.B. - this code below runs only on platforms with reliable TSC,
7004 * as that is the only way backwards_tsc is set above. Also note
7005 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7006 * have the same delta_cyc adjustment applied if backwards_tsc
7007 * is detected. Note further, this adjustment is only done once,
7008 * as we reset last_host_tsc on all VCPUs to stop this from being
7009 * called multiple times (one for each physical CPU bringup).
7010 *
4a969980 7011 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7012 * will be compensated by the logic in vcpu_load, which sets the TSC to
7013 * catchup mode. This will catchup all VCPUs to real time, but cannot
7014 * guarantee that they stay in perfect synchronization.
7015 */
7016 if (backwards_tsc) {
7017 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7018 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7019 list_for_each_entry(kvm, &vm_list, vm_list) {
7020 kvm_for_each_vcpu(i, vcpu, kvm) {
7021 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7022 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 7023 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
7024 &vcpu->requests);
0dd6a6ed
ZA		 7025 }
7026
7027 /*
7028 * We have to disable TSC offset matching.. if you were
7029 * booting a VM while issuing an S4 host suspend....
7030 * you may have some problem. Solving this issue is
7031 * left as an exercise to the reader.
7032 */
7033 kvm->arch.last_tsc_nsec = 0;
7034 kvm->arch.last_tsc_write = 0;
7035 }
7036
7037 }
7038 return 0;
e9b11c17
ZX		 7039}
7040
7041void kvm_arch_hardware_disable(void *garbage)
7042{
7043 kvm_x86_ops->hardware_disable(garbage);
3548bab5 7044 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 7045}
7046
7047int kvm_arch_hardware_setup(void)
7048{
7049 return kvm_x86_ops->hardware_setup();
7050}
7051
7052void kvm_arch_hardware_unsetup(void)
7053{
7054 kvm_x86_ops->hardware_unsetup();
7055}
7056
7057void kvm_arch_check_processor_compat(void *rtn)
7058{
7059 kvm_x86_ops->check_processor_compatibility(rtn);
7060}
7061
3e515705
AK		 7062bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7063{
7064 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7065}
7066
54e9818f
GN		 7067struct static_key kvm_no_apic_vcpu __read_mostly;
7068
e9b11c17
ZX		 7069int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7070{
7071 struct page *page;
7072 struct kvm *kvm;
7073 int r;
7074
7075 BUG_ON(vcpu->kvm == NULL);
7076 kvm = vcpu->kvm;
7077
6aef266c 7078 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7079 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7080 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7081 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7082 else
a4535290 7083 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7084
7085 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7086 if (!page) {
7087 r = -ENOMEM;
7088 goto fail;
7089 }
ad312c7c 7090 vcpu->arch.pio_data = page_address(page);
e9b11c17 7091
cc578287 7092 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7093
e9b11c17
ZX		 7094 r = kvm_mmu_create(vcpu);
7095 if (r < 0)
7096 goto fail_free_pio_data;
7097
7098 if (irqchip_in_kernel(kvm)) {
7099 r = kvm_create_lapic(vcpu);
7100 if (r < 0)
7101 goto fail_mmu_destroy;
54e9818f
GN		 7102 } else
7103 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7104
890ca9ae
HY		 7105 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7106 GFP_KERNEL);
7107 if (!vcpu->arch.mce_banks) {
7108 r = -ENOMEM;
443c39bc 7109 goto fail_free_lapic;
890ca9ae
HY		 7110 }
7111 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7112
f1797359
WY		 7113 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7114 r = -ENOMEM;
f5f48ee1 7115 goto fail_free_mce_banks;
f1797359 7116 }
f5f48ee1 7117
66f7b72e
JS		 7118 r = fx_init(vcpu);
7119 if (r)
7120 goto fail_free_wbinvd_dirty_mask;
7121
ba904635 7122 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7123 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7124
7125 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7126 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7127
af585b92 7128 kvm_async_pf_hash_reset(vcpu);
f5132b01 7129 kvm_pmu_init(vcpu);
af585b92 7130
e9b11c17 7131 return 0;
66f7b72e
JS		 7132fail_free_wbinvd_dirty_mask:
7133 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7134fail_free_mce_banks:
7135 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7136fail_free_lapic:
7137 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7138fail_mmu_destroy:
7139 kvm_mmu_destroy(vcpu);
7140fail_free_pio_data:
ad312c7c 7141 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7142fail:
7143 return r;
7144}
7145
7146void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7147{
f656ce01
MT		 7148 int idx;
7149
f5132b01 7150 kvm_pmu_destroy(vcpu);
36cb93fd 7151 kfree(vcpu->arch.mce_banks);
e9b11c17 7152 kvm_free_lapic(vcpu);
f656ce01 7153 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7154 kvm_mmu_destroy(vcpu);
f656ce01 7155 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7156 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7157 if (!irqchip_in_kernel(vcpu->kvm))
7158 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7159}
d19a9cd2 7160
e08b9637 7161int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7162{
e08b9637
CO		 7163 if (type)
7164 return -EINVAL;
7165
f05e70ac 7166 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7167 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7168 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7169 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7170
5550af4d
SY		 7171 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7172 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7173 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7174 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7175 &kvm->arch.irq_sources_bitmap);
5550af4d 7176
038f8c11 7177 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7178 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7179 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7180
7181 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7182
7e44e449 7183 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7184 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7185
d89f5eff 7186 return 0;
d19a9cd2
ZX		 7187}
7188
7189static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7190{
9fc77441
MT		 7191 int r;
7192 r = vcpu_load(vcpu);
7193 BUG_ON(r);
d19a9cd2
ZX		 7194 kvm_mmu_unload(vcpu);
7195 vcpu_put(vcpu);
7196}
7197
7198static void kvm_free_vcpus(struct kvm *kvm)
7199{
7200 unsigned int i;
988a2cae 7201 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7202
7203 /*
7204 * Unpin any mmu pages first.
7205 */
af585b92
GN		 7206 kvm_for_each_vcpu(i, vcpu, kvm) {
7207 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7208 kvm_unload_vcpu_mmu(vcpu);
af585b92 7209 }
988a2cae
GN		 7210 kvm_for_each_vcpu(i, vcpu, kvm)
7211 kvm_arch_vcpu_free(vcpu);
7212
7213 mutex_lock(&kvm->lock);
7214 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7215 kvm->vcpus[i] = NULL;
d19a9cd2 7216
988a2cae
GN		 7217 atomic_set(&kvm->online_vcpus, 0);
7218 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7219}
7220
ad8ba2cd
SY		 7221void kvm_arch_sync_events(struct kvm *kvm)
7222{
332967a3 7223 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7224 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7225 kvm_free_all_assigned_devices(kvm);
aea924f6 7226 kvm_free_pit(kvm);
ad8ba2cd
SY		 7227}
7228
d19a9cd2
ZX		 7229void kvm_arch_destroy_vm(struct kvm *kvm)
7230{
27469d29
AH		 7231 if (current->mm == kvm->mm) {
7232 /*
7233 * Free memory regions allocated on behalf of userspace,
7234 * unless the the memory map has changed due to process exit
7235 * or fd copying.
7236 */
7237 struct kvm_userspace_memory_region mem;
7238 memset(&mem, 0, sizeof(mem));
7239 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7240 kvm_set_memory_region(kvm, &mem);
7241
7242 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7243 kvm_set_memory_region(kvm, &mem);
7244
7245 mem.slot = TSS_PRIVATE_MEMSLOT;
7246 kvm_set_memory_region(kvm, &mem);
7247 }
6eb55818 7248 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7249 kfree(kvm->arch.vpic);
7250 kfree(kvm->arch.vioapic);
d19a9cd2 7251 kvm_free_vcpus(kvm);
3d45830c
AK		 7252 if (kvm->arch.apic_access_page)
7253 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7254 if (kvm->arch.ept_identity_pagetable)
7255 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7256 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7257}
0de10343 7258
5587027c 7259void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7260 struct kvm_memory_slot *dont)
7261{
7262 int i;
7263
d89cc617
TY		 7264 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7265 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7266 kvm_kvfree(free->arch.rmap[i]);
7267 free->arch.rmap[i] = NULL;
77d11309 7268 }
d89cc617
TY		 7269 if (i == 0)
7270 continue;
7271
7272 if (!dont || free->arch.lpage_info[i - 1] !=
7273 dont->arch.lpage_info[i - 1]) {
7274 kvm_kvfree(free->arch.lpage_info[i - 1]);
7275 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7276 }
7277 }
7278}
7279
5587027c
AK		 7280int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7281 unsigned long npages)
db3fe4eb
TY		 7282{
7283 int i;
7284
d89cc617 7285 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7286 unsigned long ugfn;
7287 int lpages;
d89cc617 7288 int level = i + 1;
db3fe4eb
TY		 7289
7290 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7291 slot->base_gfn, level) + 1;
7292
d89cc617
TY		 7293 slot->arch.rmap[i] =
7294 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7295 if (!slot->arch.rmap[i])
77d11309 7296 goto out_free;
d89cc617
TY		 7297 if (i == 0)
7298 continue;
77d11309 7299
d89cc617
TY		 7300 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7301 sizeof(*slot->arch.lpage_info[i - 1]));
7302 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7303 goto out_free;
7304
7305 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7306 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7307 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7308 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7309 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7310 /*
7311 * If the gfn and userspace address are not aligned wrt each
7312 * other, or if explicitly asked to, disable large page
7313 * support for this slot
7314 */
7315 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7316 !kvm_largepages_enabled()) {
7317 unsigned long j;
7318
7319 for (j = 0; j < lpages; ++j)
d89cc617 7320 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7321 }
7322 }
7323
7324 return 0;
7325
7326out_free:
d89cc617
TY		 7327 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7328 kvm_kvfree(slot->arch.rmap[i]);
7329 slot->arch.rmap[i] = NULL;
7330 if (i == 0)
7331 continue;
7332
7333 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7334 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7335 }
7336 return -ENOMEM;
7337}
7338
e59dbe09
TY		 7339void kvm_arch_memslots_updated(struct kvm *kvm)
7340{
e6dff7d1
TY		 7341 /*
7342 * memslots->generation has been incremented.
7343 * mmio generation may have reached its maximum value.
7344 */
7345 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7346}
7347
f7784b8e
MT		 7348int kvm_arch_prepare_memory_region(struct kvm *kvm,
7349 struct kvm_memory_slot *memslot,
f7784b8e 7350 struct kvm_userspace_memory_region *mem,
7b6195a9 7351 enum kvm_mr_change change)
0de10343 7352{
7a905b14
TY		 7353 /*
7354 * Only private memory slots need to be mapped here since
7355 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7356 */
7b6195a9 7357 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7358 unsigned long userspace_addr;
604b38ac 7359
7a905b14
TY		 7360 /*
7361 * MAP_SHARED to prevent internal slot pages from being moved
7362 * by fork()/COW.
7363 */
7b6195a9 7364 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7365 PROT_READ | PROT_WRITE,
7366 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7367
7a905b14
TY		 7368 if (IS_ERR((void *)userspace_addr))
7369 return PTR_ERR((void *)userspace_addr);
604b38ac 7370
7a905b14 7371 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7372 }
7373
f7784b8e
MT		 7374 return 0;
7375}
7376
7377void kvm_arch_commit_memory_region(struct kvm *kvm,
7378 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7379 const struct kvm_memory_slot *old,
7380 enum kvm_mr_change change)
f7784b8e
MT		 7381{
7382
8482644a 7383 int nr_mmu_pages = 0;
f7784b8e 7384
8482644a 7385 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7386 int ret;
7387
8482644a
TY		 7388 ret = vm_munmap(old->userspace_addr,
7389 old->npages * PAGE_SIZE);
f7784b8e
MT		 7390 if (ret < 0)
7391 printk(KERN_WARNING
7392 "kvm_vm_ioctl_set_memory_region: "
7393 "failed to munmap memory\n");
7394 }
7395
48c0e4e9
XG		 7396 if (!kvm->arch.n_requested_mmu_pages)
7397 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7398
48c0e4e9 7399 if (nr_mmu_pages)
0de10343 7400 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7401 /*
7402 * Write protect all pages for dirty logging.
c126d94f
XG		 7403 *
7404 * All the sptes including the large sptes which point to this
7405 * slot are set to readonly. We can not create any new large
7406 * spte on this slot until the end of the logging.
7407 *
7408 * See the comments in fast_page_fault().
c972f3b1 7409 */
8482644a 7410 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7411 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7412}
1d737c8a 7413
2df72e9b 7414void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7415{
6ca18b69 7416 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7417}
7418
2df72e9b
MT		 7419void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7420 struct kvm_memory_slot *slot)
7421{
6ca18b69 7422 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7423}
7424
1d737c8a
ZX		 7425int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7426{
b6b8a145
JK		 7427 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7428 kvm_x86_ops->check_nested_events(vcpu, false);
7429
af585b92
GN		 7430 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7431 !vcpu->arch.apf.halted)
7432 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7433 || kvm_apic_has_events(vcpu)
6aef266c 7434 || vcpu->arch.pv.pv_unhalted
7460fb4a 7435 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7436 (kvm_arch_interrupt_allowed(vcpu) &&
7437 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7438}
5736199a 7439
b6d33834 7440int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7441{
b6d33834 7442 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7443}
78646121
GN		 7444
7445int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7446{
7447 return kvm_x86_ops->interrupt_allowed(vcpu);
7448}
229456fc 7449
f92653ee
JK		 7450bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7451{
7452 unsigned long current_rip = kvm_rip_read(vcpu) +
7453 get_segment_base(vcpu, VCPU_SREG_CS);
7454
7455 return current_rip == linear_rip;
7456}
7457EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7458
94fe45da
JK		 7459unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7460{
7461 unsigned long rflags;
7462
7463 rflags = kvm_x86_ops->get_rflags(vcpu);
7464 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7465 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7466 return rflags;
7467}
7468EXPORT_SYMBOL_GPL(kvm_get_rflags);
7469
6addfc42 7470static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7471{
7472 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7473 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7474 rflags |= X86_EFLAGS_TF;
94fe45da 7475 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7476}
7477
7478void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7479{
7480 __kvm_set_rflags(vcpu, rflags);
3842d135 7481 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7482}
7483EXPORT_SYMBOL_GPL(kvm_set_rflags);
7484
56028d08
GN		 7485void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7486{
7487 int r;
7488
fb67e14f 7489 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7490 work->wakeup_all)
56028d08
GN		 7491 return;
7492
7493 r = kvm_mmu_reload(vcpu);
7494 if (unlikely(r))
7495 return;
7496
fb67e14f
XG		 7497 if (!vcpu->arch.mmu.direct_map &&
7498 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7499 return;
7500
56028d08
GN		 7501 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7502}
7503
af585b92
GN		 7504static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7505{
7506 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7507}
7508
7509static inline u32 kvm_async_pf_next_probe(u32 key)
7510{
7511 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7512}
7513
7514static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7515{
7516 u32 key = kvm_async_pf_hash_fn(gfn);
7517
7518 while (vcpu->arch.apf.gfns[key] != ~0)
7519 key = kvm_async_pf_next_probe(key);
7520
7521 vcpu->arch.apf.gfns[key] = gfn;
7522}
7523
7524static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7525{
7526 int i;
7527 u32 key = kvm_async_pf_hash_fn(gfn);
7528
7529 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7530 (vcpu->arch.apf.gfns[key] != gfn &&
7531 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7532 key = kvm_async_pf_next_probe(key);
7533
7534 return key;
7535}
7536
7537bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7538{
7539 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7540}
7541
7542static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7543{
7544 u32 i, j, k;
7545
7546 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7547 while (true) {
7548 vcpu->arch.apf.gfns[i] = ~0;
7549 do {
7550 j = kvm_async_pf_next_probe(j);
7551 if (vcpu->arch.apf.gfns[j] == ~0)
7552 return;
7553 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7554 /*
7555 * k lies cyclically in ]i,j]
7556 * | i.k.j |
7557 * |....j i.k.| or |.k..j i...|
7558 */
7559 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7560 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7561 i = j;
7562 }
7563}
7564
7c90705b
GN		 7565static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7566{
7567
7568 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7569 sizeof(val));
7570}
7571
af585b92
GN		 7572void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7573 struct kvm_async_pf *work)
7574{
6389ee94
AK		 7575 struct x86_exception fault;
7576
7c90705b 7577 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7578 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7579
7580 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7581 (vcpu->arch.apf.send_user_only &&
7582 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7583 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7584 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7585 fault.vector = PF_VECTOR;
7586 fault.error_code_valid = true;
7587 fault.error_code = 0;
7588 fault.nested_page_fault = false;
7589 fault.address = work->arch.token;
7590 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7591 }
af585b92
GN		 7592}
7593
7594void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7595 struct kvm_async_pf *work)
7596{
6389ee94
AK		 7597 struct x86_exception fault;
7598
7c90705b 7599 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7600 if (work->wakeup_all)
7c90705b
GN		 7601 work->arch.token = ~0; /* broadcast wakeup */
7602 else
7603 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7604
7605 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7606 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7607 fault.vector = PF_VECTOR;
7608 fault.error_code_valid = true;
7609 fault.error_code = 0;
7610 fault.nested_page_fault = false;
7611 fault.address = work->arch.token;
7612 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7613 }
e6d53e3b 7614 vcpu->arch.apf.halted = false;
a4fa1635 7615 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7616}
7617
7618bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7619{
7620 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7621 return true;
7622 else
7623 return !kvm_event_needs_reinjection(vcpu) &&
7624 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7625}
7626
e0f0bbc5
AW		 7627void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7628{
7629 atomic_inc(&kvm->arch.noncoherent_dma_count);
7630}
7631EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7632
7633void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7634{
7635 atomic_dec(&kvm->arch.noncoherent_dma_count);
7636}
7637EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7638
7639bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7640{
7641 return atomic_read(&kvm->arch.noncoherent_dma_count);
7642}
7643EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7644
229456fc
MT		 7645EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7646EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7647EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7648EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7649EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7650EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7651EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7652EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7653EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7654EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7655EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7656EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7657EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
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