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Commit | Line | Data |
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9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
9f4c815c | 7 | #include <linux/sched.h> |
9f4c815c | 8 | #include <linux/mm.h> |
76ebd054 | 9 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
10 | #include <linux/seq_file.h> |
11 | #include <linux/debugfs.h> | |
e59a1bb2 | 12 | #include <linux/pfn.h> |
8c4bfc6e | 13 | #include <linux/percpu.h> |
5a0e3ad6 | 14 | #include <linux/gfp.h> |
5bd5a452 | 15 | #include <linux/pci.h> |
d6472302 | 16 | #include <linux/vmalloc.h> |
9f4c815c | 17 | |
66441bd3 | 18 | #include <asm/e820/api.h> |
1da177e4 LT |
19 | #include <asm/processor.h> |
20 | #include <asm/tlbflush.h> | |
f8af095d | 21 | #include <asm/sections.h> |
93dbda7c | 22 | #include <asm/setup.h> |
7c0f6ba6 | 23 | #include <linux/uaccess.h> |
9f4c815c | 24 | #include <asm/pgalloc.h> |
c31c7d48 | 25 | #include <asm/proto.h> |
1219333d | 26 | #include <asm/pat.h> |
d1163651 | 27 | #include <asm/set_memory.h> |
1da177e4 | 28 | |
9df84993 IM |
29 | /* |
30 | * The current flushing context - we pass it instead of 5 arguments: | |
31 | */ | |
72e458df | 32 | struct cpa_data { |
d75586ad | 33 | unsigned long *vaddr; |
0fd64c23 | 34 | pgd_t *pgd; |
72e458df TG |
35 | pgprot_t mask_set; |
36 | pgprot_t mask_clr; | |
74256377 | 37 | unsigned long numpages; |
d75586ad | 38 | int flags; |
c31c7d48 | 39 | unsigned long pfn; |
c9caa02c | 40 | unsigned force_split : 1; |
d75586ad | 41 | int curpage; |
9ae28475 | 42 | struct page **pages; |
72e458df TG |
43 | }; |
44 | ||
ad5ca55f SS |
45 | /* |
46 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
47 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
48 | * entries change the page attribute in parallel to some other cpu | |
49 | * splitting a large page entry along with changing the attribute. | |
50 | */ | |
51 | static DEFINE_SPINLOCK(cpa_lock); | |
52 | ||
d75586ad SL |
53 | #define CPA_FLUSHTLB 1 |
54 | #define CPA_ARRAY 2 | |
9ae28475 | 55 | #define CPA_PAGES_ARRAY 4 |
d75586ad | 56 | |
65280e61 | 57 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
58 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
59 | ||
65280e61 | 60 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 61 | { |
ce0c0e50 | 62 | /* Protect against CPA */ |
a79e53d8 | 63 | spin_lock(&pgd_lock); |
ce0c0e50 | 64 | direct_pages_count[level] += pages; |
a79e53d8 | 65 | spin_unlock(&pgd_lock); |
65280e61 TG |
66 | } |
67 | ||
68 | static void split_page_count(int level) | |
69 | { | |
c9e0d391 DJ |
70 | if (direct_pages_count[level] == 0) |
71 | return; | |
72 | ||
65280e61 TG |
73 | direct_pages_count[level]--; |
74 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
75 | } | |
76 | ||
e1759c21 | 77 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 78 | { |
b9c3bfc2 | 79 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
80 | direct_pages_count[PG_LEVEL_4K] << 2); |
81 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 82 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
83 | direct_pages_count[PG_LEVEL_2M] << 11); |
84 | #else | |
b9c3bfc2 | 85 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
86 | direct_pages_count[PG_LEVEL_2M] << 12); |
87 | #endif | |
a06de630 | 88 | if (direct_gbpages) |
b9c3bfc2 | 89 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 90 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 | 91 | } |
65280e61 TG |
92 | #else |
93 | static inline void split_page_count(int level) { } | |
94 | #endif | |
ce0c0e50 | 95 | |
c31c7d48 TG |
96 | #ifdef CONFIG_X86_64 |
97 | ||
98 | static inline unsigned long highmap_start_pfn(void) | |
99 | { | |
fc8d7826 | 100 | return __pa_symbol(_text) >> PAGE_SHIFT; |
c31c7d48 TG |
101 | } |
102 | ||
103 | static inline unsigned long highmap_end_pfn(void) | |
104 | { | |
4ff53087 TG |
105 | /* Do not reference physical address outside the kernel. */ |
106 | return __pa_symbol(roundup(_brk_end, PMD_SIZE) - 1) >> PAGE_SHIFT; | |
c31c7d48 TG |
107 | } |
108 | ||
109 | #endif | |
110 | ||
ed724be6 AV |
111 | static inline int |
112 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 113 | { |
ed724be6 AV |
114 | return addr >= start && addr < end; |
115 | } | |
116 | ||
4ff53087 TG |
117 | static inline int |
118 | within_inclusive(unsigned long addr, unsigned long start, unsigned long end) | |
119 | { | |
120 | return addr >= start && addr <= end; | |
121 | } | |
122 | ||
d7c8f21a TG |
123 | /* |
124 | * Flushing functions | |
125 | */ | |
cd8ddf1a | 126 | |
cd8ddf1a TG |
127 | /** |
128 | * clflush_cache_range - flush a cache range with clflush | |
9efc31b8 | 129 | * @vaddr: virtual start address |
cd8ddf1a TG |
130 | * @size: number of bytes to flush |
131 | * | |
8b80fd8b RZ |
132 | * clflushopt is an unordered instruction which needs fencing with mfence or |
133 | * sfence to avoid ordering issues. | |
cd8ddf1a | 134 | */ |
4c61afcd | 135 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 136 | { |
1f1a89ac CW |
137 | const unsigned long clflush_size = boot_cpu_data.x86_clflush_size; |
138 | void *p = (void *)((unsigned long)vaddr & ~(clflush_size - 1)); | |
6c434d61 | 139 | void *vend = vaddr + size; |
1f1a89ac CW |
140 | |
141 | if (p >= vend) | |
142 | return; | |
d7c8f21a | 143 | |
cd8ddf1a | 144 | mb(); |
4c61afcd | 145 | |
1f1a89ac | 146 | for (; p < vend; p += clflush_size) |
6c434d61 | 147 | clflushopt(p); |
4c61afcd | 148 | |
cd8ddf1a | 149 | mb(); |
d7c8f21a | 150 | } |
e517a5e9 | 151 | EXPORT_SYMBOL_GPL(clflush_cache_range); |
d7c8f21a | 152 | |
af1e6844 | 153 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 154 | { |
6bb8383b AK |
155 | unsigned long cache = (unsigned long)arg; |
156 | ||
d7c8f21a TG |
157 | /* |
158 | * Flush all to work around Errata in early athlons regarding | |
159 | * large page flushing. | |
160 | */ | |
161 | __flush_tlb_all(); | |
162 | ||
0b827537 | 163 | if (cache && boot_cpu_data.x86 >= 4) |
d7c8f21a TG |
164 | wbinvd(); |
165 | } | |
166 | ||
6bb8383b | 167 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
168 | { |
169 | BUG_ON(irqs_disabled()); | |
170 | ||
15c8b6c1 | 171 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
172 | } |
173 | ||
57a6a46a TG |
174 | static void __cpa_flush_range(void *arg) |
175 | { | |
57a6a46a TG |
176 | /* |
177 | * We could optimize that further and do individual per page | |
178 | * tlb invalidates for a low number of pages. Caveat: we must | |
179 | * flush the high aliases on 64bit as well. | |
180 | */ | |
181 | __flush_tlb_all(); | |
57a6a46a TG |
182 | } |
183 | ||
6bb8383b | 184 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 185 | { |
4c61afcd IM |
186 | unsigned int i, level; |
187 | unsigned long addr; | |
188 | ||
57a6a46a | 189 | BUG_ON(irqs_disabled()); |
4c61afcd | 190 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 191 | |
15c8b6c1 | 192 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 193 | |
6bb8383b AK |
194 | if (!cache) |
195 | return; | |
196 | ||
3b233e52 TG |
197 | /* |
198 | * We only need to flush on one CPU, | |
199 | * clflush is a MESI-coherent instruction that | |
200 | * will cause all other CPUs to flush the same | |
201 | * cachelines: | |
202 | */ | |
4c61afcd IM |
203 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
204 | pte_t *pte = lookup_address(addr, &level); | |
205 | ||
206 | /* | |
207 | * Only flush present addresses: | |
208 | */ | |
7bfb72e8 | 209 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
210 | clflush_cache_range((void *) addr, PAGE_SIZE); |
211 | } | |
57a6a46a TG |
212 | } |
213 | ||
9ae28475 | 214 | static void cpa_flush_array(unsigned long *start, int numpages, int cache, |
215 | int in_flags, struct page **pages) | |
d75586ad SL |
216 | { |
217 | unsigned int i, level; | |
459fbe00 JO |
218 | #ifdef CONFIG_PREEMPT |
219 | /* | |
220 | * Avoid wbinvd() because it causes latencies on all CPUs, | |
221 | * regardless of any CPU isolation that may be in effect. | |
222 | * | |
223 | * This should be extended for CAT enabled systems independent of | |
224 | * PREEMPT because wbinvd() does not respect the CAT partitions and | |
225 | * this is exposed to unpriviledged users through the graphics | |
226 | * subsystem. | |
227 | */ | |
228 | unsigned long do_wbinvd = 0; | |
229 | #else | |
2171787b | 230 | unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ |
459fbe00 | 231 | #endif |
d75586ad SL |
232 | |
233 | BUG_ON(irqs_disabled()); | |
234 | ||
2171787b | 235 | on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); |
d75586ad | 236 | |
2171787b | 237 | if (!cache || do_wbinvd) |
d75586ad SL |
238 | return; |
239 | ||
d75586ad SL |
240 | /* |
241 | * We only need to flush on one CPU, | |
242 | * clflush is a MESI-coherent instruction that | |
243 | * will cause all other CPUs to flush the same | |
244 | * cachelines: | |
245 | */ | |
9ae28475 | 246 | for (i = 0; i < numpages; i++) { |
247 | unsigned long addr; | |
248 | pte_t *pte; | |
249 | ||
250 | if (in_flags & CPA_PAGES_ARRAY) | |
251 | addr = (unsigned long)page_address(pages[i]); | |
252 | else | |
253 | addr = start[i]; | |
254 | ||
255 | pte = lookup_address(addr, &level); | |
d75586ad SL |
256 | |
257 | /* | |
258 | * Only flush present addresses: | |
259 | */ | |
260 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
9ae28475 | 261 | clflush_cache_range((void *)addr, PAGE_SIZE); |
d75586ad SL |
262 | } |
263 | } | |
264 | ||
ed724be6 AV |
265 | /* |
266 | * Certain areas of memory on x86 require very specific protection flags, | |
267 | * for example the BIOS area or kernel text. Callers don't always get this | |
268 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
269 | * checks and fixes these known static required protection bits. | |
270 | */ | |
c31c7d48 TG |
271 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
272 | unsigned long pfn) | |
ed724be6 AV |
273 | { |
274 | pgprot_t forbidden = __pgprot(0); | |
275 | ||
687c4825 | 276 | /* |
ed724be6 AV |
277 | * The BIOS area between 640k and 1Mb needs to be executable for |
278 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 279 | */ |
5bd5a452 MC |
280 | #ifdef CONFIG_PCI_BIOS |
281 | if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) | |
ed724be6 | 282 | pgprot_val(forbidden) |= _PAGE_NX; |
5bd5a452 | 283 | #endif |
ed724be6 AV |
284 | |
285 | /* | |
286 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
287 | * Does not cover __inittext since that is gone later on. On |
288 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
289 | */ |
290 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
291 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 292 | |
cc0f21bb | 293 | /* |
c31c7d48 TG |
294 | * The .rodata section needs to be read-only. Using the pfn |
295 | * catches all aliases. | |
cc0f21bb | 296 | */ |
fc8d7826 AD |
297 | if (within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT, |
298 | __pa_symbol(__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 299 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 | 300 | |
9ccaf77c | 301 | #if defined(CONFIG_X86_64) |
74e08179 | 302 | /* |
502f6604 SS |
303 | * Once the kernel maps the text as RO (kernel_set_to_readonly is set), |
304 | * kernel text mappings for the large page aligned text, rodata sections | |
305 | * will be always read-only. For the kernel identity mappings covering | |
306 | * the holes caused by this alignment can be anything that user asks. | |
74e08179 SS |
307 | * |
308 | * This will preserve the large page mappings for kernel text/data | |
309 | * at no extra cost. | |
310 | */ | |
502f6604 SS |
311 | if (kernel_set_to_readonly && |
312 | within(address, (unsigned long)_text, | |
281ff33b SS |
313 | (unsigned long)__end_rodata_hpage_align)) { |
314 | unsigned int level; | |
315 | ||
316 | /* | |
317 | * Don't enforce the !RW mapping for the kernel text mapping, | |
318 | * if the current mapping is already using small page mapping. | |
319 | * No need to work hard to preserve large page mappings in this | |
320 | * case. | |
321 | * | |
322 | * This also fixes the Linux Xen paravirt guest boot failure | |
323 | * (because of unexpected read-only mappings for kernel identity | |
324 | * mappings). In this paravirt guest case, the kernel text | |
325 | * mapping and the kernel identity mapping share the same | |
326 | * page-table pages. Thus we can't really use different | |
327 | * protections for the kernel text and identity mappings. Also, | |
328 | * these shared mappings are made of small page mappings. | |
329 | * Thus this don't enforce !RW mapping for small page kernel | |
330 | * text mapping logic will help Linux Xen parvirt guest boot | |
0d2eb44f | 331 | * as well. |
281ff33b SS |
332 | */ |
333 | if (lookup_address(address, &level) && (level != PG_LEVEL_4K)) | |
334 | pgprot_val(forbidden) |= _PAGE_RW; | |
335 | } | |
74e08179 SS |
336 | #endif |
337 | ||
ed724be6 | 338 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); |
687c4825 IM |
339 | |
340 | return prot; | |
341 | } | |
342 | ||
426e34cc MF |
343 | /* |
344 | * Lookup the page table entry for a virtual address in a specific pgd. | |
345 | * Return a pointer to the entry and the level of the mapping. | |
346 | */ | |
347 | pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address, | |
348 | unsigned int *level) | |
9f4c815c | 349 | { |
45478336 | 350 | p4d_t *p4d; |
1da177e4 LT |
351 | pud_t *pud; |
352 | pmd_t *pmd; | |
9f4c815c | 353 | |
30551bb3 TG |
354 | *level = PG_LEVEL_NONE; |
355 | ||
1da177e4 LT |
356 | if (pgd_none(*pgd)) |
357 | return NULL; | |
9df84993 | 358 | |
45478336 KS |
359 | p4d = p4d_offset(pgd, address); |
360 | if (p4d_none(*p4d)) | |
361 | return NULL; | |
362 | ||
363 | *level = PG_LEVEL_512G; | |
364 | if (p4d_large(*p4d) || !p4d_present(*p4d)) | |
365 | return (pte_t *)p4d; | |
366 | ||
367 | pud = pud_offset(p4d, address); | |
1da177e4 LT |
368 | if (pud_none(*pud)) |
369 | return NULL; | |
c2f71ee2 AK |
370 | |
371 | *level = PG_LEVEL_1G; | |
372 | if (pud_large(*pud) || !pud_present(*pud)) | |
373 | return (pte_t *)pud; | |
374 | ||
1da177e4 LT |
375 | pmd = pmd_offset(pud, address); |
376 | if (pmd_none(*pmd)) | |
377 | return NULL; | |
30551bb3 TG |
378 | |
379 | *level = PG_LEVEL_2M; | |
9a14aefc | 380 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 381 | return (pte_t *)pmd; |
1da177e4 | 382 | |
30551bb3 | 383 | *level = PG_LEVEL_4K; |
9df84993 | 384 | |
9f4c815c IM |
385 | return pte_offset_kernel(pmd, address); |
386 | } | |
0fd64c23 BP |
387 | |
388 | /* | |
389 | * Lookup the page table entry for a virtual address. Return a pointer | |
390 | * to the entry and the level of the mapping. | |
391 | * | |
392 | * Note: We return pud and pmd either when the entry is marked large | |
393 | * or when the present bit is not set. Otherwise we would return a | |
394 | * pointer to a nonexisting mapping. | |
395 | */ | |
396 | pte_t *lookup_address(unsigned long address, unsigned int *level) | |
397 | { | |
426e34cc | 398 | return lookup_address_in_pgd(pgd_offset_k(address), address, level); |
0fd64c23 | 399 | } |
75bb8835 | 400 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 401 | |
0fd64c23 BP |
402 | static pte_t *_lookup_address_cpa(struct cpa_data *cpa, unsigned long address, |
403 | unsigned int *level) | |
404 | { | |
405 | if (cpa->pgd) | |
426e34cc | 406 | return lookup_address_in_pgd(cpa->pgd + pgd_index(address), |
0fd64c23 BP |
407 | address, level); |
408 | ||
409 | return lookup_address(address, level); | |
410 | } | |
411 | ||
792230c3 JG |
412 | /* |
413 | * Lookup the PMD entry for a virtual address. Return a pointer to the entry | |
414 | * or NULL if not present. | |
415 | */ | |
416 | pmd_t *lookup_pmd_address(unsigned long address) | |
417 | { | |
418 | pgd_t *pgd; | |
45478336 | 419 | p4d_t *p4d; |
792230c3 JG |
420 | pud_t *pud; |
421 | ||
422 | pgd = pgd_offset_k(address); | |
423 | if (pgd_none(*pgd)) | |
424 | return NULL; | |
425 | ||
45478336 KS |
426 | p4d = p4d_offset(pgd, address); |
427 | if (p4d_none(*p4d) || p4d_large(*p4d) || !p4d_present(*p4d)) | |
428 | return NULL; | |
429 | ||
430 | pud = pud_offset(p4d, address); | |
792230c3 JG |
431 | if (pud_none(*pud) || pud_large(*pud) || !pud_present(*pud)) |
432 | return NULL; | |
433 | ||
434 | return pmd_offset(pud, address); | |
435 | } | |
436 | ||
d7656534 DH |
437 | /* |
438 | * This is necessary because __pa() does not work on some | |
439 | * kinds of memory, like vmalloc() or the alloc_remap() | |
440 | * areas on 32-bit NUMA systems. The percpu areas can | |
441 | * end up in this kind of memory, for instance. | |
442 | * | |
443 | * This could be optimized, but it is only intended to be | |
444 | * used at inititalization time, and keeping it | |
445 | * unoptimized should increase the testing coverage for | |
446 | * the more obscure platforms. | |
447 | */ | |
448 | phys_addr_t slow_virt_to_phys(void *__virt_addr) | |
449 | { | |
450 | unsigned long virt_addr = (unsigned long)__virt_addr; | |
bf70e551 DC |
451 | phys_addr_t phys_addr; |
452 | unsigned long offset; | |
d7656534 | 453 | enum pg_level level; |
d7656534 DH |
454 | pte_t *pte; |
455 | ||
456 | pte = lookup_address(virt_addr, &level); | |
457 | BUG_ON(!pte); | |
34437e67 | 458 | |
bf70e551 DC |
459 | /* |
460 | * pXX_pfn() returns unsigned long, which must be cast to phys_addr_t | |
461 | * before being left-shifted PAGE_SHIFT bits -- this trick is to | |
462 | * make 32-PAE kernel work correctly. | |
463 | */ | |
34437e67 TK |
464 | switch (level) { |
465 | case PG_LEVEL_1G: | |
bf70e551 | 466 | phys_addr = (phys_addr_t)pud_pfn(*(pud_t *)pte) << PAGE_SHIFT; |
34437e67 TK |
467 | offset = virt_addr & ~PUD_PAGE_MASK; |
468 | break; | |
469 | case PG_LEVEL_2M: | |
bf70e551 | 470 | phys_addr = (phys_addr_t)pmd_pfn(*(pmd_t *)pte) << PAGE_SHIFT; |
34437e67 TK |
471 | offset = virt_addr & ~PMD_PAGE_MASK; |
472 | break; | |
473 | default: | |
bf70e551 | 474 | phys_addr = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT; |
34437e67 TK |
475 | offset = virt_addr & ~PAGE_MASK; |
476 | } | |
477 | ||
478 | return (phys_addr_t)(phys_addr | offset); | |
d7656534 DH |
479 | } |
480 | EXPORT_SYMBOL_GPL(slow_virt_to_phys); | |
481 | ||
9df84993 IM |
482 | /* |
483 | * Set the new pmd in all the pgds we know about: | |
484 | */ | |
9a3dc780 | 485 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 486 | { |
9f4c815c IM |
487 | /* change init_mm */ |
488 | set_pte_atomic(kpte, pte); | |
44af6c41 | 489 | #ifdef CONFIG_X86_32 |
e4b71dcf | 490 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
491 | struct page *page; |
492 | ||
e3ed910d | 493 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 | 494 | pgd_t *pgd; |
45478336 | 495 | p4d_t *p4d; |
44af6c41 IM |
496 | pud_t *pud; |
497 | pmd_t *pmd; | |
498 | ||
499 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
45478336 KS |
500 | p4d = p4d_offset(pgd, address); |
501 | pud = pud_offset(p4d, address); | |
44af6c41 IM |
502 | pmd = pmd_offset(pud, address); |
503 | set_pte_atomic((pte_t *)pmd, pte); | |
504 | } | |
1da177e4 | 505 | } |
44af6c41 | 506 | #endif |
1da177e4 LT |
507 | } |
508 | ||
9df84993 IM |
509 | static int |
510 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
511 | struct cpa_data *cpa) | |
65e074df | 512 | { |
3a19109e | 513 | unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn, old_pfn; |
65e074df | 514 | pte_t new_pte, old_pte, *tmp; |
64edc8ed | 515 | pgprot_t old_prot, new_prot, req_prot; |
fac84939 | 516 | int i, do_split = 1; |
f3c4fbb6 | 517 | enum pg_level level; |
65e074df | 518 | |
c9caa02c AK |
519 | if (cpa->force_split) |
520 | return 1; | |
521 | ||
a79e53d8 | 522 | spin_lock(&pgd_lock); |
65e074df TG |
523 | /* |
524 | * Check for races, another CPU might have split this page | |
525 | * up already: | |
526 | */ | |
82f0712c | 527 | tmp = _lookup_address_cpa(cpa, address, &level); |
65e074df TG |
528 | if (tmp != kpte) |
529 | goto out_unlock; | |
530 | ||
531 | switch (level) { | |
532 | case PG_LEVEL_2M: | |
3a19109e TK |
533 | old_prot = pmd_pgprot(*(pmd_t *)kpte); |
534 | old_pfn = pmd_pfn(*(pmd_t *)kpte); | |
535 | break; | |
65e074df | 536 | case PG_LEVEL_1G: |
3a19109e TK |
537 | old_prot = pud_pgprot(*(pud_t *)kpte); |
538 | old_pfn = pud_pfn(*(pud_t *)kpte); | |
f3c4fbb6 | 539 | break; |
65e074df | 540 | default: |
beaff633 | 541 | do_split = -EINVAL; |
65e074df TG |
542 | goto out_unlock; |
543 | } | |
544 | ||
3a19109e TK |
545 | psize = page_level_size(level); |
546 | pmask = page_level_mask(level); | |
547 | ||
65e074df TG |
548 | /* |
549 | * Calculate the number of pages, which fit into this large | |
550 | * page starting at address: | |
551 | */ | |
552 | nextpage_addr = (address + psize) & pmask; | |
553 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
554 | if (numpages < cpa->numpages) |
555 | cpa->numpages = numpages; | |
65e074df TG |
556 | |
557 | /* | |
558 | * We are safe now. Check whether the new pgprot is the same: | |
f5b2831d JG |
559 | * Convert protection attributes to 4k-format, as cpa->mask* are set |
560 | * up accordingly. | |
65e074df TG |
561 | */ |
562 | old_pte = *kpte; | |
55696b1f | 563 | req_prot = pgprot_large_2_4k(old_prot); |
65e074df | 564 | |
64edc8ed MC |
565 | pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr); |
566 | pgprot_val(req_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 | 567 | |
f5b2831d JG |
568 | /* |
569 | * req_prot is in format of 4k pages. It must be converted to large | |
570 | * page format: the caching mode includes the PAT bit located at | |
571 | * different bit positions in the two formats. | |
572 | */ | |
573 | req_prot = pgprot_4k_2_large(req_prot); | |
574 | ||
a8aed3e0 AA |
575 | /* |
576 | * Set the PSE and GLOBAL flags only if the PRESENT flag is | |
577 | * set otherwise pmd_present/pmd_huge will return true even on | |
578 | * a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL | |
579 | * for the ancient hardware that doesn't support it. | |
580 | */ | |
f76cfa3c AA |
581 | if (pgprot_val(req_prot) & _PAGE_PRESENT) |
582 | pgprot_val(req_prot) |= _PAGE_PSE | _PAGE_GLOBAL; | |
a8aed3e0 | 583 | else |
f76cfa3c | 584 | pgprot_val(req_prot) &= ~(_PAGE_PSE | _PAGE_GLOBAL); |
a8aed3e0 | 585 | |
f76cfa3c | 586 | req_prot = canon_pgprot(req_prot); |
a8aed3e0 | 587 | |
c31c7d48 | 588 | /* |
3a19109e | 589 | * old_pfn points to the large page base pfn. So we need |
c31c7d48 TG |
590 | * to add the offset of the virtual address: |
591 | */ | |
3a19109e | 592 | pfn = old_pfn + ((address & (psize - 1)) >> PAGE_SHIFT); |
c31c7d48 TG |
593 | cpa->pfn = pfn; |
594 | ||
64edc8ed | 595 | new_prot = static_protections(req_prot, address, pfn); |
65e074df | 596 | |
fac84939 TG |
597 | /* |
598 | * We need to check the full range, whether | |
599 | * static_protection() requires a different pgprot for one of | |
600 | * the pages in the range we try to preserve: | |
601 | */ | |
64edc8ed | 602 | addr = address & pmask; |
3a19109e | 603 | pfn = old_pfn; |
64edc8ed MC |
604 | for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) { |
605 | pgprot_t chk_prot = static_protections(req_prot, addr, pfn); | |
fac84939 TG |
606 | |
607 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
608 | goto out_unlock; | |
609 | } | |
610 | ||
65e074df TG |
611 | /* |
612 | * If there are no changes, return. maxpages has been updated | |
613 | * above: | |
614 | */ | |
615 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 616 | do_split = 0; |
65e074df TG |
617 | goto out_unlock; |
618 | } | |
619 | ||
620 | /* | |
621 | * We need to change the attributes. Check, whether we can | |
622 | * change the large page in one go. We request a split, when | |
623 | * the address is not aligned and the number of pages is | |
624 | * smaller than the number of pages in the large page. Note | |
625 | * that we limited the number of possible pages already to | |
626 | * the number of pages in the large page. | |
627 | */ | |
64edc8ed | 628 | if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) { |
65e074df TG |
629 | /* |
630 | * The address is aligned and the number of pages | |
631 | * covers the full page. | |
632 | */ | |
3a19109e | 633 | new_pte = pfn_pte(old_pfn, new_prot); |
65e074df | 634 | __set_pmd_pte(kpte, address, new_pte); |
d75586ad | 635 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 636 | do_split = 0; |
65e074df TG |
637 | } |
638 | ||
639 | out_unlock: | |
a79e53d8 | 640 | spin_unlock(&pgd_lock); |
9df84993 | 641 | |
beaff633 | 642 | return do_split; |
65e074df TG |
643 | } |
644 | ||
5952886b | 645 | static int |
82f0712c BP |
646 | __split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address, |
647 | struct page *base) | |
bb5c2dbd | 648 | { |
5952886b | 649 | pte_t *pbase = (pte_t *)page_address(base); |
d551aaa2 | 650 | unsigned long ref_pfn, pfn, pfninc = 1; |
9df84993 | 651 | unsigned int i, level; |
ae9aae9e | 652 | pte_t *tmp; |
9df84993 | 653 | pgprot_t ref_prot; |
bb5c2dbd | 654 | |
a79e53d8 | 655 | spin_lock(&pgd_lock); |
bb5c2dbd IM |
656 | /* |
657 | * Check for races, another CPU might have split this page | |
658 | * up for us already: | |
659 | */ | |
82f0712c | 660 | tmp = _lookup_address_cpa(cpa, address, &level); |
ae9aae9e WC |
661 | if (tmp != kpte) { |
662 | spin_unlock(&pgd_lock); | |
663 | return 1; | |
664 | } | |
bb5c2dbd | 665 | |
6944a9c8 | 666 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
f5b2831d | 667 | |
d551aaa2 TK |
668 | switch (level) { |
669 | case PG_LEVEL_2M: | |
670 | ref_prot = pmd_pgprot(*(pmd_t *)kpte); | |
671 | /* clear PSE and promote PAT bit to correct position */ | |
f5b2831d | 672 | ref_prot = pgprot_large_2_4k(ref_prot); |
d551aaa2 TK |
673 | ref_pfn = pmd_pfn(*(pmd_t *)kpte); |
674 | break; | |
bb5c2dbd | 675 | |
d551aaa2 TK |
676 | case PG_LEVEL_1G: |
677 | ref_prot = pud_pgprot(*(pud_t *)kpte); | |
678 | ref_pfn = pud_pfn(*(pud_t *)kpte); | |
f07333fd | 679 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; |
d551aaa2 | 680 | |
a8aed3e0 | 681 | /* |
d551aaa2 | 682 | * Clear the PSE flags if the PRESENT flag is not set |
a8aed3e0 AA |
683 | * otherwise pmd_present/pmd_huge will return true |
684 | * even on a non present pmd. | |
685 | */ | |
d551aaa2 | 686 | if (!(pgprot_val(ref_prot) & _PAGE_PRESENT)) |
a8aed3e0 | 687 | pgprot_val(ref_prot) &= ~_PAGE_PSE; |
d551aaa2 TK |
688 | break; |
689 | ||
690 | default: | |
691 | spin_unlock(&pgd_lock); | |
692 | return 1; | |
f07333fd | 693 | } |
f07333fd | 694 | |
a8aed3e0 AA |
695 | /* |
696 | * Set the GLOBAL flags only if the PRESENT flag is set | |
697 | * otherwise pmd/pte_present will return true even on a non | |
698 | * present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL | |
699 | * for the ancient hardware that doesn't support it. | |
700 | */ | |
701 | if (pgprot_val(ref_prot) & _PAGE_PRESENT) | |
702 | pgprot_val(ref_prot) |= _PAGE_GLOBAL; | |
703 | else | |
704 | pgprot_val(ref_prot) &= ~_PAGE_GLOBAL; | |
705 | ||
63c1dcf4 TG |
706 | /* |
707 | * Get the target pfn from the original entry: | |
708 | */ | |
d551aaa2 | 709 | pfn = ref_pfn; |
f07333fd | 710 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
a8aed3e0 | 711 | set_pte(&pbase[i], pfn_pte(pfn, canon_pgprot(ref_prot))); |
bb5c2dbd | 712 | |
2c66e24d SP |
713 | if (virt_addr_valid(address)) { |
714 | unsigned long pfn = PFN_DOWN(__pa(address)); | |
715 | ||
716 | if (pfn_range_is_mapped(pfn, pfn + 1)) | |
717 | split_page_count(level); | |
718 | } | |
f361a450 | 719 | |
bb5c2dbd | 720 | /* |
07a66d7c | 721 | * Install the new, split up pagetable. |
4c881ca1 | 722 | * |
07a66d7c IM |
723 | * We use the standard kernel pagetable protections for the new |
724 | * pagetable protections, the actual ptes set above control the | |
725 | * primary protection behavior: | |
bb5c2dbd | 726 | */ |
07a66d7c | 727 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
728 | |
729 | /* | |
730 | * Intel Atom errata AAH41 workaround. | |
731 | * | |
732 | * The real fix should be in hw or in a microcode update, but | |
733 | * we also probabilistically try to reduce the window of having | |
734 | * a large TLB mixed with 4K TLBs while instruction fetches are | |
735 | * going on. | |
736 | */ | |
737 | __flush_tlb_all(); | |
ae9aae9e | 738 | spin_unlock(&pgd_lock); |
211b3d03 | 739 | |
ae9aae9e WC |
740 | return 0; |
741 | } | |
bb5c2dbd | 742 | |
82f0712c BP |
743 | static int split_large_page(struct cpa_data *cpa, pte_t *kpte, |
744 | unsigned long address) | |
ae9aae9e | 745 | { |
ae9aae9e WC |
746 | struct page *base; |
747 | ||
288cf3c6 | 748 | if (!debug_pagealloc_enabled()) |
ae9aae9e WC |
749 | spin_unlock(&cpa_lock); |
750 | base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0); | |
288cf3c6 | 751 | if (!debug_pagealloc_enabled()) |
ae9aae9e WC |
752 | spin_lock(&cpa_lock); |
753 | if (!base) | |
754 | return -ENOMEM; | |
755 | ||
82f0712c | 756 | if (__split_large_page(cpa, kpte, address, base)) |
8311eb84 | 757 | __free_page(base); |
bb5c2dbd | 758 | |
bb5c2dbd IM |
759 | return 0; |
760 | } | |
761 | ||
52a628fb BP |
762 | static bool try_to_free_pte_page(pte_t *pte) |
763 | { | |
764 | int i; | |
765 | ||
766 | for (i = 0; i < PTRS_PER_PTE; i++) | |
767 | if (!pte_none(pte[i])) | |
768 | return false; | |
769 | ||
770 | free_page((unsigned long)pte); | |
771 | return true; | |
772 | } | |
773 | ||
774 | static bool try_to_free_pmd_page(pmd_t *pmd) | |
775 | { | |
776 | int i; | |
777 | ||
778 | for (i = 0; i < PTRS_PER_PMD; i++) | |
779 | if (!pmd_none(pmd[i])) | |
780 | return false; | |
781 | ||
782 | free_page((unsigned long)pmd); | |
783 | return true; | |
784 | } | |
785 | ||
786 | static bool unmap_pte_range(pmd_t *pmd, unsigned long start, unsigned long end) | |
787 | { | |
788 | pte_t *pte = pte_offset_kernel(pmd, start); | |
789 | ||
790 | while (start < end) { | |
791 | set_pte(pte, __pte(0)); | |
792 | ||
793 | start += PAGE_SIZE; | |
794 | pte++; | |
795 | } | |
796 | ||
797 | if (try_to_free_pte_page((pte_t *)pmd_page_vaddr(*pmd))) { | |
798 | pmd_clear(pmd); | |
799 | return true; | |
800 | } | |
801 | return false; | |
802 | } | |
803 | ||
804 | static void __unmap_pmd_range(pud_t *pud, pmd_t *pmd, | |
805 | unsigned long start, unsigned long end) | |
806 | { | |
807 | if (unmap_pte_range(pmd, start, end)) | |
808 | if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) | |
809 | pud_clear(pud); | |
810 | } | |
811 | ||
812 | static void unmap_pmd_range(pud_t *pud, unsigned long start, unsigned long end) | |
813 | { | |
814 | pmd_t *pmd = pmd_offset(pud, start); | |
815 | ||
816 | /* | |
817 | * Not on a 2MB page boundary? | |
818 | */ | |
819 | if (start & (PMD_SIZE - 1)) { | |
820 | unsigned long next_page = (start + PMD_SIZE) & PMD_MASK; | |
821 | unsigned long pre_end = min_t(unsigned long, end, next_page); | |
822 | ||
823 | __unmap_pmd_range(pud, pmd, start, pre_end); | |
824 | ||
825 | start = pre_end; | |
826 | pmd++; | |
827 | } | |
828 | ||
829 | /* | |
830 | * Try to unmap in 2M chunks. | |
831 | */ | |
832 | while (end - start >= PMD_SIZE) { | |
833 | if (pmd_large(*pmd)) | |
834 | pmd_clear(pmd); | |
835 | else | |
836 | __unmap_pmd_range(pud, pmd, start, start + PMD_SIZE); | |
837 | ||
838 | start += PMD_SIZE; | |
839 | pmd++; | |
840 | } | |
841 | ||
842 | /* | |
843 | * 4K leftovers? | |
844 | */ | |
845 | if (start < end) | |
846 | return __unmap_pmd_range(pud, pmd, start, end); | |
847 | ||
848 | /* | |
849 | * Try again to free the PMD page if haven't succeeded above. | |
850 | */ | |
851 | if (!pud_none(*pud)) | |
852 | if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) | |
853 | pud_clear(pud); | |
854 | } | |
0bb8aeee | 855 | |
45478336 | 856 | static void unmap_pud_range(p4d_t *p4d, unsigned long start, unsigned long end) |
0bb8aeee | 857 | { |
45478336 | 858 | pud_t *pud = pud_offset(p4d, start); |
0bb8aeee BP |
859 | |
860 | /* | |
861 | * Not on a GB page boundary? | |
862 | */ | |
863 | if (start & (PUD_SIZE - 1)) { | |
864 | unsigned long next_page = (start + PUD_SIZE) & PUD_MASK; | |
865 | unsigned long pre_end = min_t(unsigned long, end, next_page); | |
866 | ||
867 | unmap_pmd_range(pud, start, pre_end); | |
868 | ||
869 | start = pre_end; | |
870 | pud++; | |
871 | } | |
872 | ||
873 | /* | |
874 | * Try to unmap in 1G chunks? | |
875 | */ | |
876 | while (end - start >= PUD_SIZE) { | |
877 | ||
878 | if (pud_large(*pud)) | |
879 | pud_clear(pud); | |
880 | else | |
881 | unmap_pmd_range(pud, start, start + PUD_SIZE); | |
882 | ||
883 | start += PUD_SIZE; | |
884 | pud++; | |
885 | } | |
886 | ||
887 | /* | |
888 | * 2M leftovers? | |
889 | */ | |
890 | if (start < end) | |
891 | unmap_pmd_range(pud, start, end); | |
892 | ||
893 | /* | |
894 | * No need to try to free the PUD page because we'll free it in | |
895 | * populate_pgd's error path | |
896 | */ | |
897 | } | |
898 | ||
f900a4b8 BP |
899 | static int alloc_pte_page(pmd_t *pmd) |
900 | { | |
901 | pte_t *pte = (pte_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK); | |
902 | if (!pte) | |
903 | return -1; | |
904 | ||
905 | set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE)); | |
906 | return 0; | |
907 | } | |
908 | ||
4b23538d BP |
909 | static int alloc_pmd_page(pud_t *pud) |
910 | { | |
911 | pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK); | |
912 | if (!pmd) | |
913 | return -1; | |
914 | ||
915 | set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE)); | |
916 | return 0; | |
917 | } | |
918 | ||
c6b6f363 BP |
919 | static void populate_pte(struct cpa_data *cpa, |
920 | unsigned long start, unsigned long end, | |
921 | unsigned num_pages, pmd_t *pmd, pgprot_t pgprot) | |
922 | { | |
923 | pte_t *pte; | |
924 | ||
925 | pte = pte_offset_kernel(pmd, start); | |
926 | ||
39763015 SP |
927 | /* |
928 | * Set the GLOBAL flags only if the PRESENT flag is | |
929 | * set otherwise pte_present will return true even on | |
930 | * a non present pte. The canon_pgprot will clear | |
931 | * _PAGE_GLOBAL for the ancient hardware that doesn't | |
932 | * support it. | |
933 | */ | |
934 | if (pgprot_val(pgprot) & _PAGE_PRESENT) | |
935 | pgprot_val(pgprot) |= _PAGE_GLOBAL; | |
936 | else | |
937 | pgprot_val(pgprot) &= ~_PAGE_GLOBAL; | |
c6b6f363 | 938 | |
39763015 | 939 | pgprot = canon_pgprot(pgprot); |
c6b6f363 | 940 | |
c6b6f363 | 941 | while (num_pages-- && start < end) { |
edc3b912 | 942 | set_pte(pte, pfn_pte(cpa->pfn, pgprot)); |
c6b6f363 BP |
943 | |
944 | start += PAGE_SIZE; | |
edc3b912 | 945 | cpa->pfn++; |
c6b6f363 BP |
946 | pte++; |
947 | } | |
948 | } | |
f900a4b8 | 949 | |
e535ec08 MF |
950 | static long populate_pmd(struct cpa_data *cpa, |
951 | unsigned long start, unsigned long end, | |
952 | unsigned num_pages, pud_t *pud, pgprot_t pgprot) | |
f900a4b8 | 953 | { |
e535ec08 | 954 | long cur_pages = 0; |
f900a4b8 | 955 | pmd_t *pmd; |
f5b2831d | 956 | pgprot_t pmd_pgprot; |
f900a4b8 BP |
957 | |
958 | /* | |
959 | * Not on a 2M boundary? | |
960 | */ | |
961 | if (start & (PMD_SIZE - 1)) { | |
962 | unsigned long pre_end = start + (num_pages << PAGE_SHIFT); | |
963 | unsigned long next_page = (start + PMD_SIZE) & PMD_MASK; | |
964 | ||
965 | pre_end = min_t(unsigned long, pre_end, next_page); | |
966 | cur_pages = (pre_end - start) >> PAGE_SHIFT; | |
967 | cur_pages = min_t(unsigned int, num_pages, cur_pages); | |
968 | ||
969 | /* | |
970 | * Need a PTE page? | |
971 | */ | |
972 | pmd = pmd_offset(pud, start); | |
973 | if (pmd_none(*pmd)) | |
974 | if (alloc_pte_page(pmd)) | |
975 | return -1; | |
976 | ||
977 | populate_pte(cpa, start, pre_end, cur_pages, pmd, pgprot); | |
978 | ||
979 | start = pre_end; | |
980 | } | |
981 | ||
982 | /* | |
983 | * We mapped them all? | |
984 | */ | |
985 | if (num_pages == cur_pages) | |
986 | return cur_pages; | |
987 | ||
f5b2831d JG |
988 | pmd_pgprot = pgprot_4k_2_large(pgprot); |
989 | ||
f900a4b8 BP |
990 | while (end - start >= PMD_SIZE) { |
991 | ||
992 | /* | |
993 | * We cannot use a 1G page so allocate a PMD page if needed. | |
994 | */ | |
995 | if (pud_none(*pud)) | |
996 | if (alloc_pmd_page(pud)) | |
997 | return -1; | |
998 | ||
999 | pmd = pmd_offset(pud, start); | |
1000 | ||
edc3b912 | 1001 | set_pmd(pmd, __pmd(cpa->pfn << PAGE_SHIFT | _PAGE_PSE | |
f5b2831d | 1002 | massage_pgprot(pmd_pgprot))); |
f900a4b8 BP |
1003 | |
1004 | start += PMD_SIZE; | |
edc3b912 | 1005 | cpa->pfn += PMD_SIZE >> PAGE_SHIFT; |
f900a4b8 BP |
1006 | cur_pages += PMD_SIZE >> PAGE_SHIFT; |
1007 | } | |
1008 | ||
1009 | /* | |
1010 | * Map trailing 4K pages. | |
1011 | */ | |
1012 | if (start < end) { | |
1013 | pmd = pmd_offset(pud, start); | |
1014 | if (pmd_none(*pmd)) | |
1015 | if (alloc_pte_page(pmd)) | |
1016 | return -1; | |
1017 | ||
1018 | populate_pte(cpa, start, end, num_pages - cur_pages, | |
1019 | pmd, pgprot); | |
1020 | } | |
1021 | return num_pages; | |
1022 | } | |
4b23538d | 1023 | |
45478336 KS |
1024 | static int populate_pud(struct cpa_data *cpa, unsigned long start, p4d_t *p4d, |
1025 | pgprot_t pgprot) | |
4b23538d BP |
1026 | { |
1027 | pud_t *pud; | |
1028 | unsigned long end; | |
e535ec08 | 1029 | long cur_pages = 0; |
f5b2831d | 1030 | pgprot_t pud_pgprot; |
4b23538d BP |
1031 | |
1032 | end = start + (cpa->numpages << PAGE_SHIFT); | |
1033 | ||
1034 | /* | |
1035 | * Not on a Gb page boundary? => map everything up to it with | |
1036 | * smaller pages. | |
1037 | */ | |
1038 | if (start & (PUD_SIZE - 1)) { | |
1039 | unsigned long pre_end; | |
1040 | unsigned long next_page = (start + PUD_SIZE) & PUD_MASK; | |
1041 | ||
1042 | pre_end = min_t(unsigned long, end, next_page); | |
1043 | cur_pages = (pre_end - start) >> PAGE_SHIFT; | |
1044 | cur_pages = min_t(int, (int)cpa->numpages, cur_pages); | |
1045 | ||
45478336 | 1046 | pud = pud_offset(p4d, start); |
4b23538d BP |
1047 | |
1048 | /* | |
1049 | * Need a PMD page? | |
1050 | */ | |
1051 | if (pud_none(*pud)) | |
1052 | if (alloc_pmd_page(pud)) | |
1053 | return -1; | |
1054 | ||
1055 | cur_pages = populate_pmd(cpa, start, pre_end, cur_pages, | |
1056 | pud, pgprot); | |
1057 | if (cur_pages < 0) | |
1058 | return cur_pages; | |
1059 | ||
1060 | start = pre_end; | |
1061 | } | |
1062 | ||
1063 | /* We mapped them all? */ | |
1064 | if (cpa->numpages == cur_pages) | |
1065 | return cur_pages; | |
1066 | ||
45478336 | 1067 | pud = pud_offset(p4d, start); |
f5b2831d | 1068 | pud_pgprot = pgprot_4k_2_large(pgprot); |
4b23538d BP |
1069 | |
1070 | /* | |
1071 | * Map everything starting from the Gb boundary, possibly with 1G pages | |
1072 | */ | |
b8291adc | 1073 | while (boot_cpu_has(X86_FEATURE_GBPAGES) && end - start >= PUD_SIZE) { |
edc3b912 | 1074 | set_pud(pud, __pud(cpa->pfn << PAGE_SHIFT | _PAGE_PSE | |
f5b2831d | 1075 | massage_pgprot(pud_pgprot))); |
4b23538d BP |
1076 | |
1077 | start += PUD_SIZE; | |
edc3b912 | 1078 | cpa->pfn += PUD_SIZE >> PAGE_SHIFT; |
4b23538d BP |
1079 | cur_pages += PUD_SIZE >> PAGE_SHIFT; |
1080 | pud++; | |
1081 | } | |
1082 | ||
1083 | /* Map trailing leftover */ | |
1084 | if (start < end) { | |
e535ec08 | 1085 | long tmp; |
4b23538d | 1086 | |
45478336 | 1087 | pud = pud_offset(p4d, start); |
4b23538d BP |
1088 | if (pud_none(*pud)) |
1089 | if (alloc_pmd_page(pud)) | |
1090 | return -1; | |
1091 | ||
1092 | tmp = populate_pmd(cpa, start, end, cpa->numpages - cur_pages, | |
1093 | pud, pgprot); | |
1094 | if (tmp < 0) | |
1095 | return cur_pages; | |
1096 | ||
1097 | cur_pages += tmp; | |
1098 | } | |
1099 | return cur_pages; | |
1100 | } | |
f3f72966 BP |
1101 | |
1102 | /* | |
1103 | * Restrictions for kernel page table do not necessarily apply when mapping in | |
1104 | * an alternate PGD. | |
1105 | */ | |
1106 | static int populate_pgd(struct cpa_data *cpa, unsigned long addr) | |
1107 | { | |
1108 | pgprot_t pgprot = __pgprot(_KERNPG_TABLE); | |
f3f72966 | 1109 | pud_t *pud = NULL; /* shut up gcc */ |
45478336 | 1110 | p4d_t *p4d; |
42a54772 | 1111 | pgd_t *pgd_entry; |
e535ec08 | 1112 | long ret; |
f3f72966 BP |
1113 | |
1114 | pgd_entry = cpa->pgd + pgd_index(addr); | |
1115 | ||
45478336 KS |
1116 | if (pgd_none(*pgd_entry)) { |
1117 | p4d = (p4d_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK); | |
1118 | if (!p4d) | |
1119 | return -1; | |
1120 | ||
1121 | set_pgd(pgd_entry, __pgd(__pa(p4d) | _KERNPG_TABLE)); | |
1122 | } | |
1123 | ||
f3f72966 BP |
1124 | /* |
1125 | * Allocate a PUD page and hand it down for mapping. | |
1126 | */ | |
45478336 KS |
1127 | p4d = p4d_offset(pgd_entry, addr); |
1128 | if (p4d_none(*p4d)) { | |
f3f72966 BP |
1129 | pud = (pud_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK); |
1130 | if (!pud) | |
1131 | return -1; | |
530dd8d4 | 1132 | |
45478336 | 1133 | set_p4d(p4d, __p4d(__pa(pud) | _KERNPG_TABLE)); |
f3f72966 BP |
1134 | } |
1135 | ||
1136 | pgprot_val(pgprot) &= ~pgprot_val(cpa->mask_clr); | |
1137 | pgprot_val(pgprot) |= pgprot_val(cpa->mask_set); | |
1138 | ||
45478336 | 1139 | ret = populate_pud(cpa, addr, p4d, pgprot); |
0bb8aeee | 1140 | if (ret < 0) { |
55920d31 AL |
1141 | /* |
1142 | * Leave the PUD page in place in case some other CPU or thread | |
1143 | * already found it, but remove any useless entries we just | |
1144 | * added to it. | |
1145 | */ | |
45478336 | 1146 | unmap_pud_range(p4d, addr, |
0bb8aeee | 1147 | addr + (cpa->numpages << PAGE_SHIFT)); |
f3f72966 | 1148 | return ret; |
0bb8aeee | 1149 | } |
42a54772 | 1150 | |
f3f72966 BP |
1151 | cpa->numpages = ret; |
1152 | return 0; | |
1153 | } | |
1154 | ||
a1e46212 SS |
1155 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
1156 | int primary) | |
1157 | { | |
7fc8442f MF |
1158 | if (cpa->pgd) { |
1159 | /* | |
1160 | * Right now, we only execute this code path when mapping | |
1161 | * the EFI virtual memory map regions, no other users | |
1162 | * provide a ->pgd value. This may change in the future. | |
1163 | */ | |
82f0712c | 1164 | return populate_pgd(cpa, vaddr); |
7fc8442f | 1165 | } |
82f0712c | 1166 | |
a1e46212 SS |
1167 | /* |
1168 | * Ignore all non primary paths. | |
1169 | */ | |
405e1133 JB |
1170 | if (!primary) { |
1171 | cpa->numpages = 1; | |
a1e46212 | 1172 | return 0; |
405e1133 | 1173 | } |
a1e46212 SS |
1174 | |
1175 | /* | |
1176 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
1177 | * to have holes. | |
1178 | * Also set numpages to '1' indicating that we processed cpa req for | |
1179 | * one virtual address page and its pfn. TBD: numpages can be set based | |
1180 | * on the initial value and the level returned by lookup_address(). | |
1181 | */ | |
1182 | if (within(vaddr, PAGE_OFFSET, | |
1183 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
1184 | cpa->numpages = 1; | |
1185 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
1186 | return 0; | |
1187 | } else { | |
1188 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
1189 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
1190 | *cpa->vaddr); | |
1191 | ||
1192 | return -EFAULT; | |
1193 | } | |
1194 | } | |
1195 | ||
c31c7d48 | 1196 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 1197 | { |
d75586ad | 1198 | unsigned long address; |
da7bfc50 HH |
1199 | int do_split, err; |
1200 | unsigned int level; | |
c31c7d48 | 1201 | pte_t *kpte, old_pte; |
1da177e4 | 1202 | |
8523acfe TH |
1203 | if (cpa->flags & CPA_PAGES_ARRAY) { |
1204 | struct page *page = cpa->pages[cpa->curpage]; | |
1205 | if (unlikely(PageHighMem(page))) | |
1206 | return 0; | |
1207 | address = (unsigned long)page_address(page); | |
1208 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
1209 | address = cpa->vaddr[cpa->curpage]; |
1210 | else | |
1211 | address = *cpa->vaddr; | |
97f99fed | 1212 | repeat: |
82f0712c | 1213 | kpte = _lookup_address_cpa(cpa, address, &level); |
1da177e4 | 1214 | if (!kpte) |
a1e46212 | 1215 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
1216 | |
1217 | old_pte = *kpte; | |
dcb32d99 | 1218 | if (pte_none(old_pte)) |
a1e46212 | 1219 | return __cpa_process_fault(cpa, address, primary); |
9f4c815c | 1220 | |
30551bb3 | 1221 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 1222 | pte_t new_pte; |
626c2c9d | 1223 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 1224 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 1225 | |
72e458df TG |
1226 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
1227 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 1228 | |
c31c7d48 | 1229 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 1230 | |
a8aed3e0 AA |
1231 | /* |
1232 | * Set the GLOBAL flags only if the PRESENT flag is | |
1233 | * set otherwise pte_present will return true even on | |
1234 | * a non present pte. The canon_pgprot will clear | |
1235 | * _PAGE_GLOBAL for the ancient hardware that doesn't | |
1236 | * support it. | |
1237 | */ | |
1238 | if (pgprot_val(new_prot) & _PAGE_PRESENT) | |
1239 | pgprot_val(new_prot) |= _PAGE_GLOBAL; | |
1240 | else | |
1241 | pgprot_val(new_prot) &= ~_PAGE_GLOBAL; | |
1242 | ||
626c2c9d AV |
1243 | /* |
1244 | * We need to keep the pfn from the existing PTE, | |
1245 | * after all we're only going to change it's attributes | |
1246 | * not the memory it points to | |
1247 | */ | |
c31c7d48 TG |
1248 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
1249 | cpa->pfn = pfn; | |
f4ae5da0 TG |
1250 | /* |
1251 | * Do we really change anything ? | |
1252 | */ | |
1253 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
1254 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 1255 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 1256 | } |
9b5cf48b | 1257 | cpa->numpages = 1; |
65e074df | 1258 | return 0; |
1da177e4 | 1259 | } |
65e074df TG |
1260 | |
1261 | /* | |
1262 | * Check, whether we can keep the large page intact | |
1263 | * and just change the pte: | |
1264 | */ | |
beaff633 | 1265 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
1266 | /* |
1267 | * When the range fits into the existing large page, | |
9b5cf48b | 1268 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
1269 | * try_large_page: |
1270 | */ | |
87f7f8fe IM |
1271 | if (do_split <= 0) |
1272 | return do_split; | |
65e074df TG |
1273 | |
1274 | /* | |
1275 | * We have to split the large page: | |
1276 | */ | |
82f0712c | 1277 | err = split_large_page(cpa, kpte, address); |
87f7f8fe | 1278 | if (!err) { |
ad5ca55f SS |
1279 | /* |
1280 | * Do a global flush tlb after splitting the large page | |
1281 | * and before we do the actual change page attribute in the PTE. | |
1282 | * | |
1283 | * With out this, we violate the TLB application note, that says | |
1284 | * "The TLBs may contain both ordinary and large-page | |
1285 | * translations for a 4-KByte range of linear addresses. This | |
1286 | * may occur if software modifies the paging structures so that | |
1287 | * the page size used for the address range changes. If the two | |
1288 | * translations differ with respect to page frame or attributes | |
1289 | * (e.g., permissions), processor behavior is undefined and may | |
1290 | * be implementation-specific." | |
1291 | * | |
1292 | * We do this global tlb flush inside the cpa_lock, so that we | |
1293 | * don't allow any other cpu, with stale tlb entries change the | |
1294 | * page attribute in parallel, that also falls into the | |
1295 | * just split large page entry. | |
1296 | */ | |
1297 | flush_tlb_all(); | |
87f7f8fe IM |
1298 | goto repeat; |
1299 | } | |
beaff633 | 1300 | |
87f7f8fe | 1301 | return err; |
9f4c815c | 1302 | } |
1da177e4 | 1303 | |
c31c7d48 TG |
1304 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
1305 | ||
1306 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 1307 | { |
c31c7d48 | 1308 | struct cpa_data alias_cpa; |
992f4c1c | 1309 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
e933a73f | 1310 | unsigned long vaddr; |
992f4c1c | 1311 | int ret; |
44af6c41 | 1312 | |
8eb5779f | 1313 | if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1)) |
c31c7d48 | 1314 | return 0; |
626c2c9d | 1315 | |
f34b439f TG |
1316 | /* |
1317 | * No need to redo, when the primary call touched the direct | |
1318 | * mapping already: | |
1319 | */ | |
8523acfe TH |
1320 | if (cpa->flags & CPA_PAGES_ARRAY) { |
1321 | struct page *page = cpa->pages[cpa->curpage]; | |
1322 | if (unlikely(PageHighMem(page))) | |
1323 | return 0; | |
1324 | vaddr = (unsigned long)page_address(page); | |
1325 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
1326 | vaddr = cpa->vaddr[cpa->curpage]; |
1327 | else | |
1328 | vaddr = *cpa->vaddr; | |
1329 | ||
1330 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 1331 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 1332 | |
f34b439f | 1333 | alias_cpa = *cpa; |
992f4c1c | 1334 | alias_cpa.vaddr = &laddr; |
9ae28475 | 1335 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
d75586ad | 1336 | |
f34b439f | 1337 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
992f4c1c TH |
1338 | if (ret) |
1339 | return ret; | |
f34b439f | 1340 | } |
44af6c41 | 1341 | |
44af6c41 | 1342 | #ifdef CONFIG_X86_64 |
488fd995 | 1343 | /* |
992f4c1c TH |
1344 | * If the primary call didn't touch the high mapping already |
1345 | * and the physical address is inside the kernel map, we need | |
0879750f | 1346 | * to touch the high mapped kernel as well: |
488fd995 | 1347 | */ |
992f4c1c | 1348 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
4ff53087 TG |
1349 | within_inclusive(cpa->pfn, highmap_start_pfn(), |
1350 | highmap_end_pfn())) { | |
992f4c1c TH |
1351 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + |
1352 | __START_KERNEL_map - phys_base; | |
1353 | alias_cpa = *cpa; | |
1354 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
1355 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
c31c7d48 | 1356 | |
992f4c1c TH |
1357 | /* |
1358 | * The high mapping range is imprecise, so ignore the | |
1359 | * return value. | |
1360 | */ | |
1361 | __change_page_attr_set_clr(&alias_cpa, 0); | |
1362 | } | |
488fd995 | 1363 | #endif |
992f4c1c TH |
1364 | |
1365 | return 0; | |
1da177e4 LT |
1366 | } |
1367 | ||
c31c7d48 | 1368 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 1369 | { |
e535ec08 MF |
1370 | unsigned long numpages = cpa->numpages; |
1371 | int ret; | |
ff31452b | 1372 | |
65e074df TG |
1373 | while (numpages) { |
1374 | /* | |
1375 | * Store the remaining nr of pages for the large page | |
1376 | * preservation check. | |
1377 | */ | |
9b5cf48b | 1378 | cpa->numpages = numpages; |
d75586ad | 1379 | /* for array changes, we can't use large page */ |
9ae28475 | 1380 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 1381 | cpa->numpages = 1; |
c31c7d48 | 1382 | |
288cf3c6 | 1383 | if (!debug_pagealloc_enabled()) |
ad5ca55f | 1384 | spin_lock(&cpa_lock); |
c31c7d48 | 1385 | ret = __change_page_attr(cpa, checkalias); |
288cf3c6 | 1386 | if (!debug_pagealloc_enabled()) |
ad5ca55f | 1387 | spin_unlock(&cpa_lock); |
ff31452b TG |
1388 | if (ret) |
1389 | return ret; | |
ff31452b | 1390 | |
c31c7d48 TG |
1391 | if (checkalias) { |
1392 | ret = cpa_process_alias(cpa); | |
1393 | if (ret) | |
1394 | return ret; | |
1395 | } | |
1396 | ||
65e074df TG |
1397 | /* |
1398 | * Adjust the number of pages with the result of the | |
1399 | * CPA operation. Either a large page has been | |
1400 | * preserved or a single page update happened. | |
1401 | */ | |
74256377 | 1402 | BUG_ON(cpa->numpages > numpages || !cpa->numpages); |
9b5cf48b | 1403 | numpages -= cpa->numpages; |
9ae28475 | 1404 | if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
d75586ad SL |
1405 | cpa->curpage++; |
1406 | else | |
1407 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
1408 | ||
65e074df | 1409 | } |
ff31452b TG |
1410 | return 0; |
1411 | } | |
1412 | ||
d75586ad | 1413 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 1414 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 1415 | int force_split, int in_flag, |
1416 | struct page **pages) | |
ff31452b | 1417 | { |
72e458df | 1418 | struct cpa_data cpa; |
cacf8906 | 1419 | int ret, cache, checkalias; |
fa526d0d | 1420 | unsigned long baddr = 0; |
331e4065 | 1421 | |
82f0712c BP |
1422 | memset(&cpa, 0, sizeof(cpa)); |
1423 | ||
331e4065 TG |
1424 | /* |
1425 | * Check, if we are requested to change a not supported | |
1426 | * feature: | |
1427 | */ | |
1428 | mask_set = canon_pgprot(mask_set); | |
1429 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 1430 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
1431 | return 0; |
1432 | ||
69b1415e | 1433 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 1434 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
1435 | int i; |
1436 | for (i = 0; i < numpages; i++) { | |
1437 | if (addr[i] & ~PAGE_MASK) { | |
1438 | addr[i] &= PAGE_MASK; | |
1439 | WARN_ON_ONCE(1); | |
1440 | } | |
1441 | } | |
9ae28475 | 1442 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
1443 | /* | |
1444 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
1445 | * No need to cehck in that case | |
1446 | */ | |
1447 | if (*addr & ~PAGE_MASK) { | |
1448 | *addr &= PAGE_MASK; | |
1449 | /* | |
1450 | * People should not be passing in unaligned addresses: | |
1451 | */ | |
1452 | WARN_ON_ONCE(1); | |
1453 | } | |
fa526d0d JS |
1454 | /* |
1455 | * Save address for cache flush. *addr is modified in the call | |
1456 | * to __change_page_attr_set_clr() below. | |
1457 | */ | |
1458 | baddr = *addr; | |
69b1415e TG |
1459 | } |
1460 | ||
5843d9a4 NP |
1461 | /* Must avoid aliasing mappings in the highmem code */ |
1462 | kmap_flush_unused(); | |
1463 | ||
db64fe02 NP |
1464 | vm_unmap_aliases(); |
1465 | ||
72e458df | 1466 | cpa.vaddr = addr; |
9ae28475 | 1467 | cpa.pages = pages; |
72e458df TG |
1468 | cpa.numpages = numpages; |
1469 | cpa.mask_set = mask_set; | |
1470 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
1471 | cpa.flags = 0; |
1472 | cpa.curpage = 0; | |
c9caa02c | 1473 | cpa.force_split = force_split; |
72e458df | 1474 | |
9ae28475 | 1475 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
1476 | cpa.flags |= in_flag; | |
d75586ad | 1477 | |
af96e443 TG |
1478 | /* No alias checking for _NX bit modifications */ |
1479 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
1480 | ||
1481 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 1482 | |
f4ae5da0 TG |
1483 | /* |
1484 | * Check whether we really changed something: | |
1485 | */ | |
d75586ad | 1486 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 1487 | goto out; |
cacf8906 | 1488 | |
6bb8383b AK |
1489 | /* |
1490 | * No need to flush, when we did not set any of the caching | |
1491 | * attributes: | |
1492 | */ | |
c06814d8 | 1493 | cache = !!pgprot2cachemode(mask_set); |
6bb8383b | 1494 | |
57a6a46a | 1495 | /* |
b82ad3d3 BP |
1496 | * On success we use CLFLUSH, when the CPU supports it to |
1497 | * avoid the WBINVD. If the CPU does not support it and in the | |
f026cfa8 | 1498 | * error case we fall back to cpa_flush_all (which uses |
b82ad3d3 | 1499 | * WBINVD): |
57a6a46a | 1500 | */ |
906bf7fd | 1501 | if (!ret && boot_cpu_has(X86_FEATURE_CLFLUSH)) { |
9ae28475 | 1502 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { |
1503 | cpa_flush_array(addr, numpages, cache, | |
1504 | cpa.flags, pages); | |
1505 | } else | |
fa526d0d | 1506 | cpa_flush_range(baddr, numpages, cache); |
d75586ad | 1507 | } else |
6bb8383b | 1508 | cpa_flush_all(cache); |
cacf8906 | 1509 | |
76ebd054 | 1510 | out: |
ff31452b TG |
1511 | return ret; |
1512 | } | |
1513 | ||
d75586ad SL |
1514 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
1515 | pgprot_t mask, int array) | |
75cbade8 | 1516 | { |
d75586ad | 1517 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 1518 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
1519 | } |
1520 | ||
d75586ad SL |
1521 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
1522 | pgprot_t mask, int array) | |
72932c7a | 1523 | { |
d75586ad | 1524 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 1525 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
1526 | } |
1527 | ||
0f350755 | 1528 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
1529 | pgprot_t mask) | |
1530 | { | |
1531 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, | |
1532 | CPA_PAGES_ARRAY, pages); | |
1533 | } | |
1534 | ||
1535 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, | |
1536 | pgprot_t mask) | |
1537 | { | |
1538 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, | |
1539 | CPA_PAGES_ARRAY, pages); | |
1540 | } | |
1541 | ||
1219333d | 1542 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 1543 | { |
de33c442 SS |
1544 | /* |
1545 | * for now UC MINUS. see comments in ioremap_nocache() | |
e4b6be33 LR |
1546 | * If you really need strong UC use ioremap_uc(), but note |
1547 | * that you cannot override IO areas with set_memory_*() as | |
1548 | * these helpers cannot work with IO memory. | |
de33c442 | 1549 | */ |
d75586ad | 1550 | return change_page_attr_set(&addr, numpages, |
c06814d8 JG |
1551 | cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS), |
1552 | 0); | |
75cbade8 | 1553 | } |
1219333d | 1554 | |
1555 | int set_memory_uc(unsigned long addr, int numpages) | |
1556 | { | |
9fa3ab39 | 1557 | int ret; |
1558 | ||
de33c442 SS |
1559 | /* |
1560 | * for now UC MINUS. see comments in ioremap_nocache() | |
1561 | */ | |
9fa3ab39 | 1562 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
e00c8cc9 | 1563 | _PAGE_CACHE_MODE_UC_MINUS, NULL); |
9fa3ab39 | 1564 | if (ret) |
1565 | goto out_err; | |
1566 | ||
1567 | ret = _set_memory_uc(addr, numpages); | |
1568 | if (ret) | |
1569 | goto out_free; | |
1570 | ||
1571 | return 0; | |
1219333d | 1572 | |
9fa3ab39 | 1573 | out_free: |
1574 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1575 | out_err: | |
1576 | return ret; | |
1219333d | 1577 | } |
75cbade8 AV |
1578 | EXPORT_SYMBOL(set_memory_uc); |
1579 | ||
2d070eff | 1580 | static int _set_memory_array(unsigned long *addr, int addrinarray, |
c06814d8 | 1581 | enum page_cache_mode new_type) |
d75586ad | 1582 | { |
623dffb2 | 1583 | enum page_cache_mode set_type; |
9fa3ab39 | 1584 | int i, j; |
1585 | int ret; | |
1586 | ||
d75586ad | 1587 | for (i = 0; i < addrinarray; i++) { |
9fa3ab39 | 1588 | ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, |
4f646254 | 1589 | new_type, NULL); |
9fa3ab39 | 1590 | if (ret) |
1591 | goto out_free; | |
d75586ad SL |
1592 | } |
1593 | ||
623dffb2 TK |
1594 | /* If WC, set to UC- first and then WC */ |
1595 | set_type = (new_type == _PAGE_CACHE_MODE_WC) ? | |
1596 | _PAGE_CACHE_MODE_UC_MINUS : new_type; | |
1597 | ||
9fa3ab39 | 1598 | ret = change_page_attr_set(addr, addrinarray, |
623dffb2 | 1599 | cachemode2pgprot(set_type), 1); |
4f646254 | 1600 | |
c06814d8 | 1601 | if (!ret && new_type == _PAGE_CACHE_MODE_WC) |
4f646254 | 1602 | ret = change_page_attr_set_clr(addr, addrinarray, |
c06814d8 JG |
1603 | cachemode2pgprot( |
1604 | _PAGE_CACHE_MODE_WC), | |
4f646254 PN |
1605 | __pgprot(_PAGE_CACHE_MASK), |
1606 | 0, CPA_ARRAY, NULL); | |
9fa3ab39 | 1607 | if (ret) |
1608 | goto out_free; | |
1609 | ||
1610 | return 0; | |
1611 | ||
1612 | out_free: | |
1613 | for (j = 0; j < i; j++) | |
1614 | free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE); | |
1615 | ||
1616 | return ret; | |
d75586ad | 1617 | } |
4f646254 PN |
1618 | |
1619 | int set_memory_array_uc(unsigned long *addr, int addrinarray) | |
1620 | { | |
c06814d8 | 1621 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_UC_MINUS); |
4f646254 | 1622 | } |
d75586ad SL |
1623 | EXPORT_SYMBOL(set_memory_array_uc); |
1624 | ||
4f646254 PN |
1625 | int set_memory_array_wc(unsigned long *addr, int addrinarray) |
1626 | { | |
c06814d8 | 1627 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WC); |
4f646254 PN |
1628 | } |
1629 | EXPORT_SYMBOL(set_memory_array_wc); | |
1630 | ||
623dffb2 TK |
1631 | int set_memory_array_wt(unsigned long *addr, int addrinarray) |
1632 | { | |
1633 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WT); | |
1634 | } | |
1635 | EXPORT_SYMBOL_GPL(set_memory_array_wt); | |
1636 | ||
ef354af4 | 1637 | int _set_memory_wc(unsigned long addr, int numpages) |
1638 | { | |
3869c4aa | 1639 | int ret; |
bdc6340f PV |
1640 | unsigned long addr_copy = addr; |
1641 | ||
3869c4aa | 1642 | ret = change_page_attr_set(&addr, numpages, |
c06814d8 JG |
1643 | cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS), |
1644 | 0); | |
3869c4aa | 1645 | if (!ret) { |
bdc6340f | 1646 | ret = change_page_attr_set_clr(&addr_copy, numpages, |
c06814d8 JG |
1647 | cachemode2pgprot( |
1648 | _PAGE_CACHE_MODE_WC), | |
bdc6340f PV |
1649 | __pgprot(_PAGE_CACHE_MASK), |
1650 | 0, 0, NULL); | |
3869c4aa | 1651 | } |
1652 | return ret; | |
ef354af4 | 1653 | } |
1654 | ||
1655 | int set_memory_wc(unsigned long addr, int numpages) | |
1656 | { | |
9fa3ab39 | 1657 | int ret; |
1658 | ||
9fa3ab39 | 1659 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
e00c8cc9 | 1660 | _PAGE_CACHE_MODE_WC, NULL); |
9fa3ab39 | 1661 | if (ret) |
623dffb2 | 1662 | return ret; |
ef354af4 | 1663 | |
9fa3ab39 | 1664 | ret = _set_memory_wc(addr, numpages); |
1665 | if (ret) | |
623dffb2 | 1666 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1667 | |
9fa3ab39 | 1668 | return ret; |
ef354af4 | 1669 | } |
1670 | EXPORT_SYMBOL(set_memory_wc); | |
1671 | ||
623dffb2 TK |
1672 | int _set_memory_wt(unsigned long addr, int numpages) |
1673 | { | |
1674 | return change_page_attr_set(&addr, numpages, | |
1675 | cachemode2pgprot(_PAGE_CACHE_MODE_WT), 0); | |
1676 | } | |
1677 | ||
1678 | int set_memory_wt(unsigned long addr, int numpages) | |
1679 | { | |
1680 | int ret; | |
1681 | ||
1682 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, | |
1683 | _PAGE_CACHE_MODE_WT, NULL); | |
1684 | if (ret) | |
1685 | return ret; | |
1686 | ||
1687 | ret = _set_memory_wt(addr, numpages); | |
1688 | if (ret) | |
1689 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1690 | ||
1691 | return ret; | |
1692 | } | |
1693 | EXPORT_SYMBOL_GPL(set_memory_wt); | |
1694 | ||
1219333d | 1695 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1696 | { |
c06814d8 | 1697 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
d75586ad SL |
1698 | return change_page_attr_clear(&addr, numpages, |
1699 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1700 | } |
1219333d | 1701 | |
1702 | int set_memory_wb(unsigned long addr, int numpages) | |
1703 | { | |
9fa3ab39 | 1704 | int ret; |
1705 | ||
1706 | ret = _set_memory_wb(addr, numpages); | |
1707 | if (ret) | |
1708 | return ret; | |
1709 | ||
c15238df | 1710 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1711 | return 0; |
1219333d | 1712 | } |
75cbade8 AV |
1713 | EXPORT_SYMBOL(set_memory_wb); |
1714 | ||
d75586ad SL |
1715 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
1716 | { | |
1717 | int i; | |
a5593e0b | 1718 | int ret; |
1719 | ||
c06814d8 | 1720 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
a5593e0b | 1721 | ret = change_page_attr_clear(addr, addrinarray, |
1722 | __pgprot(_PAGE_CACHE_MASK), 1); | |
9fa3ab39 | 1723 | if (ret) |
1724 | return ret; | |
d75586ad | 1725 | |
9fa3ab39 | 1726 | for (i = 0; i < addrinarray; i++) |
1727 | free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE); | |
c5e147cf | 1728 | |
9fa3ab39 | 1729 | return 0; |
d75586ad SL |
1730 | } |
1731 | EXPORT_SYMBOL(set_memory_array_wb); | |
1732 | ||
75cbade8 AV |
1733 | int set_memory_x(unsigned long addr, int numpages) |
1734 | { | |
583140af PA |
1735 | if (!(__supported_pte_mask & _PAGE_NX)) |
1736 | return 0; | |
1737 | ||
d75586ad | 1738 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1739 | } |
1740 | EXPORT_SYMBOL(set_memory_x); | |
1741 | ||
1742 | int set_memory_nx(unsigned long addr, int numpages) | |
1743 | { | |
583140af PA |
1744 | if (!(__supported_pte_mask & _PAGE_NX)) |
1745 | return 0; | |
1746 | ||
d75586ad | 1747 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1748 | } |
1749 | EXPORT_SYMBOL(set_memory_nx); | |
1750 | ||
1751 | int set_memory_ro(unsigned long addr, int numpages) | |
1752 | { | |
d75586ad | 1753 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1754 | } |
75cbade8 AV |
1755 | |
1756 | int set_memory_rw(unsigned long addr, int numpages) | |
1757 | { | |
d75586ad | 1758 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1759 | } |
f62d0f00 IM |
1760 | |
1761 | int set_memory_np(unsigned long addr, int numpages) | |
1762 | { | |
d75586ad | 1763 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1764 | } |
75cbade8 | 1765 | |
c9caa02c AK |
1766 | int set_memory_4k(unsigned long addr, int numpages) |
1767 | { | |
d75586ad | 1768 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 1769 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
1770 | } |
1771 | ||
75cbade8 AV |
1772 | int set_pages_uc(struct page *page, int numpages) |
1773 | { | |
1774 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1775 | |
d7c8f21a | 1776 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1777 | } |
1778 | EXPORT_SYMBOL(set_pages_uc); | |
1779 | ||
4f646254 | 1780 | static int _set_pages_array(struct page **pages, int addrinarray, |
c06814d8 | 1781 | enum page_cache_mode new_type) |
0f350755 | 1782 | { |
1783 | unsigned long start; | |
1784 | unsigned long end; | |
623dffb2 | 1785 | enum page_cache_mode set_type; |
0f350755 | 1786 | int i; |
1787 | int free_idx; | |
4f646254 | 1788 | int ret; |
0f350755 | 1789 | |
1790 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1791 | if (PageHighMem(pages[i])) |
1792 | continue; | |
1793 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1794 | end = start + PAGE_SIZE; |
4f646254 | 1795 | if (reserve_memtype(start, end, new_type, NULL)) |
0f350755 | 1796 | goto err_out; |
1797 | } | |
1798 | ||
623dffb2 TK |
1799 | /* If WC, set to UC- first and then WC */ |
1800 | set_type = (new_type == _PAGE_CACHE_MODE_WC) ? | |
1801 | _PAGE_CACHE_MODE_UC_MINUS : new_type; | |
1802 | ||
4f646254 | 1803 | ret = cpa_set_pages_array(pages, addrinarray, |
623dffb2 | 1804 | cachemode2pgprot(set_type)); |
c06814d8 | 1805 | if (!ret && new_type == _PAGE_CACHE_MODE_WC) |
4f646254 | 1806 | ret = change_page_attr_set_clr(NULL, addrinarray, |
c06814d8 JG |
1807 | cachemode2pgprot( |
1808 | _PAGE_CACHE_MODE_WC), | |
4f646254 PN |
1809 | __pgprot(_PAGE_CACHE_MASK), |
1810 | 0, CPA_PAGES_ARRAY, pages); | |
1811 | if (ret) | |
1812 | goto err_out; | |
1813 | return 0; /* Success */ | |
0f350755 | 1814 | err_out: |
1815 | free_idx = i; | |
1816 | for (i = 0; i < free_idx; i++) { | |
8523acfe TH |
1817 | if (PageHighMem(pages[i])) |
1818 | continue; | |
1819 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1820 | end = start + PAGE_SIZE; |
1821 | free_memtype(start, end); | |
1822 | } | |
1823 | return -EINVAL; | |
1824 | } | |
4f646254 PN |
1825 | |
1826 | int set_pages_array_uc(struct page **pages, int addrinarray) | |
1827 | { | |
c06814d8 | 1828 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_UC_MINUS); |
4f646254 | 1829 | } |
0f350755 | 1830 | EXPORT_SYMBOL(set_pages_array_uc); |
1831 | ||
4f646254 PN |
1832 | int set_pages_array_wc(struct page **pages, int addrinarray) |
1833 | { | |
c06814d8 | 1834 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WC); |
4f646254 PN |
1835 | } |
1836 | EXPORT_SYMBOL(set_pages_array_wc); | |
1837 | ||
623dffb2 TK |
1838 | int set_pages_array_wt(struct page **pages, int addrinarray) |
1839 | { | |
1840 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WT); | |
1841 | } | |
1842 | EXPORT_SYMBOL_GPL(set_pages_array_wt); | |
1843 | ||
75cbade8 AV |
1844 | int set_pages_wb(struct page *page, int numpages) |
1845 | { | |
1846 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1847 | |
d7c8f21a | 1848 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1849 | } |
1850 | EXPORT_SYMBOL(set_pages_wb); | |
1851 | ||
0f350755 | 1852 | int set_pages_array_wb(struct page **pages, int addrinarray) |
1853 | { | |
1854 | int retval; | |
1855 | unsigned long start; | |
1856 | unsigned long end; | |
1857 | int i; | |
1858 | ||
c06814d8 | 1859 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
0f350755 | 1860 | retval = cpa_clear_pages_array(pages, addrinarray, |
1861 | __pgprot(_PAGE_CACHE_MASK)); | |
9fa3ab39 | 1862 | if (retval) |
1863 | return retval; | |
0f350755 | 1864 | |
1865 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1866 | if (PageHighMem(pages[i])) |
1867 | continue; | |
1868 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1869 | end = start + PAGE_SIZE; |
1870 | free_memtype(start, end); | |
1871 | } | |
1872 | ||
9fa3ab39 | 1873 | return 0; |
0f350755 | 1874 | } |
1875 | EXPORT_SYMBOL(set_pages_array_wb); | |
1876 | ||
75cbade8 AV |
1877 | int set_pages_x(struct page *page, int numpages) |
1878 | { | |
1879 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1880 | |
d7c8f21a | 1881 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1882 | } |
1883 | EXPORT_SYMBOL(set_pages_x); | |
1884 | ||
1885 | int set_pages_nx(struct page *page, int numpages) | |
1886 | { | |
1887 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1888 | |
d7c8f21a | 1889 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1890 | } |
1891 | EXPORT_SYMBOL(set_pages_nx); | |
1892 | ||
1893 | int set_pages_ro(struct page *page, int numpages) | |
1894 | { | |
1895 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1896 | |
d7c8f21a | 1897 | return set_memory_ro(addr, numpages); |
75cbade8 | 1898 | } |
75cbade8 AV |
1899 | |
1900 | int set_pages_rw(struct page *page, int numpages) | |
1901 | { | |
1902 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1903 | |
d7c8f21a | 1904 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1905 | } |
1906 | ||
1da177e4 | 1907 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1908 | |
1909 | static int __set_pages_p(struct page *page, int numpages) | |
1910 | { | |
d75586ad SL |
1911 | unsigned long tempaddr = (unsigned long) page_address(page); |
1912 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
82f0712c | 1913 | .pgd = NULL, |
72e458df TG |
1914 | .numpages = numpages, |
1915 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1916 | .mask_clr = __pgprot(0), |
1917 | .flags = 0}; | |
72932c7a | 1918 | |
55121b43 SS |
1919 | /* |
1920 | * No alias checking needed for setting present flag. otherwise, | |
1921 | * we may need to break large pages for 64-bit kernel text | |
1922 | * mappings (this adds to complexity if we want to do this from | |
1923 | * atomic context especially). Let's keep it simple! | |
1924 | */ | |
1925 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1926 | } |
1927 | ||
1928 | static int __set_pages_np(struct page *page, int numpages) | |
1929 | { | |
d75586ad SL |
1930 | unsigned long tempaddr = (unsigned long) page_address(page); |
1931 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
82f0712c | 1932 | .pgd = NULL, |
72e458df TG |
1933 | .numpages = numpages, |
1934 | .mask_set = __pgprot(0), | |
d75586ad SL |
1935 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1936 | .flags = 0}; | |
72932c7a | 1937 | |
55121b43 SS |
1938 | /* |
1939 | * No alias checking needed for setting not present flag. otherwise, | |
1940 | * we may need to break large pages for 64-bit kernel text | |
1941 | * mappings (this adds to complexity if we want to do this from | |
1942 | * atomic context especially). Let's keep it simple! | |
1943 | */ | |
1944 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1945 | } |
1946 | ||
031bc574 | 1947 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
1da177e4 LT |
1948 | { |
1949 | if (PageHighMem(page)) | |
1950 | return; | |
9f4c815c | 1951 | if (!enable) { |
f9b8404c IM |
1952 | debug_check_no_locks_freed(page_address(page), |
1953 | numpages * PAGE_SIZE); | |
9f4c815c | 1954 | } |
de5097c2 | 1955 | |
9f4c815c | 1956 | /* |
f8d8406b | 1957 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1958 | * Large pages for identity mappings are not used at boot time |
1959 | * and hence no memory allocations during large page split. | |
1da177e4 | 1960 | */ |
f62d0f00 IM |
1961 | if (enable) |
1962 | __set_pages_p(page, numpages); | |
1963 | else | |
1964 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1965 | |
1966 | /* | |
e4b71dcf IM |
1967 | * We should perform an IPI and flush all tlbs, |
1968 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1969 | */ |
1970 | __flush_tlb_all(); | |
26564600 BO |
1971 | |
1972 | arch_flush_lazy_mmu_mode(); | |
ee7ae7a1 TG |
1973 | } |
1974 | ||
8a235efa RW |
1975 | #ifdef CONFIG_HIBERNATION |
1976 | ||
1977 | bool kernel_page_present(struct page *page) | |
1978 | { | |
1979 | unsigned int level; | |
1980 | pte_t *pte; | |
1981 | ||
1982 | if (PageHighMem(page)) | |
1983 | return false; | |
1984 | ||
1985 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1986 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1987 | } | |
1988 | ||
1989 | #endif /* CONFIG_HIBERNATION */ | |
1990 | ||
1991 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 | 1992 | |
82f0712c BP |
1993 | int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address, |
1994 | unsigned numpages, unsigned long page_flags) | |
1995 | { | |
1996 | int retval = -EINVAL; | |
1997 | ||
1998 | struct cpa_data cpa = { | |
1999 | .vaddr = &address, | |
2000 | .pfn = pfn, | |
2001 | .pgd = pgd, | |
2002 | .numpages = numpages, | |
2003 | .mask_set = __pgprot(0), | |
2004 | .mask_clr = __pgprot(0), | |
2005 | .flags = 0, | |
2006 | }; | |
2007 | ||
2008 | if (!(__supported_pte_mask & _PAGE_NX)) | |
2009 | goto out; | |
2010 | ||
2011 | if (!(page_flags & _PAGE_NX)) | |
2012 | cpa.mask_clr = __pgprot(_PAGE_NX); | |
2013 | ||
15f003d2 SP |
2014 | if (!(page_flags & _PAGE_RW)) |
2015 | cpa.mask_clr = __pgprot(_PAGE_RW); | |
2016 | ||
82f0712c BP |
2017 | cpa.mask_set = __pgprot(_PAGE_PRESENT | page_flags); |
2018 | ||
2019 | retval = __change_page_attr_set_clr(&cpa, 0); | |
2020 | __flush_tlb_all(); | |
2021 | ||
2022 | out: | |
2023 | return retval; | |
2024 | } | |
2025 | ||
d1028a15 AV |
2026 | /* |
2027 | * The testcases use internal knowledge of the implementation that shouldn't | |
2028 | * be exposed to the rest of the kernel. Include these directly here. | |
2029 | */ | |
2030 | #ifdef CONFIG_CPA_DEBUG | |
2031 | #include "pageattr-test.c" | |
2032 | #endif |