[mirror_ubuntu-artful-kernel.git] / arch / x86 / ras / mce_amd_inj.c

/*
 * A simple MCE injection facility for testing different aspects of the RAS
 * code. This driver should be built as module so that it can be loaded
 * on production kernels for testing purposes.
 *
 * This file may be distributed under the terms of the GNU General Public
 * License version 2.
 *
 * Copyright (c) 2010-15:  Borislav Petkov <bp@alien8.de>
 *			Advanced Micro Devices Inc.
 */

#include <linux/kobject.h>
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/cpu.h>
#include <linux/string.h>
#include <linux/uaccess.h>
#include <linux/pci.h>

#include <asm/mce.h>
#include <asm/smp.h>
#include <asm/amd_nb.h>
#include <asm/irq_vectors.h>

#include "../kernel/cpu/mcheck/mce-internal.h"

/*
 * Collect all the MCi_XXX settings
 */
static struct mce i_mce;
static struct dentry *dfs_inj;

static u8 n_banks;

#define MAX_FLAG_OPT_SIZE	3
#define NBCFG			0x44

enum injection_type {
	SW_INJ = 0,	/* SW injection, simply decode the error */
	HW_INJ,		/* Trigger a #MC */
	DFR_INT_INJ,    /* Trigger Deferred error interrupt */
	THR_INT_INJ,    /* Trigger threshold interrupt */
	N_INJ_TYPES,
};

static const char * const flags_options[] = {
	[SW_INJ] = "sw",
	[HW_INJ] = "hw",
	[DFR_INT_INJ] = "df",
	[THR_INT_INJ] = "th",
	NULL
};

/* Set default injection to SW_INJ */
static enum injection_type inj_type = SW_INJ;

#define MCE_INJECT_SET(reg)						\
static int inj_##reg##_set(void *data, u64 val)				\
{									\
	struct mce *m = (struct mce *)data;				\
									\
	m->reg = val;							\
	return 0;							\
}

MCE_INJECT_SET(status);
MCE_INJECT_SET(misc);
MCE_INJECT_SET(addr);

#define MCE_INJECT_GET(reg)						\
static int inj_##reg##_get(void *data, u64 *val)			\
{									\
	struct mce *m = (struct mce *)data;				\
									\
	*val = m->reg;							\
	return 0;							\
}

MCE_INJECT_GET(status);
MCE_INJECT_GET(misc);
MCE_INJECT_GET(addr);

DEFINE_SIMPLE_ATTRIBUTE(status_fops, inj_status_get, inj_status_set, "%llx\n");
DEFINE_SIMPLE_ATTRIBUTE(misc_fops, inj_misc_get, inj_misc_set, "%llx\n");
DEFINE_SIMPLE_ATTRIBUTE(addr_fops, inj_addr_get, inj_addr_set, "%llx\n");

/*
 * Caller needs to be make sure this cpu doesn't disappear
 * from under us, i.e.: get_cpu/put_cpu.
 */
static int toggle_hw_mce_inject(unsigned int cpu, bool enable)
{
	u32 l, h;
	int err;

	err = rdmsr_on_cpu(cpu, MSR_K7_HWCR, &l, &h);
	if (err) {
		pr_err("%s: error reading HWCR\n", __func__);
		return err;
	}

	enable ? (l |= BIT(18)) : (l &= ~BIT(18));

	err = wrmsr_on_cpu(cpu, MSR_K7_HWCR, l, h);
	if (err)
		pr_err("%s: error writing HWCR\n", __func__);

	return err;
}

static int __set_inj(const char *buf)
{
	int i;

	for (i = 0; i < N_INJ_TYPES; i++) {
		if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) {
			inj_type = i;
			return 0;
		}
	}
	return -EINVAL;
}

static ssize_t flags_read(struct file *filp, char __user *ubuf,
			  size_t cnt, loff_t *ppos)
{
	char buf[MAX_FLAG_OPT_SIZE];
	int n;

	n = sprintf(buf, "%s\n", flags_options[inj_type]);

	return simple_read_from_buffer(ubuf, cnt, ppos, buf, n);
}

static ssize_t flags_write(struct file *filp, const char __user *ubuf,
			   size_t cnt, loff_t *ppos)
{
	char buf[MAX_FLAG_OPT_SIZE], *__buf;
	int err;

	if (cnt > MAX_FLAG_OPT_SIZE)
		return -EINVAL;

	if (copy_from_user(&buf, ubuf, cnt))
		return -EFAULT;

	buf[cnt - 1] = 0;

	/* strip whitespace */
	__buf = strstrip(buf);

	err = __set_inj(__buf);
	if (err) {
		pr_err("%s: Invalid flags value: %s\n", __func__, __buf);
		return err;
	}

	*ppos += cnt;

	return cnt;
}

static const struct file_operations flags_fops = {
	.read           = flags_read,
	.write          = flags_write,
	.llseek         = generic_file_llseek,
};

/*
 * On which CPU to inject?
 */
MCE_INJECT_GET(extcpu);

static int inj_extcpu_set(void *data, u64 val)
{
	struct mce *m = (struct mce *)data;

	if (val >= nr_cpu_ids || !cpu_online(val)) {
		pr_err("%s: Invalid CPU: %llu\n", __func__, val);
		return -EINVAL;
	}
	m->extcpu = val;
	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(extcpu_fops, inj_extcpu_get, inj_extcpu_set, "%llu\n");

static void trigger_mce(void *info)
{
	asm volatile("int $18");
}

static void trigger_dfr_int(void *info)
{
	asm volatile("int %0" :: "i" (DEFERRED_ERROR_VECTOR));
}

static void trigger_thr_int(void *info)
{
	asm volatile("int %0" :: "i" (THRESHOLD_APIC_VECTOR));
}

static u32 get_nbc_for_node(int node_id)
{
	struct cpuinfo_x86 *c = &boot_cpu_data;
	u32 cores_per_node;

	cores_per_node = (c->x86_max_cores * smp_num_siblings) / amd_get_nodes_per_socket();

	return cores_per_node * node_id;
}

static void toggle_nb_mca_mst_cpu(u16 nid)
{
	struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
	u32 val;
	int err;

	if (!F3)
		return;

	err = pci_read_config_dword(F3, NBCFG, &val);
	if (err) {
		pr_err("%s: Error reading F%dx%03x.\n",
		       __func__, PCI_FUNC(F3->devfn), NBCFG);
		return;
	}

	if (val & BIT(27))
		return;

	pr_err("%s: Set D18F3x44[NbMcaToMstCpuEn] which BIOS hasn't done.\n",
	       __func__);

	val |= BIT(27);
	err = pci_write_config_dword(F3, NBCFG, val);
	if (err)
		pr_err("%s: Error writing F%dx%03x.\n",
		       __func__, PCI_FUNC(F3->devfn), NBCFG);
}

static void do_inject(void)
{
	u64 mcg_status = 0;
	unsigned int cpu = i_mce.extcpu;
	u8 b = i_mce.bank;

	if (i_mce.misc)
		i_mce.status |= MCI_STATUS_MISCV;

	if (inj_type == SW_INJ) {
		mce_inject_log(&i_mce);
		return;
	}

	/* prep MCE global settings for the injection */
	mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV;

	if (!(i_mce.status & MCI_STATUS_PCC))
		mcg_status |= MCG_STATUS_RIPV;

	/*
	 * Ensure necessary status bits for deferred errors:
	 * - MCx_STATUS[Deferred]: make sure it is a deferred error
	 * - MCx_STATUS[UC] cleared: deferred errors are _not_ UC
	 */
	if (inj_type == DFR_INT_INJ) {
		i_mce.status |= MCI_STATUS_DEFERRED;
		i_mce.status |= (i_mce.status & ~MCI_STATUS_UC);
	}

	/*
	 * For multi node CPUs, logging and reporting of bank 4 errors happens
	 * only on the node base core. Refer to D18F3x44[NbMcaToMstCpuEn] for
	 * Fam10h and later BKDGs.
	 */
	if (static_cpu_has(X86_FEATURE_AMD_DCM) && b == 4) {
		toggle_nb_mca_mst_cpu(amd_get_nb_id(cpu));
		cpu = get_nbc_for_node(amd_get_nb_id(cpu));
	}

	get_online_cpus();
	if (!cpu_online(cpu))
		goto err;

	toggle_hw_mce_inject(cpu, true);

	wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS,
		     (u32)mcg_status, (u32)(mcg_status >> 32));

	if (boot_cpu_has(X86_FEATURE_SMCA)) {
		if (inj_type == DFR_INT_INJ) {
			wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_DESTAT(b),
				     (u32)i_mce.status, (u32)(i_mce.status >> 32));

			wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_DEADDR(b),
				     (u32)i_mce.addr, (u32)(i_mce.addr >> 32));
		} else {
			wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_STATUS(b),
				     (u32)i_mce.status, (u32)(i_mce.status >> 32));

			wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_ADDR(b),
				     (u32)i_mce.addr, (u32)(i_mce.addr >> 32));
		}

		wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(b),
			     (u32)i_mce.misc, (u32)(i_mce.misc >> 32));
	} else {
		wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b),
			     (u32)i_mce.status, (u32)(i_mce.status >> 32));

		wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b),
			     (u32)i_mce.addr, (u32)(i_mce.addr >> 32));

		wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b),
			     (u32)i_mce.misc, (u32)(i_mce.misc >> 32));
	}

	toggle_hw_mce_inject(cpu, false);

	switch (inj_type) {
	case DFR_INT_INJ:
		smp_call_function_single(cpu, trigger_dfr_int, NULL, 0);
		break;
	case THR_INT_INJ:
		smp_call_function_single(cpu, trigger_thr_int, NULL, 0);
		break;
	default:
		smp_call_function_single(cpu, trigger_mce, NULL, 0);
	}

err:
	put_online_cpus();

}

/*
 * This denotes into which bank we're injecting and triggers
 * the injection, at the same time.
 */
static int inj_bank_set(void *data, u64 val)
{
	struct mce *m = (struct mce *)data;

	if (val >= n_banks) {
		pr_err("Non-existent MCE bank: %llu\n", val);
		return -EINVAL;
	}

	m->bank = val;
	do_inject();

	return 0;
}

MCE_INJECT_GET(bank);

DEFINE_SIMPLE_ATTRIBUTE(bank_fops, inj_bank_get, inj_bank_set, "%llu\n");

static const char readme_msg[] =
"Description of the files and their usages:\n"
"\n"
"Note1: i refers to the bank number below.\n"
"Note2: See respective BKDGs for the exact bit definitions of the files below\n"
"as they mirror the hardware registers.\n"
"\n"
"status:\t Set MCi_STATUS: the bits in that MSR control the error type and\n"
"\t attributes of the error which caused the MCE.\n"
"\n"
"misc:\t Set MCi_MISC: provide auxiliary info about the error. It is mostly\n"
"\t used for error thresholding purposes and its validity is indicated by\n"
"\t MCi_STATUS[MiscV].\n"
"\n"
"addr:\t Error address value to be written to MCi_ADDR. Log address information\n"
"\t associated with the error.\n"
"\n"
"cpu:\t The CPU to inject the error on.\n"
"\n"
"bank:\t Specify the bank you want to inject the error into: the number of\n"
"\t banks in a processor varies and is family/model-specific, therefore, the\n"
"\t supplied value is sanity-checked. Setting the bank value also triggers the\n"
"\t injection.\n"
"\n"
"flags:\t Injection type to be performed. Writing to this file will trigger a\n"
"\t real machine check, an APIC interrupt or invoke the error decoder routines\n"
"\t for AMD processors.\n"
"\n"
"\t Allowed error injection types:\n"
"\t  - \"sw\": Software error injection. Decode error to a human-readable \n"
"\t    format only. Safe to use.\n"
"\t  - \"hw\": Hardware error injection. Causes the #MC exception handler to \n"
"\t    handle the error. Be warned: might cause system panic if MCi_STATUS[PCC] \n"
"\t    is set. Therefore, consider setting (debugfs_mountpoint)/mce/fake_panic \n"
"\t    before injecting.\n"
"\t  - \"df\": Trigger APIC interrupt for Deferred error. Causes deferred \n"
"\t    error APIC interrupt handler to handle the error if the feature is \n"
"\t    is present in hardware. \n"
"\t  - \"th\": Trigger APIC interrupt for Threshold errors. Causes threshold \n"
"\t    APIC interrupt handler to handle the error. \n"
"\n";

static ssize_t
inj_readme_read(struct file *filp, char __user *ubuf,
		       size_t cnt, loff_t *ppos)
{
	return simple_read_from_buffer(ubuf, cnt, ppos,
					readme_msg, strlen(readme_msg));
}

static const struct file_operations readme_fops = {
	.read		= inj_readme_read,
};

static struct dfs_node {
	char *name;
	struct dentry *d;
	const struct file_operations *fops;
	umode_t perm;
} dfs_fls[] = {
	{ .name = "status",	.fops = &status_fops, .perm = S_IRUSR | S_IWUSR },
	{ .name = "misc",	.fops = &misc_fops,   .perm = S_IRUSR | S_IWUSR },
	{ .name = "addr",	.fops = &addr_fops,   .perm = S_IRUSR | S_IWUSR },
	{ .name = "bank",	.fops = &bank_fops,   .perm = S_IRUSR | S_IWUSR },
	{ .name = "flags",	.fops = &flags_fops,  .perm = S_IRUSR | S_IWUSR },
	{ .name = "cpu",	.fops = &extcpu_fops, .perm = S_IRUSR | S_IWUSR },
	{ .name = "README",	.fops = &readme_fops, .perm = S_IRUSR | S_IRGRP | S_IROTH },
};

static int __init init_mce_inject(void)
{
	int i;
	u64 cap;

	rdmsrl(MSR_IA32_MCG_CAP, cap);
	n_banks = cap & MCG_BANKCNT_MASK;

	dfs_inj = debugfs_create_dir("mce-inject", NULL);
	if (!dfs_inj)
		return -EINVAL;

	for (i = 0; i < ARRAY_SIZE(dfs_fls); i++) {
		dfs_fls[i].d = debugfs_create_file(dfs_fls[i].name,
						    dfs_fls[i].perm,
						    dfs_inj,
						    &i_mce,
						    dfs_fls[i].fops);

		if (!dfs_fls[i].d)
			goto err_dfs_add;
	}

	return 0;

err_dfs_add:
	while (--i >= 0)
		debugfs_remove(dfs_fls[i].d);

	debugfs_remove(dfs_inj);
	dfs_inj = NULL;

	return -ENOMEM;
}

static void __exit exit_mce_inject(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(dfs_fls); i++)
		debugfs_remove(dfs_fls[i].d);

	memset(&dfs_fls, 0, sizeof(dfs_fls));

	debugfs_remove(dfs_inj);
	dfs_inj = NULL;
}
module_init(init_mce_inject);
module_exit(exit_mce_inject);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Borislav Petkov <bp@alien8.de>");
MODULE_AUTHOR("AMD Inc.");
MODULE_DESCRIPTION("MCE injection facility for RAS testing");
Commit	Line	Data
9cdeb404	1	/*
fd19fcd6 BP	2	* A simple MCE injection facility for testing different aspects of the RAS
	3	* code. This driver should be built as module so that it can be loaded
	4	* on production kernels for testing purposes.
9cdeb404 BP	5	*
	6	* This file may be distributed under the terms of the GNU General Public
	7	* License version 2.
	8	*
6c36dfe9	9	* Copyright (c) 2010-15: Borislav Petkov <bp@alien8.de>
9cdeb404 BP	10	* Advanced Micro Devices Inc.
	11	*/
	12
	13	#include <linux/kobject.h>
fd19fcd6	14	#include <linux/debugfs.h>
51990e82	15	#include <linux/device.h>
80a2e2e3	16	#include <linux/module.h>
51756a50	17	#include <linux/cpu.h>
0451d14d AG	18	#include <linux/string.h>
0451d14d AG	19	#include <linux/uaccess.h>
fa20a2ed	20	#include <linux/pci.h>
a1300e50	21
9cdeb404	22	#include <asm/mce.h>
ee6825c8	23	#include <asm/smp.h>
fa20a2ed	24	#include <asm/amd_nb.h>
a1300e50	25	#include <asm/irq_vectors.h>
9cdeb404	26
6c36dfe9	27	#include "../kernel/cpu/mcheck/mce-internal.h"
9cdeb404	28
9cdeb404 BP	29	/*
	30	* Collect all the MCi_XXX settings
	31	*/
	32	static struct mce i_mce;
fd19fcd6	33	static struct dentry *dfs_inj;
9cdeb404	34
685d46d7 AG	35	static u8 n_banks;
685d46d7 AG	36
0451d14d	37	#define MAX_FLAG_OPT_SIZE 3
fa20a2ed	38	#define NBCFG 0x44
0451d14d AG	39
	40	enum injection_type {
	41	SW_INJ = 0, /* SW injection, simply decode the error */
	42	HW_INJ, /* Trigger a #MC */
a1300e50 AG	43	DFR_INT_INJ, /* Trigger Deferred error interrupt */
a1300e50 AG	44	THR_INT_INJ, /* Trigger threshold interrupt */
0451d14d AG	45	N_INJ_TYPES,
	46	};
	47
	48	static const char * const flags_options[] = {
	49	[SW_INJ] = "sw",
	50	[HW_INJ] = "hw",
a1300e50 AG	51	[DFR_INT_INJ] = "df",
a1300e50 AG	52	[THR_INT_INJ] = "th",
0451d14d AG	53	NULL
	54	};
	55
	56	/* Set default injection to SW_INJ */
de277678	57	static enum injection_type inj_type = SW_INJ;
0451d14d	58
fd19fcd6 BP	59	#define MCE_INJECT_SET(reg) \
fd19fcd6 BP	60	static int inj_##reg##_set(void *data, u64 val) \
9cdeb404	61	{ \
fd19fcd6	62	struct mce m = (struct mce )data; \
9cdeb404	63	\
fd19fcd6 BP	64	m->reg = val; \
fd19fcd6 BP	65	return 0; \
9cdeb404 BP	66	}
9cdeb404 BP	67
fd19fcd6 BP	68	MCE_INJECT_SET(status);
	69	MCE_INJECT_SET(misc);
	70	MCE_INJECT_SET(addr);
9cdeb404	71
fd19fcd6 BP	72	#define MCE_INJECT_GET(reg) \
fd19fcd6 BP	73	static int inj_##reg##_get(void data, u64 val) \
9cdeb404	74	{ \
fd19fcd6 BP	75	struct mce m = (struct mce )data; \
	76	\
	77	*val = m->reg; \
	78	return 0; \
9cdeb404 BP	79	}
9cdeb404 BP	80
fd19fcd6 BP	81	MCE_INJECT_GET(status);
	82	MCE_INJECT_GET(misc);
	83	MCE_INJECT_GET(addr);
9cdeb404	84
fd19fcd6 BP	85	DEFINE_SIMPLE_ATTRIBUTE(status_fops, inj_status_get, inj_status_set, "%llx\n");
	86	DEFINE_SIMPLE_ATTRIBUTE(misc_fops, inj_misc_get, inj_misc_set, "%llx\n");
	87	DEFINE_SIMPLE_ATTRIBUTE(addr_fops, inj_addr_get, inj_addr_set, "%llx\n");
9cdeb404	88
21690934 BP	89	/*
	90	* Caller needs to be make sure this cpu doesn't disappear
	91	* from under us, i.e.: get_cpu/put_cpu.
	92	*/
	93	static int toggle_hw_mce_inject(unsigned int cpu, bool enable)
	94	{
	95	u32 l, h;
	96	int err;
	97
	98	err = rdmsr_on_cpu(cpu, MSR_K7_HWCR, &l, &h);
	99	if (err) {
	100	pr_err("%s: error reading HWCR\n", __func__);
	101	return err;
	102	}
	103
	104	enable ? (l \|= BIT(18)) : (l &= ~BIT(18));
	105
	106	err = wrmsr_on_cpu(cpu, MSR_K7_HWCR, l, h);
	107	if (err)
	108	pr_err("%s: error writing HWCR\n", __func__);
	109
	110	return err;
	111	}
	112
0451d14d	113	static int __set_inj(const char *buf)
b18f3864	114	{
0451d14d AG	115	int i;
	116
	117	for (i = 0; i < N_INJ_TYPES; i++) {
	118	if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) {
	119	inj_type = i;
	120	return 0;
	121	}
	122	}
	123	return -EINVAL;
	124	}
	125
	126	static ssize_t flags_read(struct file filp, char __user ubuf,
	127	size_t cnt, loff_t *ppos)
	128	{
	129	char buf[MAX_FLAG_OPT_SIZE];
	130	int n;
b18f3864	131
0451d14d	132	n = sprintf(buf, "%s\n", flags_options[inj_type]);
b18f3864	133
0451d14d	134	return simple_read_from_buffer(ubuf, cnt, ppos, buf, n);
b18f3864 BP	135	}
b18f3864 BP	136
0451d14d AG	137	static ssize_t flags_write(struct file filp, const char __user ubuf,
0451d14d AG	138	size_t cnt, loff_t *ppos)
b18f3864	139	{
0451d14d AG	140	char buf[MAX_FLAG_OPT_SIZE], *__buf;
0451d14d AG	141	int err;
b18f3864	142
0451d14d	143	if (cnt > MAX_FLAG_OPT_SIZE)
85c9306d	144	return -EINVAL;
0451d14d AG	145
	146	if (copy_from_user(&buf, ubuf, cnt))
	147	return -EFAULT;
	148
	149	buf[cnt - 1] = 0;
	150
	151	/* strip whitespace */
	152	__buf = strstrip(buf);
	153
	154	err = __set_inj(__buf);
	155	if (err) {
	156	pr_err("%s: Invalid flags value: %s\n", __func__, __buf);
	157	return err;
	158	}
	159
85c9306d	160	*ppos += cnt;
0451d14d	161
85c9306d	162	return cnt;
b18f3864 BP	163	}
b18f3864 BP	164
0451d14d AG	165	static const struct file_operations flags_fops = {
	166	.read = flags_read,
	167	.write = flags_write,
	168	.llseek = generic_file_llseek,
	169	};
b18f3864 BP	170
	171	/*
	172	* On which CPU to inject?
	173	*/
	174	MCE_INJECT_GET(extcpu);
	175
	176	static int inj_extcpu_set(void *data, u64 val)
	177	{
	178	struct mce m = (struct mce )data;
	179
	180	if (val >= nr_cpu_ids \|\| !cpu_online(val)) {
	181	pr_err("%s: Invalid CPU: %llu\n", __func__, val);
	182	return -EINVAL;
	183	}
	184	m->extcpu = val;
	185	return 0;
	186	}
	187
	188	DEFINE_SIMPLE_ATTRIBUTE(extcpu_fops, inj_extcpu_get, inj_extcpu_set, "%llu\n");
	189
51756a50 BP	190	static void trigger_mce(void *info)
	191	{
	192	asm volatile("int $18");
	193	}
	194
a1300e50 AG	195	static void trigger_dfr_int(void *info)
	196	{
	197	asm volatile("int %0" :: "i" (DEFERRED_ERROR_VECTOR));
	198	}
	199
	200	static void trigger_thr_int(void *info)
	201	{
	202	asm volatile("int %0" :: "i" (THRESHOLD_APIC_VECTOR));
	203	}
	204
fa20a2ed AG	205	static u32 get_nbc_for_node(int node_id)
	206	{
	207	struct cpuinfo_x86 *c = &boot_cpu_data;
	208	u32 cores_per_node;
	209
ee6825c8	210	cores_per_node = (c->x86_max_cores * smp_num_siblings) / amd_get_nodes_per_socket();
fa20a2ed AG	211
	212	return cores_per_node * node_id;
	213	}
	214
	215	static void toggle_nb_mca_mst_cpu(u16 nid)
	216	{
	217	struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
	218	u32 val;
	219	int err;
	220
	221	if (!F3)
	222	return;
	223
	224	err = pci_read_config_dword(F3, NBCFG, &val);
	225	if (err) {
	226	pr_err("%s: Error reading F%dx%03x.\n",
	227	__func__, PCI_FUNC(F3->devfn), NBCFG);
	228	return;
	229	}
	230
	231	if (val & BIT(27))
	232	return;
	233
	234	pr_err("%s: Set D18F3x44[NbMcaToMstCpuEn] which BIOS hasn't done.\n",
	235	__func__);
	236
	237	val \|= BIT(27);
	238	err = pci_write_config_dword(F3, NBCFG, val);
	239	if (err)
	240	pr_err("%s: Error writing F%dx%03x.\n",
	241	__func__, PCI_FUNC(F3->devfn), NBCFG);
	242	}
	243
51756a50 BP	244	static void do_inject(void)
	245	{
	246	u64 mcg_status = 0;
	247	unsigned int cpu = i_mce.extcpu;
	248	u8 b = i_mce.bank;
	249
cda9459d BP	250	if (i_mce.misc)
	251	i_mce.status \|= MCI_STATUS_MISCV;
	252
0451d14d	253	if (inj_type == SW_INJ) {
6c36dfe9	254	mce_inject_log(&i_mce);
51756a50 BP	255	return;
	256	}
	257
51756a50 BP	258	/* prep MCE global settings for the injection */
	259	mcg_status = MCG_STATUS_MCIP \| MCG_STATUS_EIPV;
	260
	261	if (!(i_mce.status & MCI_STATUS_PCC))
	262	mcg_status \|= MCG_STATUS_RIPV;
	263
a1300e50 AG	264	/*
	265	* Ensure necessary status bits for deferred errors:
	266	* - MCx_STATUS[Deferred]: make sure it is a deferred error
	267	* - MCx_STATUS[UC] cleared: deferred errors are _not_ UC
	268	*/
	269	if (inj_type == DFR_INT_INJ) {
	270	i_mce.status \|= MCI_STATUS_DEFERRED;
	271	i_mce.status \|= (i_mce.status & ~MCI_STATUS_UC);
	272	}
	273
fa20a2ed AG	274	/*
	275	* For multi node CPUs, logging and reporting of bank 4 errors happens
	276	* only on the node base core. Refer to D18F3x44[NbMcaToMstCpuEn] for
	277	* Fam10h and later BKDGs.
	278	*/
	279	if (static_cpu_has(X86_FEATURE_AMD_DCM) && b == 4) {
	280	toggle_nb_mca_mst_cpu(amd_get_nb_id(cpu));
	281	cpu = get_nbc_for_node(amd_get_nb_id(cpu));
	282	}
	283
6d1e9bf5 BP	284	get_online_cpus();
	285	if (!cpu_online(cpu))
	286	goto err;
	287
51756a50 BP	288	toggle_hw_mce_inject(cpu, true);
	289
	290	wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS,
	291	(u32)mcg_status, (u32)(mcg_status >> 32));
	292
754a9230 YG	293	if (boot_cpu_has(X86_FEATURE_SMCA)) {
	294	if (inj_type == DFR_INT_INJ) {
	295	wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_DESTAT(b),
	296	(u32)i_mce.status, (u32)(i_mce.status >> 32));
	297
	298	wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_DEADDR(b),
	299	(u32)i_mce.addr, (u32)(i_mce.addr >> 32));
	300	} else {
	301	wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_STATUS(b),
	302	(u32)i_mce.status, (u32)(i_mce.status >> 32));
	303
	304	wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_ADDR(b),
	305	(u32)i_mce.addr, (u32)(i_mce.addr >> 32));
	306	}
	307
	308	wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(b),
	309	(u32)i_mce.misc, (u32)(i_mce.misc >> 32));
	310	} else {
	311	wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b),
	312	(u32)i_mce.status, (u32)(i_mce.status >> 32));
51756a50	313
754a9230 YG	314	wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b),
754a9230 YG	315	(u32)i_mce.addr, (u32)(i_mce.addr >> 32));
51756a50	316
754a9230 YG	317	wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b),
	318	(u32)i_mce.misc, (u32)(i_mce.misc >> 32));
	319	}
51756a50 BP	320
	321	toggle_hw_mce_inject(cpu, false);
	322
a1300e50 AG	323	switch (inj_type) {
	324	case DFR_INT_INJ:
	325	smp_call_function_single(cpu, trigger_dfr_int, NULL, 0);
	326	break;
	327	case THR_INT_INJ:
	328	smp_call_function_single(cpu, trigger_thr_int, NULL, 0);
	329	break;
	330	default:
	331	smp_call_function_single(cpu, trigger_mce, NULL, 0);
	332	}
51756a50 BP	333
	334	err:
	335	put_online_cpus();
	336
	337	}
	338
9cdeb404 BP	339	/*
	340	* This denotes into which bank we're injecting and triggers
	341	* the injection, at the same time.
	342	*/
fd19fcd6	343	static int inj_bank_set(void *data, u64 val)
9cdeb404	344	{
fd19fcd6	345	struct mce m = (struct mce )data;
9cdeb404	346
685d46d7 AG	347	if (val >= n_banks) {
	348	pr_err("Non-existent MCE bank: %llu\n", val);
	349	return -EINVAL;
fd19fcd6	350	}
9cdeb404	351
fd19fcd6	352	m->bank = val;
51756a50	353	do_inject();
9cdeb404	354
fd19fcd6	355	return 0;
9cdeb404 BP	356	}
9cdeb404 BP	357
e7f2ea1d	358	MCE_INJECT_GET(bank);
9cdeb404	359
fd19fcd6 BP	360	DEFINE_SIMPLE_ATTRIBUTE(bank_fops, inj_bank_get, inj_bank_set, "%llu\n");
fd19fcd6 BP	361
99e21fea	362	static const char readme_msg[] =
f2f3dca1 BP	363	"Description of the files and their usages:\n"
	364	"\n"
	365	"Note1: i refers to the bank number below.\n"
	366	"Note2: See respective BKDGs for the exact bit definitions of the files below\n"
	367	"as they mirror the hardware registers.\n"
	368	"\n"
	369	"status:\t Set MCi_STATUS: the bits in that MSR control the error type and\n"
	370	"\t attributes of the error which caused the MCE.\n"
	371	"\n"
	372	"misc:\t Set MCi_MISC: provide auxiliary info about the error. It is mostly\n"
	373	"\t used for error thresholding purposes and its validity is indicated by\n"
	374	"\t MCi_STATUS[MiscV].\n"
	375	"\n"
	376	"addr:\t Error address value to be written to MCi_ADDR. Log address information\n"
	377	"\t associated with the error.\n"
	378	"\n"
	379	"cpu:\t The CPU to inject the error on.\n"
	380	"\n"
	381	"bank:\t Specify the bank you want to inject the error into: the number of\n"
	382	"\t banks in a processor varies and is family/model-specific, therefore, the\n"
	383	"\t supplied value is sanity-checked. Setting the bank value also triggers the\n"
	384	"\t injection.\n"
	385	"\n"
	386	"flags:\t Injection type to be performed. Writing to this file will trigger a\n"
	387	"\t real machine check, an APIC interrupt or invoke the error decoder routines\n"
	388	"\t for AMD processors.\n"
	389	"\n"
	390	"\t Allowed error injection types:\n"
	391	"\t - \"sw\": Software error injection. Decode error to a human-readable \n"
	392	"\t format only. Safe to use.\n"
	393	"\t - \"hw\": Hardware error injection. Causes the #MC exception handler to \n"
	394	"\t handle the error. Be warned: might cause system panic if MCi_STATUS[PCC] \n"
	395	"\t is set. Therefore, consider setting (debugfs_mountpoint)/mce/fake_panic \n"
	396	"\t before injecting.\n"
a1300e50 AG	397	"\t - \"df\": Trigger APIC interrupt for Deferred error. Causes deferred \n"
	398	"\t error APIC interrupt handler to handle the error if the feature is \n"
	399	"\t is present in hardware. \n"
	400	"\t - \"th\": Trigger APIC interrupt for Threshold errors. Causes threshold \n"
	401	"\t APIC interrupt handler to handle the error. \n"
f2f3dca1	402	"\n";
99e21fea AG	403
	404	static ssize_t
	405	inj_readme_read(struct file filp, char __user ubuf,
	406	size_t cnt, loff_t *ppos)
	407	{
	408	return simple_read_from_buffer(ubuf, cnt, ppos,
	409	readme_msg, strlen(readme_msg));
	410	}
	411
	412	static const struct file_operations readme_fops = {
	413	.read = inj_readme_read,
	414	};
	415
8c2b117f	416	static struct dfs_node {
fd19fcd6 BP	417	char *name;
	418	struct dentry *d;
	419	const struct file_operations *fops;
4c6034e8	420	umode_t perm;
fd19fcd6	421	} dfs_fls[] = {
4c6034e8 AG	422	{ .name = "status", .fops = &status_fops, .perm = S_IRUSR \| S_IWUSR },
	423	{ .name = "misc", .fops = &misc_fops, .perm = S_IRUSR \| S_IWUSR },
	424	{ .name = "addr", .fops = &addr_fops, .perm = S_IRUSR \| S_IWUSR },
	425	{ .name = "bank", .fops = &bank_fops, .perm = S_IRUSR \| S_IWUSR },
	426	{ .name = "flags", .fops = &flags_fops, .perm = S_IRUSR \| S_IWUSR },
	427	{ .name = "cpu", .fops = &extcpu_fops, .perm = S_IRUSR \| S_IWUSR },
99e21fea	428	{ .name = "README", .fops = &readme_fops, .perm = S_IRUSR \| S_IRGRP \| S_IROTH },
9cdeb404 BP	429	};
9cdeb404 BP	430
fd19fcd6	431	static int __init init_mce_inject(void)
9cdeb404	432	{
fd19fcd6	433	int i;
685d46d7 AG	434	u64 cap;
	435
	436	rdmsrl(MSR_IA32_MCG_CAP, cap);
	437	n_banks = cap & MCG_BANKCNT_MASK;
9cdeb404	438
fd19fcd6 BP	439	dfs_inj = debugfs_create_dir("mce-inject", NULL);
fd19fcd6 BP	440	if (!dfs_inj)
9cdeb404 BP	441	return -EINVAL;
9cdeb404 BP	442
fd19fcd6 BP	443	for (i = 0; i < ARRAY_SIZE(dfs_fls); i++) {
fd19fcd6 BP	444	dfs_fls[i].d = debugfs_create_file(dfs_fls[i].name,
4c6034e8	445	dfs_fls[i].perm,
fd19fcd6 BP	446	dfs_inj,
	447	&i_mce,
	448	dfs_fls[i].fops);
9cdeb404	449
fd19fcd6 BP	450	if (!dfs_fls[i].d)
fd19fcd6 BP	451	goto err_dfs_add;
9cdeb404	452	}
fd19fcd6	453
9cdeb404 BP	454	return 0;
9cdeb404 BP	455
fd19fcd6	456	err_dfs_add:
df4b2a30	457	while (--i >= 0)
fd19fcd6	458	debugfs_remove(dfs_fls[i].d);
9cdeb404	459
fd19fcd6 BP	460	debugfs_remove(dfs_inj);
fd19fcd6 BP	461	dfs_inj = NULL;
9cdeb404	462
fd19fcd6	463	return -ENOMEM;
9cdeb404 BP	464	}
9cdeb404 BP	465
fd19fcd6	466	static void __exit exit_mce_inject(void)
9cdeb404 BP	467	{
	468	int i;
	469
fd19fcd6 BP	470	for (i = 0; i < ARRAY_SIZE(dfs_fls); i++)
fd19fcd6 BP	471	debugfs_remove(dfs_fls[i].d);
9cdeb404	472
fd19fcd6	473	memset(&dfs_fls, 0, sizeof(dfs_fls));
9cdeb404	474
fd19fcd6 BP	475	debugfs_remove(dfs_inj);
fd19fcd6 BP	476	dfs_inj = NULL;
9cdeb404	477	}
fd19fcd6 BP	478	module_init(init_mce_inject);
fd19fcd6 BP	479	module_exit(exit_mce_inject);
9cdeb404 BP	480
9cdeb404 BP	481	MODULE_LICENSE("GPL");
43aff26c	482	MODULE_AUTHOR("Borislav Petkov <bp@alien8.de>");
9cdeb404	483	MODULE_AUTHOR("AMD Inc.");
fd19fcd6	484	MODULE_DESCRIPTION("MCE injection facility for RAS testing");