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1da177e4 LT |
1 | /* |
2 | * linux/arch/x86_64/nmi.c | |
3 | * | |
4 | * NMI watchdog support on APIC systems | |
5 | * | |
6 | * Started by Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes: | |
9 | * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog. | |
10 | * Mikael Pettersson : Power Management for local APIC NMI watchdog. | |
11 | * Pavel Machek and | |
12 | * Mikael Pettersson : PM converted to driver model. Disable/enable API. | |
13 | */ | |
14 | ||
15 | #include <linux/config.h> | |
16 | #include <linux/mm.h> | |
17 | #include <linux/irq.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/bootmem.h> | |
20 | #include <linux/smp_lock.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/mc146818rtc.h> | |
23 | #include <linux/kernel_stat.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/sysdev.h> | |
26 | #include <linux/nmi.h> | |
27 | #include <linux/sysctl.h> | |
28 | ||
29 | #include <asm/smp.h> | |
30 | #include <asm/mtrr.h> | |
31 | #include <asm/mpspec.h> | |
32 | #include <asm/nmi.h> | |
33 | #include <asm/msr.h> | |
34 | #include <asm/proto.h> | |
35 | #include <asm/kdebug.h> | |
75152114 | 36 | #include <asm/local.h> |
1da177e4 LT |
37 | |
38 | /* | |
39 | * lapic_nmi_owner tracks the ownership of the lapic NMI hardware: | |
40 | * - it may be reserved by some other driver, or not | |
41 | * - when not reserved by some other driver, it may be used for | |
42 | * the NMI watchdog, or not | |
43 | * | |
44 | * This is maintained separately from nmi_active because the NMI | |
45 | * watchdog may also be driven from the I/O APIC timer. | |
46 | */ | |
47 | static DEFINE_SPINLOCK(lapic_nmi_owner_lock); | |
48 | static unsigned int lapic_nmi_owner; | |
49 | #define LAPIC_NMI_WATCHDOG (1<<0) | |
50 | #define LAPIC_NMI_RESERVED (1<<1) | |
51 | ||
52 | /* nmi_active: | |
53 | * +1: the lapic NMI watchdog is active, but can be disabled | |
54 | * 0: the lapic NMI watchdog has not been set up, and cannot | |
55 | * be enabled | |
56 | * -1: the lapic NMI watchdog is disabled, but can be enabled | |
57 | */ | |
58 | int nmi_active; /* oprofile uses this */ | |
59 | int panic_on_timeout; | |
60 | ||
61 | unsigned int nmi_watchdog = NMI_DEFAULT; | |
62 | static unsigned int nmi_hz = HZ; | |
75152114 AK |
63 | static unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */ |
64 | static unsigned int nmi_p4_cccr_val; | |
1da177e4 LT |
65 | |
66 | /* Note that these events don't tick when the CPU idles. This means | |
67 | the frequency varies with CPU load. */ | |
68 | ||
69 | #define K7_EVNTSEL_ENABLE (1 << 22) | |
70 | #define K7_EVNTSEL_INT (1 << 20) | |
71 | #define K7_EVNTSEL_OS (1 << 17) | |
72 | #define K7_EVNTSEL_USR (1 << 16) | |
73 | #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76 | |
74 | #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING | |
75 | ||
75152114 AK |
76 | #define MSR_P4_MISC_ENABLE 0x1A0 |
77 | #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7) | |
78 | #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12) | |
79 | #define MSR_P4_PERFCTR0 0x300 | |
80 | #define MSR_P4_CCCR0 0x360 | |
81 | #define P4_ESCR_EVENT_SELECT(N) ((N)<<25) | |
82 | #define P4_ESCR_OS (1<<3) | |
83 | #define P4_ESCR_USR (1<<2) | |
84 | #define P4_CCCR_OVF_PMI0 (1<<26) | |
85 | #define P4_CCCR_OVF_PMI1 (1<<27) | |
86 | #define P4_CCCR_THRESHOLD(N) ((N)<<20) | |
87 | #define P4_CCCR_COMPLEMENT (1<<19) | |
88 | #define P4_CCCR_COMPARE (1<<18) | |
89 | #define P4_CCCR_REQUIRED (3<<16) | |
90 | #define P4_CCCR_ESCR_SELECT(N) ((N)<<13) | |
91 | #define P4_CCCR_ENABLE (1<<12) | |
92 | /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter | |
93 | CRU_ESCR0 (with any non-null event selector) through a complemented | |
94 | max threshold. [IA32-Vol3, Section 14.9.9] */ | |
95 | #define MSR_P4_IQ_COUNTER0 0x30C | |
96 | #define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR) | |
97 | #define P4_NMI_IQ_CCCR0 \ | |
98 | (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \ | |
99 | P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE) | |
100 | ||
e6982c67 | 101 | static __cpuinit inline int nmi_known_cpu(void) |
75152114 AK |
102 | { |
103 | switch (boot_cpu_data.x86_vendor) { | |
104 | case X86_VENDOR_AMD: | |
105 | return boot_cpu_data.x86 == 15; | |
106 | case X86_VENDOR_INTEL: | |
107 | return boot_cpu_data.x86 == 15; | |
108 | } | |
109 | return 0; | |
110 | } | |
1da177e4 LT |
111 | |
112 | /* Run after command line and cpu_init init, but before all other checks */ | |
e6982c67 | 113 | void __cpuinit nmi_watchdog_default(void) |
1da177e4 LT |
114 | { |
115 | if (nmi_watchdog != NMI_DEFAULT) | |
116 | return; | |
75152114 AK |
117 | if (nmi_known_cpu()) |
118 | nmi_watchdog = NMI_LOCAL_APIC; | |
119 | else | |
1da177e4 | 120 | nmi_watchdog = NMI_IO_APIC; |
1da177e4 LT |
121 | } |
122 | ||
75152114 AK |
123 | #ifdef CONFIG_SMP |
124 | /* The performance counters used by NMI_LOCAL_APIC don't trigger when | |
125 | * the CPU is idle. To make sure the NMI watchdog really ticks on all | |
126 | * CPUs during the test make them busy. | |
127 | */ | |
128 | static __init void nmi_cpu_busy(void *data) | |
1da177e4 | 129 | { |
75152114 AK |
130 | volatile int *endflag = data; |
131 | local_irq_enable(); | |
132 | /* Intentionally don't use cpu_relax here. This is | |
133 | to make sure that the performance counter really ticks, | |
134 | even if there is a simulator or similar that catches the | |
135 | pause instruction. On a real HT machine this is fine because | |
136 | all other CPUs are busy with "useless" delay loops and don't | |
137 | care if they get somewhat less cycles. */ | |
138 | while (*endflag == 0) | |
139 | barrier(); | |
1da177e4 | 140 | } |
75152114 | 141 | #endif |
1da177e4 | 142 | |
75152114 | 143 | int __init check_nmi_watchdog (void) |
1da177e4 | 144 | { |
75152114 | 145 | volatile int endflag = 0; |
ac6b931c | 146 | int *counts; |
1da177e4 LT |
147 | int cpu; |
148 | ||
75152114 AK |
149 | counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL); |
150 | if (!counts) | |
151 | return -1; | |
1da177e4 | 152 | |
75152114 | 153 | printk(KERN_INFO "testing NMI watchdog ... "); |
ac6b931c | 154 | |
75152114 AK |
155 | if (nmi_watchdog == NMI_LOCAL_APIC) |
156 | smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0); | |
1da177e4 LT |
157 | |
158 | for (cpu = 0; cpu < NR_CPUS; cpu++) | |
159 | counts[cpu] = cpu_pda[cpu].__nmi_count; | |
160 | local_irq_enable(); | |
161 | mdelay((10*1000)/nmi_hz); // wait 10 ticks | |
162 | ||
163 | for (cpu = 0; cpu < NR_CPUS; cpu++) { | |
75152114 AK |
164 | if (!cpu_online(cpu)) |
165 | continue; | |
1da177e4 | 166 | if (cpu_pda[cpu].__nmi_count - counts[cpu] <= 5) { |
75152114 AK |
167 | endflag = 1; |
168 | printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n", | |
1da177e4 | 169 | cpu, |
75152114 | 170 | counts[cpu], |
1da177e4 LT |
171 | cpu_pda[cpu].__nmi_count); |
172 | nmi_active = 0; | |
173 | lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG; | |
75152114 | 174 | nmi_perfctr_msr = 0; |
ac6b931c | 175 | kfree(counts); |
1da177e4 LT |
176 | return -1; |
177 | } | |
178 | } | |
75152114 | 179 | endflag = 1; |
1da177e4 LT |
180 | printk("OK.\n"); |
181 | ||
182 | /* now that we know it works we can reduce NMI frequency to | |
183 | something more reasonable; makes a difference in some configs */ | |
184 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
185 | nmi_hz = 1; | |
186 | ||
ac6b931c | 187 | kfree(counts); |
1da177e4 LT |
188 | return 0; |
189 | } | |
190 | ||
191 | int __init setup_nmi_watchdog(char *str) | |
192 | { | |
193 | int nmi; | |
194 | ||
195 | if (!strncmp(str,"panic",5)) { | |
196 | panic_on_timeout = 1; | |
197 | str = strchr(str, ','); | |
198 | if (!str) | |
199 | return 1; | |
200 | ++str; | |
201 | } | |
202 | ||
203 | get_option(&str, &nmi); | |
204 | ||
205 | if (nmi >= NMI_INVALID) | |
206 | return 0; | |
75152114 | 207 | nmi_watchdog = nmi; |
1da177e4 LT |
208 | return 1; |
209 | } | |
210 | ||
211 | __setup("nmi_watchdog=", setup_nmi_watchdog); | |
212 | ||
213 | static void disable_lapic_nmi_watchdog(void) | |
214 | { | |
215 | if (nmi_active <= 0) | |
216 | return; | |
217 | switch (boot_cpu_data.x86_vendor) { | |
218 | case X86_VENDOR_AMD: | |
219 | wrmsr(MSR_K7_EVNTSEL0, 0, 0); | |
220 | break; | |
221 | case X86_VENDOR_INTEL: | |
75152114 AK |
222 | if (boot_cpu_data.x86 == 15) { |
223 | wrmsr(MSR_P4_IQ_CCCR0, 0, 0); | |
224 | wrmsr(MSR_P4_CRU_ESCR0, 0, 0); | |
225 | } | |
1da177e4 LT |
226 | break; |
227 | } | |
228 | nmi_active = -1; | |
229 | /* tell do_nmi() and others that we're not active any more */ | |
230 | nmi_watchdog = 0; | |
231 | } | |
232 | ||
233 | static void enable_lapic_nmi_watchdog(void) | |
234 | { | |
235 | if (nmi_active < 0) { | |
236 | nmi_watchdog = NMI_LOCAL_APIC; | |
237 | setup_apic_nmi_watchdog(); | |
238 | } | |
239 | } | |
240 | ||
241 | int reserve_lapic_nmi(void) | |
242 | { | |
243 | unsigned int old_owner; | |
244 | ||
245 | spin_lock(&lapic_nmi_owner_lock); | |
246 | old_owner = lapic_nmi_owner; | |
247 | lapic_nmi_owner |= LAPIC_NMI_RESERVED; | |
248 | spin_unlock(&lapic_nmi_owner_lock); | |
249 | if (old_owner & LAPIC_NMI_RESERVED) | |
250 | return -EBUSY; | |
251 | if (old_owner & LAPIC_NMI_WATCHDOG) | |
252 | disable_lapic_nmi_watchdog(); | |
253 | return 0; | |
254 | } | |
255 | ||
256 | void release_lapic_nmi(void) | |
257 | { | |
258 | unsigned int new_owner; | |
259 | ||
260 | spin_lock(&lapic_nmi_owner_lock); | |
261 | new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED; | |
262 | lapic_nmi_owner = new_owner; | |
263 | spin_unlock(&lapic_nmi_owner_lock); | |
264 | if (new_owner & LAPIC_NMI_WATCHDOG) | |
265 | enable_lapic_nmi_watchdog(); | |
266 | } | |
267 | ||
268 | void disable_timer_nmi_watchdog(void) | |
269 | { | |
270 | if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0)) | |
271 | return; | |
272 | ||
273 | disable_irq(0); | |
274 | unset_nmi_callback(); | |
275 | nmi_active = -1; | |
276 | nmi_watchdog = NMI_NONE; | |
277 | } | |
278 | ||
279 | void enable_timer_nmi_watchdog(void) | |
280 | { | |
281 | if (nmi_active < 0) { | |
282 | nmi_watchdog = NMI_IO_APIC; | |
283 | touch_nmi_watchdog(); | |
284 | nmi_active = 1; | |
285 | enable_irq(0); | |
286 | } | |
287 | } | |
288 | ||
289 | #ifdef CONFIG_PM | |
290 | ||
291 | static int nmi_pm_active; /* nmi_active before suspend */ | |
292 | ||
829ca9a3 | 293 | static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
294 | { |
295 | nmi_pm_active = nmi_active; | |
296 | disable_lapic_nmi_watchdog(); | |
297 | return 0; | |
298 | } | |
299 | ||
300 | static int lapic_nmi_resume(struct sys_device *dev) | |
301 | { | |
302 | if (nmi_pm_active > 0) | |
303 | enable_lapic_nmi_watchdog(); | |
304 | return 0; | |
305 | } | |
306 | ||
307 | static struct sysdev_class nmi_sysclass = { | |
308 | set_kset_name("lapic_nmi"), | |
309 | .resume = lapic_nmi_resume, | |
310 | .suspend = lapic_nmi_suspend, | |
311 | }; | |
312 | ||
313 | static struct sys_device device_lapic_nmi = { | |
314 | .id = 0, | |
315 | .cls = &nmi_sysclass, | |
316 | }; | |
317 | ||
318 | static int __init init_lapic_nmi_sysfs(void) | |
319 | { | |
320 | int error; | |
321 | ||
322 | if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC) | |
323 | return 0; | |
324 | ||
325 | error = sysdev_class_register(&nmi_sysclass); | |
326 | if (!error) | |
327 | error = sysdev_register(&device_lapic_nmi); | |
328 | return error; | |
329 | } | |
330 | /* must come after the local APIC's device_initcall() */ | |
331 | late_initcall(init_lapic_nmi_sysfs); | |
332 | ||
333 | #endif /* CONFIG_PM */ | |
334 | ||
335 | /* | |
336 | * Activate the NMI watchdog via the local APIC. | |
337 | * Original code written by Keith Owens. | |
338 | */ | |
339 | ||
75152114 AK |
340 | static void clear_msr_range(unsigned int base, unsigned int n) |
341 | { | |
342 | unsigned int i; | |
343 | ||
344 | for(i = 0; i < n; ++i) | |
345 | wrmsr(base+i, 0, 0); | |
346 | } | |
347 | ||
1da177e4 LT |
348 | static void setup_k7_watchdog(void) |
349 | { | |
350 | int i; | |
351 | unsigned int evntsel; | |
352 | ||
1da177e4 LT |
353 | nmi_perfctr_msr = MSR_K7_PERFCTR0; |
354 | ||
355 | for(i = 0; i < 4; ++i) { | |
356 | /* Simulator may not support it */ | |
75152114 AK |
357 | if (checking_wrmsrl(MSR_K7_EVNTSEL0+i, 0UL)) { |
358 | nmi_perfctr_msr = 0; | |
1da177e4 | 359 | return; |
75152114 | 360 | } |
1da177e4 LT |
361 | wrmsrl(MSR_K7_PERFCTR0+i, 0UL); |
362 | } | |
363 | ||
364 | evntsel = K7_EVNTSEL_INT | |
365 | | K7_EVNTSEL_OS | |
366 | | K7_EVNTSEL_USR | |
367 | | K7_NMI_EVENT; | |
368 | ||
369 | wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); | |
75152114 | 370 | wrmsr(MSR_K7_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1); |
1da177e4 LT |
371 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
372 | evntsel |= K7_EVNTSEL_ENABLE; | |
373 | wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); | |
374 | } | |
375 | ||
75152114 AK |
376 | |
377 | static int setup_p4_watchdog(void) | |
378 | { | |
379 | unsigned int misc_enable, dummy; | |
380 | ||
381 | rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy); | |
382 | if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL)) | |
383 | return 0; | |
384 | ||
385 | nmi_perfctr_msr = MSR_P4_IQ_COUNTER0; | |
386 | nmi_p4_cccr_val = P4_NMI_IQ_CCCR0; | |
387 | #ifdef CONFIG_SMP | |
388 | if (smp_num_siblings == 2) | |
389 | nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1; | |
390 | #endif | |
391 | ||
392 | if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL)) | |
393 | clear_msr_range(0x3F1, 2); | |
394 | /* MSR 0x3F0 seems to have a default value of 0xFC00, but current | |
395 | docs doesn't fully define it, so leave it alone for now. */ | |
396 | if (boot_cpu_data.x86_model >= 0x3) { | |
397 | /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */ | |
398 | clear_msr_range(0x3A0, 26); | |
399 | clear_msr_range(0x3BC, 3); | |
400 | } else { | |
401 | clear_msr_range(0x3A0, 31); | |
402 | } | |
403 | clear_msr_range(0x3C0, 6); | |
404 | clear_msr_range(0x3C8, 6); | |
405 | clear_msr_range(0x3E0, 2); | |
406 | clear_msr_range(MSR_P4_CCCR0, 18); | |
407 | clear_msr_range(MSR_P4_PERFCTR0, 18); | |
408 | ||
409 | wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0); | |
410 | wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0); | |
411 | Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000)); | |
412 | wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1); | |
413 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
414 | wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0); | |
415 | return 1; | |
416 | } | |
417 | ||
1da177e4 LT |
418 | void setup_apic_nmi_watchdog(void) |
419 | { | |
420 | switch (boot_cpu_data.x86_vendor) { | |
421 | case X86_VENDOR_AMD: | |
72e76be2 | 422 | if (boot_cpu_data.x86 != 15) |
1da177e4 LT |
423 | return; |
424 | if (strstr(boot_cpu_data.x86_model_id, "Screwdriver")) | |
425 | return; | |
426 | setup_k7_watchdog(); | |
427 | break; | |
75152114 AK |
428 | case X86_VENDOR_INTEL: |
429 | if (boot_cpu_data.x86 != 15) | |
430 | return; | |
431 | if (!setup_p4_watchdog()) | |
432 | return; | |
433 | break; | |
434 | ||
1da177e4 LT |
435 | default: |
436 | return; | |
437 | } | |
438 | lapic_nmi_owner = LAPIC_NMI_WATCHDOG; | |
439 | nmi_active = 1; | |
440 | } | |
441 | ||
442 | /* | |
443 | * the best way to detect whether a CPU has a 'hard lockup' problem | |
444 | * is to check it's local APIC timer IRQ counts. If they are not | |
445 | * changing then that CPU has some problem. | |
446 | * | |
447 | * as these watchdog NMI IRQs are generated on every CPU, we only | |
448 | * have to check the current processor. | |
1da177e4 LT |
449 | */ |
450 | ||
75152114 AK |
451 | static DEFINE_PER_CPU(unsigned, last_irq_sum); |
452 | static DEFINE_PER_CPU(local_t, alert_counter); | |
453 | static DEFINE_PER_CPU(int, nmi_touch); | |
1da177e4 LT |
454 | |
455 | void touch_nmi_watchdog (void) | |
456 | { | |
457 | int i; | |
458 | ||
459 | /* | |
75152114 AK |
460 | * Tell other CPUs to reset their alert counters. We cannot |
461 | * do it ourselves because the alert count increase is not | |
462 | * atomic. | |
1da177e4 LT |
463 | */ |
464 | for (i = 0; i < NR_CPUS; i++) | |
75152114 | 465 | per_cpu(nmi_touch, i) = 1; |
1da177e4 LT |
466 | } |
467 | ||
468 | void nmi_watchdog_tick (struct pt_regs * regs, unsigned reason) | |
469 | { | |
75152114 AK |
470 | int sum; |
471 | int touched = 0; | |
1da177e4 | 472 | |
1da177e4 | 473 | sum = read_pda(apic_timer_irqs); |
75152114 AK |
474 | if (__get_cpu_var(nmi_touch)) { |
475 | __get_cpu_var(nmi_touch) = 0; | |
476 | touched = 1; | |
477 | } | |
478 | if (!touched && __get_cpu_var(last_irq_sum) == sum) { | |
1da177e4 LT |
479 | /* |
480 | * Ayiee, looks like this CPU is stuck ... | |
481 | * wait a few IRQs (5 seconds) before doing the oops ... | |
482 | */ | |
75152114 AK |
483 | local_inc(&__get_cpu_var(alert_counter)); |
484 | if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz) { | |
1da177e4 LT |
485 | if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) |
486 | == NOTIFY_STOP) { | |
75152114 | 487 | local_set(&__get_cpu_var(alert_counter), 0); |
1da177e4 LT |
488 | return; |
489 | } | |
490 | die_nmi("NMI Watchdog detected LOCKUP on CPU%d", regs); | |
491 | } | |
492 | } else { | |
75152114 AK |
493 | __get_cpu_var(last_irq_sum) = sum; |
494 | local_set(&__get_cpu_var(alert_counter), 0); | |
1da177e4 | 495 | } |
75152114 AK |
496 | if (nmi_perfctr_msr) { |
497 | if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) { | |
498 | /* | |
499 | * P4 quirks: | |
500 | * - An overflown perfctr will assert its interrupt | |
501 | * until the OVF flag in its CCCR is cleared. | |
502 | * - LVTPC is masked on interrupt and must be | |
503 | * unmasked by the LVTPC handler. | |
504 | */ | |
505 | wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0); | |
506 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
507 | } | |
1da177e4 | 508 | wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1); |
75152114 | 509 | } |
1da177e4 LT |
510 | } |
511 | ||
512 | static int dummy_nmi_callback(struct pt_regs * regs, int cpu) | |
513 | { | |
514 | return 0; | |
515 | } | |
516 | ||
517 | static nmi_callback_t nmi_callback = dummy_nmi_callback; | |
518 | ||
519 | asmlinkage void do_nmi(struct pt_regs * regs, long error_code) | |
520 | { | |
521 | int cpu = safe_smp_processor_id(); | |
522 | ||
523 | nmi_enter(); | |
524 | add_pda(__nmi_count,1); | |
525 | if (!nmi_callback(regs, cpu)) | |
526 | default_do_nmi(regs); | |
527 | nmi_exit(); | |
528 | } | |
529 | ||
530 | void set_nmi_callback(nmi_callback_t callback) | |
531 | { | |
532 | nmi_callback = callback; | |
533 | } | |
534 | ||
535 | void unset_nmi_callback(void) | |
536 | { | |
537 | nmi_callback = dummy_nmi_callback; | |
538 | } | |
539 | ||
540 | #ifdef CONFIG_SYSCTL | |
541 | ||
542 | static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu) | |
543 | { | |
544 | unsigned char reason = get_nmi_reason(); | |
545 | char buf[64]; | |
546 | ||
547 | if (!(reason & 0xc0)) { | |
548 | sprintf(buf, "NMI received for unknown reason %02x\n", reason); | |
549 | die_nmi(buf,regs); | |
550 | } | |
551 | return 0; | |
552 | } | |
553 | ||
554 | /* | |
555 | * proc handler for /proc/sys/kernel/unknown_nmi_panic | |
556 | */ | |
557 | int proc_unknown_nmi_panic(struct ctl_table *table, int write, struct file *file, | |
558 | void __user *buffer, size_t *length, loff_t *ppos) | |
559 | { | |
560 | int old_state; | |
561 | ||
562 | old_state = unknown_nmi_panic; | |
563 | proc_dointvec(table, write, file, buffer, length, ppos); | |
564 | if (!!old_state == !!unknown_nmi_panic) | |
565 | return 0; | |
566 | ||
567 | if (unknown_nmi_panic) { | |
568 | if (reserve_lapic_nmi() < 0) { | |
569 | unknown_nmi_panic = 0; | |
570 | return -EBUSY; | |
571 | } else { | |
572 | set_nmi_callback(unknown_nmi_panic_callback); | |
573 | } | |
574 | } else { | |
575 | release_lapic_nmi(); | |
576 | unset_nmi_callback(); | |
577 | } | |
578 | return 0; | |
579 | } | |
580 | ||
581 | #endif | |
582 | ||
583 | EXPORT_SYMBOL(nmi_active); | |
584 | EXPORT_SYMBOL(nmi_watchdog); | |
585 | EXPORT_SYMBOL(reserve_lapic_nmi); | |
586 | EXPORT_SYMBOL(release_lapic_nmi); | |
587 | EXPORT_SYMBOL(disable_timer_nmi_watchdog); | |
588 | EXPORT_SYMBOL(enable_timer_nmi_watchdog); | |
589 | EXPORT_SYMBOL(touch_nmi_watchdog); |