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1 | /* |
2 | * BSD LICENSE | |
3 | * | |
4 | * Copyright (C) EZchip Semiconductor Ltd. 2015. | |
5 | * | |
6 | * Redistribution and use in source and binary forms, with or without | |
7 | * modification, are permitted provided that the following conditions | |
8 | * are met: | |
9 | * | |
10 | * * Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | |
12 | * * Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in | |
14 | * the documentation and/or other materials provided with the | |
15 | * distribution. | |
16 | * * Neither the name of EZchip Semiconductor nor the names of its | |
17 | * contributors may be used to endorse or promote products derived | |
18 | * from this software without specific prior written permission. | |
19 | * | |
20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
21 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
22 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
23 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
24 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
25 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
26 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
27 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
28 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
30 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
31 | */ | |
32 | ||
33 | #ifndef _RTE_ATOMIC_TILE_H_ | |
34 | #define _RTE_ATOMIC_TILE_H_ | |
35 | ||
36 | #ifndef RTE_FORCE_INTRINSICS | |
37 | # error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS | |
38 | #endif | |
39 | ||
40 | #ifdef __cplusplus | |
41 | extern "C" { | |
42 | #endif | |
43 | ||
44 | #include "generic/rte_atomic.h" | |
45 | ||
46 | /** | |
47 | * General memory barrier. | |
48 | * | |
49 | * Guarantees that the LOAD and STORE operations generated before the | |
50 | * barrier occur before the LOAD and STORE operations generated after. | |
51 | * This function is architecture dependent. | |
52 | */ | |
53 | static inline void rte_mb(void) | |
54 | { | |
55 | __sync_synchronize(); | |
56 | } | |
57 | ||
58 | /** | |
59 | * Write memory barrier. | |
60 | * | |
61 | * Guarantees that the STORE operations generated before the barrier | |
62 | * occur before the STORE operations generated after. | |
63 | * This function is architecture dependent. | |
64 | */ | |
65 | static inline void rte_wmb(void) | |
66 | { | |
67 | __sync_synchronize(); | |
68 | } | |
69 | ||
70 | /** | |
71 | * Read memory barrier. | |
72 | * | |
73 | * Guarantees that the LOAD operations generated before the barrier | |
74 | * occur before the LOAD operations generated after. | |
75 | * This function is architecture dependent. | |
76 | */ | |
77 | static inline void rte_rmb(void) | |
78 | { | |
79 | __sync_synchronize(); | |
80 | } | |
81 | ||
82 | #define rte_smp_mb() rte_mb() | |
83 | ||
84 | #define rte_smp_wmb() rte_compiler_barrier() | |
85 | ||
86 | #define rte_smp_rmb() rte_compiler_barrier() | |
87 | ||
88 | #ifdef __cplusplus | |
89 | } | |
90 | #endif | |
91 | ||
92 | #endif /* _RTE_ATOMIC_TILE_H_ */ |