]>
Commit | Line | Data |
---|---|---|
9f95a23c TL |
1 | /* SPDX-License-Identifier: BSD-3-Clause |
2 | * Copyright(c) 2014-2018 Chelsio Communications. | |
3 | * All rights reserved. | |
7c673cae FG |
4 | */ |
5 | ||
6 | #ifndef _CXGBE_H_ | |
7 | #define _CXGBE_H_ | |
8 | ||
9f95a23c TL |
9 | #include "base/common.h" |
10 | #include "base/t4_regs.h" | |
7c673cae FG |
11 | |
12 | #define CXGBE_MIN_RING_DESC_SIZE 128 /* Min TX/RX descriptor ring size */ | |
13 | #define CXGBE_MAX_RING_DESC_SIZE 4096 /* Max TX/RX descriptor ring size */ | |
14 | ||
15 | #define CXGBE_DEFAULT_TX_DESC_SIZE 1024 /* Default TX ring size */ | |
16 | #define CXGBE_DEFAULT_RX_DESC_SIZE 1024 /* Default RX ring size */ | |
17 | ||
18 | #define CXGBE_MIN_RX_BUFSIZE ETHER_MIN_MTU /* min buf size */ | |
19 | #define CXGBE_MAX_RX_PKTLEN (9000 + ETHER_HDR_LEN + ETHER_CRC_LEN) /* max pkt */ | |
20 | ||
9f95a23c TL |
21 | /* Max poll time is 100 * 100msec = 10 sec */ |
22 | #define CXGBE_LINK_STATUS_POLL_MS 100 /* 100ms */ | |
23 | #define CXGBE_LINK_STATUS_POLL_CNT 100 /* Max number of times to poll */ | |
24 | ||
25 | #define CXGBE_DEFAULT_RSS_KEY_LEN 40 /* 320-bits */ | |
26 | #define CXGBE_RSS_HF_IPV4_MASK (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ | |
27 | ETH_RSS_NONFRAG_IPV4_OTHER) | |
28 | #define CXGBE_RSS_HF_IPV6_MASK (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | \ | |
29 | ETH_RSS_NONFRAG_IPV6_OTHER | \ | |
30 | ETH_RSS_IPV6_EX) | |
31 | #define CXGBE_RSS_HF_TCP_IPV6_MASK (ETH_RSS_NONFRAG_IPV6_TCP | \ | |
32 | ETH_RSS_IPV6_TCP_EX) | |
33 | #define CXGBE_RSS_HF_UDP_IPV6_MASK (ETH_RSS_NONFRAG_IPV6_UDP | \ | |
34 | ETH_RSS_IPV6_UDP_EX) | |
35 | #define CXGBE_RSS_HF_ALL (ETH_RSS_IP | ETH_RSS_TCP | ETH_RSS_UDP) | |
36 | ||
37 | /* Tx/Rx Offloads supported */ | |
38 | #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT | \ | |
39 | DEV_TX_OFFLOAD_IPV4_CKSUM | \ | |
40 | DEV_TX_OFFLOAD_UDP_CKSUM | \ | |
41 | DEV_TX_OFFLOAD_TCP_CKSUM | \ | |
42 | DEV_TX_OFFLOAD_TCP_TSO) | |
43 | ||
44 | #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP | \ | |
45 | DEV_RX_OFFLOAD_IPV4_CKSUM | \ | |
46 | DEV_RX_OFFLOAD_UDP_CKSUM | \ | |
47 | DEV_RX_OFFLOAD_TCP_CKSUM | \ | |
48 | DEV_RX_OFFLOAD_JUMBO_FRAME | \ | |
49 | DEV_RX_OFFLOAD_SCATTER) | |
50 | ||
51 | ||
52 | #define CXGBE_DEVARG_KEEP_OVLAN "keep_ovlan" | |
53 | #define CXGBE_DEVARG_FORCE_LINK_UP "force_link_up" | |
54 | ||
55 | bool cxgbe_force_linkup(struct adapter *adap); | |
7c673cae | 56 | int cxgbe_probe(struct adapter *adapter); |
9f95a23c TL |
57 | int cxgbevf_probe(struct adapter *adapter); |
58 | void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps); | |
59 | int cxgbe_set_link_status(struct port_info *pi, bool status); | |
7c673cae FG |
60 | int cxgbe_up(struct adapter *adap); |
61 | int cxgbe_down(struct port_info *pi); | |
62 | void cxgbe_close(struct adapter *adapter); | |
63 | void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats); | |
9f95a23c | 64 | void cxgbevf_stats_get(struct port_info *pi, struct port_stats *stats); |
7c673cae | 65 | void cxgbe_stats_reset(struct port_info *pi); |
9f95a23c TL |
66 | int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int us, |
67 | unsigned int cnt, struct t4_completion *c); | |
68 | int cxgbe_link_start(struct port_info *pi); | |
69 | int cxgbe_setup_sge_fwevtq(struct adapter *adapter); | |
70 | int cxgbe_setup_sge_ctrl_txq(struct adapter *adapter); | |
71 | void cxgbe_cfg_queues(struct rte_eth_dev *eth_dev); | |
72 | int cxgbe_cfg_queue_count(struct rte_eth_dev *eth_dev); | |
73 | int cxgbe_init_rss(struct adapter *adap); | |
74 | int cxgbe_setup_rss(struct port_info *pi); | |
75 | void cxgbe_enable_rx_queues(struct port_info *pi); | |
76 | void cxgbe_print_port_info(struct adapter *adap); | |
77 | void cxgbe_print_adapter_info(struct adapter *adap); | |
78 | int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key); | |
79 | void cxgbe_configure_max_ethqsets(struct adapter *adapter); | |
7c673cae FG |
80 | |
81 | #endif /* _CXGBE_H_ */ |