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9f95a23c TL |
1 | /* SPDX-License-Identifier: BSD-3-Clause |
2 | * Copyright (c) 2016 - 2018 Cavium Inc. | |
7c673cae | 3 | * All rights reserved. |
9f95a23c | 4 | * www.cavium.com |
7c673cae FG |
5 | */ |
6 | ||
7 | /**************************************************************************** | |
8 | * | |
9 | * Name: nvm_cfg.h | |
10 | * | |
11 | * Description: NVM config file - Generated file from nvm cfg excel. | |
12 | * DO NOT MODIFY !!! | |
13 | * | |
9f95a23c | 14 | * Created: 5/8/2017 |
7c673cae FG |
15 | * |
16 | ****************************************************************************/ | |
17 | ||
18 | #ifndef NVM_CFG_H | |
19 | #define NVM_CFG_H | |
20 | ||
9f95a23c | 21 | #define NVM_CFG_version 0x83000 |
11fdf7f2 | 22 | |
9f95a23c | 23 | #define NVM_CFG_new_option_seq 23 |
11fdf7f2 | 24 | |
9f95a23c | 25 | #define NVM_CFG_removed_option_seq 1 |
11fdf7f2 | 26 | |
9f95a23c | 27 | #define NVM_CFG_updated_value_seq 4 |
11fdf7f2 | 28 | |
7c673cae FG |
29 | struct nvm_cfg_mac_address { |
30 | u32 mac_addr_hi; | |
31 | #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF | |
32 | #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0 | |
33 | u32 mac_addr_lo; | |
34 | }; | |
35 | ||
36 | /****************************************** | |
37 | * nvm_cfg1 structs | |
38 | ******************************************/ | |
39 | struct nvm_cfg1_glob { | |
40 | u32 generic_cont0; /* 0x0 */ | |
41 | #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F | |
42 | #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0 | |
43 | #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0 | |
44 | #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1 | |
45 | #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2 | |
46 | #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3 | |
47 | #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0 | |
48 | #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4 | |
49 | #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0 | |
50 | #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1 | |
51 | #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2 | |
52 | #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3 | |
53 | #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4 | |
54 | #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5 | |
55 | #define NVM_CFG1_GLOB_MF_MODE_BD 0x6 | |
56 | #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7 | |
57 | #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000 | |
58 | #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12 | |
59 | #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0 | |
60 | #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1 | |
61 | #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000 | |
62 | #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13 | |
63 | #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000 | |
64 | #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21 | |
65 | #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000 | |
66 | #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29 | |
67 | #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0 | |
68 | #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1 | |
69 | #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000 | |
70 | #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30 | |
71 | #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0 | |
72 | #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1 | |
11fdf7f2 TL |
73 | #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_MASK \ |
74 | 0x80000000 | |
75 | #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_OFFSET 31 | |
76 | #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_DISABLED \ | |
77 | 0x0 | |
78 | #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_ENABLED 0x1 | |
7c673cae FG |
79 | u32 engineering_change[3]; /* 0x4 */ |
80 | u32 manufacturing_id; /* 0x10 */ | |
81 | u32 serial_number[4]; /* 0x14 */ | |
82 | u32 pcie_cfg; /* 0x24 */ | |
83 | #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003 | |
84 | #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0 | |
85 | #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0 | |
86 | #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1 | |
87 | #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2 | |
88 | #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004 | |
89 | #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2 | |
90 | #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0 | |
91 | #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1 | |
92 | #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018 | |
93 | #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3 | |
94 | #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0 | |
95 | #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1 | |
96 | #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2 | |
97 | #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3 | |
98 | #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK \ | |
99 | 0x00000020 | |
100 | #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5 | |
101 | #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0 | |
102 | #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6 | |
103 | #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00 | |
104 | #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10 | |
105 | #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0 | |
106 | #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1 | |
107 | #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2 | |
108 | #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3 | |
109 | #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000 | |
110 | #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13 | |
111 | #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000 | |
112 | #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21 | |
113 | #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000 | |
114 | #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29 | |
115 | /* Set the duration, in sec, fan failure signal should be sampled */ | |
116 | #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK \ | |
117 | 0x80000000 | |
118 | #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31 | |
119 | u32 mgmt_traffic; /* 0x28 */ | |
120 | #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001 | |
121 | #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0 | |
122 | #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE | |
123 | #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1 | |
124 | #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00 | |
125 | #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9 | |
126 | #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000 | |
127 | #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17 | |
128 | #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000 | |
129 | #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25 | |
130 | #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0 | |
131 | #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1 | |
132 | #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2 | |
133 | #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000 | |
134 | #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27 | |
135 | #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0 | |
136 | #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1 | |
137 | /* Indicates whether external thermal sonsor is available */ | |
138 | #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000 | |
139 | #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31 | |
140 | #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0 | |
141 | #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1 | |
142 | u32 core_cfg; /* 0x2C */ | |
143 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF | |
144 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0 | |
145 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0 | |
146 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1 | |
147 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2 | |
148 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3 | |
149 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4 | |
150 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5 | |
151 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB | |
152 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC | |
153 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD | |
154 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE | |
11fdf7f2 | 155 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF |
7c673cae FG |
156 | #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100 |
157 | #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8 | |
158 | #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0 | |
159 | #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_ENABLED 0x1 | |
160 | #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_MASK 0x00000200 | |
161 | #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_OFFSET 9 | |
162 | #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_DISABLED 0x0 | |
163 | #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_ENABLED 0x1 | |
164 | #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_MASK 0x0003FC00 | |
165 | #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_OFFSET 10 | |
166 | #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_MASK 0x03FC0000 | |
167 | #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_OFFSET 18 | |
168 | #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000 | |
169 | #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26 | |
170 | #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0 | |
171 | #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1 | |
172 | #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2 | |
173 | #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3 | |
174 | #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000 | |
175 | #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29 | |
176 | #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0 | |
177 | #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1 | |
178 | u32 e_lane_cfg1; /* 0x30 */ | |
179 | #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F | |
180 | #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 | |
181 | #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 | |
182 | #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 | |
183 | #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 | |
184 | #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 | |
185 | #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 | |
186 | #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 | |
187 | #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 | |
188 | #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 | |
189 | #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 | |
190 | #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 | |
191 | #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 | |
192 | #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 | |
193 | #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 | |
194 | #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 | |
195 | u32 e_lane_cfg2; /* 0x34 */ | |
196 | #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 | |
197 | #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 | |
198 | #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 | |
199 | #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 | |
200 | #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 | |
201 | #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 | |
202 | #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 | |
203 | #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 | |
204 | #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 | |
205 | #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 | |
206 | #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 | |
207 | #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 | |
208 | #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 | |
209 | #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 | |
210 | #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 | |
211 | #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 | |
212 | #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00 | |
213 | #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8 | |
214 | #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0 | |
215 | #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1 | |
216 | #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2 | |
217 | #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000 | |
218 | #define NVM_CFG1_GLOB_NCSI_OFFSET 12 | |
219 | #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0 | |
220 | #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1 | |
221 | /* Maximum advertised pcie link width */ | |
222 | #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000 | |
223 | #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16 | |
224 | #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_BB_16_LANES 0x0 | |
225 | #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1 | |
226 | #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2 | |
227 | #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3 | |
228 | #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4 | |
229 | /* ASPM L1 mode */ | |
230 | #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000 | |
231 | #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20 | |
232 | #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0 | |
233 | #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1 | |
234 | #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000 | |
235 | #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22 | |
236 | #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0 | |
237 | #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1 | |
238 | #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2 | |
239 | #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3 | |
240 | #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK \ | |
241 | 0x06000000 | |
242 | #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25 | |
243 | #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0 | |
244 | #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1 | |
245 | #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2 | |
246 | #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3 | |
247 | /* Set the PLDM sensor modes */ | |
248 | #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000 | |
249 | #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27 | |
250 | #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0 | |
251 | #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1 | |
252 | #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2 | |
11fdf7f2 TL |
253 | /* ROL enable */ |
254 | #define NVM_CFG1_GLOB_RESET_ON_LAN_MASK 0x80000000 | |
255 | #define NVM_CFG1_GLOB_RESET_ON_LAN_OFFSET 31 | |
256 | #define NVM_CFG1_GLOB_RESET_ON_LAN_DISABLED 0x0 | |
257 | #define NVM_CFG1_GLOB_RESET_ON_LAN_ENABLED 0x1 | |
7c673cae FG |
258 | u32 f_lane_cfg1; /* 0x38 */ |
259 | #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F | |
260 | #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 | |
261 | #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 | |
262 | #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 | |
263 | #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 | |
264 | #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 | |
265 | #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 | |
266 | #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 | |
267 | #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 | |
268 | #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 | |
269 | #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 | |
270 | #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 | |
271 | #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 | |
272 | #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 | |
273 | #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 | |
274 | #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 | |
275 | u32 f_lane_cfg2; /* 0x3C */ | |
276 | #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 | |
277 | #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 | |
278 | #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 | |
279 | #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 | |
280 | #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 | |
281 | #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 | |
282 | #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 | |
283 | #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 | |
284 | #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 | |
285 | #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 | |
286 | #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 | |
287 | #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 | |
288 | #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 | |
289 | #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 | |
290 | #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 | |
291 | #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 | |
292 | /* Control the period between two successive checks */ | |
293 | #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK \ | |
294 | 0x0000FF00 | |
295 | #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8 | |
296 | /* Set shutdown temperature */ | |
297 | #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK \ | |
298 | 0x00FF0000 | |
299 | #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16 | |
300 | /* Set max. count for over operational temperature */ | |
301 | #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000 | |
302 | #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24 | |
303 | u32 mps10_preemphasis; /* 0x40 */ | |
304 | #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF | |
305 | #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 | |
306 | #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 | |
307 | #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 | |
308 | #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 | |
309 | #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 | |
310 | #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 | |
311 | #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 | |
312 | u32 mps10_driver_current; /* 0x44 */ | |
313 | #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF | |
314 | #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 | |
315 | #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 | |
316 | #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 | |
317 | #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 | |
318 | #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 | |
319 | #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 | |
320 | #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 | |
321 | u32 mps25_preemphasis; /* 0x48 */ | |
322 | #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF | |
323 | #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 | |
324 | #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 | |
325 | #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 | |
326 | #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 | |
327 | #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 | |
328 | #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 | |
329 | #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 | |
330 | u32 mps25_driver_current; /* 0x4C */ | |
331 | #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF | |
332 | #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 | |
333 | #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 | |
334 | #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 | |
335 | #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 | |
336 | #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 | |
337 | #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 | |
338 | #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 | |
339 | u32 pci_id; /* 0x50 */ | |
340 | #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF | |
341 | #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0 | |
342 | /* Set caution temperature */ | |
9f95a23c TL |
343 | #define NVM_CFG1_GLOB_DEAD_TEMP_TH_TEMPERATURE_MASK 0x00FF0000 |
344 | #define NVM_CFG1_GLOB_DEAD_TEMP_TH_TEMPERATURE_OFFSET 16 | |
7c673cae FG |
345 | /* Set external thermal sensor I2C address */ |
346 | #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK \ | |
347 | 0xFF000000 | |
348 | #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24 | |
349 | u32 pci_subsys_id; /* 0x54 */ | |
350 | #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF | |
351 | #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0 | |
352 | #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000 | |
353 | #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16 | |
354 | u32 bar; /* 0x58 */ | |
355 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F | |
356 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0 | |
357 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0 | |
358 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1 | |
359 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2 | |
360 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3 | |
361 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4 | |
362 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5 | |
363 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6 | |
364 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7 | |
365 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8 | |
366 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9 | |
367 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA | |
368 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB | |
369 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC | |
370 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD | |
371 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE | |
372 | #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF | |
373 | /* BB VF BAR2 size */ | |
374 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0 | |
375 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4 | |
376 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0 | |
377 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1 | |
378 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2 | |
379 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3 | |
380 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4 | |
381 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5 | |
382 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6 | |
383 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7 | |
384 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8 | |
385 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9 | |
386 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA | |
387 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB | |
388 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC | |
389 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD | |
390 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE | |
391 | #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF | |
392 | /* BB BAR2 size (global) */ | |
393 | #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00 | |
394 | #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8 | |
395 | #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0 | |
396 | #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1 | |
397 | #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2 | |
398 | #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3 | |
399 | #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4 | |
400 | #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5 | |
401 | #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6 | |
402 | #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7 | |
403 | #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8 | |
404 | #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9 | |
405 | #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA | |
406 | #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB | |
407 | #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC | |
408 | #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD | |
409 | #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE | |
410 | #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF | |
411 | /* Set the duration, in secs, fan failure signal should be sampled */ | |
412 | #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000 | |
413 | #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12 | |
414 | /* This field defines the board total budget for bar2 when disabled | |
415 | * the regular bar size is used. | |
416 | */ | |
417 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_MASK 0x00FF0000 | |
418 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_OFFSET 16 | |
419 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_DISABLED 0x0 | |
420 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64K 0x1 | |
421 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128K 0x2 | |
422 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256K 0x3 | |
423 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512K 0x4 | |
424 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1M 0x5 | |
425 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_2M 0x6 | |
426 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_4M 0x7 | |
427 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_8M 0x8 | |
428 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_16M 0x9 | |
429 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_32M 0xA | |
430 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64M 0xB | |
431 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128M 0xC | |
432 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256M 0xD | |
433 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512M 0xE | |
434 | #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1G 0xF | |
435 | /* Enable/Disable Crash dump triggers */ | |
436 | #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_MASK 0xFF000000 | |
437 | #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_OFFSET 24 | |
438 | u32 mps10_txfir_main; /* 0x5C */ | |
439 | #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF | |
440 | #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 | |
441 | #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 | |
442 | #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 | |
443 | #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 | |
444 | #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 | |
445 | #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 | |
446 | #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 | |
447 | u32 mps10_txfir_post; /* 0x60 */ | |
448 | #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF | |
449 | #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 | |
450 | #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 | |
451 | #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 | |
452 | #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 | |
453 | #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 | |
454 | #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 | |
455 | #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 | |
456 | u32 mps25_txfir_main; /* 0x64 */ | |
457 | #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF | |
458 | #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 | |
459 | #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 | |
460 | #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 | |
461 | #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 | |
462 | #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 | |
463 | #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 | |
464 | #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 | |
465 | u32 mps25_txfir_post; /* 0x68 */ | |
466 | #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF | |
467 | #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 | |
468 | #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 | |
469 | #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 | |
470 | #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 | |
471 | #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 | |
472 | #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 | |
473 | #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 | |
474 | u32 manufacture_ver; /* 0x6C */ | |
475 | #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F | |
476 | #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0 | |
477 | #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0 | |
478 | #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6 | |
479 | #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000 | |
480 | #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12 | |
481 | #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000 | |
482 | #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18 | |
483 | #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000 | |
484 | #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24 | |
11fdf7f2 TL |
485 | /* Select package id method */ |
486 | #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_MASK 0x40000000 | |
487 | #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_OFFSET 30 | |
488 | #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_NVRAM 0x0 | |
489 | #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_IO_PINS 0x1 | |
490 | #define NVM_CFG1_GLOB_RECOVERY_MODE_MASK 0x80000000 | |
491 | #define NVM_CFG1_GLOB_RECOVERY_MODE_OFFSET 31 | |
492 | #define NVM_CFG1_GLOB_RECOVERY_MODE_DISABLED 0x0 | |
493 | #define NVM_CFG1_GLOB_RECOVERY_MODE_ENABLED 0x1 | |
7c673cae FG |
494 | u32 manufacture_time; /* 0x70 */ |
495 | #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F | |
496 | #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0 | |
497 | #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0 | |
498 | #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6 | |
499 | #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000 | |
500 | #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12 | |
11fdf7f2 TL |
501 | /* Max MSIX for Ethernet in default mode */ |
502 | #define NVM_CFG1_GLOB_MAX_MSIX_MASK 0x03FC0000 | |
503 | #define NVM_CFG1_GLOB_MAX_MSIX_OFFSET 18 | |
504 | /* PF Mapping */ | |
505 | #define NVM_CFG1_GLOB_PF_MAPPING_MASK 0x0C000000 | |
506 | #define NVM_CFG1_GLOB_PF_MAPPING_OFFSET 26 | |
507 | #define NVM_CFG1_GLOB_PF_MAPPING_CONTINUOUS 0x0 | |
508 | #define NVM_CFG1_GLOB_PF_MAPPING_FIXED 0x1 | |
9f95a23c TL |
509 | #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_MASK 0x30000000 |
510 | #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_OFFSET 28 | |
511 | #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_DISABLED 0x0 | |
512 | #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_TI 0x1 | |
7c673cae FG |
513 | u32 led_global_settings; /* 0x74 */ |
514 | #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F | |
515 | #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0 | |
516 | #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0 | |
517 | #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4 | |
518 | #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00 | |
519 | #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8 | |
520 | #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000 | |
521 | #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12 | |
11fdf7f2 TL |
522 | /* Max. continues operating temperature */ |
523 | #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_MASK 0x00FF0000 | |
524 | #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_OFFSET 16 | |
525 | /* GPIO which triggers run-time port swap according to the map | |
526 | * specified in option 205 | |
527 | */ | |
528 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_MASK 0xFF000000 | |
529 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_OFFSET 24 | |
530 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_NA 0x0 | |
531 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO0 0x1 | |
532 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO1 0x2 | |
533 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO2 0x3 | |
534 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO3 0x4 | |
535 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO4 0x5 | |
536 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO5 0x6 | |
537 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO6 0x7 | |
538 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO7 0x8 | |
539 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO8 0x9 | |
540 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO9 0xA | |
541 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO10 0xB | |
542 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO11 0xC | |
543 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO12 0xD | |
544 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO13 0xE | |
545 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO14 0xF | |
546 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO15 0x10 | |
547 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO16 0x11 | |
548 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO17 0x12 | |
549 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO18 0x13 | |
550 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO19 0x14 | |
551 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO20 0x15 | |
552 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO21 0x16 | |
553 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO22 0x17 | |
554 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO23 0x18 | |
555 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO24 0x19 | |
556 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO25 0x1A | |
557 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO26 0x1B | |
558 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO27 0x1C | |
559 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO28 0x1D | |
560 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO29 0x1E | |
561 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO30 0x1F | |
562 | #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO31 0x20 | |
7c673cae FG |
563 | u32 generic_cont1; /* 0x78 */ |
564 | #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF | |
565 | #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0 | |
566 | #define NVM_CFG1_GLOB_LANE0_SWAP_MASK 0x00000C00 | |
567 | #define NVM_CFG1_GLOB_LANE0_SWAP_OFFSET 10 | |
568 | #define NVM_CFG1_GLOB_LANE1_SWAP_MASK 0x00003000 | |
569 | #define NVM_CFG1_GLOB_LANE1_SWAP_OFFSET 12 | |
570 | #define NVM_CFG1_GLOB_LANE2_SWAP_MASK 0x0000C000 | |
571 | #define NVM_CFG1_GLOB_LANE2_SWAP_OFFSET 14 | |
572 | #define NVM_CFG1_GLOB_LANE3_SWAP_MASK 0x00030000 | |
573 | #define NVM_CFG1_GLOB_LANE3_SWAP_OFFSET 16 | |
11fdf7f2 TL |
574 | /* Enable option 195 - Overriding the PCIe Preset value */ |
575 | #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_MASK 0x00040000 | |
576 | #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_OFFSET 18 | |
577 | #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_DISABLED 0x0 | |
578 | #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_ENABLED 0x1 | |
579 | /* PCIe Preset value - applies only if option 194 is enabled */ | |
580 | #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_MASK 0x00780000 | |
581 | #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_OFFSET 19 | |
582 | /* Port mapping to be used when the run-time GPIO for port-swap is | |
583 | * defined and set. | |
584 | */ | |
585 | #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_MASK 0x01800000 | |
586 | #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_OFFSET 23 | |
587 | #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_MASK 0x06000000 | |
588 | #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_OFFSET 25 | |
589 | #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_MASK 0x18000000 | |
590 | #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_OFFSET 27 | |
591 | #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_MASK 0x60000000 | |
592 | #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_OFFSET 29 | |
7c673cae FG |
593 | u32 mbi_version; /* 0x7C */ |
594 | #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF | |
595 | #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0 | |
596 | #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00 | |
597 | #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8 | |
598 | #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000 | |
599 | #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16 | |
11fdf7f2 TL |
600 | /* If set to other than NA, 0 - Normal operation, 1 - Thermal event |
601 | * occurred | |
602 | */ | |
603 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_MASK 0xFF000000 | |
604 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_OFFSET 24 | |
605 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_NA 0x0 | |
606 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO0 0x1 | |
607 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO1 0x2 | |
608 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO2 0x3 | |
609 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO3 0x4 | |
610 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO4 0x5 | |
611 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO5 0x6 | |
612 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO6 0x7 | |
613 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO7 0x8 | |
614 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO8 0x9 | |
615 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO9 0xA | |
616 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO10 0xB | |
617 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO11 0xC | |
618 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO12 0xD | |
619 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO13 0xE | |
620 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO14 0xF | |
621 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO15 0x10 | |
622 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO16 0x11 | |
623 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO17 0x12 | |
624 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO18 0x13 | |
625 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO19 0x14 | |
626 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO20 0x15 | |
627 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO21 0x16 | |
628 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO22 0x17 | |
629 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO23 0x18 | |
630 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO24 0x19 | |
631 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO25 0x1A | |
632 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO26 0x1B | |
633 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO27 0x1C | |
634 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO28 0x1D | |
635 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO29 0x1E | |
636 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO30 0x1F | |
637 | #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO31 0x20 | |
7c673cae FG |
638 | u32 mbi_date; /* 0x80 */ |
639 | u32 misc_sig; /* 0x84 */ | |
640 | /* Define the GPIO mapping to switch i2c mux */ | |
641 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF | |
642 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0 | |
643 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00 | |
644 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8 | |
645 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0 | |
646 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1 | |
647 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2 | |
648 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3 | |
649 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4 | |
650 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5 | |
651 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6 | |
652 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7 | |
653 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8 | |
654 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9 | |
655 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA | |
656 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB | |
657 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC | |
658 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD | |
659 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE | |
660 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF | |
661 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10 | |
662 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11 | |
663 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12 | |
664 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13 | |
665 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14 | |
666 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15 | |
667 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16 | |
668 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17 | |
669 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18 | |
670 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19 | |
671 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A | |
672 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B | |
673 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C | |
674 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D | |
675 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E | |
676 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F | |
677 | #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20 | |
11fdf7f2 TL |
678 | /* Interrupt signal used for SMBus/I2C management interface |
679 | * 0 = Interrupt event occurred | |
680 | * 1 = Normal | |
681 | */ | |
682 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_MASK 0x00FF0000 | |
683 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_OFFSET 16 | |
684 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_NA 0x0 | |
685 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO0 0x1 | |
686 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO1 0x2 | |
687 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO2 0x3 | |
688 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO3 0x4 | |
689 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO4 0x5 | |
690 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO5 0x6 | |
691 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO6 0x7 | |
692 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO7 0x8 | |
693 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO8 0x9 | |
694 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO9 0xA | |
695 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO10 0xB | |
696 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO11 0xC | |
697 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO12 0xD | |
698 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO13 0xE | |
699 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO14 0xF | |
700 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO15 0x10 | |
701 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO16 0x11 | |
702 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO17 0x12 | |
703 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO18 0x13 | |
704 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO19 0x14 | |
705 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO20 0x15 | |
706 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO21 0x16 | |
707 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO22 0x17 | |
708 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO23 0x18 | |
709 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO24 0x19 | |
710 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO25 0x1A | |
711 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO26 0x1B | |
712 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO27 0x1C | |
713 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO28 0x1D | |
714 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO29 0x1E | |
715 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO30 0x1F | |
716 | #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO31 0x20 | |
717 | /* Set aLOM FAN on GPIO */ | |
718 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_MASK 0xFF000000 | |
719 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_OFFSET 24 | |
720 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_NA 0x0 | |
721 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO0 0x1 | |
722 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO1 0x2 | |
723 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO2 0x3 | |
724 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO3 0x4 | |
725 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO4 0x5 | |
726 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO5 0x6 | |
727 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO6 0x7 | |
728 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO7 0x8 | |
729 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO8 0x9 | |
730 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO9 0xA | |
731 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO10 0xB | |
732 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO11 0xC | |
733 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO12 0xD | |
734 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO13 0xE | |
735 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO14 0xF | |
736 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO15 0x10 | |
737 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO16 0x11 | |
738 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO17 0x12 | |
739 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO18 0x13 | |
740 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO19 0x14 | |
741 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO20 0x15 | |
742 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO21 0x16 | |
743 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO22 0x17 | |
744 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO23 0x18 | |
745 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO24 0x19 | |
746 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO25 0x1A | |
747 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO26 0x1B | |
748 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO27 0x1C | |
749 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO28 0x1D | |
750 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO29 0x1E | |
751 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO30 0x1F | |
752 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO31 0x20 | |
7c673cae FG |
753 | u32 device_capabilities; /* 0x88 */ |
754 | #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1 | |
755 | #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2 | |
756 | #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4 | |
757 | #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8 | |
758 | #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10 | |
759 | u32 power_dissipated; /* 0x8C */ | |
760 | #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF | |
761 | #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0 | |
762 | #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00 | |
763 | #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8 | |
764 | #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000 | |
765 | #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16 | |
766 | #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000 | |
767 | #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24 | |
768 | u32 power_consumed; /* 0x90 */ | |
769 | #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF | |
770 | #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0 | |
771 | #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00 | |
772 | #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8 | |
773 | #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000 | |
774 | #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16 | |
775 | #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000 | |
776 | #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24 | |
777 | u32 efi_version; /* 0x94 */ | |
778 | u32 multi_network_modes_capability; /* 0x98 */ | |
779 | #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X10G 0x1 | |
780 | #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X25G 0x2 | |
781 | #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X25G 0x4 | |
782 | #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X25G 0x8 | |
783 | #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X40G 0x10 | |
784 | #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X40G 0x20 | |
785 | #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G 0x40 | |
786 | #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G \ | |
787 | 0x80 | |
11fdf7f2 TL |
788 | #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X10G 0x100 |
789 | /* @DPDK */ | |
790 | u32 reserved1[12]; /* 0x9C */ | |
791 | u32 oem1_number[8]; /* 0xCC */ | |
792 | u32 oem2_number[8]; /* 0xEC */ | |
793 | u32 mps25_active_txfir_pre; /* 0x10C */ | |
794 | #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_MASK 0x000000FF | |
795 | #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_OFFSET 0 | |
796 | #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_MASK 0x0000FF00 | |
797 | #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_OFFSET 8 | |
798 | #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_MASK 0x00FF0000 | |
799 | #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_OFFSET 16 | |
800 | #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_MASK 0xFF000000 | |
801 | #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_OFFSET 24 | |
802 | u32 mps25_active_txfir_main; /* 0x110 */ | |
803 | #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_MASK 0x000000FF | |
804 | #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_OFFSET 0 | |
805 | #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_MASK 0x0000FF00 | |
806 | #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_OFFSET 8 | |
807 | #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_MASK 0x00FF0000 | |
808 | #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_OFFSET 16 | |
809 | #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_MASK 0xFF000000 | |
810 | #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_OFFSET 24 | |
811 | u32 mps25_active_txfir_post; /* 0x114 */ | |
812 | #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_MASK 0x000000FF | |
813 | #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_OFFSET 0 | |
814 | #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_MASK 0x0000FF00 | |
815 | #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_OFFSET 8 | |
816 | #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_MASK 0x00FF0000 | |
817 | #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_OFFSET 16 | |
818 | #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_MASK 0xFF000000 | |
819 | #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_OFFSET 24 | |
820 | u32 features; /* 0x118 */ | |
821 | /* Set the Aux Fan on temperature */ | |
822 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_MASK 0x000000FF | |
823 | #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_OFFSET 0 | |
824 | /* Set NC-SI package ID */ | |
825 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_MASK 0x0000FF00 | |
826 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_OFFSET 8 | |
827 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_NA 0x0 | |
828 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO0 0x1 | |
829 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO1 0x2 | |
830 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO2 0x3 | |
831 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO3 0x4 | |
832 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO4 0x5 | |
833 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO5 0x6 | |
834 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO6 0x7 | |
835 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO7 0x8 | |
836 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO8 0x9 | |
837 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO9 0xA | |
838 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO10 0xB | |
839 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO11 0xC | |
840 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO12 0xD | |
841 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO13 0xE | |
842 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO14 0xF | |
843 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO15 0x10 | |
844 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO16 0x11 | |
845 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO17 0x12 | |
846 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO18 0x13 | |
847 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO19 0x14 | |
848 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO20 0x15 | |
849 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO21 0x16 | |
850 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO22 0x17 | |
851 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO23 0x18 | |
852 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO24 0x19 | |
853 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO25 0x1A | |
854 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO26 0x1B | |
855 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO27 0x1C | |
856 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO28 0x1D | |
857 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO29 0x1E | |
858 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO30 0x1F | |
859 | #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO31 0x20 | |
860 | /* PMBUS Clock GPIO */ | |
861 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_MASK 0x00FF0000 | |
862 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_OFFSET 16 | |
863 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_NA 0x0 | |
864 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO0 0x1 | |
865 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO1 0x2 | |
866 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO2 0x3 | |
867 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO3 0x4 | |
868 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO4 0x5 | |
869 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO5 0x6 | |
870 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO6 0x7 | |
871 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO7 0x8 | |
872 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO8 0x9 | |
873 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO9 0xA | |
874 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO10 0xB | |
875 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO11 0xC | |
876 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO12 0xD | |
877 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO13 0xE | |
878 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO14 0xF | |
879 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO15 0x10 | |
880 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO16 0x11 | |
881 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO17 0x12 | |
882 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO18 0x13 | |
883 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO19 0x14 | |
884 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO20 0x15 | |
885 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO21 0x16 | |
886 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO22 0x17 | |
887 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO23 0x18 | |
888 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO24 0x19 | |
889 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO25 0x1A | |
890 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO26 0x1B | |
891 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO27 0x1C | |
892 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO28 0x1D | |
893 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO29 0x1E | |
894 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO30 0x1F | |
895 | #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO31 0x20 | |
896 | /* PMBUS Data GPIO */ | |
897 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_MASK 0xFF000000 | |
898 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_OFFSET 24 | |
899 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_NA 0x0 | |
900 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO0 0x1 | |
901 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO1 0x2 | |
902 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO2 0x3 | |
903 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO3 0x4 | |
904 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO4 0x5 | |
905 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO5 0x6 | |
906 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO6 0x7 | |
907 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO7 0x8 | |
908 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO8 0x9 | |
909 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO9 0xA | |
910 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO10 0xB | |
911 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO11 0xC | |
912 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO12 0xD | |
913 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO13 0xE | |
914 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO14 0xF | |
915 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO15 0x10 | |
916 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO16 0x11 | |
917 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO17 0x12 | |
918 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO18 0x13 | |
919 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO19 0x14 | |
920 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO20 0x15 | |
921 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO21 0x16 | |
922 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO22 0x17 | |
923 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO23 0x18 | |
924 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO24 0x19 | |
925 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO25 0x1A | |
926 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO26 0x1B | |
927 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO27 0x1C | |
928 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO28 0x1D | |
929 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO29 0x1E | |
930 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO30 0x1F | |
931 | #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO31 0x20 | |
932 | u32 tx_rx_eq_25g_hlpc; /* 0x11C */ | |
933 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_MASK 0x000000FF | |
934 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_OFFSET 0 | |
935 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_MASK 0x0000FF00 | |
936 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_OFFSET 8 | |
937 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_MASK 0x00FF0000 | |
938 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_OFFSET 16 | |
939 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_MASK 0xFF000000 | |
940 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_OFFSET 24 | |
941 | u32 tx_rx_eq_25g_llpc; /* 0x120 */ | |
942 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_MASK 0x000000FF | |
943 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_OFFSET 0 | |
944 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_MASK 0x0000FF00 | |
945 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_OFFSET 8 | |
946 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_MASK 0x00FF0000 | |
947 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_OFFSET 16 | |
948 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_MASK 0xFF000000 | |
949 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_OFFSET 24 | |
950 | u32 tx_rx_eq_25g_ac; /* 0x124 */ | |
951 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_MASK 0x000000FF | |
952 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_OFFSET 0 | |
953 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_MASK 0x0000FF00 | |
954 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_OFFSET 8 | |
955 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_MASK 0x00FF0000 | |
956 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_OFFSET 16 | |
957 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_MASK 0xFF000000 | |
958 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_OFFSET 24 | |
959 | u32 tx_rx_eq_10g_pc; /* 0x128 */ | |
960 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_MASK 0x000000FF | |
961 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_OFFSET 0 | |
962 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_MASK 0x0000FF00 | |
963 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_OFFSET 8 | |
964 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_MASK 0x00FF0000 | |
965 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_OFFSET 16 | |
966 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_MASK 0xFF000000 | |
967 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_OFFSET 24 | |
968 | u32 tx_rx_eq_10g_ac; /* 0x12C */ | |
969 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_MASK 0x000000FF | |
970 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_OFFSET 0 | |
971 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_MASK 0x0000FF00 | |
972 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_OFFSET 8 | |
973 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_MASK 0x00FF0000 | |
974 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_OFFSET 16 | |
975 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_MASK 0xFF000000 | |
976 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_OFFSET 24 | |
977 | u32 tx_rx_eq_1g; /* 0x130 */ | |
978 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_MASK 0x000000FF | |
979 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_OFFSET 0 | |
980 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_MASK 0x0000FF00 | |
981 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_OFFSET 8 | |
982 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_MASK 0x00FF0000 | |
983 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_OFFSET 16 | |
984 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_MASK 0xFF000000 | |
985 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_OFFSET 24 | |
986 | u32 tx_rx_eq_25g_bt; /* 0x134 */ | |
987 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_MASK 0x000000FF | |
988 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_OFFSET 0 | |
989 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_MASK 0x0000FF00 | |
990 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_OFFSET 8 | |
991 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_MASK 0x00FF0000 | |
992 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_OFFSET 16 | |
993 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_MASK 0xFF000000 | |
994 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_OFFSET 24 | |
995 | u32 tx_rx_eq_10g_bt; /* 0x138 */ | |
996 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_MASK 0x000000FF | |
997 | #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_OFFSET 0 | |
998 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_MASK 0x0000FF00 | |
999 | #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_OFFSET 8 | |
1000 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_MASK 0x00FF0000 | |
1001 | #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_OFFSET 16 | |
1002 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_MASK 0xFF000000 | |
1003 | #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_OFFSET 24 | |
1004 | u32 generic_cont4; /* 0x13C */ | |
1005 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_MASK 0x000000FF | |
1006 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_OFFSET 0 | |
1007 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_NA 0x0 | |
1008 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO0 0x1 | |
1009 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO1 0x2 | |
1010 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO2 0x3 | |
1011 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO3 0x4 | |
1012 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO4 0x5 | |
1013 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO5 0x6 | |
1014 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO6 0x7 | |
1015 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO7 0x8 | |
1016 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO8 0x9 | |
1017 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO9 0xA | |
1018 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO10 0xB | |
1019 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO11 0xC | |
1020 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO12 0xD | |
1021 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO13 0xE | |
1022 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO14 0xF | |
1023 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO15 0x10 | |
1024 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO16 0x11 | |
1025 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO17 0x12 | |
1026 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO18 0x13 | |
1027 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO19 0x14 | |
1028 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO20 0x15 | |
1029 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO21 0x16 | |
1030 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO22 0x17 | |
1031 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO23 0x18 | |
1032 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO24 0x19 | |
1033 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO25 0x1A | |
1034 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO26 0x1B | |
1035 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO27 0x1C | |
1036 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO28 0x1D | |
1037 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO29 0x1E | |
1038 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO30 0x1F | |
1039 | #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO31 0x20 | |
9f95a23c TL |
1040 | u32 preboot_debug_mode_std; /* 0x140 */ |
1041 | u32 preboot_debug_mode_ext; /* 0x144 */ | |
1042 | u32 ext_phy_cfg1; /* 0x148 */ | |
1043 | /* Ext PHY MDI pair swap value */ | |
1044 | #define NVM_CFG1_GLOB_EXT_PHY_MDI_PAIR_SWAP_MASK 0x0000FFFF | |
1045 | #define NVM_CFG1_GLOB_EXT_PHY_MDI_PAIR_SWAP_OFFSET 0 | |
1046 | u32 reserved[55]; /* 0x14C */ | |
7c673cae FG |
1047 | }; |
1048 | ||
1049 | struct nvm_cfg1_path { | |
11fdf7f2 | 1050 | u32 reserved[1]; /* 0x0 */ |
7c673cae FG |
1051 | }; |
1052 | ||
1053 | struct nvm_cfg1_port { | |
1054 | u32 reserved__m_relocated_to_option_123; /* 0x0 */ | |
1055 | u32 reserved__m_relocated_to_option_124; /* 0x4 */ | |
1056 | u32 generic_cont0; /* 0x8 */ | |
1057 | #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF | |
1058 | #define NVM_CFG1_PORT_LED_MODE_OFFSET 0 | |
1059 | #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0 | |
1060 | #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1 | |
1061 | #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2 | |
1062 | #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3 | |
1063 | #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4 | |
1064 | #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5 | |
1065 | #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6 | |
1066 | #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7 | |
1067 | #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8 | |
1068 | #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9 | |
1069 | #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA | |
1070 | #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB | |
1071 | #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC | |
1072 | #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD | |
1073 | #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE | |
1074 | #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF | |
1075 | #define NVM_CFG1_PORT_LED_MODE_BREAKOUT 0x10 | |
1076 | #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00 | |
1077 | #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8 | |
1078 | #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000 | |
1079 | #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16 | |
1080 | #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0 | |
1081 | #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1 | |
1082 | #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2 | |
1083 | #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3 | |
1084 | #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000 | |
1085 | #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20 | |
1086 | #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1 | |
1087 | #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2 | |
1088 | #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4 | |
11fdf7f2 TL |
1089 | /* GPIO for HW reset the PHY. In case it is the same for all ports, |
1090 | * need to set same value for all ports | |
1091 | */ | |
1092 | #define NVM_CFG1_PORT_EXT_PHY_RESET_MASK 0xFF000000 | |
1093 | #define NVM_CFG1_PORT_EXT_PHY_RESET_OFFSET 24 | |
1094 | #define NVM_CFG1_PORT_EXT_PHY_RESET_NA 0x0 | |
1095 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO0 0x1 | |
1096 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO1 0x2 | |
1097 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO2 0x3 | |
1098 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO3 0x4 | |
1099 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO4 0x5 | |
1100 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO5 0x6 | |
1101 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO6 0x7 | |
1102 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO7 0x8 | |
1103 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO8 0x9 | |
1104 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO9 0xA | |
1105 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO10 0xB | |
1106 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO11 0xC | |
1107 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO12 0xD | |
1108 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO13 0xE | |
1109 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO14 0xF | |
1110 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO15 0x10 | |
1111 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO16 0x11 | |
1112 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO17 0x12 | |
1113 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO18 0x13 | |
1114 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO19 0x14 | |
1115 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO20 0x15 | |
1116 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO21 0x16 | |
1117 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO22 0x17 | |
1118 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO23 0x18 | |
1119 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO24 0x19 | |
1120 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO25 0x1A | |
1121 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO26 0x1B | |
1122 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO27 0x1C | |
1123 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO28 0x1D | |
1124 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO29 0x1E | |
1125 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO30 0x1F | |
1126 | #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO31 0x20 | |
7c673cae FG |
1127 | u32 pcie_cfg; /* 0xC */ |
1128 | #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007 | |
1129 | #define NVM_CFG1_PORT_RESERVED15_OFFSET 0 | |
1130 | u32 features; /* 0x10 */ | |
1131 | #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001 | |
1132 | #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0 | |
1133 | #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0 | |
1134 | #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1 | |
1135 | #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002 | |
1136 | #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1 | |
1137 | #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0 | |
1138 | #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1 | |
1139 | u32 speed_cap_mask; /* 0x14 */ | |
1140 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF | |
1141 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 | |
1142 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1 | |
1143 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2 | |
9f95a23c | 1144 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4 |
7c673cae FG |
1145 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8 |
1146 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10 | |
1147 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20 | |
1148 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 | |
1149 | #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 | |
1150 | #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 | |
1151 | #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1 | |
1152 | #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2 | |
9f95a23c | 1153 | #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_20G 0x4 |
7c673cae FG |
1154 | #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8 |
1155 | #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10 | |
1156 | #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20 | |
1157 | #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 | |
1158 | u32 link_settings; /* 0x18 */ | |
1159 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F | |
1160 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0 | |
1161 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0 | |
1162 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1 | |
1163 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2 | |
9f95a23c | 1164 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3 |
7c673cae FG |
1165 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4 |
1166 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5 | |
1167 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6 | |
1168 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7 | |
7c673cae FG |
1169 | #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070 |
1170 | #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4 | |
1171 | #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1 | |
1172 | #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2 | |
1173 | #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4 | |
1174 | #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780 | |
1175 | #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7 | |
1176 | #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0 | |
1177 | #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1 | |
1178 | #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2 | |
9f95a23c | 1179 | #define NVM_CFG1_PORT_MFW_LINK_SPEED_20G 0x3 |
7c673cae FG |
1180 | #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4 |
1181 | #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5 | |
1182 | #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6 | |
1183 | #define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G 0x7 | |
7c673cae FG |
1184 | #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800 |
1185 | #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11 | |
1186 | #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1 | |
1187 | #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2 | |
1188 | #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4 | |
1189 | #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK \ | |
1190 | 0x00004000 | |
1191 | #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14 | |
1192 | #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED \ | |
1193 | 0x0 | |
1194 | #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED \ | |
1195 | 0x1 | |
1196 | #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000 | |
1197 | #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15 | |
1198 | #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0 | |
1199 | #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1 | |
1200 | #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000 | |
1201 | #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17 | |
1202 | #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0 | |
1203 | #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1 | |
1204 | #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2 | |
11fdf7f2 TL |
1205 | #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7 |
1206 | #define NVM_CFG1_PORT_FEC_AN_MODE_MASK 0x00700000 | |
1207 | #define NVM_CFG1_PORT_FEC_AN_MODE_OFFSET 20 | |
1208 | #define NVM_CFG1_PORT_FEC_AN_MODE_NONE 0x0 | |
1209 | #define NVM_CFG1_PORT_FEC_AN_MODE_10G_FIRECODE 0x1 | |
1210 | #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE 0x2 | |
1211 | #define NVM_CFG1_PORT_FEC_AN_MODE_10G_AND_25G_FIRECODE 0x3 | |
1212 | #define NVM_CFG1_PORT_FEC_AN_MODE_25G_RS 0x4 | |
1213 | #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE_AND_RS 0x5 | |
1214 | #define NVM_CFG1_PORT_FEC_AN_MODE_ALL 0x6 | |
9f95a23c TL |
1215 | #define NVM_CFG1_PORT_SMARTLINQ_MODE_MASK 0x00800000 |
1216 | #define NVM_CFG1_PORT_SMARTLINQ_MODE_OFFSET 23 | |
1217 | #define NVM_CFG1_PORT_SMARTLINQ_MODE_DISABLED 0x0 | |
1218 | #define NVM_CFG1_PORT_SMARTLINQ_MODE_ENABLED 0x1 | |
1219 | #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_MASK 0x01000000 | |
1220 | #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_OFFSET 24 | |
1221 | #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_DISABLED 0x0 | |
1222 | #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_ENABLED 0x1 | |
7c673cae FG |
1223 | u32 phy_cfg; /* 0x1C */ |
1224 | #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF | |
1225 | #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0 | |
1226 | #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1 | |
1227 | #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2 | |
1228 | #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4 | |
1229 | #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8 | |
1230 | #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10 | |
1231 | #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000 | |
1232 | #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16 | |
1233 | #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0 | |
1234 | #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2 | |
1235 | #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3 | |
1236 | #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4 | |
1237 | #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8 | |
1238 | #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9 | |
1239 | #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB | |
1240 | #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC | |
1241 | #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11 | |
1242 | #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12 | |
1243 | #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21 | |
1244 | #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22 | |
1245 | #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31 | |
1246 | #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000 | |
1247 | #define NVM_CFG1_PORT_AN_MODE_OFFSET 24 | |
1248 | #define NVM_CFG1_PORT_AN_MODE_NONE 0x0 | |
1249 | #define NVM_CFG1_PORT_AN_MODE_CL73 0x1 | |
1250 | #define NVM_CFG1_PORT_AN_MODE_CL37 0x2 | |
1251 | #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3 | |
1252 | #define NVM_CFG1_PORT_AN_MODE_BB_CL37_BAM 0x4 | |
1253 | #define NVM_CFG1_PORT_AN_MODE_BB_HPAM 0x5 | |
1254 | #define NVM_CFG1_PORT_AN_MODE_BB_SGMII 0x6 | |
1255 | u32 mgmt_traffic; /* 0x20 */ | |
1256 | #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F | |
1257 | #define NVM_CFG1_PORT_RESERVED61_OFFSET 0 | |
1258 | u32 ext_phy; /* 0x24 */ | |
1259 | #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF | |
1260 | #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0 | |
1261 | #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0 | |
11fdf7f2 | 1262 | #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM8485X 0x1 |
9f95a23c | 1263 | #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM5422X 0x2 |
7c673cae FG |
1264 | #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00 |
1265 | #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8 | |
11fdf7f2 TL |
1266 | /* EEE power saving mode */ |
1267 | #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000 | |
1268 | #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16 | |
1269 | #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0 | |
1270 | #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1 | |
1271 | #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2 | |
1272 | #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3 | |
7c673cae FG |
1273 | u32 mba_cfg1; /* 0x28 */ |
1274 | #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001 | |
1275 | #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0 | |
1276 | #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0 | |
1277 | #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1 | |
1278 | #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006 | |
1279 | #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1 | |
1280 | #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078 | |
1281 | #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3 | |
1282 | #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080 | |
1283 | #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7 | |
1284 | #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0 | |
1285 | #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1 | |
1286 | #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100 | |
1287 | #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8 | |
1288 | #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0 | |
1289 | #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1 | |
1290 | #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00 | |
1291 | #define NVM_CFG1_PORT_RESERVED5_OFFSET 9 | |
1292 | #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000 | |
1293 | #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17 | |
1294 | #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0 | |
1295 | #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1 | |
1296 | #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2 | |
9f95a23c | 1297 | #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_20G 0x3 |
7c673cae FG |
1298 | #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4 |
1299 | #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5 | |
1300 | #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6 | |
1301 | #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G 0x7 | |
7c673cae FG |
1302 | #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK \ |
1303 | 0x00E00000 | |
1304 | #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21 | |
9f95a23c TL |
1305 | #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_MASK \ |
1306 | 0x01000000 | |
1307 | #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_OFFSET 24 | |
1308 | #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_DISABLED \ | |
1309 | 0x0 | |
1310 | #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_ENABLED 0x1 | |
7c673cae FG |
1311 | u32 mba_cfg2; /* 0x2C */ |
1312 | #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF | |
1313 | #define NVM_CFG1_PORT_RESERVED65_OFFSET 0 | |
1314 | #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000 | |
1315 | #define NVM_CFG1_PORT_RESERVED66_OFFSET 16 | |
9f95a23c TL |
1316 | #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_MASK 0x01FE0000 |
1317 | #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_OFFSET 17 | |
7c673cae FG |
1318 | u32 vf_cfg; /* 0x30 */ |
1319 | #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF | |
1320 | #define NVM_CFG1_PORT_RESERVED8_OFFSET 0 | |
1321 | #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000 | |
1322 | #define NVM_CFG1_PORT_RESERVED6_OFFSET 16 | |
1323 | struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */ | |
1324 | u32 led_port_settings; /* 0x3C */ | |
1325 | #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF | |
1326 | #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0 | |
1327 | #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00 | |
1328 | #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8 | |
1329 | #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000 | |
1330 | #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16 | |
1331 | #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1 | |
1332 | #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2 | |
9f95a23c TL |
1333 | #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_25G 0x4 |
1334 | #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_25G 0x8 | |
1335 | #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_40G 0x8 | |
1336 | #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_40G 0x10 | |
1337 | #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_50G 0x10 | |
1338 | #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_50G 0x20 | |
7c673cae FG |
1339 | #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40 |
1340 | u32 transceiver_00; /* 0x40 */ | |
1341 | /* Define for mapping of transceiver signal module absent */ | |
1342 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF | |
1343 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0 | |
1344 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0 | |
1345 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1 | |
1346 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2 | |
1347 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3 | |
1348 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4 | |
1349 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5 | |
1350 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6 | |
1351 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7 | |
1352 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8 | |
1353 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9 | |
1354 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA | |
1355 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB | |
1356 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC | |
1357 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD | |
1358 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE | |
1359 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF | |
1360 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10 | |
1361 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11 | |
1362 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12 | |
1363 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13 | |
1364 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14 | |
1365 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15 | |
1366 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16 | |
1367 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17 | |
1368 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18 | |
1369 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19 | |
1370 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A | |
1371 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B | |
1372 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C | |
1373 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D | |
1374 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E | |
1375 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F | |
1376 | #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20 | |
1377 | /* Define the GPIO mux settings to switch i2c mux to this port */ | |
1378 | #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00 | |
1379 | #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8 | |
1380 | #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000 | |
1381 | #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12 | |
1382 | u32 device_ids; /* 0x44 */ | |
1383 | #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF | |
1384 | #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0 | |
1385 | #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_MASK 0x0000FF00 | |
1386 | #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_OFFSET 8 | |
1387 | #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_MASK 0x00FF0000 | |
1388 | #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_OFFSET 16 | |
1389 | #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000 | |
1390 | #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24 | |
1391 | u32 board_cfg; /* 0x48 */ | |
1392 | /* This field defines the board technology | |
1393 | * (backpane,transceiver,external PHY) | |
1394 | */ | |
1395 | #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF | |
1396 | #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0 | |
1397 | #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0 | |
1398 | #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1 | |
1399 | #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2 | |
1400 | #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3 | |
1401 | #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4 | |
1402 | /* This field defines the GPIO mapped to tx_disable signal in SFP */ | |
1403 | #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00 | |
1404 | #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8 | |
1405 | #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0 | |
1406 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1 | |
1407 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2 | |
1408 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3 | |
1409 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4 | |
1410 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5 | |
1411 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6 | |
1412 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7 | |
1413 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8 | |
1414 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9 | |
1415 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA | |
1416 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB | |
1417 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC | |
1418 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD | |
1419 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE | |
1420 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF | |
1421 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10 | |
1422 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11 | |
1423 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12 | |
1424 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13 | |
1425 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14 | |
1426 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15 | |
1427 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16 | |
1428 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17 | |
1429 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18 | |
1430 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19 | |
1431 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A | |
1432 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B | |
1433 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C | |
1434 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D | |
1435 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E | |
1436 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F | |
1437 | #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20 | |
1438 | u32 mnm_10g_cap; /* 0x4C */ | |
1439 | #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK \ | |
1440 | 0x0000FFFF | |
1441 | #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 | |
1442 | #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 | |
1443 | #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 | |
9f95a23c | 1444 | #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 |
7c673cae FG |
1445 | #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 |
1446 | #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 | |
1447 | #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 | |
1448 | #define \ | |
1449 | NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 | |
1450 | #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK \ | |
1451 | 0xFFFF0000 | |
1452 | #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_OFFSET \ | |
1453 | 16 | |
1454 | #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 | |
1455 | #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 | |
9f95a23c | 1456 | #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 |
7c673cae FG |
1457 | #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 |
1458 | #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 | |
1459 | #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 | |
1460 | #define \ | |
1461 | NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 | |
1462 | u32 mnm_10g_ctrl; /* 0x50 */ | |
1463 | #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK 0x0000000F | |
1464 | #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET 0 | |
1465 | #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0 | |
1466 | #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1 | |
1467 | #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2 | |
9f95a23c | 1468 | #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_20G 0x3 |
7c673cae FG |
1469 | #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4 |
1470 | #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5 | |
1471 | #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6 | |
1472 | #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7 | |
7c673cae FG |
1473 | #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0 |
1474 | #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4 | |
1475 | #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0 | |
1476 | #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1 | |
1477 | #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2 | |
9f95a23c | 1478 | #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_20G 0x3 |
7c673cae FG |
1479 | #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4 |
1480 | #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5 | |
1481 | #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6 | |
1482 | #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7 | |
7c673cae FG |
1483 | /* This field defines the board technology |
1484 | * (backpane,transceiver,external PHY) | |
1485 | */ | |
1486 | #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK 0x0000FF00 | |
1487 | #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_OFFSET 8 | |
1488 | #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED 0x0 | |
1489 | #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE 0x1 | |
1490 | #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE 0x2 | |
1491 | #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY 0x3 | |
1492 | #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE 0x4 | |
1493 | #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK \ | |
1494 | 0x00FF0000 | |
1495 | #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_OFFSET 16 | |
1496 | #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS 0x0 | |
1497 | #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR 0x2 | |
1498 | #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2 0x3 | |
1499 | #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4 0x4 | |
1500 | #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI 0x8 | |
1501 | #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI 0x9 | |
1502 | #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X 0xB | |
1503 | #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII 0xC | |
1504 | #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI 0x11 | |
1505 | #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI 0x12 | |
1506 | #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI 0x21 | |
1507 | #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI 0x22 | |
1508 | #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI 0x31 | |
1509 | #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK 0xFF000000 | |
1510 | #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_OFFSET 24 | |
1511 | u32 mnm_10g_misc; /* 0x54 */ | |
1512 | #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK 0x00000007 | |
1513 | #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET 0 | |
1514 | #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE 0x0 | |
1515 | #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE 0x1 | |
1516 | #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS 0x2 | |
11fdf7f2 | 1517 | #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_AUTO 0x7 |
7c673cae FG |
1518 | u32 mnm_25g_cap; /* 0x58 */ |
1519 | #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK \ | |
1520 | 0x0000FFFF | |
1521 | #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 | |
1522 | #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 | |
1523 | #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 | |
9f95a23c | 1524 | #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 |
7c673cae FG |
1525 | #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 |
1526 | #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 | |
1527 | #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 | |
1528 | #define \ | |
1529 | NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 | |
1530 | #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK \ | |
1531 | 0xFFFF0000 | |
1532 | #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_OFFSET \ | |
1533 | 16 | |
1534 | #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 | |
1535 | #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 | |
9f95a23c | 1536 | #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 |
7c673cae FG |
1537 | #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 |
1538 | #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 | |
1539 | #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 | |
1540 | #define \ | |
1541 | NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 | |
1542 | u32 mnm_25g_ctrl; /* 0x5C */ | |
1543 | #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK 0x0000000F | |
1544 | #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET 0 | |
1545 | #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0 | |
1546 | #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1 | |
1547 | #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2 | |
9f95a23c | 1548 | #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_20G 0x3 |
7c673cae FG |
1549 | #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4 |
1550 | #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5 | |
1551 | #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6 | |
1552 | #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7 | |
7c673cae FG |
1553 | #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0 |
1554 | #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4 | |
1555 | #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0 | |
1556 | #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1 | |
1557 | #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2 | |
9f95a23c | 1558 | #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_20G 0x3 |
7c673cae FG |
1559 | #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4 |
1560 | #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5 | |
1561 | #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6 | |
1562 | #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7 | |
7c673cae FG |
1563 | /* This field defines the board technology |
1564 | * (backpane,transceiver,external PHY) | |
1565 | */ | |
1566 | #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK 0x0000FF00 | |
1567 | #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_OFFSET 8 | |
1568 | #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED 0x0 | |
1569 | #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE 0x1 | |
1570 | #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE 0x2 | |
1571 | #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY 0x3 | |
1572 | #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE 0x4 | |
1573 | #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK \ | |
1574 | 0x00FF0000 | |
1575 | #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_OFFSET 16 | |
1576 | #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS 0x0 | |
1577 | #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR 0x2 | |
1578 | #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2 0x3 | |
1579 | #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4 0x4 | |
1580 | #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI 0x8 | |
1581 | #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI 0x9 | |
1582 | #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X 0xB | |
1583 | #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII 0xC | |
1584 | #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI 0x11 | |
1585 | #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI 0x12 | |
1586 | #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI 0x21 | |
1587 | #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI 0x22 | |
1588 | #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI 0x31 | |
1589 | #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK 0xFF000000 | |
1590 | #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_OFFSET 24 | |
1591 | u32 mnm_25g_misc; /* 0x60 */ | |
1592 | #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK 0x00000007 | |
1593 | #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET 0 | |
1594 | #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE 0x0 | |
1595 | #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE 0x1 | |
1596 | #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS 0x2 | |
11fdf7f2 | 1597 | #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_AUTO 0x7 |
7c673cae FG |
1598 | u32 mnm_40g_cap; /* 0x64 */ |
1599 | #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK \ | |
1600 | 0x0000FFFF | |
1601 | #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 | |
1602 | #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 | |
1603 | #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 | |
9f95a23c | 1604 | #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 |
7c673cae FG |
1605 | #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 |
1606 | #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 | |
1607 | #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 | |
1608 | #define \ | |
1609 | NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 | |
1610 | #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK \ | |
1611 | 0xFFFF0000 | |
1612 | #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_OFFSET \ | |
1613 | 16 | |
1614 | #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 | |
1615 | #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 | |
9f95a23c | 1616 | #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 |
7c673cae FG |
1617 | #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 |
1618 | #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 | |
1619 | #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 | |
1620 | #define \ | |
1621 | NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 | |
1622 | u32 mnm_40g_ctrl; /* 0x68 */ | |
1623 | #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK 0x0000000F | |
1624 | #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET 0 | |
1625 | #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0 | |
1626 | #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1 | |
1627 | #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2 | |
9f95a23c | 1628 | #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_20G 0x3 |
7c673cae FG |
1629 | #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4 |
1630 | #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5 | |
1631 | #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6 | |
1632 | #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7 | |
7c673cae FG |
1633 | #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0 |
1634 | #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4 | |
1635 | #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0 | |
1636 | #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1 | |
1637 | #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2 | |
9f95a23c | 1638 | #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_20G 0x3 |
7c673cae FG |
1639 | #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4 |
1640 | #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5 | |
1641 | #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6 | |
1642 | #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7 | |
7c673cae FG |
1643 | /* This field defines the board technology |
1644 | * (backpane,transceiver,external PHY) | |
1645 | */ | |
1646 | #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK 0x0000FF00 | |
1647 | #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_OFFSET 8 | |
1648 | #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED 0x0 | |
1649 | #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE 0x1 | |
1650 | #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE 0x2 | |
1651 | #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY 0x3 | |
1652 | #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE 0x4 | |
1653 | #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK \ | |
1654 | 0x00FF0000 | |
1655 | #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_OFFSET 16 | |
1656 | #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS 0x0 | |
1657 | #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR 0x2 | |
1658 | #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2 0x3 | |
1659 | #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4 0x4 | |
1660 | #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI 0x8 | |
1661 | #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI 0x9 | |
1662 | #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X 0xB | |
1663 | #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII 0xC | |
1664 | #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI 0x11 | |
1665 | #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI 0x12 | |
1666 | #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI 0x21 | |
1667 | #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI 0x22 | |
1668 | #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI 0x31 | |
1669 | #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK 0xFF000000 | |
1670 | #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_OFFSET 24 | |
1671 | u32 mnm_40g_misc; /* 0x6C */ | |
1672 | #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK 0x00000007 | |
1673 | #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET 0 | |
1674 | #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE 0x0 | |
1675 | #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE 0x1 | |
1676 | #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS 0x2 | |
11fdf7f2 | 1677 | #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_AUTO 0x7 |
7c673cae FG |
1678 | u32 mnm_50g_cap; /* 0x70 */ |
1679 | #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK \ | |
1680 | 0x0000FFFF | |
1681 | #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 | |
1682 | #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 | |
1683 | #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 | |
9f95a23c | 1684 | #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 |
7c673cae FG |
1685 | #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 |
1686 | #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 | |
1687 | #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 | |
1688 | #define \ | |
1689 | NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G \ | |
1690 | 0x40 | |
1691 | #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK \ | |
1692 | 0xFFFF0000 | |
1693 | #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_OFFSET \ | |
1694 | 16 | |
1695 | #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 | |
1696 | #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 | |
9f95a23c | 1697 | #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 |
7c673cae FG |
1698 | #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 |
1699 | #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 | |
1700 | #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 | |
1701 | #define \ | |
1702 | NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G \ | |
1703 | 0x40 | |
1704 | u32 mnm_50g_ctrl; /* 0x74 */ | |
1705 | #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK 0x0000000F | |
1706 | #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET 0 | |
1707 | #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0 | |
1708 | #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1 | |
1709 | #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2 | |
9f95a23c | 1710 | #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_20G 0x3 |
7c673cae FG |
1711 | #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4 |
1712 | #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5 | |
1713 | #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6 | |
1714 | #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7 | |
7c673cae FG |
1715 | #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0 |
1716 | #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4 | |
1717 | #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0 | |
1718 | #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1 | |
1719 | #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2 | |
9f95a23c | 1720 | #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_20G 0x3 |
7c673cae FG |
1721 | #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4 |
1722 | #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5 | |
1723 | #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6 | |
1724 | #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7 | |
7c673cae FG |
1725 | /* This field defines the board technology |
1726 | * (backpane,transceiver,external PHY) | |
1727 | */ | |
1728 | #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK 0x0000FF00 | |
1729 | #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_OFFSET 8 | |
1730 | #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED 0x0 | |
1731 | #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE 0x1 | |
1732 | #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE 0x2 | |
1733 | #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY 0x3 | |
1734 | #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE 0x4 | |
1735 | #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK \ | |
1736 | 0x00FF0000 | |
1737 | #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_OFFSET 16 | |
1738 | #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS 0x0 | |
1739 | #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR 0x2 | |
1740 | #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2 0x3 | |
1741 | #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4 0x4 | |
1742 | #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI 0x8 | |
1743 | #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI 0x9 | |
1744 | #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X 0xB | |
1745 | #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII 0xC | |
1746 | #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI 0x11 | |
1747 | #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI 0x12 | |
1748 | #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI 0x21 | |
1749 | #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI 0x22 | |
1750 | #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI 0x31 | |
1751 | #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK 0xFF000000 | |
1752 | #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_OFFSET 24 | |
1753 | u32 mnm_50g_misc; /* 0x78 */ | |
1754 | #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK 0x00000007 | |
1755 | #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET 0 | |
1756 | #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE 0x0 | |
1757 | #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE 0x1 | |
1758 | #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS 0x2 | |
11fdf7f2 | 1759 | #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_AUTO 0x7 |
7c673cae FG |
1760 | u32 mnm_100g_cap; /* 0x7C */ |
1761 | #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK \ | |
1762 | 0x0000FFFF | |
1763 | #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0 | |
1764 | #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1 | |
1765 | #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2 | |
9f95a23c | 1766 | #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_20G 0x4 |
7c673cae FG |
1767 | #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8 |
1768 | #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10 | |
1769 | #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20 | |
1770 | #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G 0x40 | |
1771 | #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK \ | |
1772 | 0xFFFF0000 | |
1773 | #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16 | |
1774 | #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1 | |
1775 | #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2 | |
9f95a23c | 1776 | #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_20G 0x4 |
7c673cae FG |
1777 | #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8 |
1778 | #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10 | |
1779 | #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20 | |
1780 | #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G 0x40 | |
1781 | u32 mnm_100g_ctrl; /* 0x80 */ | |
1782 | #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK 0x0000000F | |
1783 | #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET 0 | |
1784 | #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0 | |
1785 | #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1 | |
1786 | #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2 | |
9f95a23c | 1787 | #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_20G 0x3 |
7c673cae FG |
1788 | #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4 |
1789 | #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5 | |
1790 | #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6 | |
1791 | #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7 | |
7c673cae FG |
1792 | #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0 |
1793 | #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4 | |
1794 | #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0 | |
1795 | #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1 | |
1796 | #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2 | |
9f95a23c | 1797 | #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_20G 0x3 |
7c673cae FG |
1798 | #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4 |
1799 | #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5 | |
1800 | #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6 | |
1801 | #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7 | |
7c673cae FG |
1802 | /* This field defines the board technology |
1803 | * (backpane,transceiver,external PHY) | |
1804 | */ | |
1805 | #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK 0x0000FF00 | |
1806 | #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_OFFSET 8 | |
1807 | #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED 0x0 | |
1808 | #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE 0x1 | |
1809 | #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE 0x2 | |
1810 | #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY 0x3 | |
1811 | #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE 0x4 | |
1812 | #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK \ | |
1813 | 0x00FF0000 | |
1814 | #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_OFFSET 16 | |
1815 | #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS 0x0 | |
1816 | #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR 0x2 | |
1817 | #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2 0x3 | |
1818 | #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4 0x4 | |
1819 | #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI 0x8 | |
1820 | #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI 0x9 | |
1821 | #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X 0xB | |
1822 | #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII 0xC | |
1823 | #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI 0x11 | |
1824 | #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI 0x12 | |
1825 | #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI 0x21 | |
1826 | #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI 0x22 | |
1827 | #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI 0x31 | |
1828 | #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK 0xFF000000 | |
1829 | #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_OFFSET 24 | |
1830 | u32 mnm_100g_misc; /* 0x84 */ | |
1831 | #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK 0x00000007 | |
1832 | #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET 0 | |
1833 | #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE 0x0 | |
1834 | #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1 | |
1835 | #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2 | |
11fdf7f2 | 1836 | #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_AUTO 0x7 |
9f95a23c TL |
1837 | u32 temperature; /* 0x88 */ |
1838 | #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_MASK 0x000000FF | |
1839 | #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_OFFSET 0 | |
1840 | #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_MASK \ | |
1841 | 0x0000FF00 | |
1842 | #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_OFFSET 8 | |
1843 | u32 reserved[115]; /* 0x8C */ | |
7c673cae FG |
1844 | }; |
1845 | ||
1846 | struct nvm_cfg1_func { | |
1847 | struct nvm_cfg_mac_address mac_address; /* 0x0 */ | |
1848 | u32 rsrv1; /* 0x8 */ | |
1849 | #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF | |
1850 | #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0 | |
1851 | #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000 | |
1852 | #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16 | |
1853 | u32 rsrv2; /* 0xC */ | |
1854 | #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF | |
1855 | #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0 | |
1856 | #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000 | |
1857 | #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16 | |
1858 | u32 device_id; /* 0x10 */ | |
1859 | #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF | |
1860 | #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0 | |
1861 | #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000 | |
1862 | #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16 | |
1863 | u32 cmn_cfg; /* 0x14 */ | |
1864 | #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007 | |
1865 | #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0 | |
1866 | #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0 | |
1867 | #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3 | |
1868 | #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4 | |
1869 | #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7 | |
1870 | #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8 | |
1871 | #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3 | |
1872 | #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000 | |
1873 | #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19 | |
1874 | #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0 | |
1875 | #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1 | |
1876 | #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2 | |
1877 | #define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3 | |
1878 | #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000 | |
1879 | #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23 | |
1880 | #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000 | |
1881 | #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31 | |
1882 | #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0 | |
1883 | #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1 | |
1884 | u32 pci_cfg; /* 0x18 */ | |
1885 | #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F | |
1886 | #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0 | |
1887 | /* AH VF BAR2 size */ | |
1888 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_MASK 0x00003F80 | |
1889 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_OFFSET 7 | |
1890 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_DISABLED 0x0 | |
1891 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4K 0x1 | |
1892 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8K 0x2 | |
1893 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16K 0x3 | |
1894 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32K 0x4 | |
1895 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64K 0x5 | |
1896 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_128K 0x6 | |
1897 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_256K 0x7 | |
1898 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_512K 0x8 | |
1899 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_1M 0x9 | |
1900 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_2M 0xA | |
1901 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4M 0xB | |
1902 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8M 0xC | |
1903 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16M 0xD | |
1904 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32M 0xE | |
1905 | #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64M 0xF | |
1906 | #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000 | |
1907 | #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14 | |
1908 | #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0 | |
1909 | #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1 | |
1910 | #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2 | |
1911 | #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3 | |
1912 | #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4 | |
1913 | #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5 | |
1914 | #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6 | |
1915 | #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7 | |
1916 | #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8 | |
1917 | #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9 | |
1918 | #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA | |
1919 | #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB | |
1920 | #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC | |
1921 | #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD | |
1922 | #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE | |
1923 | #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF | |
1924 | #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000 | |
1925 | #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18 | |
1926 | /* Hide function in npar mode */ | |
1927 | #define NVM_CFG1_FUNC_FUNCTION_HIDE_MASK 0x04000000 | |
1928 | #define NVM_CFG1_FUNC_FUNCTION_HIDE_OFFSET 26 | |
1929 | #define NVM_CFG1_FUNC_FUNCTION_HIDE_DISABLED 0x0 | |
1930 | #define NVM_CFG1_FUNC_FUNCTION_HIDE_ENABLED 0x1 | |
1931 | /* AH BAR2 size (per function) */ | |
1932 | #define NVM_CFG1_FUNC_BAR2_SIZE_MASK 0x78000000 | |
1933 | #define NVM_CFG1_FUNC_BAR2_SIZE_OFFSET 27 | |
1934 | #define NVM_CFG1_FUNC_BAR2_SIZE_DISABLED 0x0 | |
1935 | #define NVM_CFG1_FUNC_BAR2_SIZE_1M 0x5 | |
1936 | #define NVM_CFG1_FUNC_BAR2_SIZE_2M 0x6 | |
1937 | #define NVM_CFG1_FUNC_BAR2_SIZE_4M 0x7 | |
1938 | #define NVM_CFG1_FUNC_BAR2_SIZE_8M 0x8 | |
1939 | #define NVM_CFG1_FUNC_BAR2_SIZE_16M 0x9 | |
1940 | #define NVM_CFG1_FUNC_BAR2_SIZE_32M 0xA | |
1941 | #define NVM_CFG1_FUNC_BAR2_SIZE_64M 0xB | |
1942 | #define NVM_CFG1_FUNC_BAR2_SIZE_128M 0xC | |
1943 | #define NVM_CFG1_FUNC_BAR2_SIZE_256M 0xD | |
1944 | #define NVM_CFG1_FUNC_BAR2_SIZE_512M 0xE | |
1945 | #define NVM_CFG1_FUNC_BAR2_SIZE_1G 0xF | |
1946 | struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */ | |
1947 | struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */ | |
1948 | u32 preboot_generic_cfg; /* 0x2C */ | |
1949 | #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF | |
1950 | #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0 | |
1951 | #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000 | |
1952 | #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16 | |
11fdf7f2 TL |
1953 | #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_MASK 0x001E0000 |
1954 | #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_OFFSET 17 | |
1955 | #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ETHERNET 0x1 | |
1956 | #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_FCOE 0x2 | |
1957 | #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ISCSI 0x4 | |
9f95a23c | 1958 | #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_RDMA 0x8 |
7c673cae FG |
1959 | u32 reserved[8]; /* 0x30 */ |
1960 | }; | |
1961 | ||
1962 | struct nvm_cfg1 { | |
1963 | struct nvm_cfg1_glob glob; /* 0x0 */ | |
11fdf7f2 | 1964 | struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x228 */ |
7c673cae FG |
1965 | struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */ |
1966 | struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */ | |
1967 | }; | |
1968 | ||
1969 | /****************************************** | |
1970 | * nvm_cfg structs | |
1971 | ******************************************/ | |
1972 | enum nvm_cfg_sections { | |
1973 | NVM_CFG_SECTION_NVM_CFG1, | |
1974 | NVM_CFG_SECTION_MAX | |
1975 | }; | |
1976 | ||
1977 | struct nvm_cfg { | |
1978 | u32 num_sections; | |
1979 | u32 sections_offset[NVM_CFG_SECTION_MAX]; | |
1980 | struct nvm_cfg1 cfg1; | |
1981 | }; | |
1982 | ||
1983 | #endif /* NVM_CFG_H */ |