projects / ceph.git / blame
| Commit | Line | Data |
|---|---|---|
| 11fdf7f2 TL |
1 | /* SPDX-License-Identifier: BSD-3-Clause |
| 2 | * | |
| f67539c2 TL |
3 | * Copyright(c) 2019-2020 Xilinx, Inc. |
| 4 | * Copyright(c) 2008-2019 Solarflare Communications Inc. | |
| 11fdf7f2 TL |
5 | */ |
| 6 | ||
| 9f95a23c TL |
7 | /* |
| 8 | * This file is automatically generated. DO NOT EDIT IT. | |
| 9 | * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and | |
| 10 | * rebuild this file with "make -C doc mcdiheaders". | |
| 11 | */ | |
| 11fdf7f2 TL |
12 | |
| 13 | #ifndef _SIENA_MC_DRIVER_PCOL_AOE_H | |
| 14 | #define _SIENA_MC_DRIVER_PCOL_AOE_H | |
| 15 | ||
| 16 | ||
| 17 | ||
| 18 | /***********************************/ | |
| 19 | /* MC_CMD_FC | |
| 20 | * Perform an FC operation | |
| 21 | */ | |
| 22 | #define MC_CMD_FC 0x9 | |
| 23 | ||
| 24 | /* MC_CMD_FC_IN msgrequest */ | |
| 25 | #define MC_CMD_FC_IN_LEN 4 | |
| 26 | #define MC_CMD_FC_IN_OP_HDR_OFST 0 | |
| 27 | #define MC_CMD_FC_IN_OP_HDR_LEN 4 | |
| 28 | #define MC_CMD_FC_IN_OP_LBN 0 | |
| 29 | #define MC_CMD_FC_IN_OP_WIDTH 8 | |
| 30 | /* enum: NULL MCDI command to FC. */ | |
| 31 | #define MC_CMD_FC_OP_NULL 0x1 | |
| 32 | /* enum: Unused opcode */ | |
| 33 | #define MC_CMD_FC_OP_UNUSED 0x2 | |
| 34 | /* enum: MAC driver commands */ | |
| 35 | #define MC_CMD_FC_OP_MAC 0x3 | |
| 36 | /* enum: Read FC memory */ | |
| 37 | #define MC_CMD_FC_OP_READ32 0x4 | |
| 38 | /* enum: Write to FC memory */ | |
| 39 | #define MC_CMD_FC_OP_WRITE32 0x5 | |
| 40 | /* enum: Read FC memory */ | |
| 41 | #define MC_CMD_FC_OP_TRC_READ 0x6 | |
| 42 | /* enum: Write to FC memory */ | |
| 43 | #define MC_CMD_FC_OP_TRC_WRITE 0x7 | |
| 44 | /* enum: FC firmware Version */ | |
| 45 | #define MC_CMD_FC_OP_GET_VERSION 0x8 | |
| 46 | /* enum: Read FC memory */ | |
| 47 | #define MC_CMD_FC_OP_TRC_RX_READ 0x9 | |
| 48 | /* enum: Write to FC memory */ | |
| 49 | #define MC_CMD_FC_OP_TRC_RX_WRITE 0xa | |
| 50 | /* enum: SFP parameters */ | |
| 51 | #define MC_CMD_FC_OP_SFP 0xb | |
| 52 | /* enum: DDR3 test */ | |
| 53 | #define MC_CMD_FC_OP_DDR_TEST 0xc | |
| 54 | /* enum: Get Crash context from FC */ | |
| 55 | #define MC_CMD_FC_OP_GET_ASSERT 0xd | |
| 56 | /* enum: Get FPGA Build registers */ | |
| 57 | #define MC_CMD_FC_OP_FPGA_BUILD 0xe | |
| 58 | /* enum: Read map support commands */ | |
| 59 | #define MC_CMD_FC_OP_READ_MAP 0xf | |
| 60 | /* enum: FC Capabilities */ | |
| 61 | #define MC_CMD_FC_OP_CAPABILITIES 0x10 | |
| 62 | /* enum: FC Global flags */ | |
| 63 | #define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 | |
| 64 | /* enum: FC IO using relative addressing modes */ | |
| 65 | #define MC_CMD_FC_OP_IO_REL 0x12 | |
| 66 | /* enum: FPGA link information */ | |
| 67 | #define MC_CMD_FC_OP_UHLINK 0x13 | |
| 68 | /* enum: Configure loopbacks and link on FPGA ports */ | |
| 69 | #define MC_CMD_FC_OP_SET_LINK 0x14 | |
| 70 | /* enum: Licensing operations relating to AOE */ | |
| 71 | #define MC_CMD_FC_OP_LICENSE 0x15 | |
| 72 | /* enum: Startup information to the FC */ | |
| 73 | #define MC_CMD_FC_OP_STARTUP 0x16 | |
| 74 | /* enum: Configure a DMA read */ | |
| 75 | #define MC_CMD_FC_OP_DMA 0x17 | |
| 76 | /* enum: Configure a timed read */ | |
| 77 | #define MC_CMD_FC_OP_TIMED_READ 0x18 | |
| 78 | /* enum: Control UART logging */ | |
| 79 | #define MC_CMD_FC_OP_LOG 0x19 | |
| 80 | /* enum: Get the value of a given clock_id */ | |
| 81 | #define MC_CMD_FC_OP_CLOCK 0x1a | |
| 82 | /* enum: DDR3/QDR3 parameters */ | |
| 83 | #define MC_CMD_FC_OP_DDR 0x1b | |
| 84 | /* enum: PTP and timestamp control */ | |
| 85 | #define MC_CMD_FC_OP_TIMESTAMP 0x1c | |
| 86 | /* enum: Commands for SPI Flash interface */ | |
| 87 | #define MC_CMD_FC_OP_SPI 0x1d | |
| 88 | /* enum: Commands for diagnostic components */ | |
| 89 | #define MC_CMD_FC_OP_DIAG 0x1e | |
| 90 | /* enum: External AOE port. */ | |
| 91 | #define MC_CMD_FC_IN_PORT_EXT_OFST 0x0 | |
| 92 | /* enum: Internal AOE port. */ | |
| 93 | #define MC_CMD_FC_IN_PORT_INT_OFST 0x40 | |
| 94 | ||
| 95 | /* MC_CMD_FC_IN_NULL msgrequest */ | |
| 96 | #define MC_CMD_FC_IN_NULL_LEN 4 | |
| 97 | #define MC_CMD_FC_IN_CMD_OFST 0 | |
| 98 | #define MC_CMD_FC_IN_CMD_LEN 4 | |
| 99 | ||
| 100 | /* MC_CMD_FC_IN_PHY msgrequest */ | |
| 101 | #define MC_CMD_FC_IN_PHY_LEN 5 | |
| 102 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 103 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 104 | /* FC PHY driver operation code */ | |
| 105 | #define MC_CMD_FC_IN_PHY_OP_OFST 4 | |
| 106 | #define MC_CMD_FC_IN_PHY_OP_LEN 1 | |
| 107 | /* enum: PHY init handler */ | |
| 108 | #define MC_CMD_FC_OP_PHY_OP_INIT 0x1 | |
| 109 | /* enum: PHY reconfigure handler */ | |
| 110 | #define MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2 | |
| 111 | /* enum: PHY reboot handler */ | |
| 112 | #define MC_CMD_FC_OP_PHY_OP_REBOOT 0x3 | |
| 113 | /* enum: PHY get_supported_cap handler */ | |
| 114 | #define MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4 | |
| 115 | /* enum: PHY get_config handler */ | |
| 116 | #define MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5 | |
| 117 | /* enum: PHY get_media_info handler */ | |
| 118 | #define MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6 | |
| 119 | /* enum: PHY set_led handler */ | |
| 120 | #define MC_CMD_FC_OP_PHY_OP_SET_LED 0x7 | |
| 121 | /* enum: PHY lasi_interrupt handler */ | |
| 122 | #define MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8 | |
| 123 | /* enum: PHY check_link handler */ | |
| 124 | #define MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9 | |
| 125 | /* enum: PHY fill_stats handler */ | |
| 126 | #define MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa | |
| 127 | /* enum: PHY bpx_link_state_changed handler */ | |
| 128 | #define MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb | |
| 129 | /* enum: PHY get_state handler */ | |
| 130 | #define MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc | |
| 131 | /* enum: PHY start_bist handler */ | |
| 132 | #define MC_CMD_FC_OP_PHY_OP_START_BIST 0xd | |
| 133 | /* enum: PHY poll_bist handler */ | |
| 134 | #define MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe | |
| 135 | /* enum: PHY nvram_test handler */ | |
| 136 | #define MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf | |
| 137 | /* enum: PHY relinquish handler */ | |
| 138 | #define MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10 | |
| 139 | /* enum: PHY read connection from FC - may be not required */ | |
| 140 | #define MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11 | |
| 141 | /* enum: PHY read flags from FC - may be not required */ | |
| 142 | #define MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12 | |
| 143 | ||
| 144 | /* MC_CMD_FC_IN_PHY_INIT msgrequest */ | |
| 145 | #define MC_CMD_FC_IN_PHY_INIT_LEN 4 | |
| 146 | #define MC_CMD_FC_IN_PHY_CMD_OFST 0 | |
| 147 | #define MC_CMD_FC_IN_PHY_CMD_LEN 4 | |
| 148 | ||
| 149 | /* MC_CMD_FC_IN_MAC msgrequest */ | |
| 150 | #define MC_CMD_FC_IN_MAC_LEN 8 | |
| 151 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 152 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 153 | #define MC_CMD_FC_IN_MAC_HEADER_OFST 4 | |
| 154 | #define MC_CMD_FC_IN_MAC_HEADER_LEN 4 | |
| 155 | #define MC_CMD_FC_IN_MAC_OP_LBN 0 | |
| 156 | #define MC_CMD_FC_IN_MAC_OP_WIDTH 8 | |
| 157 | /* enum: MAC reconfigure handler */ | |
| 158 | #define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 | |
| 159 | /* enum: MAC Set command - same as MC_CMD_SET_MAC */ | |
| 160 | #define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 | |
| 161 | /* enum: MAC statistics */ | |
| 162 | #define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 | |
| 163 | /* enum: MAC RX statistics */ | |
| 164 | #define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 | |
| 165 | /* enum: MAC TX statistics */ | |
| 166 | #define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 | |
| 167 | /* enum: MAC Read status */ | |
| 168 | #define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 | |
| 169 | #define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8 | |
| 170 | #define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8 | |
| 171 | /* enum: External FPGA port. */ | |
| 172 | #define MC_CMD_FC_PORT_EXT 0x0 | |
| 173 | /* enum: Internal Siena-facing FPGA ports. */ | |
| 174 | #define MC_CMD_FC_PORT_INT 0x1 | |
| 175 | #define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16 | |
| 176 | #define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8 | |
| 177 | #define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24 | |
| 178 | #define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8 | |
| 179 | /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are | |
| 180 | * irrelevant. Port number is derived from pci_fn; passed in FC header. | |
| 181 | */ | |
| 182 | #define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 | |
| 183 | /* enum: Override default port number. Port number determined by fields | |
| 184 | * PORT_TYPE and PORT_IDX. | |
| 185 | */ | |
| 186 | #define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 | |
| 187 | ||
| 188 | /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */ | |
| 189 | #define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8 | |
| 190 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 191 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 192 | /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ | |
| 193 | /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ | |
| 194 | ||
| 195 | /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */ | |
| 196 | #define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32 | |
| 197 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 198 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 199 | /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ | |
| 200 | /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ | |
| 201 | /* MTU size */ | |
| 202 | #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8 | |
| 203 | #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_LEN 4 | |
| 204 | /* Drain Tx FIFO */ | |
| 205 | #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12 | |
| 206 | #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_LEN 4 | |
| 207 | #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16 | |
| 208 | #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8 | |
| 209 | #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16 | |
| 210 | #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20 | |
| 211 | #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24 | |
| 212 | #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_LEN 4 | |
| 213 | #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0 | |
| 214 | #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1 | |
| 215 | #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1 | |
| 216 | #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1 | |
| 217 | #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28 | |
| 218 | #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_LEN 4 | |
| 219 | ||
| 220 | /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */ | |
| 221 | #define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8 | |
| 222 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 223 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 224 | /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ | |
| 225 | /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ | |
| 226 | ||
| 227 | /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */ | |
| 228 | #define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8 | |
| 229 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 230 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 231 | /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ | |
| 232 | /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ | |
| 233 | ||
| 234 | /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */ | |
| 235 | #define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8 | |
| 236 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 237 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 238 | /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ | |
| 239 | /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ | |
| 240 | ||
| 241 | /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */ | |
| 242 | #define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20 | |
| 243 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 244 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 245 | /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ | |
| 246 | /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ | |
| 247 | /* MC Statistics index */ | |
| 248 | #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8 | |
| 249 | #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_LEN 4 | |
| 250 | #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12 | |
| 251 | #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_LEN 4 | |
| 252 | #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0 | |
| 253 | #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1 | |
| 254 | #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1 | |
| 255 | #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1 | |
| 256 | #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2 | |
| 257 | #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1 | |
| 258 | /* Number of statistics to read */ | |
| 259 | #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16 | |
| 260 | #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_LEN 4 | |
| 261 | #define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */ | |
| 262 | #define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */ | |
| 263 | ||
| 264 | /* MC_CMD_FC_IN_READ32 msgrequest */ | |
| 265 | #define MC_CMD_FC_IN_READ32_LEN 16 | |
| 266 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 267 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 268 | #define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4 | |
| 269 | #define MC_CMD_FC_IN_READ32_ADDR_HI_LEN 4 | |
| 270 | #define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8 | |
| 271 | #define MC_CMD_FC_IN_READ32_ADDR_LO_LEN 4 | |
| 272 | #define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12 | |
| 273 | #define MC_CMD_FC_IN_READ32_NUMWORDS_LEN 4 | |
| 274 | ||
| 275 | /* MC_CMD_FC_IN_WRITE32 msgrequest */ | |
| 276 | #define MC_CMD_FC_IN_WRITE32_LENMIN 16 | |
| 277 | #define MC_CMD_FC_IN_WRITE32_LENMAX 252 | |
| 9f95a23c | 278 | #define MC_CMD_FC_IN_WRITE32_LENMAX_MCDI2 1020 |
| 11fdf7f2 | 279 | #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num)) |
| f67539c2 | 280 | #define MC_CMD_FC_IN_WRITE32_BUFFER_NUM(len) (((len)-12)/4) |
| 11fdf7f2 TL |
281 | /* MC_CMD_FC_IN_CMD_OFST 0 */ |
| 282 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 283 | #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4 | |
| 284 | #define MC_CMD_FC_IN_WRITE32_ADDR_HI_LEN 4 | |
| 285 | #define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8 | |
| 286 | #define MC_CMD_FC_IN_WRITE32_ADDR_LO_LEN 4 | |
| 287 | #define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12 | |
| 288 | #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4 | |
| 289 | #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1 | |
| 290 | #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60 | |
| 9f95a23c | 291 | #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM_MCDI2 252 |
| 11fdf7f2 TL |
292 | |
| 293 | /* MC_CMD_FC_IN_TRC_READ msgrequest */ | |
| 294 | #define MC_CMD_FC_IN_TRC_READ_LEN 12 | |
| 295 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 296 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 297 | #define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4 | |
| 298 | #define MC_CMD_FC_IN_TRC_READ_TRC_LEN 4 | |
| 299 | #define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8 | |
| 300 | #define MC_CMD_FC_IN_TRC_READ_CHANNEL_LEN 4 | |
| 301 | ||
| 302 | /* MC_CMD_FC_IN_TRC_WRITE msgrequest */ | |
| 303 | #define MC_CMD_FC_IN_TRC_WRITE_LEN 28 | |
| 304 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 305 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 306 | #define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4 | |
| 307 | #define MC_CMD_FC_IN_TRC_WRITE_TRC_LEN 4 | |
| 308 | #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8 | |
| 309 | #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_LEN 4 | |
| 310 | #define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12 | |
| 311 | #define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4 | |
| 312 | #define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4 | |
| 313 | ||
| 314 | /* MC_CMD_FC_IN_GET_VERSION msgrequest */ | |
| 315 | #define MC_CMD_FC_IN_GET_VERSION_LEN 4 | |
| 316 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 317 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 318 | ||
| 319 | /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */ | |
| 320 | #define MC_CMD_FC_IN_TRC_RX_READ_LEN 12 | |
| 321 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 322 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 323 | #define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4 | |
| 324 | #define MC_CMD_FC_IN_TRC_RX_READ_TRC_LEN 4 | |
| 325 | #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8 | |
| 326 | #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_LEN 4 | |
| 327 | ||
| 328 | /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */ | |
| 329 | #define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20 | |
| 330 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 331 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 332 | #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4 | |
| 333 | #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_LEN 4 | |
| 334 | #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8 | |
| 335 | #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_LEN 4 | |
| 336 | #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12 | |
| 337 | #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4 | |
| 338 | #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2 | |
| 339 | ||
| 340 | /* MC_CMD_FC_IN_SFP msgrequest */ | |
| 341 | #define MC_CMD_FC_IN_SFP_LEN 28 | |
| 342 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 343 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 344 | /* Link speed is 100, 1000, 10000, 40000 */ | |
| 345 | #define MC_CMD_FC_IN_SFP_SPEED_OFST 4 | |
| 346 | #define MC_CMD_FC_IN_SFP_SPEED_LEN 4 | |
| 347 | /* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */ | |
| 348 | #define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8 | |
| 349 | #define MC_CMD_FC_IN_SFP_COPPER_LEN_LEN 4 | |
| 350 | /* Not relevant for cards with QSFP modules. For older cards, true if module is | |
| 351 | * a dual speed SFP+ module. | |
| 352 | */ | |
| 353 | #define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12 | |
| 354 | #define MC_CMD_FC_IN_SFP_DUAL_SPEED_LEN 4 | |
| 355 | /* True if an SFP Module is present (other fields valid when true) */ | |
| 356 | #define MC_CMD_FC_IN_SFP_PRESENT_OFST 16 | |
| 357 | #define MC_CMD_FC_IN_SFP_PRESENT_LEN 4 | |
| 358 | /* The type of the SFP+ Module. For later cards with QSFP modules, this field | |
| 359 | * is unused and the type is communicated by other means. | |
| 360 | */ | |
| 361 | #define MC_CMD_FC_IN_SFP_TYPE_OFST 20 | |
| 362 | #define MC_CMD_FC_IN_SFP_TYPE_LEN 4 | |
| 363 | /* Capabilities corresponding to 1 bits. */ | |
| 364 | #define MC_CMD_FC_IN_SFP_CAPS_OFST 24 | |
| 365 | #define MC_CMD_FC_IN_SFP_CAPS_LEN 4 | |
| 366 | ||
| 367 | /* MC_CMD_FC_IN_DDR_TEST msgrequest */ | |
| 368 | #define MC_CMD_FC_IN_DDR_TEST_LEN 8 | |
| 369 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 370 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 371 | #define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 | |
| 372 | #define MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 | |
| 373 | #define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0 | |
| 374 | #define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8 | |
| 375 | /* enum: DRAM Test Start */ | |
| 376 | #define MC_CMD_FC_OP_DDR_TEST_START 0x1 | |
| 377 | /* enum: DRAM Test Poll */ | |
| 378 | #define MC_CMD_FC_OP_DDR_TEST_POLL 0x2 | |
| 379 | ||
| 380 | /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */ | |
| 381 | #define MC_CMD_FC_IN_DDR_TEST_START_LEN 12 | |
| 382 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 383 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 384 | /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ | |
| 385 | /* MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */ | |
| 386 | #define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8 | |
| 387 | #define MC_CMD_FC_IN_DDR_TEST_START_MASK_LEN 4 | |
| 388 | #define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0 | |
| 389 | #define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1 | |
| 390 | #define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1 | |
| 391 | #define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1 | |
| 392 | #define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2 | |
| 393 | #define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1 | |
| 394 | #define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3 | |
| 395 | #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 | |
| 396 | ||
| 397 | /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ | |
| 398 | #define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12 | |
| 399 | #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 | |
| 400 | #define MC_CMD_FC_IN_DDR_TEST_CMD_LEN 4 | |
| 401 | /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ | |
| 402 | /* MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */ | |
| 403 | /* Clear previous test result and prepare for restarting DDR test */ | |
| 404 | #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8 | |
| 405 | #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_LEN 4 | |
| 406 | ||
| 407 | /* MC_CMD_FC_IN_GET_ASSERT msgrequest */ | |
| 408 | #define MC_CMD_FC_IN_GET_ASSERT_LEN 4 | |
| 409 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 410 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 411 | ||
| 412 | /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */ | |
| 413 | #define MC_CMD_FC_IN_FPGA_BUILD_LEN 8 | |
| 414 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 415 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 416 | /* FPGA build info operation code */ | |
| 417 | #define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4 | |
| 418 | #define MC_CMD_FC_IN_FPGA_BUILD_OP_LEN 4 | |
| 419 | /* enum: Get the build registers */ | |
| 420 | #define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 | |
| 421 | /* enum: Get the services registers */ | |
| 422 | #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 | |
| 423 | /* enum: Get the BSP version */ | |
| 424 | #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 | |
| 425 | /* enum: Get build register for V2 (SFA974X) */ | |
| 426 | #define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4 | |
| 427 | /* enum: GEt the services register for V2 (SFA974X) */ | |
| 428 | #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5 | |
| 429 | ||
| 430 | /* MC_CMD_FC_IN_READ_MAP msgrequest */ | |
| 431 | #define MC_CMD_FC_IN_READ_MAP_LEN 8 | |
| 432 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 433 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 434 | #define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 | |
| 435 | #define MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 | |
| 436 | #define MC_CMD_FC_IN_READ_MAP_OP_LBN 0 | |
| 437 | #define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8 | |
| 438 | /* enum: Get the number of map regions */ | |
| 439 | #define MC_CMD_FC_OP_READ_MAP_COUNT 0x1 | |
| 440 | /* enum: Get the specified map */ | |
| 441 | #define MC_CMD_FC_OP_READ_MAP_INDEX 0x2 | |
| 442 | ||
| 443 | /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */ | |
| 444 | #define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8 | |
| 445 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 446 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 447 | /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ | |
| 448 | /* MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */ | |
| 449 | ||
| 450 | /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */ | |
| 451 | #define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12 | |
| 452 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 453 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 454 | /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ | |
| 455 | /* MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */ | |
| 456 | #define MC_CMD_FC_IN_MAP_INDEX_OFST 8 | |
| 457 | #define MC_CMD_FC_IN_MAP_INDEX_LEN 4 | |
| 458 | ||
| 459 | /* MC_CMD_FC_IN_CAPABILITIES msgrequest */ | |
| 460 | #define MC_CMD_FC_IN_CAPABILITIES_LEN 4 | |
| 461 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 462 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 463 | ||
| 464 | /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */ | |
| 465 | #define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8 | |
| 466 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 467 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 468 | #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4 | |
| 469 | #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_LEN 4 | |
| 470 | #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0 | |
| 471 | #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1 | |
| 472 | #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1 | |
| 473 | #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1 | |
| 474 | #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2 | |
| 475 | #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1 | |
| 476 | #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3 | |
| 477 | #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1 | |
| 478 | #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4 | |
| 479 | #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1 | |
| 480 | #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5 | |
| 481 | #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1 | |
| 482 | ||
| 483 | /* MC_CMD_FC_IN_IO_REL msgrequest */ | |
| 484 | #define MC_CMD_FC_IN_IO_REL_LEN 8 | |
| 485 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 486 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 487 | #define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 | |
| 488 | #define MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 | |
| 489 | #define MC_CMD_FC_IN_IO_REL_OP_LBN 0 | |
| 490 | #define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8 | |
| 491 | /* enum: Get the base address that the FC applies to relative commands */ | |
| 492 | #define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 | |
| 493 | /* enum: Read data */ | |
| 494 | #define MC_CMD_FC_IN_IO_REL_READ32 0x2 | |
| 495 | /* enum: Write data */ | |
| 496 | #define MC_CMD_FC_IN_IO_REL_WRITE32 0x3 | |
| 497 | #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8 | |
| 498 | #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8 | |
| 499 | /* enum: Application address space */ | |
| 500 | #define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 | |
| 501 | /* enum: Flash address space */ | |
| 502 | #define MC_CMD_FC_COMP_TYPE_FLASH 0x2 | |
| 503 | ||
| 504 | /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */ | |
| 505 | #define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8 | |
| 506 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 507 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 508 | /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ | |
| 509 | /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ | |
| 510 | ||
| 511 | /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */ | |
| 512 | #define MC_CMD_FC_IN_IO_REL_READ32_LEN 20 | |
| 513 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 514 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 515 | /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ | |
| 516 | /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ | |
| 517 | #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8 | |
| 518 | #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_LEN 4 | |
| 519 | #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12 | |
| 520 | #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_LEN 4 | |
| 521 | #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16 | |
| 522 | #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_LEN 4 | |
| 523 | ||
| 524 | /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */ | |
| 525 | #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20 | |
| 526 | #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252 | |
| 9f95a23c | 527 | #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX_MCDI2 1020 |
| 11fdf7f2 | 528 | #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num)) |
| f67539c2 | 529 | #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_NUM(len) (((len)-16)/4) |
| 11fdf7f2 TL |
530 | /* MC_CMD_FC_IN_CMD_OFST 0 */ |
| 531 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 532 | /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ | |
| 533 | /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ | |
| 534 | #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8 | |
| 535 | #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_LEN 4 | |
| 536 | #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12 | |
| 537 | #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_LEN 4 | |
| 538 | #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16 | |
| 539 | #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4 | |
| 540 | #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1 | |
| 541 | #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59 | |
| 9f95a23c | 542 | #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM_MCDI2 251 |
| 11fdf7f2 TL |
543 | |
| 544 | /* MC_CMD_FC_IN_UHLINK msgrequest */ | |
| 545 | #define MC_CMD_FC_IN_UHLINK_LEN 8 | |
| 546 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 547 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 548 | #define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 | |
| 549 | #define MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 | |
| 550 | #define MC_CMD_FC_IN_UHLINK_OP_LBN 0 | |
| 551 | #define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8 | |
| 552 | /* enum: Get PHY configuration info */ | |
| 553 | #define MC_CMD_FC_OP_UHLINK_PHY 0x1 | |
| 554 | /* enum: Get MAC configuration info */ | |
| 555 | #define MC_CMD_FC_OP_UHLINK_MAC 0x2 | |
| 556 | /* enum: Get Rx eye table */ | |
| 557 | #define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 | |
| 558 | /* enum: Get Rx eye plot */ | |
| 559 | #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 | |
| 560 | /* enum: Get Rx eye plot */ | |
| 561 | #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 | |
| 562 | /* enum: Retune Rx settings */ | |
| 563 | #define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 | |
| 564 | /* enum: Set loopback mode on fpga port */ | |
| 565 | #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 | |
| 566 | /* enum: Get loopback mode config state on fpga port */ | |
| 567 | #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 | |
| 568 | #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8 | |
| 569 | #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8 | |
| 570 | #define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16 | |
| 571 | #define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8 | |
| 572 | #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24 | |
| 573 | #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8 | |
| 574 | /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are | |
| 575 | * irrelevant. Port number is derived from pci_fn; passed in FC header. | |
| 576 | */ | |
| 577 | #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 | |
| 578 | /* enum: Override default port number. Port number determined by fields | |
| 579 | * PORT_TYPE and PORT_IDX. | |
| 580 | */ | |
| 581 | #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 | |
| 582 | ||
| 583 | /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */ | |
| 584 | #define MC_CMD_FC_OP_UHLINK_PHY_LEN 8 | |
| 585 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 586 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 587 | /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ | |
| 588 | /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ | |
| 589 | ||
| 590 | /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */ | |
| 591 | #define MC_CMD_FC_OP_UHLINK_MAC_LEN 8 | |
| 592 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 593 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 594 | /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ | |
| 595 | /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ | |
| 596 | ||
| 597 | /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */ | |
| 598 | #define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12 | |
| 599 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 600 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 601 | /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ | |
| 602 | /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ | |
| 603 | #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8 | |
| 604 | #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_LEN 4 | |
| 605 | #define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */ | |
| 606 | ||
| 607 | /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */ | |
| 608 | #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8 | |
| 609 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 610 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 611 | /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ | |
| 612 | /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ | |
| 613 | ||
| 614 | /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */ | |
| 615 | #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20 | |
| 616 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 617 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 618 | /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ | |
| 619 | /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ | |
| 620 | #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8 | |
| 621 | #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_LEN 4 | |
| 622 | #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12 | |
| 623 | #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_LEN 4 | |
| 624 | #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16 | |
| 625 | #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_LEN 4 | |
| 626 | #define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */ | |
| 627 | ||
| 628 | /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */ | |
| 629 | #define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8 | |
| 630 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 631 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 632 | /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ | |
| 633 | /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ | |
| 634 | ||
| 635 | /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */ | |
| 636 | #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16 | |
| 637 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 638 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 639 | /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ | |
| 640 | /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ | |
| 641 | #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8 | |
| 642 | #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_LEN 4 | |
| 643 | #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */ | |
| 644 | #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */ | |
| 645 | #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */ | |
| 646 | #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12 | |
| 647 | #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_LEN 4 | |
| 648 | #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */ | |
| 649 | #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */ | |
| 650 | ||
| 651 | /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */ | |
| 652 | #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12 | |
| 653 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 654 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 655 | /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ | |
| 656 | /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ | |
| 657 | #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8 | |
| 658 | #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_LEN 4 | |
| 659 | ||
| 660 | /* MC_CMD_FC_IN_SET_LINK msgrequest */ | |
| 661 | #define MC_CMD_FC_IN_SET_LINK_LEN 16 | |
| 662 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 663 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 664 | /* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ | |
| 665 | #define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4 | |
| 666 | #define MC_CMD_FC_IN_SET_LINK_MODE_LEN 4 | |
| 667 | #define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8 | |
| 668 | #define MC_CMD_FC_IN_SET_LINK_SPEED_LEN 4 | |
| 669 | #define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12 | |
| 670 | #define MC_CMD_FC_IN_SET_LINK_FLAGS_LEN 4 | |
| 671 | #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0 | |
| 672 | #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1 | |
| 673 | #define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1 | |
| 674 | #define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1 | |
| 675 | #define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2 | |
| 676 | #define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1 | |
| 677 | ||
| 678 | /* MC_CMD_FC_IN_LICENSE msgrequest */ | |
| 679 | #define MC_CMD_FC_IN_LICENSE_LEN 8 | |
| 680 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 681 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 682 | #define MC_CMD_FC_IN_LICENSE_OP_OFST 4 | |
| 683 | #define MC_CMD_FC_IN_LICENSE_OP_LEN 4 | |
| 684 | #define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */ | |
| 685 | #define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */ | |
| 686 | ||
| 687 | /* MC_CMD_FC_IN_STARTUP msgrequest */ | |
| 688 | #define MC_CMD_FC_IN_STARTUP_LEN 40 | |
| 689 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 690 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 691 | #define MC_CMD_FC_IN_STARTUP_BASE_OFST 4 | |
| 692 | #define MC_CMD_FC_IN_STARTUP_BASE_LEN 4 | |
| 693 | #define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8 | |
| 694 | #define MC_CMD_FC_IN_STARTUP_LENGTH_LEN 4 | |
| 695 | /* Length of identifier */ | |
| 696 | #define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12 | |
| 697 | #define MC_CMD_FC_IN_STARTUP_IDLENGTH_LEN 4 | |
| 698 | /* Identifier for AOE FPGA */ | |
| 699 | #define MC_CMD_FC_IN_STARTUP_ID_OFST 16 | |
| 700 | #define MC_CMD_FC_IN_STARTUP_ID_LEN 1 | |
| 701 | #define MC_CMD_FC_IN_STARTUP_ID_NUM 24 | |
| 702 | ||
| 703 | /* MC_CMD_FC_IN_DMA msgrequest */ | |
| 704 | #define MC_CMD_FC_IN_DMA_LEN 8 | |
| 705 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 706 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 707 | #define MC_CMD_FC_IN_DMA_OP_OFST 4 | |
| 708 | #define MC_CMD_FC_IN_DMA_OP_LEN 4 | |
| 709 | #define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */ | |
| 710 | #define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */ | |
| 711 | ||
| 712 | /* MC_CMD_FC_IN_DMA_STOP msgrequest */ | |
| 713 | #define MC_CMD_FC_IN_DMA_STOP_LEN 12 | |
| 714 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 715 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 716 | /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ | |
| 717 | /* MC_CMD_FC_IN_DMA_OP_LEN 4 */ | |
| 718 | /* FC supplied handle */ | |
| 719 | #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8 | |
| 720 | #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_LEN 4 | |
| 721 | ||
| 722 | /* MC_CMD_FC_IN_DMA_READ msgrequest */ | |
| 723 | #define MC_CMD_FC_IN_DMA_READ_LEN 16 | |
| 724 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 725 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 726 | /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ | |
| 727 | /* MC_CMD_FC_IN_DMA_OP_LEN 4 */ | |
| 728 | #define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8 | |
| 729 | #define MC_CMD_FC_IN_DMA_READ_OFFSET_LEN 4 | |
| 730 | #define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12 | |
| 731 | #define MC_CMD_FC_IN_DMA_READ_LENGTH_LEN 4 | |
| 732 | ||
| 733 | /* MC_CMD_FC_IN_TIMED_READ msgrequest */ | |
| 734 | #define MC_CMD_FC_IN_TIMED_READ_LEN 8 | |
| 735 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 736 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 737 | #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 | |
| 738 | #define MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 | |
| 739 | #define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */ | |
| 740 | #define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */ | |
| 741 | #define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */ | |
| 742 | ||
| 743 | /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */ | |
| 744 | #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52 | |
| 745 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 746 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 747 | /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ | |
| 748 | /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ | |
| 749 | /* Host supplied handle (unique) */ | |
| 750 | #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8 | |
| 751 | #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_LEN 4 | |
| 752 | /* Address into which to transfer data in host */ | |
| 753 | #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12 | |
| 754 | #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8 | |
| 755 | #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12 | |
| 756 | #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16 | |
| 757 | /* AOE address from which to transfer data */ | |
| 758 | #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20 | |
| 759 | #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8 | |
| 760 | #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20 | |
| 761 | #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24 | |
| 762 | /* Length of AOE transfer (total) */ | |
| 763 | #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28 | |
| 764 | #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_LEN 4 | |
| 765 | /* Length of host transfer (total) */ | |
| 766 | #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32 | |
| 767 | #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_LEN 4 | |
| 768 | /* Offset back from aoe_address to apply operation to */ | |
| 769 | #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36 | |
| 770 | #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_LEN 4 | |
| 771 | /* Data to apply at offset */ | |
| 772 | #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40 | |
| 773 | #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_LEN 4 | |
| 774 | #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44 | |
| 775 | #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_LEN 4 | |
| 776 | #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0 | |
| 777 | #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1 | |
| 778 | #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1 | |
| 779 | #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1 | |
| 780 | #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2 | |
| 781 | #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1 | |
| 782 | #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3 | |
| 783 | #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2 | |
| 784 | #define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */ | |
| 785 | #define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */ | |
| 786 | #define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */ | |
| 787 | #define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */ | |
| 788 | /* Period at which reads are performed (100ms units) */ | |
| 789 | #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48 | |
| 790 | #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_LEN 4 | |
| 791 | ||
| 792 | /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */ | |
| 793 | #define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12 | |
| 794 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 795 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 796 | /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ | |
| 797 | /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ | |
| 798 | /* FC supplied handle */ | |
| 799 | #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8 | |
| 800 | #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_LEN 4 | |
| 801 | ||
| 802 | /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */ | |
| 803 | #define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12 | |
| 804 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 805 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 806 | /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ | |
| 807 | /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ | |
| 808 | /* FC supplied handle */ | |
| 809 | #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8 | |
| 810 | #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_LEN 4 | |
| 811 | ||
| 812 | /* MC_CMD_FC_IN_LOG msgrequest */ | |
| 813 | #define MC_CMD_FC_IN_LOG_LEN 8 | |
| 814 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 815 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 816 | #define MC_CMD_FC_IN_LOG_OP_OFST 4 | |
| 817 | #define MC_CMD_FC_IN_LOG_OP_LEN 4 | |
| 818 | #define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */ | |
| 819 | #define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */ | |
| 820 | ||
| 821 | /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */ | |
| 822 | #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20 | |
| 823 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 824 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 825 | /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ | |
| 826 | /* MC_CMD_FC_IN_LOG_OP_LEN 4 */ | |
| 827 | /* Partition offset into flash */ | |
| 828 | #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8 | |
| 829 | #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_LEN 4 | |
| 830 | /* Partition length */ | |
| 831 | #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12 | |
| 832 | #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_LEN 4 | |
| 833 | /* Partition erase size */ | |
| 834 | #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16 | |
| 835 | #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_LEN 4 | |
| 836 | ||
| 837 | /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */ | |
| 838 | #define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12 | |
| 839 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 840 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 841 | /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ | |
| 842 | /* MC_CMD_FC_IN_LOG_OP_LEN 4 */ | |
| 843 | /* Enable/disable printing to JTAG UART */ | |
| 844 | #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8 | |
| 845 | #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_LEN 4 | |
| 846 | ||
| 847 | /* MC_CMD_FC_IN_CLOCK msgrequest: Perform a clock operation */ | |
| 848 | #define MC_CMD_FC_IN_CLOCK_LEN 12 | |
| 849 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 850 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 851 | #define MC_CMD_FC_IN_CLOCK_OP_OFST 4 | |
| 852 | #define MC_CMD_FC_IN_CLOCK_OP_LEN 4 | |
| 853 | #define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */ | |
| 854 | #define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */ | |
| 855 | #define MC_CMD_FC_IN_CLOCK_ID_OFST 8 | |
| 856 | #define MC_CMD_FC_IN_CLOCK_ID_LEN 4 | |
| 857 | #define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */ | |
| 858 | #define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */ | |
| 859 | ||
| 860 | /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest: Retrieve the clock value of the | |
| 861 | * specified clock | |
| 862 | */ | |
| 863 | #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12 | |
| 864 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 865 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 866 | /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ | |
| 867 | /* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */ | |
| 868 | /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ | |
| 869 | /* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */ | |
| 870 | ||
| 871 | /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest: Set the clock value of the specified | |
| 872 | * clock | |
| 873 | */ | |
| 874 | #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24 | |
| 875 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 876 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 877 | /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ | |
| 878 | /* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */ | |
| 879 | /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ | |
| 880 | /* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */ | |
| 881 | #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12 | |
| 882 | #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8 | |
| 883 | #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12 | |
| 884 | #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16 | |
| 885 | #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20 | |
| 886 | #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4 | |
| 887 | ||
| 888 | /* MC_CMD_FC_IN_DDR msgrequest */ | |
| 889 | #define MC_CMD_FC_IN_DDR_LEN 12 | |
| 890 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 891 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 892 | #define MC_CMD_FC_IN_DDR_OP_OFST 4 | |
| 893 | #define MC_CMD_FC_IN_DDR_OP_LEN 4 | |
| 894 | #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ | |
| 895 | #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ | |
| 896 | #define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */ | |
| 897 | #define MC_CMD_FC_IN_DDR_BANK_OFST 8 | |
| 898 | #define MC_CMD_FC_IN_DDR_BANK_LEN 4 | |
| 899 | #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ | |
| 900 | #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ | |
| 901 | #define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */ | |
| 902 | #define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */ | |
| 903 | #define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */ | |
| 904 | ||
| 905 | /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */ | |
| 906 | #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148 | |
| 907 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 908 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 909 | /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ | |
| 910 | /* MC_CMD_FC_IN_DDR_OP_LEN 4 */ | |
| 911 | /* Affected bank */ | |
| 912 | /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ | |
| 913 | /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ | |
| 914 | /* Flags */ | |
| 915 | #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12 | |
| 916 | #define MC_CMD_FC_IN_DDR_FLAGS_LEN 4 | |
| 917 | #define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */ | |
| 918 | /* 128-byte page of serial presence detect data read from module's EEPROM */ | |
| 919 | #define MC_CMD_FC_IN_DDR_SPD_OFST 16 | |
| 920 | #define MC_CMD_FC_IN_DDR_SPD_LEN 1 | |
| 921 | #define MC_CMD_FC_IN_DDR_SPD_NUM 128 | |
| 922 | /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */ | |
| 923 | #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 | |
| 924 | #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_LEN 4 | |
| 925 | ||
| 926 | /* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */ | |
| 927 | #define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16 | |
| 928 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 929 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 930 | /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ | |
| 931 | /* MC_CMD_FC_IN_DDR_OP_LEN 4 */ | |
| 932 | /* Affected bank */ | |
| 933 | /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ | |
| 934 | /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ | |
| 935 | /* Size of DDR */ | |
| 936 | #define MC_CMD_FC_IN_DDR_SIZE_OFST 12 | |
| 937 | #define MC_CMD_FC_IN_DDR_SIZE_LEN 4 | |
| 938 | ||
| 939 | /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ | |
| 940 | #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 | |
| 941 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 942 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 943 | /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ | |
| 944 | /* MC_CMD_FC_IN_DDR_OP_LEN 4 */ | |
| 945 | /* Affected bank */ | |
| 946 | /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ | |
| 947 | /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ | |
| 948 | ||
| 949 | /* MC_CMD_FC_IN_TIMESTAMP msgrequest */ | |
| 950 | #define MC_CMD_FC_IN_TIMESTAMP_LEN 8 | |
| 951 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 952 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 953 | /* FC timestamp operation code */ | |
| 954 | #define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4 | |
| 955 | #define MC_CMD_FC_IN_TIMESTAMP_OP_LEN 4 | |
| 956 | /* enum: Read transmit timestamp(s) */ | |
| 957 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 | |
| 958 | /* enum: Read snapshot timestamps */ | |
| 959 | #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 | |
| 960 | /* enum: Clear all transmit timestamps */ | |
| 961 | #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 | |
| 962 | ||
| 963 | /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */ | |
| 964 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28 | |
| 965 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 966 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 967 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4 | |
| 968 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_LEN 4 | |
| 969 | /* Control filtering of the returned timestamp and sequence number specified | |
| 970 | * here | |
| 971 | */ | |
| 972 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8 | |
| 973 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_LEN 4 | |
| 974 | /* enum: Return most recent timestamp. No filtering */ | |
| 975 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 | |
| 976 | /* enum: Match timestamp against the PTP clock ID, port number and sequence | |
| 977 | * number specified | |
| 978 | */ | |
| 979 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 | |
| 980 | /* Clock identity of PTP packet for which timestamp required */ | |
| 981 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12 | |
| 982 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8 | |
| 983 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12 | |
| 984 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16 | |
| 985 | /* Port number of PTP packet for which timestamp required */ | |
| 986 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20 | |
| 987 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_LEN 4 | |
| 988 | /* Sequence number of PTP packet for which timestamp required */ | |
| 989 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24 | |
| 990 | #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_LEN 4 | |
| 991 | ||
| 992 | /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */ | |
| 993 | #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8 | |
| 994 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 995 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 996 | #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4 | |
| 997 | #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_LEN 4 | |
| 998 | ||
| 999 | /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */ | |
| 1000 | #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8 | |
| 1001 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1002 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1003 | #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4 | |
| 1004 | #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_LEN 4 | |
| 1005 | ||
| 1006 | /* MC_CMD_FC_IN_SPI msgrequest */ | |
| 1007 | #define MC_CMD_FC_IN_SPI_LEN 8 | |
| 1008 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1009 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1010 | /* Basic commands for SPI Flash. */ | |
| 1011 | #define MC_CMD_FC_IN_SPI_OP_OFST 4 | |
| 1012 | #define MC_CMD_FC_IN_SPI_OP_LEN 4 | |
| 1013 | /* enum: SPI Flash read */ | |
| 1014 | #define MC_CMD_FC_IN_SPI_READ 0x0 | |
| 1015 | /* enum: SPI Flash write */ | |
| 1016 | #define MC_CMD_FC_IN_SPI_WRITE 0x1 | |
| 1017 | /* enum: SPI Flash erase */ | |
| 1018 | #define MC_CMD_FC_IN_SPI_ERASE 0x2 | |
| 1019 | ||
| 1020 | /* MC_CMD_FC_IN_SPI_READ msgrequest */ | |
| 1021 | #define MC_CMD_FC_IN_SPI_READ_LEN 16 | |
| 1022 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1023 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1024 | #define MC_CMD_FC_IN_SPI_READ_OP_OFST 4 | |
| 1025 | #define MC_CMD_FC_IN_SPI_READ_OP_LEN 4 | |
| 1026 | #define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8 | |
| 1027 | #define MC_CMD_FC_IN_SPI_READ_ADDR_LEN 4 | |
| 1028 | #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12 | |
| 1029 | #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_LEN 4 | |
| 1030 | ||
| 1031 | /* MC_CMD_FC_IN_SPI_WRITE msgrequest */ | |
| 1032 | #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16 | |
| 1033 | #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252 | |
| 9f95a23c | 1034 | #define MC_CMD_FC_IN_SPI_WRITE_LENMAX_MCDI2 1020 |
| 11fdf7f2 | 1035 | #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num)) |
| f67539c2 | 1036 | #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_NUM(len) (((len)-12)/4) |
| 11fdf7f2 TL |
1037 | /* MC_CMD_FC_IN_CMD_OFST 0 */ |
| 1038 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1039 | #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4 | |
| 1040 | #define MC_CMD_FC_IN_SPI_WRITE_OP_LEN 4 | |
| 1041 | #define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8 | |
| 1042 | #define MC_CMD_FC_IN_SPI_WRITE_ADDR_LEN 4 | |
| 1043 | #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12 | |
| 1044 | #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4 | |
| 1045 | #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1 | |
| 1046 | #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60 | |
| 9f95a23c | 1047 | #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM_MCDI2 252 |
| 11fdf7f2 TL |
1048 | |
| 1049 | /* MC_CMD_FC_IN_SPI_ERASE msgrequest */ | |
| 1050 | #define MC_CMD_FC_IN_SPI_ERASE_LEN 16 | |
| 1051 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1052 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1053 | #define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4 | |
| 1054 | #define MC_CMD_FC_IN_SPI_ERASE_OP_LEN 4 | |
| 1055 | #define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8 | |
| 1056 | #define MC_CMD_FC_IN_SPI_ERASE_ADDR_LEN 4 | |
| 1057 | #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12 | |
| 1058 | #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_LEN 4 | |
| 1059 | ||
| 1060 | /* MC_CMD_FC_IN_DIAG msgrequest */ | |
| 1061 | #define MC_CMD_FC_IN_DIAG_LEN 8 | |
| 1062 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1063 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1064 | /* Operation code indicating component type */ | |
| 1065 | #define MC_CMD_FC_IN_DIAG_OP_OFST 4 | |
| 1066 | #define MC_CMD_FC_IN_DIAG_OP_LEN 4 | |
| 1067 | /* enum: Power noise generator. */ | |
| 1068 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 | |
| 1069 | /* enum: DDR soak test component. */ | |
| 1070 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 | |
| 1071 | /* enum: Diagnostics datapath control component. */ | |
| 1072 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 | |
| 1073 | ||
| 1074 | /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */ | |
| 1075 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12 | |
| 1076 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1077 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1078 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4 | |
| 1079 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_LEN 4 | |
| 1080 | /* Sub-opcode describing the operation to be carried out */ | |
| 1081 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8 | |
| 1082 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_LEN 4 | |
| 1083 | /* enum: Read the configuration (the 32-bit values in each of the clock enable | |
| 1084 | * count and toggle count registers) | |
| 1085 | */ | |
| 1086 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 | |
| 1087 | /* enum: Write a new configuration to the clock enable count and toggle count | |
| 1088 | * registers | |
| 1089 | */ | |
| 1090 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 | |
| 1091 | ||
| 1092 | /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */ | |
| 1093 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12 | |
| 1094 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1095 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1096 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4 | |
| 1097 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_LEN 4 | |
| 1098 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8 | |
| 1099 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_LEN 4 | |
| 1100 | ||
| 1101 | /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */ | |
| 1102 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20 | |
| 1103 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1104 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1105 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4 | |
| 1106 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_LEN 4 | |
| 1107 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8 | |
| 1108 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_LEN 4 | |
| 1109 | /* The 32-bit value to be written to the toggle count register */ | |
| 1110 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12 | |
| 1111 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_LEN 4 | |
| 1112 | /* The 32-bit value to be written to the clock enable count register */ | |
| 1113 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16 | |
| 1114 | #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_LEN 4 | |
| 1115 | ||
| 1116 | /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */ | |
| 1117 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12 | |
| 1118 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1119 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1120 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4 | |
| 1121 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_LEN 4 | |
| 1122 | /* Sub-opcode describing the operation to be carried out */ | |
| 1123 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8 | |
| 1124 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_LEN 4 | |
| 1125 | /* enum: Starts DDR soak test on selected banks */ | |
| 1126 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 | |
| 1127 | /* enum: Read status of DDR soak test */ | |
| 1128 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 | |
| 1129 | /* enum: Stop test */ | |
| 1130 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 | |
| 1131 | /* enum: Set or clear bit that triggers fake errors. These cause subsequent | |
| 1132 | * tests to fail until the bit is cleared. | |
| 1133 | */ | |
| 1134 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 | |
| 1135 | ||
| 1136 | /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */ | |
| 1137 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24 | |
| 1138 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1139 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1140 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4 | |
| 1141 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_LEN 4 | |
| 1142 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8 | |
| 1143 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_LEN 4 | |
| 1144 | /* Mask of DDR banks to be tested */ | |
| 1145 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12 | |
| 1146 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_LEN 4 | |
| 1147 | /* Pattern to use in the soak test */ | |
| 1148 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16 | |
| 1149 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_LEN 4 | |
| 1150 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */ | |
| 1151 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */ | |
| 1152 | /* Either multiple automatic tests until a STOP command is issued, or one | |
| 1153 | * single test | |
| 1154 | */ | |
| 1155 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20 | |
| 1156 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_LEN 4 | |
| 1157 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */ | |
| 1158 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */ | |
| 1159 | ||
| 1160 | /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */ | |
| 1161 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16 | |
| 1162 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1163 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1164 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4 | |
| 1165 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_LEN 4 | |
| 1166 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8 | |
| 1167 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_LEN 4 | |
| 1168 | /* DDR bank to read status from */ | |
| 1169 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12 | |
| 1170 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_LEN 4 | |
| 1171 | #define MC_CMD_FC_DDR_BANK0 0x0 /* enum */ | |
| 1172 | #define MC_CMD_FC_DDR_BANK1 0x1 /* enum */ | |
| 1173 | #define MC_CMD_FC_DDR_BANK2 0x2 /* enum */ | |
| 1174 | #define MC_CMD_FC_DDR_BANK3 0x3 /* enum */ | |
| 1175 | #define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */ | |
| 1176 | ||
| 1177 | /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */ | |
| 1178 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16 | |
| 1179 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1180 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1181 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4 | |
| 1182 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_LEN 4 | |
| 1183 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8 | |
| 1184 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_LEN 4 | |
| 1185 | /* Mask of DDR banks to be tested */ | |
| 1186 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12 | |
| 1187 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_LEN 4 | |
| 1188 | ||
| 1189 | /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */ | |
| 1190 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20 | |
| 1191 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1192 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1193 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4 | |
| 1194 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_LEN 4 | |
| 1195 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8 | |
| 1196 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_LEN 4 | |
| 1197 | /* Mask of DDR banks to set/clear error flag on */ | |
| 1198 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12 | |
| 1199 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_LEN 4 | |
| 1200 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16 | |
| 1201 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_LEN 4 | |
| 1202 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */ | |
| 1203 | #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */ | |
| 1204 | ||
| 1205 | /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */ | |
| 1206 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12 | |
| 1207 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1208 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1209 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4 | |
| 1210 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_LEN 4 | |
| 1211 | /* Sub-opcode describing the operation to be carried out */ | |
| 1212 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8 | |
| 1213 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_LEN 4 | |
| 1214 | /* enum: Set a known datapath configuration */ | |
| 1215 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 | |
| 1216 | /* enum: Apply raw config to datapath control registers */ | |
| 1217 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 | |
| 1218 | ||
| 1219 | /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */ | |
| 1220 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16 | |
| 1221 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1222 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1223 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4 | |
| 1224 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_LEN 4 | |
| 1225 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8 | |
| 1226 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_LEN 4 | |
| 1227 | /* Datapath configuration identifier */ | |
| 1228 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12 | |
| 1229 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_LEN 4 | |
| 1230 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */ | |
| 1231 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */ | |
| 1232 | ||
| 1233 | /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */ | |
| 1234 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24 | |
| 1235 | /* MC_CMD_FC_IN_CMD_OFST 0 */ | |
| 1236 | /* MC_CMD_FC_IN_CMD_LEN 4 */ | |
| 1237 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4 | |
| 1238 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_LEN 4 | |
| 1239 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8 | |
| 1240 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_LEN 4 | |
| 1241 | /* Value to write into control register 1 */ | |
| 1242 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12 | |
| 1243 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_LEN 4 | |
| 1244 | /* Value to write into control register 2 */ | |
| 1245 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16 | |
| 1246 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_LEN 4 | |
| 1247 | /* Value to write into control register 3 */ | |
| 1248 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20 | |
| 1249 | #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_LEN 4 | |
| 1250 | ||
| 1251 | /* MC_CMD_FC_OUT msgresponse */ | |
| 1252 | #define MC_CMD_FC_OUT_LEN 0 | |
| 1253 | ||
| 1254 | /* MC_CMD_FC_OUT_NULL msgresponse */ | |
| 1255 | #define MC_CMD_FC_OUT_NULL_LEN 0 | |
| 1256 | ||
| 1257 | /* MC_CMD_FC_OUT_READ32 msgresponse */ | |
| 1258 | #define MC_CMD_FC_OUT_READ32_LENMIN 4 | |
| 1259 | #define MC_CMD_FC_OUT_READ32_LENMAX 252 | |
| 9f95a23c | 1260 | #define MC_CMD_FC_OUT_READ32_LENMAX_MCDI2 1020 |
| 11fdf7f2 | 1261 | #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num)) |
| f67539c2 | 1262 | #define MC_CMD_FC_OUT_READ32_BUFFER_NUM(len) (((len)-0)/4) |
| 11fdf7f2 TL |
1263 | #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0 |
| 1264 | #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4 | |
| 1265 | #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1 | |
| 1266 | #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63 | |
| 9f95a23c | 1267 | #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM_MCDI2 255 |
| 11fdf7f2 TL |
1268 | |
| 1269 | /* MC_CMD_FC_OUT_WRITE32 msgresponse */ | |
| 1270 | #define MC_CMD_FC_OUT_WRITE32_LEN 0 | |
| 1271 | ||
| 1272 | /* MC_CMD_FC_OUT_TRC_READ msgresponse */ | |
| 1273 | #define MC_CMD_FC_OUT_TRC_READ_LEN 16 | |
| 1274 | #define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0 | |
| 1275 | #define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4 | |
| 1276 | #define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4 | |
| 1277 | ||
| 1278 | /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */ | |
| 1279 | #define MC_CMD_FC_OUT_TRC_WRITE_LEN 0 | |
| 1280 | ||
| 1281 | /* MC_CMD_FC_OUT_GET_VERSION msgresponse */ | |
| 1282 | #define MC_CMD_FC_OUT_GET_VERSION_LEN 12 | |
| 1283 | #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0 | |
| 1284 | #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_LEN 4 | |
| 1285 | #define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4 | |
| 1286 | #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8 | |
| 1287 | #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4 | |
| 1288 | #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8 | |
| 1289 | ||
| 1290 | /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */ | |
| 1291 | #define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8 | |
| 1292 | #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0 | |
| 1293 | #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4 | |
| 1294 | #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2 | |
| 1295 | ||
| 1296 | /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */ | |
| 1297 | #define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0 | |
| 1298 | ||
| 1299 | /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */ | |
| 1300 | #define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0 | |
| 1301 | ||
| 1302 | /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */ | |
| 1303 | #define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0 | |
| 1304 | ||
| 1305 | /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */ | |
| 1306 | #define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4 | |
| 1307 | #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0 | |
| 1308 | #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_LEN 4 | |
| 1309 | ||
| 1310 | /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */ | |
| 1311 | #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3) | |
| 1312 | #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0 | |
| 1313 | #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8 | |
| 1314 | #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0 | |
| 1315 | #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4 | |
| 1316 | #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS | |
| 1317 | #define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */ | |
| 1318 | #define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */ | |
| 1319 | #define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */ | |
| 1320 | #define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ | |
| 1321 | #define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */ | |
| 1322 | #define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */ | |
| 1323 | #define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */ | |
| 1324 | #define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */ | |
| 1325 | #define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */ | |
| 1326 | #define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */ | |
| 1327 | #define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */ | |
| 1328 | #define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */ | |
| 1329 | #define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */ | |
| 1330 | #define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */ | |
| 1331 | #define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */ | |
| 1332 | #define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */ | |
| 1333 | #define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */ | |
| 1334 | #define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */ | |
| 1335 | #define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */ | |
| 1336 | #define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */ | |
| 1337 | #define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */ | |
| 1338 | #define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */ | |
| 1339 | #define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */ | |
| 1340 | #define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */ | |
| 1341 | #define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */ | |
| 1342 | /* enum: (Last entry) */ | |
| 1343 | #define MC_CMD_FC_MAC_RX_NSTATS 0x19 | |
| 1344 | ||
| 1345 | /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */ | |
| 1346 | #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3) | |
| 1347 | #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0 | |
| 1348 | #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8 | |
| 1349 | #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0 | |
| 1350 | #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4 | |
| 1351 | #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS | |
| 1352 | #define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */ | |
| 1353 | #define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */ | |
| 1354 | #define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */ | |
| 1355 | #define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ | |
| 1356 | #define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */ | |
| 1357 | #define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */ | |
| 1358 | #define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */ | |
| 1359 | #define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */ | |
| 1360 | #define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */ | |
| 1361 | #define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */ | |
| 1362 | #define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */ | |
| 1363 | #define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */ | |
| 1364 | #define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */ | |
| 1365 | #define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */ | |
| 1366 | #define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */ | |
| 1367 | #define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */ | |
| 1368 | #define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */ | |
| 1369 | #define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */ | |
| 1370 | #define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */ | |
| 1371 | #define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */ | |
| 1372 | #define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */ | |
| 1373 | #define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */ | |
| 1374 | /* enum: (Last entry) */ | |
| 1375 | #define MC_CMD_FC_MAC_TX_NSTATS 0x16 | |
| 1376 | ||
| 1377 | /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */ | |
| 1378 | #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3) | |
| 1379 | /* MAC Statistics */ | |
| 1380 | #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0 | |
| 1381 | #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8 | |
| 1382 | #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0 | |
| 1383 | #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4 | |
| 1384 | #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK | |
| 1385 | ||
| 1386 | /* MC_CMD_FC_OUT_MAC msgresponse */ | |
| 1387 | #define MC_CMD_FC_OUT_MAC_LEN 0 | |
| 1388 | ||
| 1389 | /* MC_CMD_FC_OUT_SFP msgresponse */ | |
| 1390 | #define MC_CMD_FC_OUT_SFP_LEN 0 | |
| 1391 | ||
| 1392 | /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */ | |
| 1393 | #define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0 | |
| 1394 | ||
| 1395 | /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */ | |
| 1396 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8 | |
| 1397 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0 | |
| 1398 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_LEN 4 | |
| 1399 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0 | |
| 1400 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8 | |
| 1401 | /* enum: Test not yet initiated */ | |
| 1402 | #define MC_CMD_FC_OP_DDR_TEST_NONE 0x0 | |
| 1403 | /* enum: Test is in progress */ | |
| 1404 | #define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 | |
| 1405 | /* enum: Timed completed */ | |
| 1406 | #define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 | |
| 1407 | /* enum: Test did not complete in specified time */ | |
| 1408 | #define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 | |
| 1409 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11 | |
| 1410 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1 | |
| 1411 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10 | |
| 1412 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1 | |
| 1413 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9 | |
| 1414 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1 | |
| 1415 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8 | |
| 1416 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1 | |
| 1417 | /* Test result from FPGA */ | |
| 1418 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4 | |
| 1419 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_LEN 4 | |
| 1420 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31 | |
| 1421 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1 | |
| 1422 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30 | |
| 1423 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1 | |
| 1424 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29 | |
| 1425 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1 | |
| 1426 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28 | |
| 1427 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1 | |
| 1428 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15 | |
| 1429 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5 | |
| 1430 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10 | |
| 1431 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5 | |
| 1432 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5 | |
| 1433 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5 | |
| 1434 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0 | |
| 1435 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5 | |
| 1436 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */ | |
| 1437 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */ | |
| 1438 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */ | |
| 1439 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */ | |
| 1440 | #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */ | |
| 1441 | ||
| 1442 | /* MC_CMD_FC_OUT_DDR_TEST msgresponse */ | |
| 1443 | #define MC_CMD_FC_OUT_DDR_TEST_LEN 0 | |
| 1444 | ||
| 1445 | /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */ | |
| 1446 | #define MC_CMD_FC_OUT_GET_ASSERT_LEN 144 | |
| 1447 | /* Assertion status flag. */ | |
| 1448 | #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0 | |
| 1449 | #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_LEN 4 | |
| 1450 | #define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8 | |
| 1451 | #define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8 | |
| 1452 | /* enum: No crash data available */ | |
| 1453 | #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 | |
| 1454 | /* enum: New crash data available */ | |
| 1455 | #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 | |
| 1456 | /* enum: Crash data has been sent */ | |
| 1457 | #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 | |
| 1458 | #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0 | |
| 1459 | #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8 | |
| 1460 | /* enum: No crash has been recorded. */ | |
| 1461 | #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 | |
| 1462 | /* enum: Crash due to exception. */ | |
| 1463 | #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 | |
| 1464 | /* enum: Crash due to assertion. */ | |
| 1465 | #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 | |
| 1466 | /* Failing PC value */ | |
| 1467 | #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4 | |
| 1468 | #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_LEN 4 | |
| 1469 | /* Saved GP regs */ | |
| 1470 | #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8 | |
| 1471 | #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4 | |
| 1472 | #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31 | |
| 1473 | /* Exception Type */ | |
| 1474 | #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132 | |
| 1475 | #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_LEN 4 | |
| 1476 | /* Instruction at which exception occurred */ | |
| 1477 | #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136 | |
| 1478 | #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_LEN 4 | |
| 1479 | /* BAD Address that triggered address-based exception */ | |
| 1480 | #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140 | |
| 1481 | #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_LEN 4 | |
| 1482 | ||
| 1483 | /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */ | |
| 1484 | #define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32 | |
| 1485 | #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0 | |
| 1486 | #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_LEN 4 | |
| 1487 | #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31 | |
| 1488 | #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1 | |
| 1489 | #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30 | |
| 1490 | #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1 | |
| 1491 | #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16 | |
| 1492 | #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14 | |
| 1493 | #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12 | |
| 1494 | #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4 | |
| 1495 | #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4 | |
| 1496 | #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8 | |
| 1497 | #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0 | |
| 1498 | #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4 | |
| 1499 | /* Build timestamp (seconds since epoch) */ | |
| 1500 | #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4 | |
| 1501 | #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_LEN 4 | |
| 1502 | #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8 | |
| 1503 | #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_LEN 4 | |
| 1504 | #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0 | |
| 1505 | #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8 | |
| 1506 | #define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */ | |
| 1507 | #define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */ | |
| 1508 | #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8 | |
| 1509 | #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10 | |
| 1510 | #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18 | |
| 1511 | #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1 | |
| 1512 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19 | |
| 1513 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1 | |
| 1514 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20 | |
| 1515 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1 | |
| 1516 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21 | |
| 1517 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1 | |
| 1518 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22 | |
| 1519 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1 | |
| 1520 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23 | |
| 1521 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1 | |
| 1522 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24 | |
| 1523 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1 | |
| 1524 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25 | |
| 1525 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1 | |
| 1526 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26 | |
| 1527 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1 | |
| 1528 | #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27 | |
| 1529 | #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1 | |
| 1530 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28 | |
| 1531 | #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1 | |
| 1532 | #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29 | |
| 1533 | #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2 | |
| 1534 | #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31 | |
| 1535 | #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1 | |
| 1536 | #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12 | |
| 1537 | #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_LEN 4 | |
| 1538 | #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0 | |
| 1539 | #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16 | |
| 1540 | #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16 | |
| 1541 | #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1 | |
| 1542 | #define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */ | |
| 1543 | #define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */ | |
| 1544 | #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17 | |
| 1545 | #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15 | |
| 1546 | #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16 | |
| 1547 | #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_LEN 4 | |
| 1548 | #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0 | |
| 1549 | #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16 | |
| 1550 | #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16 | |
| 1551 | #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 | |
| 1552 | #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20 | |
| 1553 | #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_LEN 4 | |
| 1554 | #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0 | |
| 1555 | #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16 | |
| 1556 | #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16 | |
| 1557 | #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16 | |
| 1558 | #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16 | |
| 1559 | #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8 | |
| 1560 | #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16 | |
| 1561 | #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20 | |
| 1562 | #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24 | |
| 1563 | #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_LEN 4 | |
| 1564 | #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28 | |
| 1565 | #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_LEN 4 | |
| 1566 | #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 | |
| 1567 | #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 | |
| 1568 | ||
| 1569 | /* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */ | |
| 1570 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32 | |
| 1571 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0 | |
| 1572 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_LEN 4 | |
| 1573 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31 | |
| 1574 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1 | |
| 1575 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30 | |
| 1576 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1 | |
| 1577 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16 | |
| 1578 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14 | |
| 1579 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12 | |
| 1580 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4 | |
| 1581 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4 | |
| 1582 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8 | |
| 1583 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0 | |
| 1584 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4 | |
| 1585 | /* Build timestamp (seconds since epoch) */ | |
| 1586 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4 | |
| 1587 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_LEN 4 | |
| 1588 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8 | |
| 1589 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_LEN 4 | |
| 1590 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31 | |
| 1591 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1 | |
| 1592 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29 | |
| 1593 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1 | |
| 1594 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28 | |
| 1595 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1 | |
| 1596 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27 | |
| 1597 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1 | |
| 1598 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26 | |
| 1599 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1 | |
| 1600 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25 | |
| 1601 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1 | |
| 1602 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24 | |
| 1603 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1 | |
| 1604 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23 | |
| 1605 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1 | |
| 1606 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22 | |
| 1607 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1 | |
| 1608 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21 | |
| 1609 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1 | |
| 1610 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20 | |
| 1611 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1 | |
| 1612 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19 | |
| 1613 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1 | |
| 1614 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18 | |
| 1615 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1 | |
| 1616 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */ | |
| 1617 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */ | |
| 1618 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17 | |
| 1619 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1 | |
| 1620 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */ | |
| 1621 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */ | |
| 1622 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16 | |
| 1623 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1 | |
| 1624 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */ | |
| 1625 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */ | |
| 1626 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15 | |
| 1627 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1 | |
| 1628 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14 | |
| 1629 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1 | |
| 1630 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13 | |
| 1631 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1 | |
| 1632 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12 | |
| 1633 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1 | |
| 1634 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11 | |
| 1635 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1 | |
| 1636 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10 | |
| 1637 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1 | |
| 1638 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9 | |
| 1639 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1 | |
| 1640 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8 | |
| 1641 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1 | |
| 1642 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7 | |
| 1643 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1 | |
| 1644 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6 | |
| 1645 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1 | |
| 1646 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5 | |
| 1647 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1 | |
| 1648 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4 | |
| 1649 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1 | |
| 1650 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0 | |
| 1651 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4 | |
| 1652 | #define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */ | |
| 1653 | #define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */ | |
| 1654 | #define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */ | |
| 1655 | #define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */ | |
| 1656 | #define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */ | |
| 1657 | #define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */ | |
| 1658 | #define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */ | |
| 1659 | #define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */ | |
| 1660 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12 | |
| 1661 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_LEN 4 | |
| 1662 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0 | |
| 1663 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16 | |
| 1664 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16 | |
| 1665 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1 | |
| 1666 | /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ | |
| 1667 | /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ | |
| 1668 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16 | |
| 1669 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_LEN 4 | |
| 1670 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0 | |
| 1671 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16 | |
| 1672 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16 | |
| 1673 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 | |
| 1674 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20 | |
| 1675 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_LEN 4 | |
| 1676 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0 | |
| 1677 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16 | |
| 1678 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16 | |
| 1679 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16 | |
| 1680 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24 | |
| 1681 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_LEN 4 | |
| 1682 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28 | |
| 1683 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_LEN 4 | |
| 1684 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0 | |
| 1685 | #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16 | |
| 1686 | ||
| 1687 | /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ | |
| 1688 | #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 | |
| 1689 | #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 | |
| 1690 | #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_LEN 4 | |
| 1691 | #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31 | |
| 1692 | #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1 | |
| 1693 | #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30 | |
| 1694 | #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1 | |
| 1695 | #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16 | |
| 1696 | #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14 | |
| 1697 | #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12 | |
| 1698 | #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4 | |
| 1699 | #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4 | |
| 1700 | #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8 | |
| 1701 | #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0 | |
| 1702 | #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4 | |
| 1703 | /* Build timestamp (seconds since epoch) */ | |
| 1704 | #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4 | |
| 1705 | #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_LEN 4 | |
| 1706 | #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8 | |
| 1707 | #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_LEN 4 | |
| 1708 | #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8 | |
| 1709 | #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1 | |
| 1710 | #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27 | |
| 1711 | #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1 | |
| 1712 | #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28 | |
| 1713 | #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1 | |
| 1714 | #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29 | |
| 1715 | #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1 | |
| 1716 | #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30 | |
| 1717 | #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1 | |
| 1718 | #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31 | |
| 1719 | #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1 | |
| 1720 | #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12 | |
| 1721 | #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_LEN 4 | |
| 1722 | #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0 | |
| 1723 | #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16 | |
| 1724 | #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16 | |
| 1725 | #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1 | |
| 1726 | #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16 | |
| 1727 | #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_LEN 4 | |
| 1728 | #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0 | |
| 1729 | #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16 | |
| 1730 | #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16 | |
| 1731 | #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16 | |
| 1732 | #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20 | |
| 1733 | #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_LEN 4 | |
| 1734 | #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0 | |
| 1735 | #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16 | |
| 1736 | #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16 | |
| 1737 | #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16 | |
| 1738 | #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24 | |
| 1739 | #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_LEN 4 | |
| 1740 | #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28 | |
| 1741 | #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_LEN 4 | |
| 1742 | #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 | |
| 1743 | #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 | |
| 1744 | ||
| 1745 | /* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */ | |
| 1746 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32 | |
| 1747 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0 | |
| 1748 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_LEN 4 | |
| 1749 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31 | |
| 1750 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1 | |
| 1751 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30 | |
| 1752 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1 | |
| 1753 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16 | |
| 1754 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14 | |
| 1755 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12 | |
| 1756 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4 | |
| 1757 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4 | |
| 1758 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8 | |
| 1759 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0 | |
| 1760 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4 | |
| 1761 | /* Build timestamp (seconds since epoch) */ | |
| 1762 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4 | |
| 1763 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_LEN 4 | |
| 1764 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8 | |
| 1765 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_LEN 4 | |
| 1766 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0 | |
| 1767 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1 | |
| 1768 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8 | |
| 1769 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1 | |
| 1770 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12 | |
| 1771 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_LEN 4 | |
| 1772 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0 | |
| 1773 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16 | |
| 1774 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16 | |
| 1775 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1 | |
| 1776 | /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ | |
| 1777 | /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ | |
| 1778 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24 | |
| 1779 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_LEN 4 | |
| 1780 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28 | |
| 1781 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_LEN 4 | |
| 1782 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0 | |
| 1783 | #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16 | |
| 1784 | ||
| 1785 | /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ | |
| 1786 | #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 | |
| 1787 | /* Qsys system ID */ | |
| 1788 | #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0 | |
| 1789 | #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_LEN 4 | |
| 1790 | #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12 | |
| 1791 | #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4 | |
| 1792 | #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4 | |
| 1793 | #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8 | |
| 1794 | #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0 | |
| 1795 | #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4 | |
| 1796 | ||
| 1797 | /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */ | |
| 1798 | #define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4 | |
| 1799 | /* Number of maps */ | |
| 1800 | #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0 | |
| 1801 | #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_LEN 4 | |
| 1802 | ||
| 1803 | /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */ | |
| 1804 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164 | |
| 1805 | /* Index of the map */ | |
| 1806 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0 | |
| 1807 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_LEN 4 | |
| 1808 | /* Options for the map */ | |
| 1809 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4 | |
| 1810 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_LEN 4 | |
| 1811 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */ | |
| 1812 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */ | |
| 1813 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */ | |
| 1814 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */ | |
| 1815 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */ | |
| 1816 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */ | |
| 1817 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */ | |
| 1818 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */ | |
| 1819 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */ | |
| 1820 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */ | |
| 1821 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */ | |
| 1822 | /* Address of start of map */ | |
| 1823 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8 | |
| 1824 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8 | |
| 1825 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8 | |
| 1826 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12 | |
| 1827 | /* Length of address map */ | |
| 1828 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16 | |
| 1829 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8 | |
| 1830 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16 | |
| 1831 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20 | |
| 1832 | /* Component information field */ | |
| 1833 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24 | |
| 1834 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_LEN 4 | |
| 1835 | /* License expiry data for map */ | |
| 1836 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28 | |
| 1837 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8 | |
| 1838 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28 | |
| 1839 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32 | |
| 1840 | /* Name of the component */ | |
| 1841 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36 | |
| 1842 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1 | |
| 1843 | #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128 | |
| 1844 | ||
| 1845 | /* MC_CMD_FC_OUT_READ_MAP msgresponse */ | |
| 1846 | #define MC_CMD_FC_OUT_READ_MAP_LEN 0 | |
| 1847 | ||
| 1848 | /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */ | |
| 1849 | #define MC_CMD_FC_OUT_CAPABILITIES_LEN 8 | |
| 1850 | /* Number of internal ports */ | |
| 1851 | #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0 | |
| 1852 | #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_LEN 4 | |
| 1853 | /* Number of external ports */ | |
| 1854 | #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4 | |
| 1855 | #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_LEN 4 | |
| 1856 | ||
| 1857 | /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */ | |
| 1858 | #define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4 | |
| 1859 | #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0 | |
| 1860 | #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_LEN 4 | |
| 1861 | ||
| 1862 | /* MC_CMD_FC_OUT_IO_REL msgresponse */ | |
| 1863 | #define MC_CMD_FC_OUT_IO_REL_LEN 0 | |
| 1864 | ||
| 1865 | /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */ | |
| 1866 | #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8 | |
| 1867 | #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0 | |
| 1868 | #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_LEN 4 | |
| 1869 | #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4 | |
| 1870 | #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_LEN 4 | |
| 1871 | ||
| 1872 | /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */ | |
| 1873 | #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4 | |
| 1874 | #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252 | |
| 9f95a23c | 1875 | #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX_MCDI2 1020 |
| 11fdf7f2 | 1876 | #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num)) |
| f67539c2 | 1877 | #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_NUM(len) (((len)-0)/4) |
| 11fdf7f2 TL |
1878 | #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0 |
| 1879 | #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4 | |
| 1880 | #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1 | |
| 1881 | #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63 | |
| 9f95a23c | 1882 | #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM_MCDI2 255 |
| 11fdf7f2 TL |
1883 | |
| 1884 | /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */ | |
| 1885 | #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0 | |
| 1886 | ||
| 1887 | /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */ | |
| 1888 | #define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48 | |
| 1889 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0 | |
| 1890 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_LEN 4 | |
| 1891 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0 | |
| 1892 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16 | |
| 1893 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16 | |
| 1894 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16 | |
| 1895 | /* Transceiver Transmit settings */ | |
| 1896 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4 | |
| 1897 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_LEN 4 | |
| 1898 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0 | |
| 1899 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16 | |
| 1900 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16 | |
| 1901 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16 | |
| 1902 | /* Transceiver Receive settings */ | |
| 1903 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8 | |
| 1904 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_LEN 4 | |
| 1905 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0 | |
| 1906 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16 | |
| 1907 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16 | |
| 1908 | #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16 | |
| 1909 | /* Rx eye opening */ | |
| 1910 | #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12 | |
| 1911 | #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_LEN 4 | |
| 1912 | #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0 | |
| 1913 | #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16 | |
| 1914 | #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16 | |
| 1915 | #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16 | |
| 1916 | /* PCS status word */ | |
| 1917 | #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16 | |
| 1918 | #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_LEN 4 | |
| 1919 | /* Link status word */ | |
| 1920 | #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20 | |
| 1921 | #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_LEN 4 | |
| 1922 | #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0 | |
| 1923 | #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1 | |
| 1924 | #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1 | |
| 1925 | #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1 | |
| 1926 | /* Current SFp parameters applied */ | |
| 1927 | #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24 | |
| 1928 | #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20 | |
| 1929 | /* Link speed is 100, 1000, 10000 */ | |
| 1930 | #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24 | |
| 1931 | #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_LEN 4 | |
| 1932 | /* Length of copper cable - zero when not relevant */ | |
| 1933 | #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28 | |
| 1934 | #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_LEN 4 | |
| 1935 | /* True if a dual speed SFP+ module */ | |
| 1936 | #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32 | |
| 1937 | #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_LEN 4 | |
| 1938 | /* True if an SFP Module is present (other fields valid when true) */ | |
| 1939 | #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36 | |
| 1940 | #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_LEN 4 | |
| 1941 | /* The type of the SFP+ Module */ | |
| 1942 | #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40 | |
| 1943 | #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_LEN 4 | |
| 1944 | /* PHY config flags */ | |
| 1945 | #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44 | |
| 1946 | #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_LEN 4 | |
| 1947 | #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0 | |
| 1948 | #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1 | |
| 1949 | #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1 | |
| 1950 | #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1 | |
| 1951 | #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2 | |
| 1952 | #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1 | |
| 1953 | ||
| 1954 | /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */ | |
| 1955 | #define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20 | |
| 1956 | /* MAC configuration applied */ | |
| 1957 | #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0 | |
| 1958 | #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_LEN 4 | |
| 1959 | /* MTU size */ | |
| 1960 | #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4 | |
| 1961 | #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_LEN 4 | |
| 1962 | /* IF Mode status */ | |
| 1963 | #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8 | |
| 1964 | #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_LEN 4 | |
| 1965 | /* MAC address configured */ | |
| 1966 | #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12 | |
| 1967 | #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8 | |
| 1968 | #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12 | |
| 1969 | #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16 | |
| 1970 | ||
| 1971 | /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */ | |
| 1972 | #define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3) | |
| 1973 | /* Rx Eye measurements */ | |
| 1974 | #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0 | |
| 1975 | #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4 | |
| 1976 | #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK | |
| 1977 | ||
| 1978 | /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */ | |
| 1979 | #define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0 | |
| 1980 | ||
| 1981 | /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */ | |
| 1982 | #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3) | |
| 1983 | /* Has the eye plot dump completed and data returned is valid? */ | |
| 1984 | #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0 | |
| 1985 | #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_LEN 4 | |
| 1986 | /* Rx Eye binary plot */ | |
| 1987 | #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4 | |
| 1988 | #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8 | |
| 1989 | #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4 | |
| 1990 | #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8 | |
| 1991 | #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK | |
| 1992 | ||
| 1993 | /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */ | |
| 1994 | #define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0 | |
| 1995 | ||
| 1996 | /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */ | |
| 1997 | #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0 | |
| 1998 | ||
| 1999 | /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */ | |
| 2000 | #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4 | |
| 2001 | #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0 | |
| 2002 | #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_LEN 4 | |
| 2003 | ||
| 2004 | /* MC_CMD_FC_OUT_UHLINK msgresponse */ | |
| 2005 | #define MC_CMD_FC_OUT_UHLINK_LEN 0 | |
| 2006 | ||
| 2007 | /* MC_CMD_FC_OUT_SET_LINK msgresponse */ | |
| 2008 | #define MC_CMD_FC_OUT_SET_LINK_LEN 0 | |
| 2009 | ||
| 2010 | /* MC_CMD_FC_OUT_LICENSE msgresponse */ | |
| 2011 | #define MC_CMD_FC_OUT_LICENSE_LEN 12 | |
| 2012 | /* Count of valid keys */ | |
| 2013 | #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0 | |
| 2014 | #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_LEN 4 | |
| 2015 | /* Count of invalid keys */ | |
| 2016 | #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4 | |
| 2017 | #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_LEN 4 | |
| 2018 | /* Count of blacklisted keys */ | |
| 2019 | #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8 | |
| 2020 | #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_LEN 4 | |
| 2021 | ||
| 2022 | /* MC_CMD_FC_OUT_STARTUP msgresponse */ | |
| 2023 | #define MC_CMD_FC_OUT_STARTUP_LEN 4 | |
| 2024 | /* Capabilities of the FPGA/FC */ | |
| 2025 | #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0 | |
| 2026 | #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_LEN 4 | |
| 2027 | #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0 | |
| 2028 | #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1 | |
| 2029 | ||
| 2030 | /* MC_CMD_FC_OUT_DMA_READ msgresponse */ | |
| 2031 | #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1 | |
| 2032 | #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252 | |
| 9f95a23c | 2033 | #define MC_CMD_FC_OUT_DMA_READ_LENMAX_MCDI2 1020 |
| 11fdf7f2 | 2034 | #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num)) |
| f67539c2 | 2035 | #define MC_CMD_FC_OUT_DMA_READ_DATA_NUM(len) (((len)-0)/1) |
| 11fdf7f2 TL |
2036 | /* The data read */ |
| 2037 | #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0 | |
| 2038 | #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1 | |
| 2039 | #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1 | |
| 2040 | #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252 | |
| 9f95a23c | 2041 | #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM_MCDI2 1020 |
| 11fdf7f2 TL |
2042 | |
| 2043 | /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */ | |
| 2044 | #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4 | |
| 2045 | /* Timer handle */ | |
| 2046 | #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0 | |
| 2047 | #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_LEN 4 | |
| 2048 | ||
| 2049 | /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */ | |
| 2050 | #define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52 | |
| 2051 | /* Host supplied handle (unique) */ | |
| 2052 | #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0 | |
| 2053 | #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_LEN 4 | |
| 2054 | /* Address into which to transfer data in host */ | |
| 2055 | #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4 | |
| 2056 | #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8 | |
| 2057 | #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4 | |
| 2058 | #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8 | |
| 2059 | /* AOE address from which to transfer data */ | |
| 2060 | #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12 | |
| 2061 | #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8 | |
| 2062 | #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12 | |
| 2063 | #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16 | |
| 2064 | /* Length of AOE transfer (total) */ | |
| 2065 | #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20 | |
| 2066 | #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_LEN 4 | |
| 2067 | /* Length of host transfer (total) */ | |
| 2068 | #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24 | |
| 2069 | #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_LEN 4 | |
| 2070 | /* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */ | |
| 2071 | #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28 | |
| 2072 | #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_LEN 4 | |
| 2073 | #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32 | |
| 2074 | #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_LEN 4 | |
| 2075 | /* When active, start read time */ | |
| 2076 | #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36 | |
| 2077 | #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8 | |
| 2078 | #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36 | |
| 2079 | #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40 | |
| 2080 | /* When active, end read time */ | |
| 2081 | #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44 | |
| 2082 | #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8 | |
| 2083 | #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44 | |
| 2084 | #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48 | |
| 2085 | ||
| 2086 | /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */ | |
| 2087 | #define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0 | |
| 2088 | ||
| 2089 | /* MC_CMD_FC_OUT_LOG msgresponse */ | |
| 2090 | #define MC_CMD_FC_OUT_LOG_LEN 0 | |
| 2091 | ||
| 2092 | /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */ | |
| 2093 | #define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24 | |
| 2094 | #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0 | |
| 2095 | #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_LEN 4 | |
| 2096 | #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4 | |
| 2097 | #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8 | |
| 2098 | #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4 | |
| 2099 | #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8 | |
| 2100 | #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12 | |
| 2101 | #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_LEN 4 | |
| 2102 | #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16 | |
| 2103 | #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_LEN 4 | |
| 2104 | #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20 | |
| 2105 | #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_LEN 4 | |
| 2106 | ||
| 2107 | /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */ | |
| 2108 | #define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0 | |
| 2109 | ||
| 2110 | /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ | |
| 2111 | #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 | |
| 2112 | ||
| 2113 | /* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */ | |
| 2114 | #define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0 | |
| 2115 | ||
| 2116 | /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ | |
| 2117 | #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 | |
| 2118 | #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 | |
| 2119 | #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_LEN 4 | |
| 2120 | #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0 | |
| 2121 | #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1 | |
| 2122 | #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1 | |
| 2123 | #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1 | |
| 2124 | ||
| 2125 | /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */ | |
| 2126 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8 | |
| 2127 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0 | |
| 2128 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_LEN 4 | |
| 2129 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4 | |
| 2130 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_LEN 4 | |
| 2131 | ||
| 2132 | /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */ | |
| 2133 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8 | |
| 2134 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248 | |
| 9f95a23c | 2135 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX_MCDI2 1016 |
| 11fdf7f2 | 2136 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num)) |
| f67539c2 | 2137 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_NUM(len) (((len)-0)/8) |
| 11fdf7f2 TL |
2138 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0 |
| 2139 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_LEN 4 | |
| 2140 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4 | |
| 2141 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_LEN 4 | |
| 2142 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0 | |
| 2143 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8 | |
| 2144 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0 | |
| 2145 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4 | |
| 2146 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0 | |
| 2147 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31 | |
| 9f95a23c | 2148 | #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM_MCDI2 127 |
| 11fdf7f2 TL |
2149 | |
| 2150 | /* MC_CMD_FC_OUT_SPI_READ msgresponse */ | |
| 2151 | #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4 | |
| 2152 | #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252 | |
| 9f95a23c | 2153 | #define MC_CMD_FC_OUT_SPI_READ_LENMAX_MCDI2 1020 |
| 11fdf7f2 | 2154 | #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num)) |
| f67539c2 | 2155 | #define MC_CMD_FC_OUT_SPI_READ_BUFFER_NUM(len) (((len)-0)/4) |
| 11fdf7f2 TL |
2156 | #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0 |
| 2157 | #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4 | |
| 2158 | #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1 | |
| 2159 | #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63 | |
| 9f95a23c | 2160 | #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM_MCDI2 255 |
| 11fdf7f2 TL |
2161 | |
| 2162 | /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */ | |
| 2163 | #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0 | |
| 2164 | ||
| 2165 | /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */ | |
| 2166 | #define MC_CMD_FC_OUT_SPI_ERASE_LEN 0 | |
| 2167 | ||
| 2168 | /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */ | |
| 2169 | #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8 | |
| 2170 | /* The 32-bit value read from the toggle count register */ | |
| 2171 | #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0 | |
| 2172 | #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_LEN 4 | |
| 2173 | /* The 32-bit value read from the clock enable count register */ | |
| 2174 | #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4 | |
| 2175 | #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_LEN 4 | |
| 2176 | ||
| 2177 | /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */ | |
| 2178 | #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0 | |
| 2179 | ||
| 2180 | /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */ | |
| 2181 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0 | |
| 2182 | ||
| 2183 | /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */ | |
| 2184 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8 | |
| 2185 | /* DDR soak test status word; bits [4:0] are relevant. */ | |
| 2186 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0 | |
| 2187 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_LEN 4 | |
| 2188 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0 | |
| 2189 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1 | |
| 2190 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1 | |
| 2191 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1 | |
| 2192 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2 | |
| 2193 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1 | |
| 2194 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3 | |
| 2195 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1 | |
| 2196 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4 | |
| 2197 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1 | |
| 2198 | /* DDR soak test error count */ | |
| 2199 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4 | |
| 2200 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_LEN 4 | |
| 2201 | ||
| 2202 | /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */ | |
| 2203 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0 | |
| 2204 | ||
| 2205 | /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */ | |
| 2206 | #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0 | |
| 2207 | ||
| 2208 | /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */ | |
| 2209 | #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0 | |
| 2210 | ||
| 2211 | /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */ | |
| 2212 | #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0 | |
| 2213 | ||
| 2214 | ||
| 2215 | /***********************************/ | |
| 2216 | /* MC_CMD_AOE | |
| 2217 | * AOE operations on MC | |
| 2218 | */ | |
| 2219 | #define MC_CMD_AOE 0xa | |
| 2220 | ||
| 2221 | /* MC_CMD_AOE_IN msgrequest */ | |
| 2222 | #define MC_CMD_AOE_IN_LEN 4 | |
| 2223 | #define MC_CMD_AOE_IN_OP_HDR_OFST 0 | |
| 2224 | #define MC_CMD_AOE_IN_OP_HDR_LEN 4 | |
| 2225 | #define MC_CMD_AOE_IN_OP_LBN 0 | |
| 2226 | #define MC_CMD_AOE_IN_OP_WIDTH 8 | |
| 2227 | /* enum: FPGA and CPLD information */ | |
| 2228 | #define MC_CMD_AOE_OP_INFO 0x1 | |
| 2229 | /* enum: Currents and voltages read from MCP3424s; DEBUG */ | |
| 2230 | #define MC_CMD_AOE_OP_CURRENTS 0x2 | |
| 2231 | /* enum: Temperatures at locations around the PCB; DEBUG */ | |
| 2232 | #define MC_CMD_AOE_OP_TEMPERATURES 0x3 | |
| 2233 | /* enum: Set CPLD to idle */ | |
| 2234 | #define MC_CMD_AOE_OP_CPLD_IDLE 0x4 | |
| 2235 | /* enum: Read from CPLD register */ | |
| 2236 | #define MC_CMD_AOE_OP_CPLD_READ 0x5 | |
| 2237 | /* enum: Write to CPLD register */ | |
| 2238 | #define MC_CMD_AOE_OP_CPLD_WRITE 0x6 | |
| 2239 | /* enum: Execute CPLD instruction */ | |
| 2240 | #define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 | |
| 2241 | /* enum: Reprogram the CPLD on the AOE device */ | |
| 2242 | #define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 | |
| 2243 | /* enum: AOE power control */ | |
| 2244 | #define MC_CMD_AOE_OP_POWER 0x9 | |
| 2245 | /* enum: AOE image loading */ | |
| 2246 | #define MC_CMD_AOE_OP_LOAD 0xa | |
| 2247 | /* enum: Fan monitoring */ | |
| 2248 | #define MC_CMD_AOE_OP_FAN_CONTROL 0xb | |
| 2249 | /* enum: Fan failures since last reset */ | |
| 2250 | #define MC_CMD_AOE_OP_FAN_FAILURES 0xc | |
| 2251 | /* enum: Get generic AOE MAC statistics */ | |
| 2252 | #define MC_CMD_AOE_OP_MAC_STATS 0xd | |
| 2253 | /* enum: Retrieve PHY specific information */ | |
| 2254 | #define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe | |
| 2255 | /* enum: Write a number of JTAG primitive commands, return will give data */ | |
| 2256 | #define MC_CMD_AOE_OP_JTAG_WRITE 0xf | |
| 2257 | /* enum: Control access to the FPGA via the Siena JTAG Chain */ | |
| 2258 | #define MC_CMD_AOE_OP_FPGA_ACCESS 0x10 | |
| 2259 | /* enum: Set the MTU offset between Siena and AOE MACs */ | |
| 2260 | #define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 | |
| 2261 | /* enum: How link state is handled */ | |
| 2262 | #define MC_CMD_AOE_OP_LINK_STATE 0x12 | |
| 2263 | /* enum: How Siena MAC statistics are reported (deprecated - use | |
| 2264 | * MC_CMD_AOE_OP_ASIC_STATS) | |
| 2265 | */ | |
| 2266 | #define MC_CMD_AOE_OP_SIENA_STATS 0x13 | |
| 2267 | /* enum: How native ASIC MAC statistics are reported - replaces the deprecated | |
| 2268 | * command MC_CMD_AOE_OP_SIENA_STATS | |
| 2269 | */ | |
| 2270 | #define MC_CMD_AOE_OP_ASIC_STATS 0x13 | |
| 2271 | /* enum: DDR memory information */ | |
| 2272 | #define MC_CMD_AOE_OP_DDR 0x14 | |
| 2273 | /* enum: FC control */ | |
| 2274 | #define MC_CMD_AOE_OP_FC 0x15 | |
| 2275 | /* enum: DDR ECC status reads */ | |
| 2276 | #define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 | |
| 2277 | /* enum: Commands for MC-SPI Master emulation */ | |
| 2278 | #define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 | |
| 2279 | /* enum: Commands for FC boot control */ | |
| 2280 | #define MC_CMD_AOE_OP_FC_BOOT 0x18 | |
| 2281 | /* enum: Get number of internal ports */ | |
| 2282 | #define MC_CMD_AOE_OP_GET_ASIC_PORTS 0x19 | |
| 2283 | /* enum: Get FC assert information and register dump */ | |
| 2284 | #define MC_CMD_AOE_OP_GET_FC_ASSERT_INFO 0x1a | |
| 9f95a23c TL |
2285 | /* enum: Set MUM startup FUSE byte with extended delay */ |
| 2286 | #define MC_CMD_AOE_OP_MUM_STARTUP_FUSE 0x1b | |
| 11fdf7f2 TL |
2287 | |
| 2288 | /* MC_CMD_AOE_OUT msgresponse */ | |
| 2289 | #define MC_CMD_AOE_OUT_LEN 0 | |
| 2290 | ||
| 2291 | /* MC_CMD_AOE_IN_INFO msgrequest */ | |
| 2292 | #define MC_CMD_AOE_IN_INFO_LEN 4 | |
| 2293 | #define MC_CMD_AOE_IN_CMD_OFST 0 | |
| 2294 | #define MC_CMD_AOE_IN_CMD_LEN 4 | |
| 2295 | ||
| 2296 | /* MC_CMD_AOE_IN_CURRENTS msgrequest */ | |
| 2297 | #define MC_CMD_AOE_IN_CURRENTS_LEN 4 | |
| 2298 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2299 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2300 | ||
| 2301 | /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */ | |
| 2302 | #define MC_CMD_AOE_IN_TEMPERATURES_LEN 4 | |
| 2303 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2304 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2305 | ||
| 2306 | /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */ | |
| 2307 | #define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4 | |
| 2308 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2309 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2310 | ||
| 2311 | /* MC_CMD_AOE_IN_CPLD_READ msgrequest */ | |
| 2312 | #define MC_CMD_AOE_IN_CPLD_READ_LEN 12 | |
| 2313 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2314 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2315 | #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4 | |
| 2316 | #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_LEN 4 | |
| 2317 | #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8 | |
| 2318 | #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_LEN 4 | |
| 2319 | ||
| 2320 | /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */ | |
| 2321 | #define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16 | |
| 2322 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2323 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2324 | #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4 | |
| 2325 | #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_LEN 4 | |
| 2326 | #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8 | |
| 2327 | #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_LEN 4 | |
| 2328 | #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12 | |
| 2329 | #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_LEN 4 | |
| 2330 | ||
| 2331 | /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */ | |
| 2332 | #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8 | |
| 2333 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2334 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2335 | #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4 | |
| 2336 | #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_LEN 4 | |
| 2337 | ||
| 2338 | /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */ | |
| 2339 | #define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8 | |
| 2340 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2341 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2342 | #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4 | |
| 2343 | #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_LEN 4 | |
| 2344 | /* enum: Reprogram CPLD, poll for completion */ | |
| 2345 | #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 | |
| 2346 | /* enum: Reprogram CPLD, send event on completion */ | |
| 2347 | #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 | |
| 2348 | /* enum: Get status of reprogramming operation */ | |
| 2349 | #define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 | |
| 2350 | ||
| 2351 | /* MC_CMD_AOE_IN_POWER msgrequest */ | |
| 2352 | #define MC_CMD_AOE_IN_POWER_LEN 8 | |
| 2353 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2354 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2355 | /* Turn on or off AOE power */ | |
| 2356 | #define MC_CMD_AOE_IN_POWER_OP_OFST 4 | |
| 2357 | #define MC_CMD_AOE_IN_POWER_OP_LEN 4 | |
| 2358 | /* enum: Turn off FPGA power */ | |
| 2359 | #define MC_CMD_AOE_IN_POWER_OFF 0x0 | |
| 2360 | /* enum: Turn on FPGA power */ | |
| 2361 | #define MC_CMD_AOE_IN_POWER_ON 0x1 | |
| 2362 | /* enum: Clear peak power measurement */ | |
| 2363 | #define MC_CMD_AOE_IN_POWER_CLEAR 0x2 | |
| 2364 | /* enum: Show current power in sensors output */ | |
| 2365 | #define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 | |
| 2366 | /* enum: Show peak power in sensors output */ | |
| 2367 | #define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 | |
| 2368 | /* enum: Show current DDR current */ | |
| 2369 | #define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 | |
| 2370 | /* enum: Show peak DDR current */ | |
| 2371 | #define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 | |
| 2372 | /* enum: Clear peak DDR current */ | |
| 2373 | #define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 | |
| 2374 | ||
| 2375 | /* MC_CMD_AOE_IN_LOAD msgrequest */ | |
| 2376 | #define MC_CMD_AOE_IN_LOAD_LEN 8 | |
| 2377 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2378 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2379 | /* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence | |
| 2380 | */ | |
| 2381 | #define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4 | |
| 2382 | #define MC_CMD_AOE_IN_LOAD_IMAGE_LEN 4 | |
| 2383 | ||
| 2384 | /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */ | |
| 2385 | #define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8 | |
| 2386 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2387 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2388 | /* If non zero report measured fan RPM rather than nominal */ | |
| 2389 | #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4 | |
| 2390 | #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_LEN 4 | |
| 2391 | ||
| 2392 | /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */ | |
| 2393 | #define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4 | |
| 2394 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2395 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2396 | ||
| 2397 | /* MC_CMD_AOE_IN_MAC_STATS msgrequest */ | |
| 2398 | #define MC_CMD_AOE_IN_MAC_STATS_LEN 24 | |
| 2399 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2400 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2401 | /* AOE port */ | |
| 2402 | #define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4 | |
| 2403 | #define MC_CMD_AOE_IN_MAC_STATS_PORT_LEN 4 | |
| 2404 | /* Host memory address for statistics */ | |
| 2405 | #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8 | |
| 2406 | #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8 | |
| 2407 | #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8 | |
| 2408 | #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12 | |
| 2409 | #define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16 | |
| 2410 | #define MC_CMD_AOE_IN_MAC_STATS_CMD_LEN 4 | |
| 2411 | #define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0 | |
| 2412 | #define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1 | |
| 2413 | #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1 | |
| 2414 | #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1 | |
| 2415 | #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2 | |
| 2416 | #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1 | |
| 2417 | #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3 | |
| 2418 | #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1 | |
| 2419 | #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4 | |
| 2420 | #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1 | |
| 2421 | #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5 | |
| 2422 | #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1 | |
| 2423 | #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16 | |
| 2424 | #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16 | |
| 2425 | /* Length of DMA data (optional) */ | |
| 2426 | #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20 | |
| 2427 | #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_LEN 4 | |
| 2428 | ||
| 2429 | /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */ | |
| 2430 | #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12 | |
| 2431 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2432 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2433 | /* AOE port */ | |
| 2434 | #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4 | |
| 2435 | #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_LEN 4 | |
| 2436 | #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8 | |
| 2437 | #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_LEN 4 | |
| 2438 | ||
| 2439 | /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */ | |
| 2440 | #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12 | |
| 2441 | #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252 | |
| 9f95a23c | 2442 | #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX_MCDI2 1020 |
| 11fdf7f2 | 2443 | #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num)) |
| f67539c2 | 2444 | #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_NUM(len) (((len)-8)/4) |
| 11fdf7f2 TL |
2445 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ |
| 2446 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2447 | #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4 | |
| 2448 | #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_LEN 4 | |
| 2449 | #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8 | |
| 2450 | #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4 | |
| 2451 | #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1 | |
| 2452 | #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61 | |
| 9f95a23c | 2453 | #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM_MCDI2 253 |
| 11fdf7f2 TL |
2454 | |
| 2455 | /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */ | |
| 2456 | #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8 | |
| 2457 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2458 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2459 | /* Enable or disable access */ | |
| 2460 | #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4 | |
| 2461 | #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_LEN 4 | |
| 2462 | /* enum: Enable access */ | |
| 2463 | #define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 | |
| 2464 | /* enum: Disable access */ | |
| 2465 | #define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 | |
| 2466 | ||
| 2467 | /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */ | |
| 2468 | #define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12 | |
| 2469 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2470 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2471 | /* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */ | |
| 2472 | #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4 | |
| 2473 | #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_LEN 4 | |
| 2474 | /* enum: Apply to all external ports */ | |
| 2475 | #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 | |
| 2476 | /* enum: Apply to all internal ports */ | |
| 2477 | #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 | |
| 2478 | /* The MTU offset to be applied to the external ports */ | |
| 2479 | #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8 | |
| 2480 | #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_LEN 4 | |
| 2481 | ||
| 2482 | /* MC_CMD_AOE_IN_LINK_STATE msgrequest */ | |
| 2483 | #define MC_CMD_AOE_IN_LINK_STATE_LEN 8 | |
| 2484 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2485 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2486 | #define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4 | |
| 2487 | #define MC_CMD_AOE_IN_LINK_STATE_MODE_LEN 4 | |
| 2488 | #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0 | |
| 2489 | #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8 | |
| 2490 | /* enum: AOE and associated external port */ | |
| 2491 | #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 | |
| 2492 | /* enum: AOE and OR of all external ports */ | |
| 2493 | #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 | |
| 2494 | /* enum: Individual ports */ | |
| 2495 | #define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 | |
| 2496 | /* enum: Configure link state mode on given AOE port */ | |
| 2497 | #define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 | |
| 2498 | #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8 | |
| 2499 | #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8 | |
| 2500 | /* enum: No-op */ | |
| 2501 | #define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 | |
| 2502 | /* enum: logical OR of all SFP ports link status */ | |
| 2503 | #define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 | |
| 2504 | /* enum: logical AND of all SFP ports link status */ | |
| 2505 | #define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 | |
| 2506 | #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16 | |
| 2507 | #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16 | |
| 2508 | ||
| 2509 | /* MC_CMD_AOE_IN_GET_ASIC_PORTS msgrequest */ | |
| 2510 | #define MC_CMD_AOE_IN_GET_ASIC_PORTS_LEN 4 | |
| 2511 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2512 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2513 | ||
| 2514 | /* MC_CMD_AOE_IN_GET_FC_ASSERT_INFO msgrequest */ | |
| 2515 | #define MC_CMD_AOE_IN_GET_FC_ASSERT_INFO_LEN 4 | |
| 2516 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2517 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2518 | ||
| 2519 | /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */ | |
| 2520 | #define MC_CMD_AOE_IN_SIENA_STATS_LEN 8 | |
| 2521 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2522 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2523 | /* How MAC statistics are reported */ | |
| 2524 | #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4 | |
| 2525 | #define MC_CMD_AOE_IN_SIENA_STATS_MODE_LEN 4 | |
| 2526 | /* enum: Statistics from Siena (default) */ | |
| 2527 | #define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 | |
| 2528 | /* enum: Statistics from AOE external ports */ | |
| 2529 | #define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 | |
| 2530 | ||
| 2531 | /* MC_CMD_AOE_IN_ASIC_STATS msgrequest */ | |
| 2532 | #define MC_CMD_AOE_IN_ASIC_STATS_LEN 8 | |
| 2533 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2534 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2535 | /* How MAC statistics are reported */ | |
| 2536 | #define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4 | |
| 2537 | #define MC_CMD_AOE_IN_ASIC_STATS_MODE_LEN 4 | |
| 2538 | /* enum: Statistics from the ASIC (default) */ | |
| 2539 | #define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0 | |
| 2540 | /* enum: Statistics from AOE external ports */ | |
| 2541 | #define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1 | |
| 2542 | ||
| 2543 | /* MC_CMD_AOE_IN_DDR msgrequest */ | |
| 2544 | #define MC_CMD_AOE_IN_DDR_LEN 12 | |
| 2545 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2546 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2547 | #define MC_CMD_AOE_IN_DDR_BANK_OFST 4 | |
| 2548 | #define MC_CMD_AOE_IN_DDR_BANK_LEN 4 | |
| 2549 | /* Enum values, see field(s): */ | |
| 2550 | /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ | |
| 2551 | /* Page index of SPD data */ | |
| 2552 | #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8 | |
| 2553 | #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_LEN 4 | |
| 2554 | ||
| 2555 | /* MC_CMD_AOE_IN_FC msgrequest */ | |
| 2556 | #define MC_CMD_AOE_IN_FC_LEN 4 | |
| 2557 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2558 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2559 | ||
| 2560 | /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */ | |
| 2561 | #define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8 | |
| 2562 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2563 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2564 | #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4 | |
| 2565 | #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_LEN 4 | |
| 2566 | /* Enum values, see field(s): */ | |
| 2567 | /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ | |
| 2568 | ||
| 2569 | /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */ | |
| 2570 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8 | |
| 2571 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2572 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2573 | /* Basic commands for MC SPI Master emulation. */ | |
| 2574 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4 | |
| 2575 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_LEN 4 | |
| 2576 | /* enum: MC SPI read */ | |
| 2577 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 | |
| 2578 | /* enum: MC SPI write */ | |
| 2579 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 | |
| 2580 | ||
| 2581 | /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */ | |
| 2582 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12 | |
| 2583 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2584 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2585 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4 | |
| 2586 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_LEN 4 | |
| 2587 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8 | |
| 2588 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_LEN 4 | |
| 2589 | ||
| 2590 | /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */ | |
| 2591 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16 | |
| 2592 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2593 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2594 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4 | |
| 2595 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_LEN 4 | |
| 2596 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8 | |
| 2597 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_LEN 4 | |
| 2598 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12 | |
| 2599 | #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_LEN 4 | |
| 2600 | ||
| 2601 | /* MC_CMD_AOE_IN_FC_BOOT msgrequest */ | |
| 2602 | #define MC_CMD_AOE_IN_FC_BOOT_LEN 8 | |
| 2603 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2604 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2605 | /* FC boot control flags */ | |
| 2606 | #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4 | |
| 2607 | #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_LEN 4 | |
| 2608 | #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0 | |
| 2609 | #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1 | |
| 2610 | ||
| 9f95a23c TL |
2611 | /* MC_CMD_AOE_IN_MUM_STARTUP_FUSE msgrequest: On AOE2, set MUM startup FUSE |
| 2612 | * byte with extended delay of 64ms. On some servers with noisy power rails, | |
| 2613 | * this ensures that the MUM IO pins do not show spurious transitions while the | |
| 2614 | * power rails are stabilising. Note that this operation requires a hard- | |
| 2615 | * powercycle to take effect. See bug76446. | |
| 2616 | */ | |
| 2617 | #define MC_CMD_AOE_IN_MUM_STARTUP_FUSE_LEN 4 | |
| 2618 | /* Must be MC_CMD_AOE_OP_MUM_STARTUP_FUSE */ | |
| 2619 | /* MC_CMD_AOE_IN_CMD_OFST 0 */ | |
| 2620 | /* MC_CMD_AOE_IN_CMD_LEN 4 */ | |
| 2621 | ||
| 11fdf7f2 TL |
2622 | /* MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO msgresponse */ |
| 2623 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_LEN 144 | |
| 2624 | /* Assertion status flag. */ | |
| 2625 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_OFST 0 | |
| 2626 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_LEN 4 | |
| 2627 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_LBN 8 | |
| 2628 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_WIDTH 8 | |
| 2629 | /* enum: No crash data available */ | |
| 2630 | /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 */ | |
| 2631 | /* enum: New crash data available */ | |
| 2632 | /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 */ | |
| 2633 | /* enum: Crash data has been sent */ | |
| 2634 | /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 */ | |
| 2635 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_LBN 0 | |
| 2636 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_WIDTH 8 | |
| 2637 | /* enum: No crash has been recorded. */ | |
| 2638 | /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 */ | |
| 2639 | /* enum: Crash due to exception. */ | |
| 2640 | /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 */ | |
| 2641 | /* enum: Crash due to assertion. */ | |
| 2642 | /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 */ | |
| 2643 | /* Failing PC value */ | |
| 2644 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_OFST 4 | |
| 2645 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_LEN 4 | |
| 2646 | /* Saved GP regs */ | |
| 2647 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_OFST 8 | |
| 2648 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_LEN 4 | |
| 2649 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_NUM 31 | |
| 2650 | /* Exception Type */ | |
| 2651 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_OFST 132 | |
| 2652 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_LEN 4 | |
| 2653 | /* Instruction at which exception occurred */ | |
| 2654 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_OFST 136 | |
| 2655 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_LEN 4 | |
| 2656 | /* BAD Address that triggered address-based exception */ | |
| 2657 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_OFST 140 | |
| 2658 | #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_LEN 4 | |
| 2659 | ||
| 2660 | /* MC_CMD_AOE_OUT_INFO msgresponse */ | |
| 2661 | #define MC_CMD_AOE_OUT_INFO_LEN 44 | |
| 2662 | /* JTAG IDCODE of CPLD */ | |
| 2663 | #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0 | |
| 2664 | #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_LEN 4 | |
| 2665 | /* Version of CPLD */ | |
| 2666 | #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4 | |
| 2667 | #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_LEN 4 | |
| 2668 | /* JTAG IDCODE of FPGA */ | |
| 2669 | #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8 | |
| 2670 | #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_LEN 4 | |
| 2671 | /* JTAG USERCODE of FPGA */ | |
| 2672 | #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 | |
| 2673 | #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_LEN 4 | |
| 2674 | /* FPGA type - read from CPLD straps */ | |
| 2675 | #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 | |
| 2676 | #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_LEN 4 | |
| 2677 | #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */ | |
| 2678 | #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */ | |
| 2679 | /* FPGA state (debug) */ | |
| 2680 | #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 | |
| 2681 | #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_LEN 4 | |
| 2682 | /* FPGA image - partition from which loaded */ | |
| 2683 | #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24 | |
| 2684 | #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_LEN 4 | |
| 2685 | /* FC state */ | |
| 2686 | #define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28 | |
| 2687 | #define MC_CMD_AOE_OUT_INFO_FC_STATE_LEN 4 | |
| 2688 | /* enum: Set if watchdog working */ | |
| 2689 | #define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 | |
| 2690 | /* enum: Set if MC-FC communications working */ | |
| 2691 | #define MC_CMD_AOE_OUT_INFO_COMMS 0x2 | |
| 2692 | /* Random pieces of information */ | |
| 2693 | #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 | |
| 2694 | #define MC_CMD_AOE_OUT_INFO_FLAGS_LEN 4 | |
| 2695 | /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ | |
| 2696 | #define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 | |
| 2697 | /* enum: CPLD apparently good */ | |
| 2698 | #define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 | |
| 2699 | /* enum: FPGA working normally */ | |
| 2700 | #define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 | |
| 2701 | /* enum: FPGA is powered */ | |
| 2702 | #define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 | |
| 2703 | /* enum: Board has incompatible SODIMMs fitted */ | |
| 2704 | #define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 | |
| 2705 | /* enum: Board has ByteBlaster connected */ | |
| 2706 | #define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 | |
| 2707 | /* enum: FPGA Boot flash has an invalid header. */ | |
| 2708 | #define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40 | |
| 2709 | /* enum: FPGA Application flash is accessible. */ | |
| 2710 | #define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80 | |
| 2711 | /* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */ | |
| 2712 | #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 | |
| 2713 | #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_LEN 4 | |
| 2714 | #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ | |
| 2715 | #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ | |
| 2716 | #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ | |
| 2717 | #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ | |
| 2718 | #define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */ | |
| 2719 | /* Result of FC booting - not valid while a ByteBlaster is connected. */ | |
| 2720 | #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 | |
| 2721 | #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_LEN 4 | |
| 2722 | /* enum: No error */ | |
| 2723 | #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 | |
| 2724 | /* enum: Bad address set in CPLD */ | |
| 2725 | #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 | |
| 2726 | /* enum: Bad header */ | |
| 2727 | #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 | |
| 2728 | /* enum: Bad text section details */ | |
| 2729 | #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 | |
| 2730 | /* enum: Bad checksum */ | |
| 2731 | #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 | |
| 2732 | /* enum: Bad BSP */ | |
| 2733 | #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 | |
| 2734 | /* enum: Flash mode is invalid */ | |
| 2735 | #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_INVALID_FLASH_MODE 0x6 | |
| 2736 | /* enum: FC application loaded and execution attempted */ | |
| 2737 | #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 | |
| 2738 | /* enum: FC application Started */ | |
| 2739 | #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81 | |
| 2740 | /* enum: No bootrom in FPGA */ | |
| 2741 | #define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff | |
| 2742 | ||
| 2743 | /* MC_CMD_AOE_OUT_CURRENTS msgresponse */ | |
| 2744 | #define MC_CMD_AOE_OUT_CURRENTS_LEN 68 | |
| 2745 | /* Set of currents and voltages (mA or mV as appropriate) */ | |
| 2746 | #define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0 | |
| 2747 | #define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4 | |
| 2748 | #define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17 | |
| 2749 | #define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */ | |
| 2750 | #define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */ | |
| 2751 | #define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */ | |
| 2752 | #define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */ | |
| 2753 | #define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */ | |
| 2754 | #define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */ | |
| 2755 | #define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */ | |
| 2756 | #define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */ | |
| 2757 | #define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */ | |
| 2758 | #define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */ | |
| 2759 | #define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */ | |
| 2760 | #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */ | |
| 2761 | #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */ | |
| 2762 | #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */ | |
| 2763 | #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */ | |
| 2764 | #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */ | |
| 2765 | #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */ | |
| 2766 | ||
| 2767 | /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */ | |
| 2768 | #define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40 | |
| 2769 | /* Set of temperatures */ | |
| 2770 | #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0 | |
| 2771 | #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4 | |
| 2772 | #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10 | |
| 2773 | /* enum: The first set of enum values are for Modena code. */ | |
| 2774 | #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 | |
| 2775 | #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */ | |
| 2776 | #define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */ | |
| 2777 | #define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */ | |
| 2778 | #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */ | |
| 2779 | #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */ | |
| 2780 | #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */ | |
| 2781 | #define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */ | |
| 2782 | #define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */ | |
| 2783 | #define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */ | |
| 2784 | /* enum: The second set of enum values are for Sorrento code. */ | |
| 2785 | #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0 | |
| 2786 | #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */ | |
| 2787 | #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */ | |
| 2788 | #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */ | |
| 2789 | #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */ | |
| 2790 | #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */ | |
| 2791 | #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */ | |
| 2792 | #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */ | |
| 2793 | #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */ | |
| 2794 | ||
| 2795 | /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */ | |
| 2796 | #define MC_CMD_AOE_OUT_CPLD_READ_LEN 4 | |
| 2797 | /* The value read from the CPLD */ | |
| 2798 | #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0 | |
| 2799 | #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_LEN 4 | |
| 2800 | ||
| 2801 | /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */ | |
| 2802 | #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4 | |
| 2803 | #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252 | |
| 9f95a23c | 2804 | #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX_MCDI2 1020 |
| 11fdf7f2 | 2805 | #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num)) |
| f67539c2 | 2806 | #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_NUM(len) (((len)-0)/4) |
| 11fdf7f2 TL |
2807 | /* Failure counts for each fan */ |
| 2808 | #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0 | |
| 2809 | #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4 | |
| 2810 | #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1 | |
| 2811 | #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63 | |
| 9f95a23c | 2812 | #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM_MCDI2 255 |
| 11fdf7f2 TL |
2813 | |
| 2814 | /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */ | |
| 2815 | #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4 | |
| 2816 | /* Results of status command (only) */ | |
| 2817 | #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0 | |
| 2818 | #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_LEN 4 | |
| 2819 | ||
| 2820 | /* MC_CMD_AOE_OUT_POWER_OFF msgresponse */ | |
| 2821 | #define MC_CMD_AOE_OUT_POWER_OFF_LEN 0 | |
| 2822 | ||
| 2823 | /* MC_CMD_AOE_OUT_POWER_ON msgresponse */ | |
| 2824 | #define MC_CMD_AOE_OUT_POWER_ON_LEN 0 | |
| 2825 | ||
| 2826 | /* MC_CMD_AOE_OUT_LOAD msgresponse */ | |
| 2827 | #define MC_CMD_AOE_OUT_LOAD_LEN 0 | |
| 2828 | ||
| 2829 | /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */ | |
| 2830 | #define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0 | |
| 2831 | ||
| 2832 | /* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA | |
| 2833 | * for details | |
| 2834 | */ | |
| 2835 | #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) | |
| 2836 | #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0 | |
| 2837 | #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8 | |
| 2838 | #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0 | |
| 2839 | #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4 | |
| 2840 | #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS | |
| 2841 | ||
| 2842 | /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */ | |
| 2843 | #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5 | |
| 2844 | #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252 | |
| 9f95a23c | 2845 | #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX_MCDI2 1020 |
| 11fdf7f2 | 2846 | #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num)) |
| f67539c2 | 2847 | #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1) |
| 11fdf7f2 TL |
2848 | /* in bytes */ |
| 2849 | #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0 | |
| 2850 | #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_LEN 4 | |
| 2851 | #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4 | |
| 2852 | #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1 | |
| 2853 | #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1 | |
| 2854 | #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248 | |
| 9f95a23c | 2855 | #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM_MCDI2 1016 |
| 11fdf7f2 TL |
2856 | |
| 2857 | /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */ | |
| 2858 | #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12 | |
| 2859 | #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252 | |
| 9f95a23c | 2860 | #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX_MCDI2 1020 |
| 11fdf7f2 | 2861 | #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num)) |
| f67539c2 | 2862 | #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_NUM(len) (((len)-8)/4) |
| 11fdf7f2 TL |
2863 | /* Used to align the in and out data blocks so the MC can re-use the cmd */ |
| 2864 | #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0 | |
| 2865 | #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_LEN 4 | |
| 2866 | /* out bytes */ | |
| 2867 | #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4 | |
| 2868 | #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_LEN 4 | |
| 2869 | #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8 | |
| 2870 | #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4 | |
| 2871 | #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1 | |
| 2872 | #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61 | |
| 9f95a23c | 2873 | #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM_MCDI2 253 |
| 11fdf7f2 TL |
2874 | |
| 2875 | /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */ | |
| 2876 | #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0 | |
| 2877 | ||
| 2878 | /* MC_CMD_AOE_OUT_DDR msgresponse */ | |
| 2879 | #define MC_CMD_AOE_OUT_DDR_LENMIN 17 | |
| 2880 | #define MC_CMD_AOE_OUT_DDR_LENMAX 252 | |
| 9f95a23c | 2881 | #define MC_CMD_AOE_OUT_DDR_LENMAX_MCDI2 1020 |
| 11fdf7f2 | 2882 | #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num)) |
| f67539c2 | 2883 | #define MC_CMD_AOE_OUT_DDR_SPD_NUM(len) (((len)-16)/1) |
| 11fdf7f2 TL |
2884 | /* Information on the module. */ |
| 2885 | #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0 | |
| 2886 | #define MC_CMD_AOE_OUT_DDR_FLAGS_LEN 4 | |
| 2887 | #define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0 | |
| 2888 | #define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1 | |
| 2889 | #define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1 | |
| 2890 | #define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1 | |
| 2891 | #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2 | |
| 2892 | #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1 | |
| 2893 | #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3 | |
| 2894 | #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1 | |
| 2895 | /* Memory size, in MB. */ | |
| 2896 | #define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4 | |
| 2897 | #define MC_CMD_AOE_OUT_DDR_CAPACITY_LEN 4 | |
| 2898 | /* The memory type, as reported from SPD information */ | |
| 2899 | #define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8 | |
| 2900 | #define MC_CMD_AOE_OUT_DDR_TYPE_LEN 4 | |
| 2901 | /* Nominal voltage of the module (as applied) */ | |
| 2902 | #define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12 | |
| 2903 | #define MC_CMD_AOE_OUT_DDR_VOLTAGE_LEN 4 | |
| 2904 | /* SPD data read from the module */ | |
| 2905 | #define MC_CMD_AOE_OUT_DDR_SPD_OFST 16 | |
| 2906 | #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1 | |
| 2907 | #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1 | |
| 2908 | #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236 | |
| 9f95a23c | 2909 | #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM_MCDI2 1004 |
| 11fdf7f2 TL |
2910 | |
| 2911 | /* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */ | |
| 2912 | #define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0 | |
| 2913 | ||
| 2914 | /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */ | |
| 2915 | #define MC_CMD_AOE_OUT_LINK_STATE_LEN 0 | |
| 2916 | ||
| 2917 | /* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */ | |
| 2918 | #define MC_CMD_AOE_OUT_SIENA_STATS_LEN 0 | |
| 2919 | ||
| 2920 | /* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */ | |
| 2921 | #define MC_CMD_AOE_OUT_ASIC_STATS_LEN 0 | |
| 2922 | ||
| 2923 | /* MC_CMD_AOE_OUT_FC msgresponse */ | |
| 2924 | #define MC_CMD_AOE_OUT_FC_LEN 0 | |
| 2925 | ||
| 2926 | /* MC_CMD_AOE_OUT_GET_ASIC_PORTS msgresponse */ | |
| 2927 | #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_LEN 4 | |
| 2928 | /* get the number of internal ports */ | |
| 2929 | #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_OFST 0 | |
| 2930 | #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_LEN 4 | |
| 2931 | ||
| 2932 | /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */ | |
| 2933 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8 | |
| 2934 | /* Flags describing status info on the module. */ | |
| 2935 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0 | |
| 2936 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_LEN 4 | |
| 2937 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0 | |
| 2938 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1 | |
| 2939 | /* DDR ECC status on the module. */ | |
| 2940 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4 | |
| 2941 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_LEN 4 | |
| 2942 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0 | |
| 2943 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1 | |
| 2944 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1 | |
| 2945 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1 | |
| 2946 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2 | |
| 2947 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1 | |
| 2948 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8 | |
| 2949 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8 | |
| 2950 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16 | |
| 2951 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8 | |
| 2952 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24 | |
| 2953 | #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8 | |
| 2954 | ||
| 2955 | /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */ | |
| 2956 | #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4 | |
| 2957 | #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0 | |
| 2958 | #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_LEN 4 | |
| 2959 | ||
| 2960 | /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */ | |
| 2961 | #define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0 | |
| 2962 | ||
| 2963 | /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */ | |
| 2964 | #define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0 | |
| 2965 | ||
| 2966 | /* MC_CMD_AOE_OUT_FC_BOOT msgresponse */ | |
| 2967 | #define MC_CMD_AOE_OUT_FC_BOOT_LEN 0 | |
| 2968 | ||
| 9f95a23c TL |
2969 | /* MC_CMD_AOE_OUT_MUM_STARTUP_FUSE msgresponse */ |
| 2970 | #define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_LEN 4 | |
| 2971 | /* Current value of startup FUSE byte (fusebyte#4) read back after the update | |
| 2972 | * operation. | |
| 2973 | */ | |
| 2974 | #define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_READBACK_VALUE_OFST 0 | |
| 2975 | #define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_READBACK_VALUE_LEN 4 | |
| 2976 | ||
| 11fdf7f2 | 2977 | #endif /* _SIENA_MC_DRIVER_PCOL_AOE_H */ |