]>
Commit | Line | Data |
---|---|---|
c30ab7b3 SL |
1 | // Targets the Cortex-M0, Cortex-M0+ and Cortex-M1 processors (ARMv6-M architecture) |
2 | ||
29967ef6 | 3 | use crate::spec::{Target, TargetOptions}; |
c30ab7b3 | 4 | |
29967ef6 XL |
5 | pub fn target() -> Target { |
6 | Target { | |
5e7ed085 | 7 | llvm_target: "thumbv6m-none-eabi".into(), |
29967ef6 | 8 | pointer_width: 32, |
5e7ed085 FG |
9 | data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), |
10 | arch: "arm".into(), | |
c30ab7b3 SL |
11 | |
12 | options: TargetOptions { | |
5e7ed085 | 13 | abi: "eabi".into(), |
c30ab7b3 SL |
14 | // The ARMv6-M architecture doesn't support unaligned loads/stores so we disable them |
15 | // with +strict-align. | |
f2b60f7d FG |
16 | // Also force-enable 32-bit atomics, which allows the use of atomic load/store only. |
17 | // The resulting atomics are ABI incompatible with atomics backed by libatomic. | |
18 | features: "+strict-align,+atomics-32".into(), | |
8faf50e0 | 19 | // There are no atomic CAS instructions available in the instruction set of the ARMv6-M |
c30ab7b3 | 20 | // architecture |
8faf50e0 | 21 | atomic_cas: false, |
dfeec247 XL |
22 | ..super::thumb_base::opts() |
23 | }, | |
29967ef6 | 24 | } |
c30ab7b3 | 25 | } |