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Commit | Line | Data |
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5a9fdfec FB |
1 | /* |
2 | * defines common to all virtual CPUs | |
5fafdf24 | 3 | * |
5a9fdfec FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
5a9fdfec FB |
18 | */ |
19 | #ifndef CPU_ALL_H | |
20 | #define CPU_ALL_H | |
21 | ||
7d99a001 | 22 | #include "qemu-common.h" |
1ad2134f | 23 | #include "cpu-common.h" |
0ac4bd56 | 24 | |
5fafdf24 TS |
25 | /* some important defines: |
26 | * | |
0ac4bd56 FB |
27 | * WORDS_ALIGNED : if defined, the host cpu can only make word aligned |
28 | * memory accesses. | |
5fafdf24 | 29 | * |
0ac4bd56 FB |
30 | * WORDS_BIGENDIAN : if defined, the host cpu is big endian and |
31 | * otherwise little endian. | |
5fafdf24 | 32 | * |
0ac4bd56 | 33 | * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet)) |
5fafdf24 | 34 | * |
0ac4bd56 FB |
35 | * TARGET_WORDS_BIGENDIAN : same for target cpu |
36 | */ | |
37 | ||
939ef593 | 38 | #include "softfloat.h" |
f193c797 FB |
39 | |
40 | #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) | |
41 | #define BSWAP_NEEDED | |
42 | #endif | |
43 | ||
44 | #ifdef BSWAP_NEEDED | |
45 | ||
46 | static inline uint16_t tswap16(uint16_t s) | |
47 | { | |
48 | return bswap16(s); | |
49 | } | |
50 | ||
51 | static inline uint32_t tswap32(uint32_t s) | |
52 | { | |
53 | return bswap32(s); | |
54 | } | |
55 | ||
56 | static inline uint64_t tswap64(uint64_t s) | |
57 | { | |
58 | return bswap64(s); | |
59 | } | |
60 | ||
61 | static inline void tswap16s(uint16_t *s) | |
62 | { | |
63 | *s = bswap16(*s); | |
64 | } | |
65 | ||
66 | static inline void tswap32s(uint32_t *s) | |
67 | { | |
68 | *s = bswap32(*s); | |
69 | } | |
70 | ||
71 | static inline void tswap64s(uint64_t *s) | |
72 | { | |
73 | *s = bswap64(*s); | |
74 | } | |
75 | ||
76 | #else | |
77 | ||
78 | static inline uint16_t tswap16(uint16_t s) | |
79 | { | |
80 | return s; | |
81 | } | |
82 | ||
83 | static inline uint32_t tswap32(uint32_t s) | |
84 | { | |
85 | return s; | |
86 | } | |
87 | ||
88 | static inline uint64_t tswap64(uint64_t s) | |
89 | { | |
90 | return s; | |
91 | } | |
92 | ||
93 | static inline void tswap16s(uint16_t *s) | |
94 | { | |
95 | } | |
96 | ||
97 | static inline void tswap32s(uint32_t *s) | |
98 | { | |
99 | } | |
100 | ||
101 | static inline void tswap64s(uint64_t *s) | |
102 | { | |
103 | } | |
104 | ||
105 | #endif | |
106 | ||
107 | #if TARGET_LONG_SIZE == 4 | |
108 | #define tswapl(s) tswap32(s) | |
109 | #define tswapls(s) tswap32s((uint32_t *)(s)) | |
0a962c02 | 110 | #define bswaptls(s) bswap32s(s) |
f193c797 FB |
111 | #else |
112 | #define tswapl(s) tswap64(s) | |
113 | #define tswapls(s) tswap64s((uint64_t *)(s)) | |
0a962c02 | 114 | #define bswaptls(s) bswap64s(s) |
f193c797 FB |
115 | #endif |
116 | ||
0ca9d380 AJ |
117 | typedef union { |
118 | float32 f; | |
119 | uint32_t l; | |
120 | } CPU_FloatU; | |
121 | ||
832ed0fa FB |
122 | /* NOTE: arm FPA is horrible as double 32 bit words are stored in big |
123 | endian ! */ | |
0ac4bd56 | 124 | typedef union { |
53cd6637 | 125 | float64 d; |
9d60cac0 FB |
126 | #if defined(WORDS_BIGENDIAN) \ |
127 | || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT)) | |
0ac4bd56 | 128 | struct { |
0ac4bd56 | 129 | uint32_t upper; |
832ed0fa | 130 | uint32_t lower; |
0ac4bd56 FB |
131 | } l; |
132 | #else | |
133 | struct { | |
0ac4bd56 | 134 | uint32_t lower; |
832ed0fa | 135 | uint32_t upper; |
0ac4bd56 FB |
136 | } l; |
137 | #endif | |
138 | uint64_t ll; | |
139 | } CPU_DoubleU; | |
140 | ||
1f587329 BS |
141 | #ifdef TARGET_SPARC |
142 | typedef union { | |
143 | float128 q; | |
144 | #if defined(WORDS_BIGENDIAN) \ | |
145 | || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT)) | |
146 | struct { | |
147 | uint32_t upmost; | |
148 | uint32_t upper; | |
149 | uint32_t lower; | |
150 | uint32_t lowest; | |
151 | } l; | |
152 | struct { | |
153 | uint64_t upper; | |
154 | uint64_t lower; | |
155 | } ll; | |
156 | #else | |
157 | struct { | |
158 | uint32_t lowest; | |
159 | uint32_t lower; | |
160 | uint32_t upper; | |
161 | uint32_t upmost; | |
162 | } l; | |
163 | struct { | |
164 | uint64_t lower; | |
165 | uint64_t upper; | |
166 | } ll; | |
167 | #endif | |
168 | } CPU_QuadU; | |
169 | #endif | |
170 | ||
61382a50 FB |
171 | /* CPU memory access without any memory or io remapping */ |
172 | ||
83d73968 FB |
173 | /* |
174 | * the generic syntax for the memory accesses is: | |
175 | * | |
176 | * load: ld{type}{sign}{size}{endian}_{access_type}(ptr) | |
177 | * | |
178 | * store: st{type}{size}{endian}_{access_type}(ptr, val) | |
179 | * | |
180 | * type is: | |
181 | * (empty): integer access | |
182 | * f : float access | |
5fafdf24 | 183 | * |
83d73968 FB |
184 | * sign is: |
185 | * (empty): for floats or 32 bit size | |
186 | * u : unsigned | |
187 | * s : signed | |
188 | * | |
189 | * size is: | |
190 | * b: 8 bits | |
191 | * w: 16 bits | |
192 | * l: 32 bits | |
193 | * q: 64 bits | |
5fafdf24 | 194 | * |
83d73968 FB |
195 | * endian is: |
196 | * (empty): target cpu endianness or 8 bit access | |
197 | * r : reversed target cpu endianness (not implemented yet) | |
198 | * be : big endian (not implemented yet) | |
199 | * le : little endian (not implemented yet) | |
200 | * | |
201 | * access_type is: | |
202 | * raw : host memory access | |
203 | * user : user mode access using soft MMU | |
204 | * kernel : kernel mode access using soft MMU | |
205 | */ | |
8bba3ea1 | 206 | static inline int ldub_p(const void *ptr) |
5a9fdfec FB |
207 | { |
208 | return *(uint8_t *)ptr; | |
209 | } | |
210 | ||
8bba3ea1 | 211 | static inline int ldsb_p(const void *ptr) |
5a9fdfec FB |
212 | { |
213 | return *(int8_t *)ptr; | |
214 | } | |
215 | ||
c27004ec | 216 | static inline void stb_p(void *ptr, int v) |
5a9fdfec FB |
217 | { |
218 | *(uint8_t *)ptr = v; | |
219 | } | |
220 | ||
221 | /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the | |
222 | kernel handles unaligned load/stores may give better results, but | |
223 | it is a system wide setting : bad */ | |
2df3b95d | 224 | #if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED) |
5a9fdfec FB |
225 | |
226 | /* conservative code for little endian unaligned accesses */ | |
8bba3ea1 | 227 | static inline int lduw_le_p(const void *ptr) |
5a9fdfec | 228 | { |
e58ffeb3 | 229 | #ifdef _ARCH_PPC |
5a9fdfec FB |
230 | int val; |
231 | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); | |
232 | return val; | |
233 | #else | |
e01fe6d5 | 234 | const uint8_t *p = ptr; |
5a9fdfec FB |
235 | return p[0] | (p[1] << 8); |
236 | #endif | |
237 | } | |
238 | ||
8bba3ea1 | 239 | static inline int ldsw_le_p(const void *ptr) |
5a9fdfec | 240 | { |
e58ffeb3 | 241 | #ifdef _ARCH_PPC |
5a9fdfec FB |
242 | int val; |
243 | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); | |
244 | return (int16_t)val; | |
245 | #else | |
e01fe6d5 | 246 | const uint8_t *p = ptr; |
5a9fdfec FB |
247 | return (int16_t)(p[0] | (p[1] << 8)); |
248 | #endif | |
249 | } | |
250 | ||
8bba3ea1 | 251 | static inline int ldl_le_p(const void *ptr) |
5a9fdfec | 252 | { |
e58ffeb3 | 253 | #ifdef _ARCH_PPC |
5a9fdfec FB |
254 | int val; |
255 | __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr)); | |
256 | return val; | |
257 | #else | |
e01fe6d5 | 258 | const uint8_t *p = ptr; |
5a9fdfec FB |
259 | return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); |
260 | #endif | |
261 | } | |
262 | ||
8bba3ea1 | 263 | static inline uint64_t ldq_le_p(const void *ptr) |
5a9fdfec | 264 | { |
e01fe6d5 | 265 | const uint8_t *p = ptr; |
5a9fdfec | 266 | uint32_t v1, v2; |
f0aca822 FB |
267 | v1 = ldl_le_p(p); |
268 | v2 = ldl_le_p(p + 4); | |
5a9fdfec FB |
269 | return v1 | ((uint64_t)v2 << 32); |
270 | } | |
271 | ||
2df3b95d | 272 | static inline void stw_le_p(void *ptr, int v) |
5a9fdfec | 273 | { |
e58ffeb3 | 274 | #ifdef _ARCH_PPC |
5a9fdfec FB |
275 | __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr)); |
276 | #else | |
277 | uint8_t *p = ptr; | |
278 | p[0] = v; | |
279 | p[1] = v >> 8; | |
280 | #endif | |
281 | } | |
282 | ||
2df3b95d | 283 | static inline void stl_le_p(void *ptr, int v) |
5a9fdfec | 284 | { |
e58ffeb3 | 285 | #ifdef _ARCH_PPC |
5a9fdfec FB |
286 | __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr)); |
287 | #else | |
288 | uint8_t *p = ptr; | |
289 | p[0] = v; | |
290 | p[1] = v >> 8; | |
291 | p[2] = v >> 16; | |
292 | p[3] = v >> 24; | |
293 | #endif | |
294 | } | |
295 | ||
2df3b95d | 296 | static inline void stq_le_p(void *ptr, uint64_t v) |
5a9fdfec FB |
297 | { |
298 | uint8_t *p = ptr; | |
f0aca822 FB |
299 | stl_le_p(p, (uint32_t)v); |
300 | stl_le_p(p + 4, v >> 32); | |
5a9fdfec FB |
301 | } |
302 | ||
303 | /* float access */ | |
304 | ||
8bba3ea1 | 305 | static inline float32 ldfl_le_p(const void *ptr) |
5a9fdfec FB |
306 | { |
307 | union { | |
53cd6637 | 308 | float32 f; |
5a9fdfec FB |
309 | uint32_t i; |
310 | } u; | |
2df3b95d | 311 | u.i = ldl_le_p(ptr); |
5a9fdfec FB |
312 | return u.f; |
313 | } | |
314 | ||
2df3b95d | 315 | static inline void stfl_le_p(void *ptr, float32 v) |
5a9fdfec FB |
316 | { |
317 | union { | |
53cd6637 | 318 | float32 f; |
5a9fdfec FB |
319 | uint32_t i; |
320 | } u; | |
321 | u.f = v; | |
2df3b95d | 322 | stl_le_p(ptr, u.i); |
5a9fdfec FB |
323 | } |
324 | ||
8bba3ea1 | 325 | static inline float64 ldfq_le_p(const void *ptr) |
5a9fdfec | 326 | { |
0ac4bd56 | 327 | CPU_DoubleU u; |
2df3b95d FB |
328 | u.l.lower = ldl_le_p(ptr); |
329 | u.l.upper = ldl_le_p(ptr + 4); | |
5a9fdfec FB |
330 | return u.d; |
331 | } | |
332 | ||
2df3b95d | 333 | static inline void stfq_le_p(void *ptr, float64 v) |
5a9fdfec | 334 | { |
0ac4bd56 | 335 | CPU_DoubleU u; |
5a9fdfec | 336 | u.d = v; |
2df3b95d FB |
337 | stl_le_p(ptr, u.l.lower); |
338 | stl_le_p(ptr + 4, u.l.upper); | |
5a9fdfec FB |
339 | } |
340 | ||
2df3b95d FB |
341 | #else |
342 | ||
8bba3ea1 | 343 | static inline int lduw_le_p(const void *ptr) |
2df3b95d FB |
344 | { |
345 | return *(uint16_t *)ptr; | |
346 | } | |
347 | ||
8bba3ea1 | 348 | static inline int ldsw_le_p(const void *ptr) |
2df3b95d FB |
349 | { |
350 | return *(int16_t *)ptr; | |
351 | } | |
93ac68bc | 352 | |
8bba3ea1 | 353 | static inline int ldl_le_p(const void *ptr) |
2df3b95d FB |
354 | { |
355 | return *(uint32_t *)ptr; | |
356 | } | |
357 | ||
8bba3ea1 | 358 | static inline uint64_t ldq_le_p(const void *ptr) |
2df3b95d FB |
359 | { |
360 | return *(uint64_t *)ptr; | |
361 | } | |
362 | ||
363 | static inline void stw_le_p(void *ptr, int v) | |
364 | { | |
365 | *(uint16_t *)ptr = v; | |
366 | } | |
367 | ||
368 | static inline void stl_le_p(void *ptr, int v) | |
369 | { | |
370 | *(uint32_t *)ptr = v; | |
371 | } | |
372 | ||
373 | static inline void stq_le_p(void *ptr, uint64_t v) | |
374 | { | |
375 | *(uint64_t *)ptr = v; | |
376 | } | |
377 | ||
378 | /* float access */ | |
379 | ||
8bba3ea1 | 380 | static inline float32 ldfl_le_p(const void *ptr) |
2df3b95d FB |
381 | { |
382 | return *(float32 *)ptr; | |
383 | } | |
384 | ||
8bba3ea1 | 385 | static inline float64 ldfq_le_p(const void *ptr) |
2df3b95d FB |
386 | { |
387 | return *(float64 *)ptr; | |
388 | } | |
389 | ||
390 | static inline void stfl_le_p(void *ptr, float32 v) | |
391 | { | |
392 | *(float32 *)ptr = v; | |
393 | } | |
394 | ||
395 | static inline void stfq_le_p(void *ptr, float64 v) | |
396 | { | |
397 | *(float64 *)ptr = v; | |
398 | } | |
399 | #endif | |
400 | ||
401 | #if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED) | |
402 | ||
8bba3ea1 | 403 | static inline int lduw_be_p(const void *ptr) |
93ac68bc | 404 | { |
83d73968 FB |
405 | #if defined(__i386__) |
406 | int val; | |
407 | asm volatile ("movzwl %1, %0\n" | |
408 | "xchgb %b0, %h0\n" | |
409 | : "=q" (val) | |
410 | : "m" (*(uint16_t *)ptr)); | |
411 | return val; | |
412 | #else | |
e01fe6d5 | 413 | const uint8_t *b = ptr; |
83d73968 FB |
414 | return ((b[0] << 8) | b[1]); |
415 | #endif | |
93ac68bc FB |
416 | } |
417 | ||
8bba3ea1 | 418 | static inline int ldsw_be_p(const void *ptr) |
93ac68bc | 419 | { |
83d73968 FB |
420 | #if defined(__i386__) |
421 | int val; | |
422 | asm volatile ("movzwl %1, %0\n" | |
423 | "xchgb %b0, %h0\n" | |
424 | : "=q" (val) | |
425 | : "m" (*(uint16_t *)ptr)); | |
426 | return (int16_t)val; | |
427 | #else | |
e01fe6d5 | 428 | const uint8_t *b = ptr; |
83d73968 FB |
429 | return (int16_t)((b[0] << 8) | b[1]); |
430 | #endif | |
93ac68bc FB |
431 | } |
432 | ||
8bba3ea1 | 433 | static inline int ldl_be_p(const void *ptr) |
93ac68bc | 434 | { |
4f2ac237 | 435 | #if defined(__i386__) || defined(__x86_64__) |
83d73968 FB |
436 | int val; |
437 | asm volatile ("movl %1, %0\n" | |
438 | "bswap %0\n" | |
439 | : "=r" (val) | |
440 | : "m" (*(uint32_t *)ptr)); | |
441 | return val; | |
442 | #else | |
e01fe6d5 | 443 | const uint8_t *b = ptr; |
83d73968 FB |
444 | return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; |
445 | #endif | |
93ac68bc FB |
446 | } |
447 | ||
8bba3ea1 | 448 | static inline uint64_t ldq_be_p(const void *ptr) |
93ac68bc FB |
449 | { |
450 | uint32_t a,b; | |
2df3b95d | 451 | a = ldl_be_p(ptr); |
4d7a0880 | 452 | b = ldl_be_p((uint8_t *)ptr + 4); |
93ac68bc FB |
453 | return (((uint64_t)a<<32)|b); |
454 | } | |
455 | ||
2df3b95d | 456 | static inline void stw_be_p(void *ptr, int v) |
93ac68bc | 457 | { |
83d73968 FB |
458 | #if defined(__i386__) |
459 | asm volatile ("xchgb %b0, %h0\n" | |
460 | "movw %w0, %1\n" | |
461 | : "=q" (v) | |
462 | : "m" (*(uint16_t *)ptr), "0" (v)); | |
463 | #else | |
93ac68bc FB |
464 | uint8_t *d = (uint8_t *) ptr; |
465 | d[0] = v >> 8; | |
466 | d[1] = v; | |
83d73968 | 467 | #endif |
93ac68bc FB |
468 | } |
469 | ||
2df3b95d | 470 | static inline void stl_be_p(void *ptr, int v) |
93ac68bc | 471 | { |
4f2ac237 | 472 | #if defined(__i386__) || defined(__x86_64__) |
83d73968 FB |
473 | asm volatile ("bswap %0\n" |
474 | "movl %0, %1\n" | |
475 | : "=r" (v) | |
476 | : "m" (*(uint32_t *)ptr), "0" (v)); | |
477 | #else | |
93ac68bc FB |
478 | uint8_t *d = (uint8_t *) ptr; |
479 | d[0] = v >> 24; | |
480 | d[1] = v >> 16; | |
481 | d[2] = v >> 8; | |
482 | d[3] = v; | |
83d73968 | 483 | #endif |
93ac68bc FB |
484 | } |
485 | ||
2df3b95d | 486 | static inline void stq_be_p(void *ptr, uint64_t v) |
93ac68bc | 487 | { |
2df3b95d | 488 | stl_be_p(ptr, v >> 32); |
4d7a0880 | 489 | stl_be_p((uint8_t *)ptr + 4, v); |
0ac4bd56 FB |
490 | } |
491 | ||
492 | /* float access */ | |
493 | ||
8bba3ea1 | 494 | static inline float32 ldfl_be_p(const void *ptr) |
0ac4bd56 FB |
495 | { |
496 | union { | |
53cd6637 | 497 | float32 f; |
0ac4bd56 FB |
498 | uint32_t i; |
499 | } u; | |
2df3b95d | 500 | u.i = ldl_be_p(ptr); |
0ac4bd56 FB |
501 | return u.f; |
502 | } | |
503 | ||
2df3b95d | 504 | static inline void stfl_be_p(void *ptr, float32 v) |
0ac4bd56 FB |
505 | { |
506 | union { | |
53cd6637 | 507 | float32 f; |
0ac4bd56 FB |
508 | uint32_t i; |
509 | } u; | |
510 | u.f = v; | |
2df3b95d | 511 | stl_be_p(ptr, u.i); |
0ac4bd56 FB |
512 | } |
513 | ||
8bba3ea1 | 514 | static inline float64 ldfq_be_p(const void *ptr) |
0ac4bd56 FB |
515 | { |
516 | CPU_DoubleU u; | |
2df3b95d | 517 | u.l.upper = ldl_be_p(ptr); |
4d7a0880 | 518 | u.l.lower = ldl_be_p((uint8_t *)ptr + 4); |
0ac4bd56 FB |
519 | return u.d; |
520 | } | |
521 | ||
2df3b95d | 522 | static inline void stfq_be_p(void *ptr, float64 v) |
0ac4bd56 FB |
523 | { |
524 | CPU_DoubleU u; | |
525 | u.d = v; | |
2df3b95d | 526 | stl_be_p(ptr, u.l.upper); |
4d7a0880 | 527 | stl_be_p((uint8_t *)ptr + 4, u.l.lower); |
93ac68bc FB |
528 | } |
529 | ||
5a9fdfec FB |
530 | #else |
531 | ||
8bba3ea1 | 532 | static inline int lduw_be_p(const void *ptr) |
5a9fdfec FB |
533 | { |
534 | return *(uint16_t *)ptr; | |
535 | } | |
536 | ||
8bba3ea1 | 537 | static inline int ldsw_be_p(const void *ptr) |
5a9fdfec FB |
538 | { |
539 | return *(int16_t *)ptr; | |
540 | } | |
541 | ||
8bba3ea1 | 542 | static inline int ldl_be_p(const void *ptr) |
5a9fdfec FB |
543 | { |
544 | return *(uint32_t *)ptr; | |
545 | } | |
546 | ||
8bba3ea1 | 547 | static inline uint64_t ldq_be_p(const void *ptr) |
5a9fdfec FB |
548 | { |
549 | return *(uint64_t *)ptr; | |
550 | } | |
551 | ||
2df3b95d | 552 | static inline void stw_be_p(void *ptr, int v) |
5a9fdfec FB |
553 | { |
554 | *(uint16_t *)ptr = v; | |
555 | } | |
556 | ||
2df3b95d | 557 | static inline void stl_be_p(void *ptr, int v) |
5a9fdfec FB |
558 | { |
559 | *(uint32_t *)ptr = v; | |
560 | } | |
561 | ||
2df3b95d | 562 | static inline void stq_be_p(void *ptr, uint64_t v) |
5a9fdfec FB |
563 | { |
564 | *(uint64_t *)ptr = v; | |
565 | } | |
566 | ||
567 | /* float access */ | |
568 | ||
8bba3ea1 | 569 | static inline float32 ldfl_be_p(const void *ptr) |
5a9fdfec | 570 | { |
53cd6637 | 571 | return *(float32 *)ptr; |
5a9fdfec FB |
572 | } |
573 | ||
8bba3ea1 | 574 | static inline float64 ldfq_be_p(const void *ptr) |
5a9fdfec | 575 | { |
53cd6637 | 576 | return *(float64 *)ptr; |
5a9fdfec FB |
577 | } |
578 | ||
2df3b95d | 579 | static inline void stfl_be_p(void *ptr, float32 v) |
5a9fdfec | 580 | { |
53cd6637 | 581 | *(float32 *)ptr = v; |
5a9fdfec FB |
582 | } |
583 | ||
2df3b95d | 584 | static inline void stfq_be_p(void *ptr, float64 v) |
5a9fdfec | 585 | { |
53cd6637 | 586 | *(float64 *)ptr = v; |
5a9fdfec | 587 | } |
2df3b95d FB |
588 | |
589 | #endif | |
590 | ||
591 | /* target CPU memory access functions */ | |
592 | #if defined(TARGET_WORDS_BIGENDIAN) | |
593 | #define lduw_p(p) lduw_be_p(p) | |
594 | #define ldsw_p(p) ldsw_be_p(p) | |
595 | #define ldl_p(p) ldl_be_p(p) | |
596 | #define ldq_p(p) ldq_be_p(p) | |
597 | #define ldfl_p(p) ldfl_be_p(p) | |
598 | #define ldfq_p(p) ldfq_be_p(p) | |
599 | #define stw_p(p, v) stw_be_p(p, v) | |
600 | #define stl_p(p, v) stl_be_p(p, v) | |
601 | #define stq_p(p, v) stq_be_p(p, v) | |
602 | #define stfl_p(p, v) stfl_be_p(p, v) | |
603 | #define stfq_p(p, v) stfq_be_p(p, v) | |
604 | #else | |
605 | #define lduw_p(p) lduw_le_p(p) | |
606 | #define ldsw_p(p) ldsw_le_p(p) | |
607 | #define ldl_p(p) ldl_le_p(p) | |
608 | #define ldq_p(p) ldq_le_p(p) | |
609 | #define ldfl_p(p) ldfl_le_p(p) | |
610 | #define ldfq_p(p) ldfq_le_p(p) | |
611 | #define stw_p(p, v) stw_le_p(p, v) | |
612 | #define stl_p(p, v) stl_le_p(p, v) | |
613 | #define stq_p(p, v) stq_le_p(p, v) | |
614 | #define stfl_p(p, v) stfl_le_p(p, v) | |
615 | #define stfq_p(p, v) stfq_le_p(p, v) | |
5a9fdfec FB |
616 | #endif |
617 | ||
61382a50 FB |
618 | /* MMU memory access macros */ |
619 | ||
53a5960a | 620 | #if defined(CONFIG_USER_ONLY) |
0e62fd79 AJ |
621 | #include <assert.h> |
622 | #include "qemu-types.h" | |
623 | ||
53a5960a PB |
624 | /* On some host systems the guest address space is reserved on the host. |
625 | * This allows the guest address space to be offset to a convenient location. | |
626 | */ | |
627 | //#define GUEST_BASE 0x20000000 | |
628 | #define GUEST_BASE 0 | |
629 | ||
630 | /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ | |
631 | #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE)) | |
0e62fd79 AJ |
632 | #define h2g(x) ({ \ |
633 | unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \ | |
634 | /* Check if given address fits target address space */ \ | |
635 | assert(__ret == (abi_ulong)__ret); \ | |
636 | (abi_ulong)__ret; \ | |
637 | }) | |
14cc46b1 AJ |
638 | #define h2g_valid(x) ({ \ |
639 | unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \ | |
640 | (__guest == (abi_ulong)__guest); \ | |
641 | }) | |
53a5960a PB |
642 | |
643 | #define saddr(x) g2h(x) | |
644 | #define laddr(x) g2h(x) | |
645 | ||
646 | #else /* !CONFIG_USER_ONLY */ | |
c27004ec FB |
647 | /* NOTE: we use double casts if pointers and target_ulong have |
648 | different sizes */ | |
53a5960a PB |
649 | #define saddr(x) (uint8_t *)(long)(x) |
650 | #define laddr(x) (uint8_t *)(long)(x) | |
651 | #endif | |
652 | ||
653 | #define ldub_raw(p) ldub_p(laddr((p))) | |
654 | #define ldsb_raw(p) ldsb_p(laddr((p))) | |
655 | #define lduw_raw(p) lduw_p(laddr((p))) | |
656 | #define ldsw_raw(p) ldsw_p(laddr((p))) | |
657 | #define ldl_raw(p) ldl_p(laddr((p))) | |
658 | #define ldq_raw(p) ldq_p(laddr((p))) | |
659 | #define ldfl_raw(p) ldfl_p(laddr((p))) | |
660 | #define ldfq_raw(p) ldfq_p(laddr((p))) | |
661 | #define stb_raw(p, v) stb_p(saddr((p)), v) | |
662 | #define stw_raw(p, v) stw_p(saddr((p)), v) | |
663 | #define stl_raw(p, v) stl_p(saddr((p)), v) | |
664 | #define stq_raw(p, v) stq_p(saddr((p)), v) | |
665 | #define stfl_raw(p, v) stfl_p(saddr((p)), v) | |
666 | #define stfq_raw(p, v) stfq_p(saddr((p)), v) | |
c27004ec FB |
667 | |
668 | ||
5fafdf24 | 669 | #if defined(CONFIG_USER_ONLY) |
61382a50 FB |
670 | |
671 | /* if user mode, no other memory access functions */ | |
672 | #define ldub(p) ldub_raw(p) | |
673 | #define ldsb(p) ldsb_raw(p) | |
674 | #define lduw(p) lduw_raw(p) | |
675 | #define ldsw(p) ldsw_raw(p) | |
676 | #define ldl(p) ldl_raw(p) | |
677 | #define ldq(p) ldq_raw(p) | |
678 | #define ldfl(p) ldfl_raw(p) | |
679 | #define ldfq(p) ldfq_raw(p) | |
680 | #define stb(p, v) stb_raw(p, v) | |
681 | #define stw(p, v) stw_raw(p, v) | |
682 | #define stl(p, v) stl_raw(p, v) | |
683 | #define stq(p, v) stq_raw(p, v) | |
684 | #define stfl(p, v) stfl_raw(p, v) | |
685 | #define stfq(p, v) stfq_raw(p, v) | |
686 | ||
687 | #define ldub_code(p) ldub_raw(p) | |
688 | #define ldsb_code(p) ldsb_raw(p) | |
689 | #define lduw_code(p) lduw_raw(p) | |
690 | #define ldsw_code(p) ldsw_raw(p) | |
691 | #define ldl_code(p) ldl_raw(p) | |
bc98a7ef | 692 | #define ldq_code(p) ldq_raw(p) |
61382a50 FB |
693 | |
694 | #define ldub_kernel(p) ldub_raw(p) | |
695 | #define ldsb_kernel(p) ldsb_raw(p) | |
696 | #define lduw_kernel(p) lduw_raw(p) | |
697 | #define ldsw_kernel(p) ldsw_raw(p) | |
698 | #define ldl_kernel(p) ldl_raw(p) | |
bc98a7ef | 699 | #define ldq_kernel(p) ldq_raw(p) |
0ac4bd56 FB |
700 | #define ldfl_kernel(p) ldfl_raw(p) |
701 | #define ldfq_kernel(p) ldfq_raw(p) | |
61382a50 FB |
702 | #define stb_kernel(p, v) stb_raw(p, v) |
703 | #define stw_kernel(p, v) stw_raw(p, v) | |
704 | #define stl_kernel(p, v) stl_raw(p, v) | |
705 | #define stq_kernel(p, v) stq_raw(p, v) | |
0ac4bd56 FB |
706 | #define stfl_kernel(p, v) stfl_raw(p, v) |
707 | #define stfq_kernel(p, vt) stfq_raw(p, v) | |
61382a50 FB |
708 | |
709 | #endif /* defined(CONFIG_USER_ONLY) */ | |
710 | ||
5a9fdfec FB |
711 | /* page related stuff */ |
712 | ||
03875444 | 713 | #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) |
5a9fdfec FB |
714 | #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) |
715 | #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) | |
716 | ||
53a5960a | 717 | /* ??? These should be the larger of unsigned long and target_ulong. */ |
83fb7adf FB |
718 | extern unsigned long qemu_real_host_page_size; |
719 | extern unsigned long qemu_host_page_bits; | |
720 | extern unsigned long qemu_host_page_size; | |
721 | extern unsigned long qemu_host_page_mask; | |
5a9fdfec | 722 | |
83fb7adf | 723 | #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) |
5a9fdfec FB |
724 | |
725 | /* same as PROT_xxx */ | |
726 | #define PAGE_READ 0x0001 | |
727 | #define PAGE_WRITE 0x0002 | |
728 | #define PAGE_EXEC 0x0004 | |
729 | #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) | |
730 | #define PAGE_VALID 0x0008 | |
731 | /* original state of the write flag (used when tracking self-modifying | |
732 | code */ | |
5fafdf24 | 733 | #define PAGE_WRITE_ORG 0x0010 |
50a9569b | 734 | #define PAGE_RESERVED 0x0020 |
5a9fdfec FB |
735 | |
736 | void page_dump(FILE *f); | |
edf8e2af MW |
737 | int walk_memory_regions(void *, |
738 | int (*fn)(void *, unsigned long, unsigned long, unsigned long)); | |
53a5960a PB |
739 | int page_get_flags(target_ulong address); |
740 | void page_set_flags(target_ulong start, target_ulong end, int flags); | |
3d97b40b | 741 | int page_check_range(target_ulong start, target_ulong len, int flags); |
5a9fdfec | 742 | |
26a5f13b | 743 | void cpu_exec_init_all(unsigned long tb_size); |
c5be9f08 | 744 | CPUState *cpu_copy(CPUState *env); |
950f1472 | 745 | CPUState *qemu_get_cpu(int cpu); |
c5be9f08 | 746 | |
5fafdf24 | 747 | void cpu_dump_state(CPUState *env, FILE *f, |
7fe48483 FB |
748 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
749 | int flags); | |
76a66253 JM |
750 | void cpu_dump_statistics (CPUState *env, FILE *f, |
751 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
752 | int flags); | |
7fe48483 | 753 | |
a5e50b26 | 754 | void QEMU_NORETURN cpu_abort(CPUState *env, const char *fmt, ...) |
7d99a001 | 755 | __attribute__ ((__format__ (__printf__, 2, 3))); |
f0aca822 | 756 | extern CPUState *first_cpu; |
e2f22898 | 757 | extern CPUState *cpu_single_env; |
2e70f6ef PB |
758 | extern int64_t qemu_icount; |
759 | extern int use_icount; | |
5a9fdfec | 760 | |
9acbed06 FB |
761 | #define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */ |
762 | #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */ | |
ef792f9d | 763 | #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */ |
98699967 | 764 | #define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */ |
ba3c64fb | 765 | #define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */ |
3b21e03e | 766 | #define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */ |
6658ffb8 | 767 | #define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */ |
0573fbfc | 768 | #define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */ |
474ea849 | 769 | #define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */ |
b09ea7d5 GN |
770 | #define CPU_INTERRUPT_INIT 0x400 /* INIT pending. */ |
771 | #define CPU_INTERRUPT_SIPI 0x800 /* SIPI pending. */ | |
79c4f6b0 | 772 | #define CPU_INTERRUPT_MCE 0x1000 /* (x86 only) MCE pending. */ |
98699967 | 773 | |
4690764b | 774 | void cpu_interrupt(CPUState *s, int mask); |
b54ad049 | 775 | void cpu_reset_interrupt(CPUState *env, int mask); |
68a79315 | 776 | |
3098dba0 AJ |
777 | void cpu_exit(CPUState *s); |
778 | ||
6a4955a8 AL |
779 | int qemu_cpu_has_work(CPUState *env); |
780 | ||
a1d1bb31 AL |
781 | /* Breakpoint/watchpoint flags */ |
782 | #define BP_MEM_READ 0x01 | |
783 | #define BP_MEM_WRITE 0x02 | |
784 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
06d55cc1 | 785 | #define BP_STOP_BEFORE_ACCESS 0x04 |
6e140f28 | 786 | #define BP_WATCHPOINT_HIT 0x08 |
a1d1bb31 | 787 | #define BP_GDB 0x10 |
2dc9f411 | 788 | #define BP_CPU 0x20 |
a1d1bb31 AL |
789 | |
790 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, | |
791 | CPUBreakpoint **breakpoint); | |
792 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags); | |
793 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint); | |
794 | void cpu_breakpoint_remove_all(CPUState *env, int mask); | |
795 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, | |
796 | int flags, CPUWatchpoint **watchpoint); | |
797 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, | |
798 | target_ulong len, int flags); | |
799 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint); | |
800 | void cpu_watchpoint_remove_all(CPUState *env, int mask); | |
60897d36 EI |
801 | |
802 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ | |
803 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
804 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
805 | ||
c33a346e | 806 | void cpu_single_step(CPUState *env, int enabled); |
d95dc32d | 807 | void cpu_reset(CPUState *s); |
4c3a88a2 | 808 | |
13eb76e0 FB |
809 | /* Return the physical page corresponding to a virtual one. Use it |
810 | only for debugging because no protection checks are done. Return -1 | |
811 | if no page found. */ | |
9b3c35e0 | 812 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr); |
13eb76e0 | 813 | |
5fafdf24 | 814 | #define CPU_LOG_TB_OUT_ASM (1 << 0) |
9fddaa0c | 815 | #define CPU_LOG_TB_IN_ASM (1 << 1) |
f193c797 FB |
816 | #define CPU_LOG_TB_OP (1 << 2) |
817 | #define CPU_LOG_TB_OP_OPT (1 << 3) | |
818 | #define CPU_LOG_INT (1 << 4) | |
819 | #define CPU_LOG_EXEC (1 << 5) | |
820 | #define CPU_LOG_PCALL (1 << 6) | |
fd872598 | 821 | #define CPU_LOG_IOPORT (1 << 7) |
9fddaa0c | 822 | #define CPU_LOG_TB_CPU (1 << 8) |
eca1bdf4 | 823 | #define CPU_LOG_RESET (1 << 9) |
f193c797 FB |
824 | |
825 | /* define log items */ | |
826 | typedef struct CPULogItem { | |
827 | int mask; | |
828 | const char *name; | |
829 | const char *help; | |
830 | } CPULogItem; | |
831 | ||
c7cd6a37 | 832 | extern const CPULogItem cpu_log_items[]; |
f193c797 | 833 | |
34865134 FB |
834 | void cpu_set_log(int log_flags); |
835 | void cpu_set_log_filename(const char *filename); | |
f193c797 | 836 | int cpu_str_to_log_mask(const char *str); |
34865134 | 837 | |
09683d35 | 838 | /* IO ports API */ |
32993977 | 839 | #include "ioport.h" |
09683d35 | 840 | |
33417e70 FB |
841 | /* memory API */ |
842 | ||
edf75d59 | 843 | extern int phys_ram_fd; |
1ccde1cb | 844 | extern uint8_t *phys_ram_dirty; |
00f82b8a | 845 | extern ram_addr_t ram_size; |
94a6b54f | 846 | extern ram_addr_t last_ram_offset; |
edf75d59 FB |
847 | |
848 | /* physical memory access */ | |
0f459d16 PB |
849 | |
850 | /* MMIO pages are identified by a combination of an IO device index and | |
851 | 3 flags. The ROMD code stores the page ram offset in iotlb entry, | |
852 | so only a limited number of ids are avaiable. */ | |
853 | ||
98699967 | 854 | #define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT)) |
edf75d59 | 855 | |
0f459d16 PB |
856 | /* Flags stored in the low bits of the TLB virtual address. These are |
857 | defined so that fast path ram access is all zeros. */ | |
858 | /* Zero if TLB entry is valid. */ | |
859 | #define TLB_INVALID_MASK (1 << 3) | |
860 | /* Set if TLB entry references a clean RAM page. The iotlb entry will | |
861 | contain the page physical address. */ | |
862 | #define TLB_NOTDIRTY (1 << 4) | |
863 | /* Set if TLB entry is an IO callback. */ | |
864 | #define TLB_MMIO (1 << 5) | |
865 | ||
5fafdf24 | 866 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
8b1f24b0 | 867 | uint8_t *buf, int len, int is_write); |
13eb76e0 | 868 | |
74576198 AL |
869 | #define VGA_DIRTY_FLAG 0x01 |
870 | #define CODE_DIRTY_FLAG 0x02 | |
871 | #define KQEMU_DIRTY_FLAG 0x04 | |
872 | #define MIGRATION_DIRTY_FLAG 0x08 | |
0a962c02 | 873 | |
1ccde1cb | 874 | /* read dirty bit (return 0 or 1) */ |
04c504cc | 875 | static inline int cpu_physical_memory_is_dirty(ram_addr_t addr) |
1ccde1cb | 876 | { |
0a962c02 FB |
877 | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff; |
878 | } | |
879 | ||
5fafdf24 | 880 | static inline int cpu_physical_memory_get_dirty(ram_addr_t addr, |
0a962c02 FB |
881 | int dirty_flags) |
882 | { | |
883 | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags; | |
1ccde1cb FB |
884 | } |
885 | ||
04c504cc | 886 | static inline void cpu_physical_memory_set_dirty(ram_addr_t addr) |
1ccde1cb | 887 | { |
0a962c02 | 888 | phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff; |
1ccde1cb FB |
889 | } |
890 | ||
04c504cc | 891 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
0a962c02 | 892 | int dirty_flags); |
04c504cc | 893 | void cpu_tlb_update_dirty(CPUState *env); |
1ccde1cb | 894 | |
74576198 AL |
895 | int cpu_physical_memory_set_dirty_tracking(int enable); |
896 | ||
897 | int cpu_physical_memory_get_dirty_tracking(void); | |
898 | ||
151f7749 JK |
899 | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, |
900 | target_phys_addr_t end_addr); | |
2bec46dc | 901 | |
e3db7226 FB |
902 | void dump_exec_info(FILE *f, |
903 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); | |
904 | ||
f65ed4c1 AL |
905 | /* Coalesced MMIO regions are areas where write operations can be reordered. |
906 | * This usually implies that write operations are side-effect free. This allows | |
907 | * batching which can make a major impact on performance when using | |
908 | * virtualization. | |
909 | */ | |
910 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size); | |
911 | ||
912 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size); | |
913 | ||
effedbc9 FB |
914 | /*******************************************/ |
915 | /* host CPU ticks (if available) */ | |
916 | ||
e58ffeb3 | 917 | #if defined(_ARCH_PPC) |
effedbc9 | 918 | |
effedbc9 FB |
919 | static inline int64_t cpu_get_real_ticks(void) |
920 | { | |
5e10fc90 | 921 | int64_t retval; |
922 | #ifdef _ARCH_PPC64 | |
923 | /* This reads timebase in one 64bit go and includes Cell workaround from: | |
924 | http://ozlabs.org/pipermail/linuxppc-dev/2006-October/027052.html | |
925 | */ | |
926 | __asm__ __volatile__ ( | |
927 | "mftb %0\n\t" | |
928 | "cmpwi %0,0\n\t" | |
929 | "beq- $-8" | |
930 | : "=r" (retval)); | |
931 | #else | |
932 | /* http://ozlabs.org/pipermail/linuxppc-dev/1999-October/003889.html */ | |
933 | unsigned long junk; | |
934 | __asm__ __volatile__ ( | |
935 | "mftbu %1\n\t" | |
936 | "mftb %L0\n\t" | |
937 | "mftbu %0\n\t" | |
938 | "cmpw %0,%1\n\t" | |
939 | "bne $-16" | |
940 | : "=r" (retval), "=r" (junk)); | |
941 | #endif | |
942 | return retval; | |
effedbc9 FB |
943 | } |
944 | ||
945 | #elif defined(__i386__) | |
946 | ||
947 | static inline int64_t cpu_get_real_ticks(void) | |
5f1ce948 FB |
948 | { |
949 | int64_t val; | |
950 | asm volatile ("rdtsc" : "=A" (val)); | |
951 | return val; | |
952 | } | |
953 | ||
effedbc9 FB |
954 | #elif defined(__x86_64__) |
955 | ||
956 | static inline int64_t cpu_get_real_ticks(void) | |
957 | { | |
958 | uint32_t low,high; | |
959 | int64_t val; | |
960 | asm volatile("rdtsc" : "=a" (low), "=d" (high)); | |
961 | val = high; | |
962 | val <<= 32; | |
963 | val |= low; | |
964 | return val; | |
965 | } | |
966 | ||
f54b3f92 AJ |
967 | #elif defined(__hppa__) |
968 | ||
969 | static inline int64_t cpu_get_real_ticks(void) | |
970 | { | |
971 | int val; | |
972 | asm volatile ("mfctl %%cr16, %0" : "=r"(val)); | |
973 | return val; | |
974 | } | |
975 | ||
effedbc9 FB |
976 | #elif defined(__ia64) |
977 | ||
978 | static inline int64_t cpu_get_real_ticks(void) | |
979 | { | |
980 | int64_t val; | |
981 | asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory"); | |
982 | return val; | |
983 | } | |
984 | ||
985 | #elif defined(__s390__) | |
986 | ||
987 | static inline int64_t cpu_get_real_ticks(void) | |
988 | { | |
989 | int64_t val; | |
990 | asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc"); | |
991 | return val; | |
992 | } | |
993 | ||
3142255c | 994 | #elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__) |
effedbc9 FB |
995 | |
996 | static inline int64_t cpu_get_real_ticks (void) | |
997 | { | |
998 | #if defined(_LP64) | |
999 | uint64_t rval; | |
1000 | asm volatile("rd %%tick,%0" : "=r"(rval)); | |
1001 | return rval; | |
1002 | #else | |
1003 | union { | |
1004 | uint64_t i64; | |
1005 | struct { | |
1006 | uint32_t high; | |
1007 | uint32_t low; | |
1008 | } i32; | |
1009 | } rval; | |
1010 | asm volatile("rd %%tick,%1; srlx %1,32,%0" | |
1011 | : "=r"(rval.i32.high), "=r"(rval.i32.low)); | |
1012 | return rval.i64; | |
1013 | #endif | |
1014 | } | |
c4b89d18 TS |
1015 | |
1016 | #elif defined(__mips__) | |
1017 | ||
1018 | static inline int64_t cpu_get_real_ticks(void) | |
1019 | { | |
1020 | #if __mips_isa_rev >= 2 | |
1021 | uint32_t count; | |
1022 | static uint32_t cyc_per_count = 0; | |
1023 | ||
1024 | if (!cyc_per_count) | |
1025 | __asm__ __volatile__("rdhwr %0, $3" : "=r" (cyc_per_count)); | |
1026 | ||
1027 | __asm__ __volatile__("rdhwr %1, $2" : "=r" (count)); | |
1028 | return (int64_t)(count * cyc_per_count); | |
1029 | #else | |
1030 | /* FIXME */ | |
1031 | static int64_t ticks = 0; | |
1032 | return ticks++; | |
1033 | #endif | |
1034 | } | |
1035 | ||
46152182 PB |
1036 | #else |
1037 | /* The host CPU doesn't have an easily accessible cycle counter. | |
85028e4d TS |
1038 | Just return a monotonically increasing value. This will be |
1039 | totally wrong, but hopefully better than nothing. */ | |
46152182 PB |
1040 | static inline int64_t cpu_get_real_ticks (void) |
1041 | { | |
1042 | static int64_t ticks = 0; | |
1043 | return ticks++; | |
1044 | } | |
effedbc9 FB |
1045 | #endif |
1046 | ||
1047 | /* profiling */ | |
1048 | #ifdef CONFIG_PROFILER | |
1049 | static inline int64_t profile_getclock(void) | |
1050 | { | |
1051 | return cpu_get_real_ticks(); | |
1052 | } | |
1053 | ||
5f1ce948 FB |
1054 | extern int64_t kqemu_time, kqemu_time_start; |
1055 | extern int64_t qemu_time, qemu_time_start; | |
1056 | extern int64_t tlb_flush_time; | |
1057 | extern int64_t kqemu_exec_count; | |
1058 | extern int64_t dev_time; | |
1059 | extern int64_t kqemu_ret_int_count; | |
1060 | extern int64_t kqemu_ret_excp_count; | |
1061 | extern int64_t kqemu_ret_intr_count; | |
5f1ce948 FB |
1062 | #endif |
1063 | ||
79c4f6b0 HY |
1064 | void cpu_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, |
1065 | uint64_t mcg_status, uint64_t addr, uint64_t misc); | |
1066 | ||
5a9fdfec | 1067 | #endif /* CPU_ALL_H */ |