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7d13299d FB |
1 | /* |
2 | * i386 emulator main execution loop | |
3 | * | |
66321a11 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
7d13299d | 5 | * |
3ef693a0 FB |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
7d13299d | 10 | * |
3ef693a0 FB |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
7d13299d | 15 | * |
3ef693a0 FB |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
7d13299d | 19 | */ |
e4533c7a | 20 | #include "config.h" |
93ac68bc | 21 | #include "exec.h" |
956034d7 | 22 | #include "disas.h" |
7d13299d | 23 | |
fbf9eeb3 FB |
24 | #if !defined(CONFIG_SOFTMMU) |
25 | #undef EAX | |
26 | #undef ECX | |
27 | #undef EDX | |
28 | #undef EBX | |
29 | #undef ESP | |
30 | #undef EBP | |
31 | #undef ESI | |
32 | #undef EDI | |
33 | #undef EIP | |
34 | #include <signal.h> | |
35 | #include <sys/ucontext.h> | |
36 | #endif | |
37 | ||
36bdbe54 FB |
38 | int tb_invalidated_flag; |
39 | ||
dc99065b | 40 | //#define DEBUG_EXEC |
9de5e440 | 41 | //#define DEBUG_SIGNAL |
7d13299d | 42 | |
93ac68bc | 43 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) |
e4533c7a FB |
44 | /* XXX: unify with i386 target */ |
45 | void cpu_loop_exit(void) | |
46 | { | |
47 | longjmp(env->jmp_env, 1); | |
48 | } | |
49 | #endif | |
50 | ||
fbf9eeb3 FB |
51 | /* exit the current TB from a signal handler. The host registers are |
52 | restored in a state compatible with the CPU emulator | |
53 | */ | |
54 | void cpu_resume_from_signal(CPUState *env1, void *puc) | |
55 | { | |
56 | #if !defined(CONFIG_SOFTMMU) | |
57 | struct ucontext *uc = puc; | |
58 | #endif | |
59 | ||
60 | env = env1; | |
61 | ||
62 | /* XXX: restore cpu registers saved in host registers */ | |
63 | ||
64 | #if !defined(CONFIG_SOFTMMU) | |
65 | if (puc) { | |
66 | /* XXX: use siglongjmp ? */ | |
67 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); | |
68 | } | |
69 | #endif | |
70 | longjmp(env->jmp_env, 1); | |
71 | } | |
72 | ||
7d13299d FB |
73 | /* main execution loop */ |
74 | ||
e4533c7a | 75 | int cpu_exec(CPUState *env1) |
7d13299d | 76 | { |
e4533c7a FB |
77 | int saved_T0, saved_T1, saved_T2; |
78 | CPUState *saved_env; | |
04369ff2 FB |
79 | #ifdef reg_EAX |
80 | int saved_EAX; | |
81 | #endif | |
82 | #ifdef reg_ECX | |
83 | int saved_ECX; | |
84 | #endif | |
85 | #ifdef reg_EDX | |
86 | int saved_EDX; | |
87 | #endif | |
88 | #ifdef reg_EBX | |
89 | int saved_EBX; | |
90 | #endif | |
91 | #ifdef reg_ESP | |
92 | int saved_ESP; | |
93 | #endif | |
94 | #ifdef reg_EBP | |
95 | int saved_EBP; | |
96 | #endif | |
97 | #ifdef reg_ESI | |
98 | int saved_ESI; | |
99 | #endif | |
100 | #ifdef reg_EDI | |
101 | int saved_EDI; | |
8c6939c0 FB |
102 | #endif |
103 | #ifdef __sparc__ | |
104 | int saved_i7, tmp_T0; | |
04369ff2 | 105 | #endif |
68a79315 | 106 | int code_gen_size, ret, interrupt_request; |
7d13299d | 107 | void (*gen_func)(void); |
9de5e440 | 108 | TranslationBlock *tb, **ptb; |
c27004ec FB |
109 | target_ulong cs_base, pc; |
110 | uint8_t *tc_ptr; | |
6dbad63e | 111 | unsigned int flags; |
8c6939c0 | 112 | |
7d13299d | 113 | /* first we save global registers */ |
c27004ec FB |
114 | saved_env = env; |
115 | env = env1; | |
7d13299d FB |
116 | saved_T0 = T0; |
117 | saved_T1 = T1; | |
e4533c7a | 118 | saved_T2 = T2; |
e4533c7a FB |
119 | #ifdef __sparc__ |
120 | /* we also save i7 because longjmp may not restore it */ | |
121 | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); | |
122 | #endif | |
123 | ||
124 | #if defined(TARGET_I386) | |
04369ff2 FB |
125 | #ifdef reg_EAX |
126 | saved_EAX = EAX; | |
04369ff2 FB |
127 | #endif |
128 | #ifdef reg_ECX | |
129 | saved_ECX = ECX; | |
04369ff2 FB |
130 | #endif |
131 | #ifdef reg_EDX | |
132 | saved_EDX = EDX; | |
04369ff2 FB |
133 | #endif |
134 | #ifdef reg_EBX | |
135 | saved_EBX = EBX; | |
04369ff2 FB |
136 | #endif |
137 | #ifdef reg_ESP | |
138 | saved_ESP = ESP; | |
04369ff2 FB |
139 | #endif |
140 | #ifdef reg_EBP | |
141 | saved_EBP = EBP; | |
04369ff2 FB |
142 | #endif |
143 | #ifdef reg_ESI | |
144 | saved_ESI = ESI; | |
04369ff2 FB |
145 | #endif |
146 | #ifdef reg_EDI | |
147 | saved_EDI = EDI; | |
04369ff2 | 148 | #endif |
0d1a29f9 FB |
149 | |
150 | env_to_regs(); | |
9de5e440 | 151 | /* put eflags in CPU temporary format */ |
fc2b4c48 FB |
152 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
153 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); | |
9de5e440 | 154 | CC_OP = CC_OP_EFLAGS; |
fc2b4c48 | 155 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e4533c7a FB |
156 | #elif defined(TARGET_ARM) |
157 | { | |
158 | unsigned int psr; | |
159 | psr = env->cpsr; | |
160 | env->CF = (psr >> 29) & 1; | |
161 | env->NZF = (psr & 0xc0000000) ^ 0x40000000; | |
162 | env->VF = (psr << 3) & 0x80000000; | |
99c475ab FB |
163 | env->QF = (psr >> 27) & 1; |
164 | env->cpsr = psr & ~CACHED_CPSR_BITS; | |
e4533c7a | 165 | } |
93ac68bc | 166 | #elif defined(TARGET_SPARC) |
67867308 | 167 | #elif defined(TARGET_PPC) |
e4533c7a FB |
168 | #else |
169 | #error unsupported target CPU | |
170 | #endif | |
3fb2ded1 | 171 | env->exception_index = -1; |
9d27abd9 | 172 | |
7d13299d | 173 | /* prepare setjmp context for exception handling */ |
3fb2ded1 FB |
174 | for(;;) { |
175 | if (setjmp(env->jmp_env) == 0) { | |
ee8b7021 | 176 | env->current_tb = NULL; |
3fb2ded1 FB |
177 | /* if an exception is pending, we execute it here */ |
178 | if (env->exception_index >= 0) { | |
179 | if (env->exception_index >= EXCP_INTERRUPT) { | |
180 | /* exit request from the cpu execution loop */ | |
181 | ret = env->exception_index; | |
182 | break; | |
183 | } else if (env->user_mode_only) { | |
184 | /* if user mode only, we simulate a fake exception | |
185 | which will be hanlded outside the cpu execution | |
186 | loop */ | |
83479e77 | 187 | #if defined(TARGET_I386) |
3fb2ded1 FB |
188 | do_interrupt_user(env->exception_index, |
189 | env->exception_is_int, | |
190 | env->error_code, | |
191 | env->exception_next_eip); | |
83479e77 | 192 | #endif |
3fb2ded1 FB |
193 | ret = env->exception_index; |
194 | break; | |
195 | } else { | |
83479e77 | 196 | #if defined(TARGET_I386) |
3fb2ded1 FB |
197 | /* simulate a real cpu exception. On i386, it can |
198 | trigger new exceptions, but we do not handle | |
199 | double or triple faults yet. */ | |
200 | do_interrupt(env->exception_index, | |
201 | env->exception_is_int, | |
202 | env->error_code, | |
d05e66d2 | 203 | env->exception_next_eip, 0); |
ce09776b FB |
204 | #elif defined(TARGET_PPC) |
205 | do_interrupt(env); | |
e95c8d51 | 206 | #elif defined(TARGET_SPARC) |
1a0c3292 | 207 | do_interrupt(env->exception_index); |
83479e77 | 208 | #endif |
3fb2ded1 FB |
209 | } |
210 | env->exception_index = -1; | |
9df217a3 FB |
211 | } |
212 | #ifdef USE_KQEMU | |
213 | if (kqemu_is_ok(env) && env->interrupt_request == 0) { | |
214 | int ret; | |
215 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); | |
216 | ret = kqemu_cpu_exec(env); | |
217 | /* put eflags in CPU temporary format */ | |
218 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
219 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); | |
220 | CC_OP = CC_OP_EFLAGS; | |
221 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
222 | if (ret == 1) { | |
223 | /* exception */ | |
224 | longjmp(env->jmp_env, 1); | |
225 | } else if (ret == 2) { | |
226 | /* softmmu execution needed */ | |
227 | } else { | |
228 | if (env->interrupt_request != 0) { | |
229 | /* hardware interrupt will be executed just after */ | |
230 | } else { | |
231 | /* otherwise, we restart */ | |
232 | longjmp(env->jmp_env, 1); | |
233 | } | |
234 | } | |
3fb2ded1 | 235 | } |
9df217a3 FB |
236 | #endif |
237 | ||
3fb2ded1 FB |
238 | T0 = 0; /* force lookup of first TB */ |
239 | for(;;) { | |
8c6939c0 | 240 | #ifdef __sparc__ |
3fb2ded1 FB |
241 | /* g1 can be modified by some libc? functions */ |
242 | tmp_T0 = T0; | |
8c6939c0 | 243 | #endif |
68a79315 | 244 | interrupt_request = env->interrupt_request; |
2e255c6b | 245 | if (__builtin_expect(interrupt_request, 0)) { |
68a79315 FB |
246 | #if defined(TARGET_I386) |
247 | /* if hardware interrupt pending, we execute it */ | |
248 | if ((interrupt_request & CPU_INTERRUPT_HARD) && | |
3f337316 FB |
249 | (env->eflags & IF_MASK) && |
250 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { | |
68a79315 | 251 | int intno; |
fbf9eeb3 | 252 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
a541f297 | 253 | intno = cpu_get_pic_interrupt(env); |
f193c797 | 254 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
68a79315 FB |
255 | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); |
256 | } | |
d05e66d2 | 257 | do_interrupt(intno, 0, 0, 0, 1); |
907a5b26 FB |
258 | /* ensure that no TB jump will be modified as |
259 | the program flow was changed */ | |
260 | #ifdef __sparc__ | |
261 | tmp_T0 = 0; | |
262 | #else | |
263 | T0 = 0; | |
264 | #endif | |
68a79315 | 265 | } |
ce09776b | 266 | #elif defined(TARGET_PPC) |
9fddaa0c FB |
267 | #if 0 |
268 | if ((interrupt_request & CPU_INTERRUPT_RESET)) { | |
269 | cpu_ppc_reset(env); | |
270 | } | |
271 | #endif | |
272 | if (msr_ee != 0) { | |
ce09776b | 273 | if ((interrupt_request & CPU_INTERRUPT_HARD)) { |
9fddaa0c FB |
274 | /* Raise it */ |
275 | env->exception_index = EXCP_EXTERNAL; | |
276 | env->error_code = 0; | |
ce09776b FB |
277 | do_interrupt(env); |
278 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
9fddaa0c FB |
279 | } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) { |
280 | /* Raise it */ | |
281 | env->exception_index = EXCP_DECR; | |
282 | env->error_code = 0; | |
283 | do_interrupt(env); | |
284 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; | |
285 | } | |
ce09776b | 286 | } |
e95c8d51 | 287 | #elif defined(TARGET_SPARC) |
66321a11 FB |
288 | if ((interrupt_request & CPU_INTERRUPT_HARD) && |
289 | (env->psret != 0)) { | |
290 | int pil = env->interrupt_index & 15; | |
291 | int type = env->interrupt_index & 0xf0; | |
292 | ||
293 | if (((type == TT_EXTINT) && | |
294 | (pil == 15 || pil > env->psrpil)) || | |
295 | type != TT_EXTINT) { | |
296 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
297 | do_interrupt(env->interrupt_index); | |
298 | env->interrupt_index = 0; | |
299 | } | |
e95c8d51 FB |
300 | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
301 | //do_interrupt(0, 0, 0, 0, 0); | |
302 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; | |
303 | } | |
68a79315 | 304 | #endif |
bf3e8bf1 FB |
305 | if (interrupt_request & CPU_INTERRUPT_EXITTB) { |
306 | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; | |
307 | /* ensure that no TB jump will be modified as | |
308 | the program flow was changed */ | |
309 | #ifdef __sparc__ | |
310 | tmp_T0 = 0; | |
311 | #else | |
312 | T0 = 0; | |
313 | #endif | |
314 | } | |
68a79315 FB |
315 | if (interrupt_request & CPU_INTERRUPT_EXIT) { |
316 | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; | |
317 | env->exception_index = EXCP_INTERRUPT; | |
318 | cpu_loop_exit(); | |
319 | } | |
3fb2ded1 | 320 | } |
7d13299d | 321 | #ifdef DEBUG_EXEC |
c27004ec | 322 | if ((loglevel & CPU_LOG_EXEC)) { |
e4533c7a | 323 | #if defined(TARGET_I386) |
3fb2ded1 FB |
324 | /* restore flags in standard format */ |
325 | env->regs[R_EAX] = EAX; | |
326 | env->regs[R_EBX] = EBX; | |
327 | env->regs[R_ECX] = ECX; | |
328 | env->regs[R_EDX] = EDX; | |
329 | env->regs[R_ESI] = ESI; | |
330 | env->regs[R_EDI] = EDI; | |
331 | env->regs[R_EBP] = EBP; | |
332 | env->regs[R_ESP] = ESP; | |
333 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); | |
7fe48483 | 334 | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
3fb2ded1 | 335 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e4533c7a | 336 | #elif defined(TARGET_ARM) |
1b21b62a | 337 | env->cpsr = compute_cpsr(); |
7fe48483 | 338 | cpu_dump_state(env, logfile, fprintf, 0); |
99c475ab | 339 | env->cpsr &= ~CACHED_CPSR_BITS; |
93ac68bc | 340 | #elif defined(TARGET_SPARC) |
7fe48483 | 341 | cpu_dump_state (env, logfile, fprintf, 0); |
67867308 | 342 | #elif defined(TARGET_PPC) |
7fe48483 | 343 | cpu_dump_state(env, logfile, fprintf, 0); |
e4533c7a FB |
344 | #else |
345 | #error unsupported target CPU | |
346 | #endif | |
3fb2ded1 | 347 | } |
7d13299d | 348 | #endif |
3f337316 FB |
349 | /* we record a subset of the CPU state. It will |
350 | always be the same before a given translated block | |
351 | is executed. */ | |
e4533c7a | 352 | #if defined(TARGET_I386) |
2e255c6b | 353 | flags = env->hflags; |
3f337316 | 354 | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
3fb2ded1 FB |
355 | cs_base = env->segs[R_CS].base; |
356 | pc = cs_base + env->eip; | |
e4533c7a | 357 | #elif defined(TARGET_ARM) |
b7bcbe95 FB |
358 | flags = env->thumb | (env->vfp.vec_len << 1) |
359 | | (env->vfp.vec_stride << 4); | |
3fb2ded1 | 360 | cs_base = 0; |
c27004ec | 361 | pc = env->regs[15]; |
93ac68bc | 362 | #elif defined(TARGET_SPARC) |
67867308 | 363 | flags = 0; |
c27004ec FB |
364 | cs_base = env->npc; |
365 | pc = env->pc; | |
67867308 | 366 | #elif defined(TARGET_PPC) |
111bfab3 FB |
367 | flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) | |
368 | (msr_se << MSR_SE) | (msr_le << MSR_LE); | |
67867308 | 369 | cs_base = 0; |
c27004ec | 370 | pc = env->nip; |
e4533c7a FB |
371 | #else |
372 | #error unsupported CPU | |
373 | #endif | |
c27004ec | 374 | tb = tb_find(&ptb, pc, cs_base, |
3fb2ded1 | 375 | flags); |
d4e8164f | 376 | if (!tb) { |
1376847f FB |
377 | TranslationBlock **ptb1; |
378 | unsigned int h; | |
379 | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; | |
380 | ||
381 | ||
3fb2ded1 | 382 | spin_lock(&tb_lock); |
1376847f FB |
383 | |
384 | tb_invalidated_flag = 0; | |
0d1a29f9 FB |
385 | |
386 | regs_to_env(); /* XXX: do it just before cpu_gen_code() */ | |
1376847f FB |
387 | |
388 | /* find translated block using physical mappings */ | |
c27004ec | 389 | phys_pc = get_phys_addr_code(env, pc); |
1376847f FB |
390 | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
391 | phys_page2 = -1; | |
392 | h = tb_phys_hash_func(phys_pc); | |
393 | ptb1 = &tb_phys_hash[h]; | |
394 | for(;;) { | |
395 | tb = *ptb1; | |
396 | if (!tb) | |
397 | goto not_found; | |
c27004ec | 398 | if (tb->pc == pc && |
1376847f | 399 | tb->page_addr[0] == phys_page1 && |
c27004ec | 400 | tb->cs_base == cs_base && |
1376847f FB |
401 | tb->flags == flags) { |
402 | /* check next page if needed */ | |
b516f85c | 403 | if (tb->page_addr[1] != -1) { |
c27004ec | 404 | virt_page2 = (pc & TARGET_PAGE_MASK) + |
b516f85c | 405 | TARGET_PAGE_SIZE; |
1376847f FB |
406 | phys_page2 = get_phys_addr_code(env, virt_page2); |
407 | if (tb->page_addr[1] == phys_page2) | |
408 | goto found; | |
409 | } else { | |
410 | goto found; | |
411 | } | |
412 | } | |
413 | ptb1 = &tb->phys_hash_next; | |
414 | } | |
415 | not_found: | |
3fb2ded1 | 416 | /* if no translated code available, then translate it now */ |
c27004ec | 417 | tb = tb_alloc(pc); |
3fb2ded1 FB |
418 | if (!tb) { |
419 | /* flush must be done */ | |
b453b70b | 420 | tb_flush(env); |
3fb2ded1 | 421 | /* cannot fail at this point */ |
c27004ec | 422 | tb = tb_alloc(pc); |
3fb2ded1 | 423 | /* don't forget to invalidate previous TB info */ |
c27004ec | 424 | ptb = &tb_hash[tb_hash_func(pc)]; |
3fb2ded1 FB |
425 | T0 = 0; |
426 | } | |
427 | tc_ptr = code_gen_ptr; | |
428 | tb->tc_ptr = tc_ptr; | |
c27004ec | 429 | tb->cs_base = cs_base; |
3fb2ded1 | 430 | tb->flags = flags; |
facc68be | 431 | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
1376847f FB |
432 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
433 | ||
434 | /* check next page if needed */ | |
c27004ec | 435 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
1376847f | 436 | phys_page2 = -1; |
c27004ec | 437 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
1376847f FB |
438 | phys_page2 = get_phys_addr_code(env, virt_page2); |
439 | } | |
440 | tb_link_phys(tb, phys_pc, phys_page2); | |
441 | ||
442 | found: | |
36bdbe54 FB |
443 | if (tb_invalidated_flag) { |
444 | /* as some TB could have been invalidated because | |
445 | of memory exceptions while generating the code, we | |
446 | must recompute the hash index here */ | |
c27004ec | 447 | ptb = &tb_hash[tb_hash_func(pc)]; |
36bdbe54 FB |
448 | while (*ptb != NULL) |
449 | ptb = &(*ptb)->hash_next; | |
450 | T0 = 0; | |
451 | } | |
1376847f | 452 | /* we add the TB in the virtual pc hash table */ |
3fb2ded1 FB |
453 | *ptb = tb; |
454 | tb->hash_next = NULL; | |
455 | tb_link(tb); | |
25eb4484 | 456 | spin_unlock(&tb_lock); |
9de5e440 | 457 | } |
9d27abd9 | 458 | #ifdef DEBUG_EXEC |
c1135f61 | 459 | if ((loglevel & CPU_LOG_EXEC)) { |
c27004ec FB |
460 | fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
461 | (long)tb->tc_ptr, tb->pc, | |
462 | lookup_symbol(tb->pc)); | |
3fb2ded1 | 463 | } |
9d27abd9 | 464 | #endif |
8c6939c0 | 465 | #ifdef __sparc__ |
3fb2ded1 | 466 | T0 = tmp_T0; |
8c6939c0 | 467 | #endif |
facc68be | 468 | /* see if we can patch the calling TB. */ |
c27004ec FB |
469 | { |
470 | if (T0 != 0 | |
bf3e8bf1 FB |
471 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) |
472 | && (tb->cflags & CF_CODE_COPY) == | |
473 | (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY) | |
474 | #endif | |
475 | ) { | |
3fb2ded1 | 476 | spin_lock(&tb_lock); |
c27004ec | 477 | tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); |
97eb5b14 FB |
478 | #if defined(USE_CODE_COPY) |
479 | /* propagates the FP use info */ | |
480 | ((TranslationBlock *)(T0 & ~3))->cflags |= | |
481 | (tb->cflags & CF_FP_USED); | |
482 | #endif | |
3fb2ded1 FB |
483 | spin_unlock(&tb_lock); |
484 | } | |
c27004ec | 485 | } |
3fb2ded1 | 486 | tc_ptr = tb->tc_ptr; |
83479e77 | 487 | env->current_tb = tb; |
3fb2ded1 FB |
488 | /* execute the generated code */ |
489 | gen_func = (void *)tc_ptr; | |
8c6939c0 | 490 | #if defined(__sparc__) |
3fb2ded1 FB |
491 | __asm__ __volatile__("call %0\n\t" |
492 | "mov %%o7,%%i0" | |
493 | : /* no outputs */ | |
494 | : "r" (gen_func) | |
495 | : "i0", "i1", "i2", "i3", "i4", "i5"); | |
8c6939c0 | 496 | #elif defined(__arm__) |
3fb2ded1 FB |
497 | asm volatile ("mov pc, %0\n\t" |
498 | ".global exec_loop\n\t" | |
499 | "exec_loop:\n\t" | |
500 | : /* no outputs */ | |
501 | : "r" (gen_func) | |
502 | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); | |
bf3e8bf1 FB |
503 | #elif defined(TARGET_I386) && defined(USE_CODE_COPY) |
504 | { | |
505 | if (!(tb->cflags & CF_CODE_COPY)) { | |
97eb5b14 FB |
506 | if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) { |
507 | save_native_fp_state(env); | |
508 | } | |
bf3e8bf1 FB |
509 | gen_func(); |
510 | } else { | |
97eb5b14 FB |
511 | if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) { |
512 | restore_native_fp_state(env); | |
513 | } | |
bf3e8bf1 FB |
514 | /* we work with native eflags */ |
515 | CC_SRC = cc_table[CC_OP].compute_all(); | |
516 | CC_OP = CC_OP_EFLAGS; | |
517 | asm(".globl exec_loop\n" | |
518 | "\n" | |
519 | "debug1:\n" | |
520 | " pushl %%ebp\n" | |
521 | " fs movl %10, %9\n" | |
522 | " fs movl %11, %%eax\n" | |
523 | " andl $0x400, %%eax\n" | |
524 | " fs orl %8, %%eax\n" | |
525 | " pushl %%eax\n" | |
526 | " popf\n" | |
527 | " fs movl %%esp, %12\n" | |
528 | " fs movl %0, %%eax\n" | |
529 | " fs movl %1, %%ecx\n" | |
530 | " fs movl %2, %%edx\n" | |
531 | " fs movl %3, %%ebx\n" | |
532 | " fs movl %4, %%esp\n" | |
533 | " fs movl %5, %%ebp\n" | |
534 | " fs movl %6, %%esi\n" | |
535 | " fs movl %7, %%edi\n" | |
536 | " fs jmp *%9\n" | |
537 | "exec_loop:\n" | |
538 | " fs movl %%esp, %4\n" | |
539 | " fs movl %12, %%esp\n" | |
540 | " fs movl %%eax, %0\n" | |
541 | " fs movl %%ecx, %1\n" | |
542 | " fs movl %%edx, %2\n" | |
543 | " fs movl %%ebx, %3\n" | |
544 | " fs movl %%ebp, %5\n" | |
545 | " fs movl %%esi, %6\n" | |
546 | " fs movl %%edi, %7\n" | |
547 | " pushf\n" | |
548 | " popl %%eax\n" | |
549 | " movl %%eax, %%ecx\n" | |
550 | " andl $0x400, %%ecx\n" | |
551 | " shrl $9, %%ecx\n" | |
552 | " andl $0x8d5, %%eax\n" | |
553 | " fs movl %%eax, %8\n" | |
554 | " movl $1, %%eax\n" | |
555 | " subl %%ecx, %%eax\n" | |
556 | " fs movl %%eax, %11\n" | |
557 | " fs movl %9, %%ebx\n" /* get T0 value */ | |
558 | " popl %%ebp\n" | |
559 | : | |
560 | : "m" (*(uint8_t *)offsetof(CPUState, regs[0])), | |
561 | "m" (*(uint8_t *)offsetof(CPUState, regs[1])), | |
562 | "m" (*(uint8_t *)offsetof(CPUState, regs[2])), | |
563 | "m" (*(uint8_t *)offsetof(CPUState, regs[3])), | |
564 | "m" (*(uint8_t *)offsetof(CPUState, regs[4])), | |
565 | "m" (*(uint8_t *)offsetof(CPUState, regs[5])), | |
566 | "m" (*(uint8_t *)offsetof(CPUState, regs[6])), | |
567 | "m" (*(uint8_t *)offsetof(CPUState, regs[7])), | |
568 | "m" (*(uint8_t *)offsetof(CPUState, cc_src)), | |
569 | "m" (*(uint8_t *)offsetof(CPUState, tmp0)), | |
570 | "a" (gen_func), | |
571 | "m" (*(uint8_t *)offsetof(CPUState, df)), | |
572 | "m" (*(uint8_t *)offsetof(CPUState, saved_esp)) | |
573 | : "%ecx", "%edx" | |
574 | ); | |
575 | } | |
576 | } | |
b8076a74 FB |
577 | #elif defined(__ia64) |
578 | struct fptr { | |
579 | void *ip; | |
580 | void *gp; | |
581 | } fp; | |
582 | ||
583 | fp.ip = tc_ptr; | |
584 | fp.gp = code_gen_buffer + 2 * (1 << 20); | |
585 | (*(void (*)(void)) &fp)(); | |
ae228531 | 586 | #else |
3fb2ded1 | 587 | gen_func(); |
ae228531 | 588 | #endif |
83479e77 | 589 | env->current_tb = NULL; |
4cbf74b6 FB |
590 | /* reset soft MMU for next block (it can currently |
591 | only be set by a memory fault) */ | |
592 | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU) | |
3f337316 FB |
593 | if (env->hflags & HF_SOFTMMU_MASK) { |
594 | env->hflags &= ~HF_SOFTMMU_MASK; | |
4cbf74b6 FB |
595 | /* do not allow linking to another block */ |
596 | T0 = 0; | |
597 | } | |
598 | #endif | |
3fb2ded1 FB |
599 | } |
600 | } else { | |
0d1a29f9 | 601 | env_to_regs(); |
7d13299d | 602 | } |
3fb2ded1 FB |
603 | } /* for(;;) */ |
604 | ||
7d13299d | 605 | |
e4533c7a | 606 | #if defined(TARGET_I386) |
97eb5b14 FB |
607 | #if defined(USE_CODE_COPY) |
608 | if (env->native_fp_regs) { | |
609 | save_native_fp_state(env); | |
610 | } | |
611 | #endif | |
9de5e440 | 612 | /* restore flags in standard format */ |
fc2b4c48 | 613 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
9de5e440 | 614 | |
7d13299d | 615 | /* restore global registers */ |
04369ff2 FB |
616 | #ifdef reg_EAX |
617 | EAX = saved_EAX; | |
618 | #endif | |
619 | #ifdef reg_ECX | |
620 | ECX = saved_ECX; | |
621 | #endif | |
622 | #ifdef reg_EDX | |
623 | EDX = saved_EDX; | |
624 | #endif | |
625 | #ifdef reg_EBX | |
626 | EBX = saved_EBX; | |
627 | #endif | |
628 | #ifdef reg_ESP | |
629 | ESP = saved_ESP; | |
630 | #endif | |
631 | #ifdef reg_EBP | |
632 | EBP = saved_EBP; | |
633 | #endif | |
634 | #ifdef reg_ESI | |
635 | ESI = saved_ESI; | |
636 | #endif | |
637 | #ifdef reg_EDI | |
638 | EDI = saved_EDI; | |
8c6939c0 | 639 | #endif |
e4533c7a | 640 | #elif defined(TARGET_ARM) |
1b21b62a | 641 | env->cpsr = compute_cpsr(); |
b7bcbe95 | 642 | /* XXX: Save/restore host fpu exception state?. */ |
93ac68bc | 643 | #elif defined(TARGET_SPARC) |
67867308 | 644 | #elif defined(TARGET_PPC) |
e4533c7a FB |
645 | #else |
646 | #error unsupported target CPU | |
647 | #endif | |
8c6939c0 FB |
648 | #ifdef __sparc__ |
649 | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); | |
04369ff2 | 650 | #endif |
7d13299d FB |
651 | T0 = saved_T0; |
652 | T1 = saved_T1; | |
e4533c7a | 653 | T2 = saved_T2; |
7d13299d FB |
654 | env = saved_env; |
655 | return ret; | |
656 | } | |
6dbad63e | 657 | |
fbf9eeb3 FB |
658 | /* must only be called from the generated code as an exception can be |
659 | generated */ | |
660 | void tb_invalidate_page_range(target_ulong start, target_ulong end) | |
661 | { | |
dc5d0b3d FB |
662 | /* XXX: cannot enable it yet because it yields to MMU exception |
663 | where NIP != read address on PowerPC */ | |
664 | #if 0 | |
fbf9eeb3 FB |
665 | target_ulong phys_addr; |
666 | phys_addr = get_phys_addr_code(env, start); | |
667 | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0); | |
dc5d0b3d | 668 | #endif |
fbf9eeb3 FB |
669 | } |
670 | ||
1a18c71b | 671 | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY) |
e4533c7a | 672 | |
6dbad63e FB |
673 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
674 | { | |
675 | CPUX86State *saved_env; | |
676 | ||
677 | saved_env = env; | |
678 | env = s; | |
a412ac57 | 679 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
a513fe19 | 680 | selector &= 0xffff; |
2e255c6b | 681 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
c27004ec | 682 | (selector << 4), 0xffff, 0); |
a513fe19 | 683 | } else { |
b453b70b | 684 | load_seg(seg_reg, selector); |
a513fe19 | 685 | } |
6dbad63e FB |
686 | env = saved_env; |
687 | } | |
9de5e440 | 688 | |
d0a1ffc9 FB |
689 | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
690 | { | |
691 | CPUX86State *saved_env; | |
692 | ||
693 | saved_env = env; | |
694 | env = s; | |
695 | ||
c27004ec | 696 | helper_fsave((target_ulong)ptr, data32); |
d0a1ffc9 FB |
697 | |
698 | env = saved_env; | |
699 | } | |
700 | ||
701 | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) | |
702 | { | |
703 | CPUX86State *saved_env; | |
704 | ||
705 | saved_env = env; | |
706 | env = s; | |
707 | ||
c27004ec | 708 | helper_frstor((target_ulong)ptr, data32); |
d0a1ffc9 FB |
709 | |
710 | env = saved_env; | |
711 | } | |
712 | ||
e4533c7a FB |
713 | #endif /* TARGET_I386 */ |
714 | ||
67b915a5 FB |
715 | #if !defined(CONFIG_SOFTMMU) |
716 | ||
3fb2ded1 FB |
717 | #if defined(TARGET_I386) |
718 | ||
b56dad1c | 719 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
fd6ce8f6 FB |
720 | the effective address of the memory exception. 'is_write' is 1 if a |
721 | write caused the exception and otherwise 0'. 'old_set' is the | |
722 | signal set which should be restored */ | |
2b413144 | 723 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bf3e8bf1 FB |
724 | int is_write, sigset_t *old_set, |
725 | void *puc) | |
9de5e440 | 726 | { |
a513fe19 FB |
727 | TranslationBlock *tb; |
728 | int ret; | |
68a79315 | 729 | |
83479e77 FB |
730 | if (cpu_single_env) |
731 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
fd6ce8f6 | 732 | #if defined(DEBUG_SIGNAL) |
bf3e8bf1 FB |
733 | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
734 | pc, address, is_write, *(unsigned long *)old_set); | |
9de5e440 | 735 | #endif |
25eb4484 | 736 | /* XXX: locking issue */ |
fbf9eeb3 | 737 | if (is_write && page_unprotect(address, pc, puc)) { |
fd6ce8f6 FB |
738 | return 1; |
739 | } | |
fbf9eeb3 | 740 | |
3fb2ded1 | 741 | /* see if it is an MMU fault */ |
93a40ea9 FB |
742 | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
743 | ((env->hflags & HF_CPL_MASK) == 3), 0); | |
3fb2ded1 FB |
744 | if (ret < 0) |
745 | return 0; /* not an MMU fault */ | |
746 | if (ret == 0) | |
747 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
748 | /* now we have a real cpu fault */ | |
a513fe19 FB |
749 | tb = tb_find_pc(pc); |
750 | if (tb) { | |
9de5e440 FB |
751 | /* the PC is inside the translated code. It means that we have |
752 | a virtual CPU fault */ | |
bf3e8bf1 | 753 | cpu_restore_state(tb, env, pc, puc); |
3fb2ded1 | 754 | } |
4cbf74b6 | 755 | if (ret == 1) { |
3fb2ded1 | 756 | #if 0 |
4cbf74b6 FB |
757 | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", |
758 | env->eip, env->cr[2], env->error_code); | |
3fb2ded1 | 759 | #endif |
4cbf74b6 FB |
760 | /* we restore the process signal mask as the sigreturn should |
761 | do it (XXX: use sigsetjmp) */ | |
762 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
763 | raise_exception_err(EXCP0E_PAGE, env->error_code); | |
764 | } else { | |
765 | /* activate soft MMU for this block */ | |
3f337316 | 766 | env->hflags |= HF_SOFTMMU_MASK; |
fbf9eeb3 | 767 | cpu_resume_from_signal(env, puc); |
4cbf74b6 | 768 | } |
3fb2ded1 FB |
769 | /* never comes here */ |
770 | return 1; | |
771 | } | |
772 | ||
e4533c7a | 773 | #elif defined(TARGET_ARM) |
3fb2ded1 | 774 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bf3e8bf1 FB |
775 | int is_write, sigset_t *old_set, |
776 | void *puc) | |
3fb2ded1 | 777 | { |
68016c62 FB |
778 | TranslationBlock *tb; |
779 | int ret; | |
780 | ||
781 | if (cpu_single_env) | |
782 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
783 | #if defined(DEBUG_SIGNAL) | |
784 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
785 | pc, address, is_write, *(unsigned long *)old_set); | |
786 | #endif | |
9f0777ed FB |
787 | /* XXX: locking issue */ |
788 | if (is_write && page_unprotect(address, pc, puc)) { | |
789 | return 1; | |
790 | } | |
68016c62 FB |
791 | /* see if it is an MMU fault */ |
792 | ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0); | |
793 | if (ret < 0) | |
794 | return 0; /* not an MMU fault */ | |
795 | if (ret == 0) | |
796 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
797 | /* now we have a real cpu fault */ | |
798 | tb = tb_find_pc(pc); | |
799 | if (tb) { | |
800 | /* the PC is inside the translated code. It means that we have | |
801 | a virtual CPU fault */ | |
802 | cpu_restore_state(tb, env, pc, puc); | |
803 | } | |
804 | /* we restore the process signal mask as the sigreturn should | |
805 | do it (XXX: use sigsetjmp) */ | |
806 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
807 | cpu_loop_exit(); | |
3fb2ded1 | 808 | } |
93ac68bc FB |
809 | #elif defined(TARGET_SPARC) |
810 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
bf3e8bf1 FB |
811 | int is_write, sigset_t *old_set, |
812 | void *puc) | |
93ac68bc | 813 | { |
68016c62 FB |
814 | TranslationBlock *tb; |
815 | int ret; | |
816 | ||
817 | if (cpu_single_env) | |
818 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
819 | #if defined(DEBUG_SIGNAL) | |
820 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
821 | pc, address, is_write, *(unsigned long *)old_set); | |
822 | #endif | |
b453b70b | 823 | /* XXX: locking issue */ |
fbf9eeb3 | 824 | if (is_write && page_unprotect(address, pc, puc)) { |
b453b70b FB |
825 | return 1; |
826 | } | |
68016c62 FB |
827 | /* see if it is an MMU fault */ |
828 | ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0); | |
829 | if (ret < 0) | |
830 | return 0; /* not an MMU fault */ | |
831 | if (ret == 0) | |
832 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
833 | /* now we have a real cpu fault */ | |
834 | tb = tb_find_pc(pc); | |
835 | if (tb) { | |
836 | /* the PC is inside the translated code. It means that we have | |
837 | a virtual CPU fault */ | |
838 | cpu_restore_state(tb, env, pc, puc); | |
839 | } | |
840 | /* we restore the process signal mask as the sigreturn should | |
841 | do it (XXX: use sigsetjmp) */ | |
842 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
843 | cpu_loop_exit(); | |
93ac68bc | 844 | } |
67867308 FB |
845 | #elif defined (TARGET_PPC) |
846 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
bf3e8bf1 FB |
847 | int is_write, sigset_t *old_set, |
848 | void *puc) | |
67867308 FB |
849 | { |
850 | TranslationBlock *tb; | |
ce09776b | 851 | int ret; |
67867308 | 852 | |
67867308 FB |
853 | if (cpu_single_env) |
854 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
67867308 FB |
855 | #if defined(DEBUG_SIGNAL) |
856 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
857 | pc, address, is_write, *(unsigned long *)old_set); | |
858 | #endif | |
859 | /* XXX: locking issue */ | |
fbf9eeb3 | 860 | if (is_write && page_unprotect(address, pc, puc)) { |
67867308 FB |
861 | return 1; |
862 | } | |
863 | ||
ce09776b | 864 | /* see if it is an MMU fault */ |
7f957d28 | 865 | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0); |
ce09776b FB |
866 | if (ret < 0) |
867 | return 0; /* not an MMU fault */ | |
868 | if (ret == 0) | |
869 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
870 | ||
67867308 FB |
871 | /* now we have a real cpu fault */ |
872 | tb = tb_find_pc(pc); | |
873 | if (tb) { | |
874 | /* the PC is inside the translated code. It means that we have | |
875 | a virtual CPU fault */ | |
bf3e8bf1 | 876 | cpu_restore_state(tb, env, pc, puc); |
67867308 | 877 | } |
ce09776b | 878 | if (ret == 1) { |
67867308 | 879 | #if 0 |
ce09776b FB |
880 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
881 | env->nip, env->error_code, tb); | |
67867308 FB |
882 | #endif |
883 | /* we restore the process signal mask as the sigreturn should | |
884 | do it (XXX: use sigsetjmp) */ | |
bf3e8bf1 | 885 | sigprocmask(SIG_SETMASK, old_set, NULL); |
9fddaa0c | 886 | do_raise_exception_err(env->exception_index, env->error_code); |
ce09776b FB |
887 | } else { |
888 | /* activate soft MMU for this block */ | |
fbf9eeb3 | 889 | cpu_resume_from_signal(env, puc); |
ce09776b | 890 | } |
67867308 FB |
891 | /* never comes here */ |
892 | return 1; | |
893 | } | |
e4533c7a FB |
894 | #else |
895 | #error unsupported target CPU | |
896 | #endif | |
9de5e440 | 897 | |
2b413144 FB |
898 | #if defined(__i386__) |
899 | ||
bf3e8bf1 FB |
900 | #if defined(USE_CODE_COPY) |
901 | static void cpu_send_trap(unsigned long pc, int trap, | |
902 | struct ucontext *uc) | |
903 | { | |
904 | TranslationBlock *tb; | |
905 | ||
906 | if (cpu_single_env) | |
907 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
908 | /* now we have a real cpu fault */ | |
909 | tb = tb_find_pc(pc); | |
910 | if (tb) { | |
911 | /* the PC is inside the translated code. It means that we have | |
912 | a virtual CPU fault */ | |
913 | cpu_restore_state(tb, env, pc, uc); | |
914 | } | |
915 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); | |
916 | raise_exception_err(trap, env->error_code); | |
917 | } | |
918 | #endif | |
919 | ||
e4533c7a FB |
920 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
921 | void *puc) | |
9de5e440 | 922 | { |
9de5e440 FB |
923 | struct ucontext *uc = puc; |
924 | unsigned long pc; | |
bf3e8bf1 | 925 | int trapno; |
97eb5b14 | 926 | |
d691f669 FB |
927 | #ifndef REG_EIP |
928 | /* for glibc 2.1 */ | |
fd6ce8f6 FB |
929 | #define REG_EIP EIP |
930 | #define REG_ERR ERR | |
931 | #define REG_TRAPNO TRAPNO | |
d691f669 | 932 | #endif |
fc2b4c48 | 933 | pc = uc->uc_mcontext.gregs[REG_EIP]; |
bf3e8bf1 FB |
934 | trapno = uc->uc_mcontext.gregs[REG_TRAPNO]; |
935 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) | |
936 | if (trapno == 0x00 || trapno == 0x05) { | |
937 | /* send division by zero or bound exception */ | |
938 | cpu_send_trap(pc, trapno, uc); | |
939 | return 1; | |
940 | } else | |
941 | #endif | |
942 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
943 | trapno == 0xe ? | |
944 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, | |
945 | &uc->uc_sigmask, puc); | |
2b413144 FB |
946 | } |
947 | ||
bc51c5c9 FB |
948 | #elif defined(__x86_64__) |
949 | ||
950 | int cpu_signal_handler(int host_signum, struct siginfo *info, | |
951 | void *puc) | |
952 | { | |
953 | struct ucontext *uc = puc; | |
954 | unsigned long pc; | |
955 | ||
956 | pc = uc->uc_mcontext.gregs[REG_RIP]; | |
957 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
958 | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? | |
959 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, | |
960 | &uc->uc_sigmask, puc); | |
961 | } | |
962 | ||
83fb7adf | 963 | #elif defined(__powerpc__) |
2b413144 | 964 | |
83fb7adf FB |
965 | /*********************************************************************** |
966 | * signal context platform-specific definitions | |
967 | * From Wine | |
968 | */ | |
969 | #ifdef linux | |
970 | /* All Registers access - only for local access */ | |
971 | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name) | |
972 | /* Gpr Registers access */ | |
973 | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) | |
974 | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ | |
975 | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ | |
976 | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ | |
977 | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ | |
978 | # define LR_sig(context) REG_sig(link, context) /* Link register */ | |
979 | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ | |
980 | /* Float Registers access */ | |
981 | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) | |
982 | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) | |
983 | /* Exception Registers access */ | |
984 | # define DAR_sig(context) REG_sig(dar, context) | |
985 | # define DSISR_sig(context) REG_sig(dsisr, context) | |
986 | # define TRAP_sig(context) REG_sig(trap, context) | |
987 | #endif /* linux */ | |
988 | ||
989 | #ifdef __APPLE__ | |
990 | # include <sys/ucontext.h> | |
991 | typedef struct ucontext SIGCONTEXT; | |
992 | /* All Registers access - only for local access */ | |
993 | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name) | |
994 | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name) | |
995 | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name) | |
996 | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name) | |
997 | /* Gpr Registers access */ | |
998 | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) | |
999 | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ | |
1000 | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ | |
1001 | # define CTR_sig(context) REG_sig(ctr, context) | |
1002 | # define XER_sig(context) REG_sig(xer, context) /* Link register */ | |
1003 | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ | |
1004 | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ | |
1005 | /* Float Registers access */ | |
1006 | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context) | |
1007 | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) | |
1008 | /* Exception Registers access */ | |
1009 | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ | |
1010 | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context) | |
1011 | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ | |
1012 | #endif /* __APPLE__ */ | |
1013 | ||
d1d9f421 | 1014 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
e4533c7a | 1015 | void *puc) |
2b413144 | 1016 | { |
25eb4484 | 1017 | struct ucontext *uc = puc; |
25eb4484 | 1018 | unsigned long pc; |
25eb4484 FB |
1019 | int is_write; |
1020 | ||
83fb7adf | 1021 | pc = IAR_sig(uc); |
25eb4484 FB |
1022 | is_write = 0; |
1023 | #if 0 | |
1024 | /* ppc 4xx case */ | |
83fb7adf | 1025 | if (DSISR_sig(uc) & 0x00800000) |
25eb4484 FB |
1026 | is_write = 1; |
1027 | #else | |
83fb7adf | 1028 | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
25eb4484 FB |
1029 | is_write = 1; |
1030 | #endif | |
1031 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 1032 | is_write, &uc->uc_sigmask, puc); |
2b413144 FB |
1033 | } |
1034 | ||
2f87c607 FB |
1035 | #elif defined(__alpha__) |
1036 | ||
e4533c7a | 1037 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
2f87c607 FB |
1038 | void *puc) |
1039 | { | |
1040 | struct ucontext *uc = puc; | |
1041 | uint32_t *pc = uc->uc_mcontext.sc_pc; | |
1042 | uint32_t insn = *pc; | |
1043 | int is_write = 0; | |
1044 | ||
8c6939c0 | 1045 | /* XXX: need kernel patch to get write flag faster */ |
2f87c607 FB |
1046 | switch (insn >> 26) { |
1047 | case 0x0d: // stw | |
1048 | case 0x0e: // stb | |
1049 | case 0x0f: // stq_u | |
1050 | case 0x24: // stf | |
1051 | case 0x25: // stg | |
1052 | case 0x26: // sts | |
1053 | case 0x27: // stt | |
1054 | case 0x2c: // stl | |
1055 | case 0x2d: // stq | |
1056 | case 0x2e: // stl_c | |
1057 | case 0x2f: // stq_c | |
1058 | is_write = 1; | |
1059 | } | |
1060 | ||
1061 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 1062 | is_write, &uc->uc_sigmask, puc); |
2f87c607 | 1063 | } |
8c6939c0 FB |
1064 | #elif defined(__sparc__) |
1065 | ||
e4533c7a FB |
1066 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1067 | void *puc) | |
8c6939c0 FB |
1068 | { |
1069 | uint32_t *regs = (uint32_t *)(info + 1); | |
1070 | void *sigmask = (regs + 20); | |
1071 | unsigned long pc; | |
1072 | int is_write; | |
1073 | uint32_t insn; | |
1074 | ||
1075 | /* XXX: is there a standard glibc define ? */ | |
1076 | pc = regs[1]; | |
1077 | /* XXX: need kernel patch to get write flag faster */ | |
1078 | is_write = 0; | |
1079 | insn = *(uint32_t *)pc; | |
1080 | if ((insn >> 30) == 3) { | |
1081 | switch((insn >> 19) & 0x3f) { | |
1082 | case 0x05: // stb | |
1083 | case 0x06: // sth | |
1084 | case 0x04: // st | |
1085 | case 0x07: // std | |
1086 | case 0x24: // stf | |
1087 | case 0x27: // stdf | |
1088 | case 0x25: // stfsr | |
1089 | is_write = 1; | |
1090 | break; | |
1091 | } | |
1092 | } | |
1093 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 1094 | is_write, sigmask, NULL); |
8c6939c0 FB |
1095 | } |
1096 | ||
1097 | #elif defined(__arm__) | |
1098 | ||
e4533c7a FB |
1099 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1100 | void *puc) | |
8c6939c0 FB |
1101 | { |
1102 | struct ucontext *uc = puc; | |
1103 | unsigned long pc; | |
1104 | int is_write; | |
1105 | ||
1106 | pc = uc->uc_mcontext.gregs[R15]; | |
1107 | /* XXX: compute is_write */ | |
1108 | is_write = 0; | |
1109 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1110 | is_write, | |
1111 | &uc->uc_sigmask); | |
1112 | } | |
1113 | ||
38e584a0 FB |
1114 | #elif defined(__mc68000) |
1115 | ||
1116 | int cpu_signal_handler(int host_signum, struct siginfo *info, | |
1117 | void *puc) | |
1118 | { | |
1119 | struct ucontext *uc = puc; | |
1120 | unsigned long pc; | |
1121 | int is_write; | |
1122 | ||
1123 | pc = uc->uc_mcontext.gregs[16]; | |
1124 | /* XXX: compute is_write */ | |
1125 | is_write = 0; | |
1126 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1127 | is_write, | |
bf3e8bf1 | 1128 | &uc->uc_sigmask, puc); |
38e584a0 FB |
1129 | } |
1130 | ||
b8076a74 FB |
1131 | #elif defined(__ia64) |
1132 | ||
1133 | #ifndef __ISR_VALID | |
1134 | /* This ought to be in <bits/siginfo.h>... */ | |
1135 | # define __ISR_VALID 1 | |
1136 | # define si_flags _sifields._sigfault._si_pad0 | |
1137 | #endif | |
1138 | ||
1139 | int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc) | |
1140 | { | |
1141 | struct ucontext *uc = puc; | |
1142 | unsigned long ip; | |
1143 | int is_write = 0; | |
1144 | ||
1145 | ip = uc->uc_mcontext.sc_ip; | |
1146 | switch (host_signum) { | |
1147 | case SIGILL: | |
1148 | case SIGFPE: | |
1149 | case SIGSEGV: | |
1150 | case SIGBUS: | |
1151 | case SIGTRAP: | |
1152 | if (info->si_code && (info->si_flags & __ISR_VALID)) | |
1153 | /* ISR.W (write-access) is bit 33: */ | |
1154 | is_write = (info->si_isr >> 33) & 1; | |
1155 | break; | |
1156 | ||
1157 | default: | |
1158 | break; | |
1159 | } | |
1160 | return handle_cpu_signal(ip, (unsigned long)info->si_addr, | |
1161 | is_write, | |
1162 | &uc->uc_sigmask, puc); | |
1163 | } | |
1164 | ||
9de5e440 | 1165 | #else |
2b413144 | 1166 | |
3fb2ded1 | 1167 | #error host CPU specific signal handler needed |
2b413144 | 1168 | |
9de5e440 | 1169 | #endif |
67b915a5 FB |
1170 | |
1171 | #endif /* !defined(CONFIG_SOFTMMU) */ |