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7d13299d
FB		 1/*
2 * i386 emulator main execution loop
3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0
FB		 16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d 19 */
e4533c7a 20#include "config.h"
93ac68bc 21#include "exec.h"
956034d7 22#include "disas.h"
7d13299d 23
fbf9eeb3
FB		 24#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
36bdbe54
FB		 38int tb_invalidated_flag;
39
dc99065b 40//#define DEBUG_EXEC
9de5e440 41//#define DEBUG_SIGNAL
7d13299d 42
e6e5906b 43#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K)
e4533c7a
FB		 44/* XXX: unify with i386 target */
45void cpu_loop_exit(void)
46{
47 longjmp(env->jmp_env, 1);
48}
49#endif
e6e5906b 50#if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
3475187d
FB		 51#define reg_T2
52#endif
e4533c7a 53
fbf9eeb3
FB		 54/* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57void cpu_resume_from_signal(CPUState *env1, void *puc)
58{
59#if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61#endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67#if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72#endif
73 longjmp(env->jmp_env, 1);
74}
75
8a40a180
FB		 76
77static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80{
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
15388002 129 tb_invalidated_flag = 1;
8a40a180
FB		 130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
8a40a180
FB		 147 /* we add the TB in the virtual pc hash table */
148 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
149 spin_unlock(&tb_lock);
150 return tb;
151}
152
153static inline TranslationBlock *tb_find_fast(void)
154{
155 TranslationBlock *tb;
156 target_ulong cs_base, pc;
157 unsigned int flags;
158
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
161 is executed. */
162#if defined(TARGET_I386)
163 flags = env->hflags;
164 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
165 cs_base = env->segs[R_CS].base;
166 pc = cs_base + env->eip;
167#elif defined(TARGET_ARM)
168 flags = env->thumb | (env->vfp.vec_len << 1)
b5ff1b31
FB		 169 | (env->vfp.vec_stride << 4);
170 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
171 flags |= (1 << 6);
40f137e1
PB		 172 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
173 flags |= (1 << 7);
8a40a180
FB		 174 cs_base = 0;
175 pc = env->regs[15];
176#elif defined(TARGET_SPARC)
177#ifdef TARGET_SPARC64
a80dde08
FB		 178 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
179 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
180 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
8a40a180 181#else
a80dde08
FB		 182 // FPU enable . MMU enabled . MMU no-fault . Supervisor
183 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
184 | env->psrs;
8a40a180
FB		 185#endif
186 cs_base = env->npc;
187 pc = env->pc;
188#elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 cs_base = 0;
192 pc = env->nip;
193#elif defined(TARGET_MIPS)
56b19403 194 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
cc9442b9 195 cs_base = 0;
8a40a180 196 pc = env->PC;
e6e5906b
PB		 197#elif defined(TARGET_M68K)
198 flags = env->fpcr & M68K_FPCR_PREC;
199 cs_base = 0;
200 pc = env->pc;
fdf9b3e8
FB		 201#elif defined(TARGET_SH4)
202 flags = env->sr & (SR_MD | SR_RB);
203 cs_base = 0; /* XXXXX */
204 pc = env->pc;
8a40a180
FB		 205#else
206#error unsupported CPU
207#endif
208 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
209 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
210 tb->flags != flags, 0)) {
211 tb = tb_find_slow(pc, cs_base, flags);
15388002
FB		 212 /* Note: we do it here to avoid a gcc bug on Mac OS X when
213 doing it in tb_find_slow */
214 if (tb_invalidated_flag) {
215 /* as some TB could have been invalidated because
216 of memory exceptions while generating the code, we
217 must recompute the hash index here */
218 T0 = 0;
219 }
8a40a180
FB		 220 }
221 return tb;
222}
223
224
7d13299d
FB		 225/* main execution loop */
226
e4533c7a 227int cpu_exec(CPUState *env1)
7d13299d 228{
3475187d
FB		 229 int saved_T0, saved_T1;
230#if defined(reg_T2)
231 int saved_T2;
232#endif
e4533c7a 233 CPUState *saved_env;
3475187d 234#if defined(TARGET_I386)
04369ff2
FB		 235#ifdef reg_EAX
236 int saved_EAX;
237#endif
238#ifdef reg_ECX
239 int saved_ECX;
240#endif
241#ifdef reg_EDX
242 int saved_EDX;
243#endif
244#ifdef reg_EBX
245 int saved_EBX;
246#endif
247#ifdef reg_ESP
248 int saved_ESP;
249#endif
250#ifdef reg_EBP
251 int saved_EBP;
252#endif
253#ifdef reg_ESI
254 int saved_ESI;
255#endif
256#ifdef reg_EDI
257 int saved_EDI;
8c6939c0 258#endif
3475187d
FB		 259#elif defined(TARGET_SPARC)
260#if defined(reg_REGWPTR)
261 uint32_t *saved_regwptr;
262#endif
263#endif
fdbb4691 264#if defined(__sparc__) && !defined(HOST_SOLARIS)
8c6939c0 265 int saved_i7, tmp_T0;
04369ff2 266#endif
8a40a180 267 int ret, interrupt_request;
7d13299d 268 void (*gen_func)(void);
8a40a180 269 TranslationBlock *tb;
c27004ec 270 uint8_t *tc_ptr;
8c6939c0 271
5a1e3cfc
FB		 272#if defined(TARGET_I386)
273 /* handle exit of HALTED state */
274 if (env1->hflags & HF_HALTED_MASK) {
275 /* disable halt condition */
276 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
277 (env1->eflags & IF_MASK)) {
278 env1->hflags &= ~HF_HALTED_MASK;
279 } else {
280 return EXCP_HALTED;
e80e1cc4
FB		 281 }
282 }
283#elif defined(TARGET_PPC)
50443c98 284 if (env1->halted) {
e80e1cc4
FB		 285 if (env1->msr[MSR_EE] &&
286 (env1->interrupt_request &
287 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
50443c98 288 env1->halted = 0;
e80e1cc4
FB		 289 } else {
290 return EXCP_HALTED;
5a1e3cfc
FB		 291 }
292 }
ba3c64fb
FB		 293#elif defined(TARGET_SPARC)
294 if (env1->halted) {
295 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
296 (env1->psret != 0)) {
297 env1->halted = 0;
298 } else {
299 return EXCP_HALTED;
300 }
301 }
9332f9da
FB		 302#elif defined(TARGET_ARM)
303 if (env1->halted) {
304 /* An interrupt wakes the CPU even if the I and F CPSR bits are
305 set. */
306 if (env1->interrupt_request
307 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
308 env1->halted = 0;
309 } else {
310 return EXCP_HALTED;
311 }
312 }
6810e154
FB		 313#elif defined(TARGET_MIPS)
314 if (env1->halted) {
315 if (env1->interrupt_request &
316 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
317 env1->halted = 0;
318 } else {
319 return EXCP_HALTED;
320 }
321 }
5a1e3cfc
FB		 322#endif
323
6a00d601
FB		 324 cpu_single_env = env1;
325
7d13299d 326 /* first we save global registers */
c27004ec
FB		 327 saved_env = env;
328 env = env1;
7d13299d
FB		 329 saved_T0 = T0;
330 saved_T1 = T1;
3475187d 331#if defined(reg_T2)
e4533c7a 332 saved_T2 = T2;
3475187d 333#endif
fdbb4691 334#if defined(__sparc__) && !defined(HOST_SOLARIS)
e4533c7a
FB		 335 /* we also save i7 because longjmp may not restore it */
336 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
337#endif
338
339#if defined(TARGET_I386)
04369ff2
FB		 340#ifdef reg_EAX
341 saved_EAX = EAX;
04369ff2
FB		 342#endif
343#ifdef reg_ECX
344 saved_ECX = ECX;
04369ff2
FB		 345#endif
346#ifdef reg_EDX
347 saved_EDX = EDX;
04369ff2
FB		 348#endif
349#ifdef reg_EBX
350 saved_EBX = EBX;
04369ff2
FB		 351#endif
352#ifdef reg_ESP
353 saved_ESP = ESP;
04369ff2
FB		 354#endif
355#ifdef reg_EBP
356 saved_EBP = EBP;
04369ff2
FB		 357#endif
358#ifdef reg_ESI
359 saved_ESI = ESI;
04369ff2
FB		 360#endif
361#ifdef reg_EDI
362 saved_EDI = EDI;
04369ff2 363#endif
0d1a29f9
FB		 364
365 env_to_regs();
9de5e440 366 /* put eflags in CPU temporary format */
fc2b4c48
FB		 367 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
368 DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440 369 CC_OP = CC_OP_EFLAGS;
fc2b4c48 370 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 371#elif defined(TARGET_ARM)
93ac68bc 372#elif defined(TARGET_SPARC)
3475187d
FB		 373#if defined(reg_REGWPTR)
374 saved_regwptr = REGWPTR;
375#endif
67867308 376#elif defined(TARGET_PPC)
e6e5906b
PB		 377#elif defined(TARGET_M68K)
378 env->cc_op = CC_OP_FLAGS;
379 env->cc_dest = env->sr & 0xf;
380 env->cc_x = (env->sr >> 4) & 1;
6af0bf9c 381#elif defined(TARGET_MIPS)
fdf9b3e8
FB		 382#elif defined(TARGET_SH4)
383 /* XXXXX */
e4533c7a
FB		 384#else
385#error unsupported target CPU
386#endif
3fb2ded1 387 env->exception_index = -1;
9d27abd9 388
7d13299d 389 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 390 for(;;) {
391 if (setjmp(env->jmp_env) == 0) {
ee8b7021 392 env->current_tb = NULL;
3fb2ded1
FB		 393 /* if an exception is pending, we execute it here */
394 if (env->exception_index >= 0) {
395 if (env->exception_index >= EXCP_INTERRUPT) {
396 /* exit request from the cpu execution loop */
397 ret = env->exception_index;
398 break;
399 } else if (env->user_mode_only) {
400 /* if user mode only, we simulate a fake exception
401 which will be hanlded outside the cpu execution
402 loop */
83479e77 403#if defined(TARGET_I386)
3fb2ded1
FB		 404 do_interrupt_user(env->exception_index,
405 env->exception_is_int,
406 env->error_code,
407 env->exception_next_eip);
83479e77 408#endif
3fb2ded1
FB		 409 ret = env->exception_index;
410 break;
411 } else {
83479e77 412#if defined(TARGET_I386)
3fb2ded1
FB		 413 /* simulate a real cpu exception. On i386, it can
414 trigger new exceptions, but we do not handle
415 double or triple faults yet. */
416 do_interrupt(env->exception_index,
417 env->exception_is_int,
418 env->error_code,
d05e66d2 419 env->exception_next_eip, 0);
ce09776b
FB		 420#elif defined(TARGET_PPC)
421 do_interrupt(env);
6af0bf9c
FB		 422#elif defined(TARGET_MIPS)
423 do_interrupt(env);
e95c8d51 424#elif defined(TARGET_SPARC)
1a0c3292 425 do_interrupt(env->exception_index);
b5ff1b31
FB		 426#elif defined(TARGET_ARM)
427 do_interrupt(env);
fdf9b3e8
FB		 428#elif defined(TARGET_SH4)
429 do_interrupt(env);
83479e77 430#endif
3fb2ded1
FB		 431 }
432 env->exception_index = -1;
9df217a3
FB		 433 }
434#ifdef USE_KQEMU
435 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
436 int ret;
437 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
438 ret = kqemu_cpu_exec(env);
439 /* put eflags in CPU temporary format */
440 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
441 DF = 1 - (2 * ((env->eflags >> 10) & 1));
442 CC_OP = CC_OP_EFLAGS;
443 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
444 if (ret == 1) {
445 /* exception */
446 longjmp(env->jmp_env, 1);
447 } else if (ret == 2) {
448 /* softmmu execution needed */
449 } else {
450 if (env->interrupt_request != 0) {
451 /* hardware interrupt will be executed just after */
452 } else {
453 /* otherwise, we restart */
454 longjmp(env->jmp_env, 1);
455 }
456 }
3fb2ded1 457 }
9df217a3
FB		 458#endif
459
3fb2ded1
FB		 460 T0 = 0; /* force lookup of first TB */
461 for(;;) {
fdbb4691 462#if defined(__sparc__) && !defined(HOST_SOLARIS)
3fb2ded1
FB		 463 /* g1 can be modified by some libc? functions */
464 tmp_T0 = T0;
8c6939c0 465#endif
68a79315 466 interrupt_request = env->interrupt_request;
2e255c6b 467 if (__builtin_expect(interrupt_request, 0)) {
68a79315 468#if defined(TARGET_I386)
3b21e03e
FB		 469 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
470 !(env->hflags & HF_SMM_MASK)) {
471 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
472 do_smm_enter();
473#if defined(__sparc__) && !defined(HOST_SOLARIS)
474 tmp_T0 = 0;
475#else
476 T0 = 0;
477#endif
478 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
3f337316
FB		 479 (env->eflags & IF_MASK) &&
480 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
68a79315 481 int intno;
fbf9eeb3 482 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
a541f297 483 intno = cpu_get_pic_interrupt(env);
f193c797 484 if (loglevel & CPU_LOG_TB_IN_ASM) {
68a79315
FB		 485 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
486 }
d05e66d2 487 do_interrupt(intno, 0, 0, 0, 1);
907a5b26
FB		 488 /* ensure that no TB jump will be modified as
489 the program flow was changed */
fdbb4691 490#if defined(__sparc__) && !defined(HOST_SOLARIS)
907a5b26
FB		 491 tmp_T0 = 0;
492#else
493 T0 = 0;
494#endif
68a79315 495 }
ce09776b 496#elif defined(TARGET_PPC)
9fddaa0c
FB		 497#if 0
498 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
499 cpu_ppc_reset(env);
500 }
501#endif
502 if (msr_ee != 0) {
8a40a180 503 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
9fddaa0c
FB		 504 /* Raise it */
505 env->exception_index = EXCP_EXTERNAL;
506 env->error_code = 0;
ce09776b 507 do_interrupt(env);
8a40a180 508 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
fdbb4691 509#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 510 tmp_T0 = 0;
511#else
512 T0 = 0;
513#endif
514 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
515 /* Raise it */
516 env->exception_index = EXCP_DECR;
517 env->error_code = 0;
518 do_interrupt(env);
9fddaa0c 519 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
fdbb4691 520#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 521 tmp_T0 = 0;
522#else
523 T0 = 0;
524#endif
525 }
ce09776b 526 }
6af0bf9c
FB		 527#elif defined(TARGET_MIPS)
528 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
529 (env->CP0_Status & (1 << CP0St_IE)) &&
7ebab699 530 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
6af0bf9c
FB		 531 !(env->hflags & MIPS_HFLAG_EXL) &&
532 !(env->hflags & MIPS_HFLAG_ERL) &&
533 !(env->hflags & MIPS_HFLAG_DM)) {
534 /* Raise it */
535 env->exception_index = EXCP_EXT_INTERRUPT;
536 env->error_code = 0;
537 do_interrupt(env);
538 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
fdbb4691 539#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 540 tmp_T0 = 0;
541#else
542 T0 = 0;
543#endif
6af0bf9c 544 }
e95c8d51 545#elif defined(TARGET_SPARC)
66321a11
FB		 546 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
547 (env->psret != 0)) {
548 int pil = env->interrupt_index & 15;
549 int type = env->interrupt_index & 0xf0;
550
551 if (((type == TT_EXTINT) &&
552 (pil == 15 || pil > env->psrpil)) ||
553 type != TT_EXTINT) {
554 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
555 do_interrupt(env->interrupt_index);
556 env->interrupt_index = 0;
fdbb4691 557#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 558 tmp_T0 = 0;
559#else
560 T0 = 0;
561#endif
66321a11 562 }
e95c8d51
FB		 563 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
564 //do_interrupt(0, 0, 0, 0, 0);
565 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
ba3c64fb 566 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
df52b000
FB		 567 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
568 env->halted = 1;
569 env->exception_index = EXCP_HLT;
570 cpu_loop_exit();
ba3c64fb 571 }
b5ff1b31
FB		 572#elif defined(TARGET_ARM)
573 if (interrupt_request & CPU_INTERRUPT_FIQ
574 && !(env->uncached_cpsr & CPSR_F)) {
575 env->exception_index = EXCP_FIQ;
576 do_interrupt(env);
577 }
578 if (interrupt_request & CPU_INTERRUPT_HARD
579 && !(env->uncached_cpsr & CPSR_I)) {
580 env->exception_index = EXCP_IRQ;
581 do_interrupt(env);
582 }
fdf9b3e8
FB		 583#elif defined(TARGET_SH4)
584 /* XXXXX */
68a79315 585#endif
9d05095e
FB		 586 /* Don't use the cached interupt_request value,
587 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 588 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 589 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
590 /* ensure that no TB jump will be modified as
591 the program flow was changed */
fdbb4691 592#if defined(__sparc__) && !defined(HOST_SOLARIS)
bf3e8bf1
FB		 593 tmp_T0 = 0;
594#else
595 T0 = 0;
596#endif
597 }
68a79315
FB		 598 if (interrupt_request & CPU_INTERRUPT_EXIT) {
599 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
600 env->exception_index = EXCP_INTERRUPT;
601 cpu_loop_exit();
602 }
3fb2ded1 603 }
7d13299d 604#ifdef DEBUG_EXEC
b5ff1b31 605 if ((loglevel & CPU_LOG_TB_CPU)) {
e4533c7a 606#if defined(TARGET_I386)
3fb2ded1 607 /* restore flags in standard format */
fc9f715d 608#ifdef reg_EAX
3fb2ded1 609 env->regs[R_EAX] = EAX;
fc9f715d
FB		 610#endif
611#ifdef reg_EBX
3fb2ded1 612 env->regs[R_EBX] = EBX;
fc9f715d
FB		 613#endif
614#ifdef reg_ECX
3fb2ded1 615 env->regs[R_ECX] = ECX;
fc9f715d
FB		 616#endif
617#ifdef reg_EDX
3fb2ded1 618 env->regs[R_EDX] = EDX;
fc9f715d
FB		 619#endif
620#ifdef reg_ESI
3fb2ded1 621 env->regs[R_ESI] = ESI;
fc9f715d
FB		 622#endif
623#ifdef reg_EDI
3fb2ded1 624 env->regs[R_EDI] = EDI;
fc9f715d
FB		 625#endif
626#ifdef reg_EBP
3fb2ded1 627 env->regs[R_EBP] = EBP;
fc9f715d
FB		 628#endif
629#ifdef reg_ESP
3fb2ded1 630 env->regs[R_ESP] = ESP;
fc9f715d 631#endif
3fb2ded1 632 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
7fe48483 633 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
3fb2ded1 634 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 635#elif defined(TARGET_ARM)
7fe48483 636 cpu_dump_state(env, logfile, fprintf, 0);
93ac68bc 637#elif defined(TARGET_SPARC)
3475187d
FB		 638 REGWPTR = env->regbase + (env->cwp * 16);
639 env->regwptr = REGWPTR;
640 cpu_dump_state(env, logfile, fprintf, 0);
67867308 641#elif defined(TARGET_PPC)
7fe48483 642 cpu_dump_state(env, logfile, fprintf, 0);
e6e5906b
PB		 643#elif defined(TARGET_M68K)
644 cpu_m68k_flush_flags(env, env->cc_op);
645 env->cc_op = CC_OP_FLAGS;
646 env->sr = (env->sr & 0xffe0)
647 | env->cc_dest | (env->cc_x << 4);
648 cpu_dump_state(env, logfile, fprintf, 0);
6af0bf9c
FB		 649#elif defined(TARGET_MIPS)
650 cpu_dump_state(env, logfile, fprintf, 0);
fdf9b3e8
FB		 651#elif defined(TARGET_SH4)
652 cpu_dump_state(env, logfile, fprintf, 0);
e4533c7a
FB		 653#else
654#error unsupported target CPU
655#endif
3fb2ded1 656 }
7d13299d 657#endif
8a40a180 658 tb = tb_find_fast();
9d27abd9 659#ifdef DEBUG_EXEC
c1135f61 660 if ((loglevel & CPU_LOG_EXEC)) {
c27004ec
FB		 661 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
662 (long)tb->tc_ptr, tb->pc,
663 lookup_symbol(tb->pc));
3fb2ded1 664 }
9d27abd9 665#endif
fdbb4691 666#if defined(__sparc__) && !defined(HOST_SOLARIS)
3fb2ded1 667 T0 = tmp_T0;
8c6939c0 668#endif
8a40a180
FB		 669 /* see if we can patch the calling TB. When the TB
670 spans two pages, we cannot safely do a direct
671 jump. */
c27004ec 672 {
8a40a180 673 if (T0 != 0 &&
f32fc648
FB		 674#if USE_KQEMU
675 (env->kqemu_enabled != 2) &&
676#endif
8a40a180 677 tb->page_addr[1] == -1
bf3e8bf1
FB		 678#if defined(TARGET_I386) && defined(USE_CODE_COPY)
679 && (tb->cflags & CF_CODE_COPY) ==
680 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
681#endif
682 ) {
3fb2ded1 683 spin_lock(&tb_lock);
c27004ec 684 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
97eb5b14
FB		 685#if defined(USE_CODE_COPY)
686 /* propagates the FP use info */
687 ((TranslationBlock *)(T0 & ~3))->cflags |=
688 (tb->cflags & CF_FP_USED);
689#endif
3fb2ded1
FB		 690 spin_unlock(&tb_lock);
691 }
c27004ec 692 }
3fb2ded1 693 tc_ptr = tb->tc_ptr;
83479e77 694 env->current_tb = tb;
3fb2ded1
FB		 695 /* execute the generated code */
696 gen_func = (void *)tc_ptr;
8c6939c0 697#if defined(__sparc__)
3fb2ded1
FB		 698 __asm__ __volatile__("call %0\n\t"
699 "mov %%o7,%%i0"
700 : /* no outputs */
701 : "r" (gen_func)
fdbb4691
FB		 702 : "i0", "i1", "i2", "i3", "i4", "i5",
703 "l0", "l1", "l2", "l3", "l4", "l5",
704 "l6", "l7");
8c6939c0 705#elif defined(__arm__)
3fb2ded1
FB		 706 asm volatile ("mov pc, %0\n\t"
707 ".global exec_loop\n\t"
708 "exec_loop:\n\t"
709 : /* no outputs */
710 : "r" (gen_func)
711 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bf3e8bf1
FB		 712#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
713{
714 if (!(tb->cflags & CF_CODE_COPY)) {
97eb5b14
FB		 715 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
716 save_native_fp_state(env);
717 }
bf3e8bf1
FB		 718 gen_func();
719 } else {
97eb5b14
FB		 720 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
721 restore_native_fp_state(env);
722 }
bf3e8bf1
FB		 723 /* we work with native eflags */
724 CC_SRC = cc_table[CC_OP].compute_all();
725 CC_OP = CC_OP_EFLAGS;
726 asm(".globl exec_loop\n"
727 "\n"
728 "debug1:\n"
729 " pushl %%ebp\n"
730 " fs movl %10, %9\n"
731 " fs movl %11, %%eax\n"
732 " andl $0x400, %%eax\n"
733 " fs orl %8, %%eax\n"
734 " pushl %%eax\n"
735 " popf\n"
736 " fs movl %%esp, %12\n"
737 " fs movl %0, %%eax\n"
738 " fs movl %1, %%ecx\n"
739 " fs movl %2, %%edx\n"
740 " fs movl %3, %%ebx\n"
741 " fs movl %4, %%esp\n"
742 " fs movl %5, %%ebp\n"
743 " fs movl %6, %%esi\n"
744 " fs movl %7, %%edi\n"
745 " fs jmp *%9\n"
746 "exec_loop:\n"
747 " fs movl %%esp, %4\n"
748 " fs movl %12, %%esp\n"
749 " fs movl %%eax, %0\n"
750 " fs movl %%ecx, %1\n"
751 " fs movl %%edx, %2\n"
752 " fs movl %%ebx, %3\n"
753 " fs movl %%ebp, %5\n"
754 " fs movl %%esi, %6\n"
755 " fs movl %%edi, %7\n"
756 " pushf\n"
757 " popl %%eax\n"
758 " movl %%eax, %%ecx\n"
759 " andl $0x400, %%ecx\n"
760 " shrl $9, %%ecx\n"
761 " andl $0x8d5, %%eax\n"
762 " fs movl %%eax, %8\n"
763 " movl $1, %%eax\n"
764 " subl %%ecx, %%eax\n"
765 " fs movl %%eax, %11\n"
766 " fs movl %9, %%ebx\n" /* get T0 value */
767 " popl %%ebp\n"
768 :
769 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
770 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
771 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
772 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
773 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
774 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
775 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
776 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
777 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
778 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
779 "a" (gen_func),
780 "m" (*(uint8_t *)offsetof(CPUState, df)),
781 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
782 : "%ecx", "%edx"
783 );
784 }
785}
b8076a74
FB		 786#elif defined(__ia64)
787 struct fptr {
788 void *ip;
789 void *gp;
790 } fp;
791
792 fp.ip = tc_ptr;
793 fp.gp = code_gen_buffer + 2 * (1 << 20);
794 (*(void (*)(void)) &fp)();
ae228531 795#else
3fb2ded1 796 gen_func();
ae228531 797#endif
83479e77 798 env->current_tb = NULL;
4cbf74b6
FB		 799 /* reset soft MMU for next block (it can currently
800 only be set by a memory fault) */
801#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
3f337316
FB		 802 if (env->hflags & HF_SOFTMMU_MASK) {
803 env->hflags &= ~HF_SOFTMMU_MASK;
4cbf74b6
FB		 804 /* do not allow linking to another block */
805 T0 = 0;
806 }
f32fc648
FB		 807#endif
808#if defined(USE_KQEMU)
809#define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
810 if (kqemu_is_ok(env) &&
811 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
812 cpu_loop_exit();
813 }
4cbf74b6 814#endif
3fb2ded1
FB		 815 }
816 } else {
0d1a29f9 817 env_to_regs();
7d13299d 818 }
3fb2ded1
FB		 819 } /* for(;;) */
820
7d13299d 821
e4533c7a 822#if defined(TARGET_I386)
97eb5b14
FB		 823#if defined(USE_CODE_COPY)
824 if (env->native_fp_regs) {
825 save_native_fp_state(env);
826 }
827#endif
9de5e440 828 /* restore flags in standard format */
fc2b4c48 829 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
9de5e440 830
7d13299d 831 /* restore global registers */
04369ff2
FB		 832#ifdef reg_EAX
833 EAX = saved_EAX;
834#endif
835#ifdef reg_ECX
836 ECX = saved_ECX;
837#endif
838#ifdef reg_EDX
839 EDX = saved_EDX;
840#endif
841#ifdef reg_EBX
842 EBX = saved_EBX;
843#endif
844#ifdef reg_ESP
845 ESP = saved_ESP;
846#endif
847#ifdef reg_EBP
848 EBP = saved_EBP;
849#endif
850#ifdef reg_ESI
851 ESI = saved_ESI;
852#endif
853#ifdef reg_EDI
854 EDI = saved_EDI;
8c6939c0 855#endif
e4533c7a 856#elif defined(TARGET_ARM)
b7bcbe95 857 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 858#elif defined(TARGET_SPARC)
3475187d
FB		 859#if defined(reg_REGWPTR)
860 REGWPTR = saved_regwptr;
861#endif
67867308 862#elif defined(TARGET_PPC)
e6e5906b
PB		 863#elif defined(TARGET_M68K)
864 cpu_m68k_flush_flags(env, env->cc_op);
865 env->cc_op = CC_OP_FLAGS;
866 env->sr = (env->sr & 0xffe0)
867 | env->cc_dest | (env->cc_x << 4);
6af0bf9c 868#elif defined(TARGET_MIPS)
fdf9b3e8
FB		 869#elif defined(TARGET_SH4)
870 /* XXXXX */
e4533c7a
FB		 871#else
872#error unsupported target CPU
873#endif
fdbb4691 874#if defined(__sparc__) && !defined(HOST_SOLARIS)
8c6939c0 875 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2 876#endif
7d13299d
FB		 877 T0 = saved_T0;
878 T1 = saved_T1;
3475187d 879#if defined(reg_T2)
e4533c7a 880 T2 = saved_T2;
3475187d 881#endif
7d13299d 882 env = saved_env;
6a00d601
FB		 883 /* fail safe : never use cpu_single_env outside cpu_exec() */
884 cpu_single_env = NULL;
7d13299d
FB		 885 return ret;
886}
6dbad63e 887
fbf9eeb3
FB		 888/* must only be called from the generated code as an exception can be
889 generated */
890void tb_invalidate_page_range(target_ulong start, target_ulong end)
891{
dc5d0b3d
FB		 892 /* XXX: cannot enable it yet because it yields to MMU exception
893 where NIP != read address on PowerPC */
894#if 0
fbf9eeb3
FB		 895 target_ulong phys_addr;
896 phys_addr = get_phys_addr_code(env, start);
897 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 898#endif
fbf9eeb3
FB		 899}
900
1a18c71b 901#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 902
6dbad63e
FB		 903void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
904{
905 CPUX86State *saved_env;
906
907 saved_env = env;
908 env = s;
a412ac57 909 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 910 selector &= 0xffff;
2e255c6b 911 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 912 (selector << 4), 0xffff, 0);
a513fe19 913 } else {
b453b70b 914 load_seg(seg_reg, selector);
a513fe19 915 }
6dbad63e
FB		 916 env = saved_env;
917}
9de5e440 918
d0a1ffc9
FB		 919void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
920{
921 CPUX86State *saved_env;
922
923 saved_env = env;
924 env = s;
925
c27004ec 926 helper_fsave((target_ulong)ptr, data32);
d0a1ffc9
FB		 927
928 env = saved_env;
929}
930
931void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
932{
933 CPUX86State *saved_env;
934
935 saved_env = env;
936 env = s;
937
c27004ec 938 helper_frstor((target_ulong)ptr, data32);
d0a1ffc9
FB		 939
940 env = saved_env;
941}
942
e4533c7a
FB		 943#endif /* TARGET_I386 */
944
67b915a5
FB		 945#if !defined(CONFIG_SOFTMMU)
946
3fb2ded1
FB		 947#if defined(TARGET_I386)
948
b56dad1c 949/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 950 the effective address of the memory exception. 'is_write' is 1 if a
951 write caused the exception and otherwise 0'. 'old_set' is the
952 signal set which should be restored */
2b413144 953static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 954 int is_write, sigset_t *old_set,
955 void *puc)
9de5e440 956{
a513fe19
FB		 957 TranslationBlock *tb;
958 int ret;
68a79315 959
83479e77
FB		 960 if (cpu_single_env)
961 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 962#if defined(DEBUG_SIGNAL)
bf3e8bf1
FB		 963 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
964 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 965#endif
25eb4484 966 /* XXX: locking issue */
53a5960a 967 if (is_write && page_unprotect(h2g(address), pc, puc)) {
fd6ce8f6
FB		 968 return 1;
969 }
fbf9eeb3 970
3fb2ded1 971 /* see if it is an MMU fault */
93a40ea9
FB		 972 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
973 ((env->hflags & HF_CPL_MASK) == 3), 0);
3fb2ded1
FB		 974 if (ret < 0)
975 return 0; /* not an MMU fault */
976 if (ret == 0)
977 return 1; /* the MMU fault was handled without causing real CPU fault */
978 /* now we have a real cpu fault */
a513fe19
FB		 979 tb = tb_find_pc(pc);
980 if (tb) {
9de5e440
FB		 981 /* the PC is inside the translated code. It means that we have
982 a virtual CPU fault */
bf3e8bf1 983 cpu_restore_state(tb, env, pc, puc);
3fb2ded1 984 }
4cbf74b6 985 if (ret == 1) {
3fb2ded1 986#if 0
4cbf74b6
FB		 987 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
988 env->eip, env->cr[2], env->error_code);
3fb2ded1 989#endif
4cbf74b6
FB		 990 /* we restore the process signal mask as the sigreturn should
991 do it (XXX: use sigsetjmp) */
992 sigprocmask(SIG_SETMASK, old_set, NULL);
54ca9095 993 raise_exception_err(env->exception_index, env->error_code);
4cbf74b6
FB		 994 } else {
995 /* activate soft MMU for this block */
3f337316 996 env->hflags |= HF_SOFTMMU_MASK;
fbf9eeb3 997 cpu_resume_from_signal(env, puc);
4cbf74b6 998 }
3fb2ded1
FB		 999 /* never comes here */
1000 return 1;
1001}
1002
e4533c7a 1003#elif defined(TARGET_ARM)
3fb2ded1 1004static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 1005 int is_write, sigset_t *old_set,
1006 void *puc)
3fb2ded1 1007{
68016c62
FB		 1008 TranslationBlock *tb;
1009 int ret;
1010
1011 if (cpu_single_env)
1012 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1013#if defined(DEBUG_SIGNAL)
1014 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1015 pc, address, is_write, *(unsigned long *)old_set);
1016#endif
9f0777ed 1017 /* XXX: locking issue */
53a5960a 1018 if (is_write && page_unprotect(h2g(address), pc, puc)) {
9f0777ed
FB		 1019 return 1;
1020 }
68016c62
FB		 1021 /* see if it is an MMU fault */
1022 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
1023 if (ret < 0)
1024 return 0; /* not an MMU fault */
1025 if (ret == 0)
1026 return 1; /* the MMU fault was handled without causing real CPU fault */
1027 /* now we have a real cpu fault */
1028 tb = tb_find_pc(pc);
1029 if (tb) {
1030 /* the PC is inside the translated code. It means that we have
1031 a virtual CPU fault */
1032 cpu_restore_state(tb, env, pc, puc);
1033 }
1034 /* we restore the process signal mask as the sigreturn should
1035 do it (XXX: use sigsetjmp) */
1036 sigprocmask(SIG_SETMASK, old_set, NULL);
1037 cpu_loop_exit();
3fb2ded1 1038}
93ac68bc
FB		 1039#elif defined(TARGET_SPARC)
1040static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 1041 int is_write, sigset_t *old_set,
1042 void *puc)
93ac68bc 1043{
68016c62
FB		 1044 TranslationBlock *tb;
1045 int ret;
1046
1047 if (cpu_single_env)
1048 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1049#if defined(DEBUG_SIGNAL)
1050 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1051 pc, address, is_write, *(unsigned long *)old_set);
1052#endif
b453b70b 1053 /* XXX: locking issue */
53a5960a 1054 if (is_write && page_unprotect(h2g(address), pc, puc)) {
b453b70b
FB		 1055 return 1;
1056 }
68016c62
FB		 1057 /* see if it is an MMU fault */
1058 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
1059 if (ret < 0)
1060 return 0; /* not an MMU fault */
1061 if (ret == 0)
1062 return 1; /* the MMU fault was handled without causing real CPU fault */
1063 /* now we have a real cpu fault */
1064 tb = tb_find_pc(pc);
1065 if (tb) {
1066 /* the PC is inside the translated code. It means that we have
1067 a virtual CPU fault */
1068 cpu_restore_state(tb, env, pc, puc);
1069 }
1070 /* we restore the process signal mask as the sigreturn should
1071 do it (XXX: use sigsetjmp) */
1072 sigprocmask(SIG_SETMASK, old_set, NULL);
1073 cpu_loop_exit();
93ac68bc 1074}
67867308
FB		 1075#elif defined (TARGET_PPC)
1076static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 1077 int is_write, sigset_t *old_set,
1078 void *puc)
67867308
FB		 1079{
1080 TranslationBlock *tb;
ce09776b 1081 int ret;
67867308 1082
67867308
FB		 1083 if (cpu_single_env)
1084 env = cpu_single_env; /* XXX: find a correct solution for multithread */
67867308
FB		 1085#if defined(DEBUG_SIGNAL)
1086 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1087 pc, address, is_write, *(unsigned long *)old_set);
1088#endif
1089 /* XXX: locking issue */
53a5960a 1090 if (is_write && page_unprotect(h2g(address), pc, puc)) {
67867308
FB		 1091 return 1;
1092 }
1093
ce09776b 1094 /* see if it is an MMU fault */
7f957d28 1095 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
ce09776b
FB		 1096 if (ret < 0)
1097 return 0; /* not an MMU fault */
1098 if (ret == 0)
1099 return 1; /* the MMU fault was handled without causing real CPU fault */
1100
67867308
FB		 1101 /* now we have a real cpu fault */
1102 tb = tb_find_pc(pc);
1103 if (tb) {
1104 /* the PC is inside the translated code. It means that we have
1105 a virtual CPU fault */
bf3e8bf1 1106 cpu_restore_state(tb, env, pc, puc);
67867308 1107 }
ce09776b 1108 if (ret == 1) {
67867308 1109#if 0
ce09776b
FB		 1110 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1111 env->nip, env->error_code, tb);
67867308
FB		 1112#endif
1113 /* we restore the process signal mask as the sigreturn should
1114 do it (XXX: use sigsetjmp) */
bf3e8bf1 1115 sigprocmask(SIG_SETMASK, old_set, NULL);
9fddaa0c 1116 do_raise_exception_err(env->exception_index, env->error_code);
ce09776b
FB		 1117 } else {
1118 /* activate soft MMU for this block */
fbf9eeb3 1119 cpu_resume_from_signal(env, puc);
ce09776b 1120 }
67867308 1121 /* never comes here */
e6e5906b
PB		 1122 return 1;
1123}
1124
1125#elif defined(TARGET_M68K)
1126static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1127 int is_write, sigset_t *old_set,
1128 void *puc)
1129{
1130 TranslationBlock *tb;
1131 int ret;
1132
1133 if (cpu_single_env)
1134 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1135#if defined(DEBUG_SIGNAL)
1136 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1137 pc, address, is_write, *(unsigned long *)old_set);
1138#endif
1139 /* XXX: locking issue */
1140 if (is_write && page_unprotect(address, pc, puc)) {
1141 return 1;
1142 }
1143 /* see if it is an MMU fault */
1144 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1145 if (ret < 0)
1146 return 0; /* not an MMU fault */
1147 if (ret == 0)
1148 return 1; /* the MMU fault was handled without causing real CPU fault */
1149 /* now we have a real cpu fault */
1150 tb = tb_find_pc(pc);
1151 if (tb) {
1152 /* the PC is inside the translated code. It means that we have
1153 a virtual CPU fault */
1154 cpu_restore_state(tb, env, pc, puc);
1155 }
1156 /* we restore the process signal mask as the sigreturn should
1157 do it (XXX: use sigsetjmp) */
1158 sigprocmask(SIG_SETMASK, old_set, NULL);
1159 cpu_loop_exit();
1160 /* never comes here */
67867308
FB		 1161 return 1;
1162}
6af0bf9c
FB		 1163
1164#elif defined (TARGET_MIPS)
1165static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1166 int is_write, sigset_t *old_set,
1167 void *puc)
1168{
1169 TranslationBlock *tb;
1170 int ret;
1171
1172 if (cpu_single_env)
1173 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1174#if defined(DEBUG_SIGNAL)
1175 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1176 pc, address, is_write, *(unsigned long *)old_set);
1177#endif
1178 /* XXX: locking issue */
53a5960a 1179 if (is_write && page_unprotect(h2g(address), pc, puc)) {
6af0bf9c
FB		 1180 return 1;
1181 }
1182
1183 /* see if it is an MMU fault */
cc9442b9 1184 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
6af0bf9c
FB		 1185 if (ret < 0)
1186 return 0; /* not an MMU fault */
1187 if (ret == 0)
1188 return 1; /* the MMU fault was handled without causing real CPU fault */
1189
1190 /* now we have a real cpu fault */
1191 tb = tb_find_pc(pc);
1192 if (tb) {
1193 /* the PC is inside the translated code. It means that we have
1194 a virtual CPU fault */
1195 cpu_restore_state(tb, env, pc, puc);
1196 }
1197 if (ret == 1) {
1198#if 0
1199 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1200 env->nip, env->error_code, tb);
1201#endif
1202 /* we restore the process signal mask as the sigreturn should
1203 do it (XXX: use sigsetjmp) */
1204 sigprocmask(SIG_SETMASK, old_set, NULL);
1205 do_raise_exception_err(env->exception_index, env->error_code);
1206 } else {
1207 /* activate soft MMU for this block */
1208 cpu_resume_from_signal(env, puc);
1209 }
1210 /* never comes here */
1211 return 1;
1212}
1213
fdf9b3e8
FB		 1214#elif defined (TARGET_SH4)
1215static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1216 int is_write, sigset_t *old_set,
1217 void *puc)
1218{
1219 TranslationBlock *tb;
1220 int ret;
1221
1222 if (cpu_single_env)
1223 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1224#if defined(DEBUG_SIGNAL)
1225 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1226 pc, address, is_write, *(unsigned long *)old_set);
1227#endif
1228 /* XXX: locking issue */
1229 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1230 return 1;
1231 }
1232
1233 /* see if it is an MMU fault */
1234 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1235 if (ret < 0)
1236 return 0; /* not an MMU fault */
1237 if (ret == 0)
1238 return 1; /* the MMU fault was handled without causing real CPU fault */
1239
1240 /* now we have a real cpu fault */
1241 tb = tb_find_pc(pc);
1242 if (tb) {
1243 /* the PC is inside the translated code. It means that we have
1244 a virtual CPU fault */
1245 cpu_restore_state(tb, env, pc, puc);
1246 }
fdf9b3e8
FB		 1247#if 0
1248 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1249 env->nip, env->error_code, tb);
1250#endif
1251 /* we restore the process signal mask as the sigreturn should
1252 do it (XXX: use sigsetjmp) */
355fb23d
PB		 1253 sigprocmask(SIG_SETMASK, old_set, NULL);
1254 cpu_loop_exit();
fdf9b3e8
FB		 1255 /* never comes here */
1256 return 1;
1257}
e4533c7a
FB		 1258#else
1259#error unsupported target CPU
1260#endif
9de5e440 1261
2b413144
FB		 1262#if defined(__i386__)
1263
bf3e8bf1
FB		 1264#if defined(USE_CODE_COPY)
1265static void cpu_send_trap(unsigned long pc, int trap,
1266 struct ucontext *uc)
1267{
1268 TranslationBlock *tb;
1269
1270 if (cpu_single_env)
1271 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1272 /* now we have a real cpu fault */
1273 tb = tb_find_pc(pc);
1274 if (tb) {
1275 /* the PC is inside the translated code. It means that we have
1276 a virtual CPU fault */
1277 cpu_restore_state(tb, env, pc, uc);
1278 }
1279 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1280 raise_exception_err(trap, env->error_code);
1281}
1282#endif
1283
e4533c7a
FB		 1284int cpu_signal_handler(int host_signum, struct siginfo *info,
1285 void *puc)
9de5e440 1286{
9de5e440
FB		 1287 struct ucontext *uc = puc;
1288 unsigned long pc;
bf3e8bf1 1289 int trapno;
97eb5b14 1290
d691f669
FB		 1291#ifndef REG_EIP
1292/* for glibc 2.1 */
fd6ce8f6
FB		 1293#define REG_EIP EIP
1294#define REG_ERR ERR
1295#define REG_TRAPNO TRAPNO
d691f669 1296#endif
fc2b4c48 1297 pc = uc->uc_mcontext.gregs[REG_EIP];
bf3e8bf1
FB		 1298 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1299#if defined(TARGET_I386) && defined(USE_CODE_COPY)
1300 if (trapno == 0x00 || trapno == 0x05) {
1301 /* send division by zero or bound exception */
1302 cpu_send_trap(pc, trapno, uc);
1303 return 1;
1304 } else
1305#endif
1306 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1307 trapno == 0xe ?
1308 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1309 &uc->uc_sigmask, puc);
2b413144
FB		 1310}
1311
bc51c5c9
FB		 1312#elif defined(__x86_64__)
1313
1314int cpu_signal_handler(int host_signum, struct siginfo *info,
1315 void *puc)
1316{
1317 struct ucontext *uc = puc;
1318 unsigned long pc;
1319
1320 pc = uc->uc_mcontext.gregs[REG_RIP];
1321 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1322 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1323 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1324 &uc->uc_sigmask, puc);
1325}
1326
83fb7adf 1327#elif defined(__powerpc__)
2b413144 1328
83fb7adf
FB		 1329/***********************************************************************
1330 * signal context platform-specific definitions
1331 * From Wine
1332 */
1333#ifdef linux
1334/* All Registers access - only for local access */
1335# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1336/* Gpr Registers access */
1337# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1338# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1339# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1340# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1341# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1342# define LR_sig(context) REG_sig(link, context) /* Link register */
1343# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1344/* Float Registers access */
1345# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1346# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1347/* Exception Registers access */
1348# define DAR_sig(context) REG_sig(dar, context)
1349# define DSISR_sig(context) REG_sig(dsisr, context)
1350# define TRAP_sig(context) REG_sig(trap, context)
1351#endif /* linux */
1352
1353#ifdef __APPLE__
1354# include <sys/ucontext.h>
1355typedef struct ucontext SIGCONTEXT;
1356/* All Registers access - only for local access */
1357# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1358# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1359# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1360# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1361/* Gpr Registers access */
1362# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1363# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1364# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1365# define CTR_sig(context) REG_sig(ctr, context)
1366# define XER_sig(context) REG_sig(xer, context) /* Link register */
1367# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1368# define CR_sig(context) REG_sig(cr, context) /* Condition register */
1369/* Float Registers access */
1370# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1371# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1372/* Exception Registers access */
1373# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1374# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1375# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1376#endif /* __APPLE__ */
1377
d1d9f421 1378int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a 1379 void *puc)
2b413144 1380{
25eb4484 1381 struct ucontext *uc = puc;
25eb4484 1382 unsigned long pc;
25eb4484
FB		 1383 int is_write;
1384
83fb7adf 1385 pc = IAR_sig(uc);
25eb4484
FB		 1386 is_write = 0;
1387#if 0
1388 /* ppc 4xx case */
83fb7adf 1389 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 1390 is_write = 1;
1391#else
83fb7adf 1392 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 1393 is_write = 1;
1394#endif
1395 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1396 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 1397}
1398
2f87c607
FB		 1399#elif defined(__alpha__)
1400
e4533c7a 1401int cpu_signal_handler(int host_signum, struct siginfo *info,
2f87c607
FB		 1402 void *puc)
1403{
1404 struct ucontext *uc = puc;
1405 uint32_t *pc = uc->uc_mcontext.sc_pc;
1406 uint32_t insn = *pc;
1407 int is_write = 0;
1408
8c6939c0 1409 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 1410 switch (insn >> 26) {
1411 case 0x0d: // stw
1412 case 0x0e: // stb
1413 case 0x0f: // stq_u
1414 case 0x24: // stf
1415 case 0x25: // stg
1416 case 0x26: // sts
1417 case 0x27: // stt
1418 case 0x2c: // stl
1419 case 0x2d: // stq
1420 case 0x2e: // stl_c
1421 case 0x2f: // stq_c
1422 is_write = 1;
1423 }
1424
1425 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1426 is_write, &uc->uc_sigmask, puc);
2f87c607 1427}
8c6939c0
FB		 1428#elif defined(__sparc__)
1429
e4533c7a
FB		 1430int cpu_signal_handler(int host_signum, struct siginfo *info,
1431 void *puc)
8c6939c0
FB		 1432{
1433 uint32_t *regs = (uint32_t *)(info + 1);
1434 void *sigmask = (regs + 20);
1435 unsigned long pc;
1436 int is_write;
1437 uint32_t insn;
1438
1439 /* XXX: is there a standard glibc define ? */
1440 pc = regs[1];
1441 /* XXX: need kernel patch to get write flag faster */
1442 is_write = 0;
1443 insn = *(uint32_t *)pc;
1444 if ((insn >> 30) == 3) {
1445 switch((insn >> 19) & 0x3f) {
1446 case 0x05: // stb
1447 case 0x06: // sth
1448 case 0x04: // st
1449 case 0x07: // std
1450 case 0x24: // stf
1451 case 0x27: // stdf
1452 case 0x25: // stfsr
1453 is_write = 1;
1454 break;
1455 }
1456 }
1457 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1458 is_write, sigmask, NULL);
8c6939c0
FB		 1459}
1460
1461#elif defined(__arm__)
1462
e4533c7a
FB		 1463int cpu_signal_handler(int host_signum, struct siginfo *info,
1464 void *puc)
8c6939c0
FB		 1465{
1466 struct ucontext *uc = puc;
1467 unsigned long pc;
1468 int is_write;
1469
1470 pc = uc->uc_mcontext.gregs[R15];
1471 /* XXX: compute is_write */
1472 is_write = 0;
1473 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1474 is_write,
f3a9676a 1475 &uc->uc_sigmask, puc);
8c6939c0
FB		 1476}
1477
38e584a0
FB		 1478#elif defined(__mc68000)
1479
1480int cpu_signal_handler(int host_signum, struct siginfo *info,
1481 void *puc)
1482{
1483 struct ucontext *uc = puc;
1484 unsigned long pc;
1485 int is_write;
1486
1487 pc = uc->uc_mcontext.gregs[16];
1488 /* XXX: compute is_write */
1489 is_write = 0;
1490 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1491 is_write,
bf3e8bf1 1492 &uc->uc_sigmask, puc);
38e584a0
FB		 1493}
1494
b8076a74
FB		 1495#elif defined(__ia64)
1496
1497#ifndef __ISR_VALID
1498 /* This ought to be in <bits/siginfo.h>... */
1499# define __ISR_VALID 1
b8076a74
FB		 1500#endif
1501
1502int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1503{
1504 struct ucontext *uc = puc;
1505 unsigned long ip;
1506 int is_write = 0;
1507
1508 ip = uc->uc_mcontext.sc_ip;
1509 switch (host_signum) {
1510 case SIGILL:
1511 case SIGFPE:
1512 case SIGSEGV:
1513 case SIGBUS:
1514 case SIGTRAP:
fd4a43e4 1515 if (info->si_code && (info->si_segvflags & __ISR_VALID))
b8076a74
FB		 1516 /* ISR.W (write-access) is bit 33: */
1517 is_write = (info->si_isr >> 33) & 1;
1518 break;
1519
1520 default:
1521 break;
1522 }
1523 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1524 is_write,
1525 &uc->uc_sigmask, puc);
1526}
1527
90cb9493
FB		 1528#elif defined(__s390__)
1529
1530int cpu_signal_handler(int host_signum, struct siginfo *info,
1531 void *puc)
1532{
1533 struct ucontext *uc = puc;
1534 unsigned long pc;
1535 int is_write;
1536
1537 pc = uc->uc_mcontext.psw.addr;
1538 /* XXX: compute is_write */
1539 is_write = 0;
1540 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1541 is_write,
1542 &uc->uc_sigmask, puc);
1543}
1544
9de5e440 1545#else
2b413144 1546
3fb2ded1 1547#error host CPU specific signal handler needed
2b413144 1548
9de5e440 1549#endif
67b915a5
FB		 1550
1551#endif /* !defined(CONFIG_SOFTMMU) */
Qemu copy for testing