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1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/cpufreq.h> | |
35 | #include <linux/proc_fs.h> | |
36 | #include <linux/seq_file.h> | |
37 | #include <linux/acpi.h> | |
38 | #include <linux/dmi.h> | |
39 | #include <linux/moduleparam.h> | |
4e57b681 | 40 | #include <linux/sched.h> /* need_resched() */ |
5c87579e | 41 | #include <linux/latency.h> |
e9e2cdb4 | 42 | #include <linux/clockchips.h> |
4f86d3a8 | 43 | #include <linux/cpuidle.h> |
1da177e4 | 44 | |
3434933b TG |
45 | /* |
46 | * Include the apic definitions for x86 to have the APIC timer related defines | |
47 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
48 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
49 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
50 | */ | |
51 | #ifdef CONFIG_X86 | |
52 | #include <asm/apic.h> | |
53 | #endif | |
54 | ||
1da177e4 LT |
55 | #include <asm/io.h> |
56 | #include <asm/uaccess.h> | |
57 | ||
58 | #include <acpi/acpi_bus.h> | |
59 | #include <acpi/processor.h> | |
60 | ||
61 | #define ACPI_PROCESSOR_COMPONENT 0x01000000 | |
62 | #define ACPI_PROCESSOR_CLASS "processor" | |
1da177e4 | 63 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 64 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 65 | #define ACPI_PROCESSOR_FILE_POWER "power" |
1da177e4 | 66 | #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000) |
2aa44d05 | 67 | #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) |
4f86d3a8 | 68 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
69 | #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */ |
70 | #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */ | |
b6835052 | 71 | static void (*pm_idle_save) (void) __read_mostly; |
4f86d3a8 LB |
72 | #else |
73 | #define C2_OVERHEAD 1 /* 1us */ | |
74 | #define C3_OVERHEAD 1 /* 1us */ | |
75 | #endif | |
76 | #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) | |
1da177e4 | 77 | |
4f86d3a8 LB |
78 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
79 | module_param(max_cstate, uint, 0000); | |
b6835052 | 80 | static unsigned int nocst __read_mostly; |
1da177e4 LT |
81 | module_param(nocst, uint, 0000); |
82 | ||
4f86d3a8 | 83 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
84 | /* |
85 | * bm_history -- bit-mask with a bit per jiffy of bus-master activity | |
86 | * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms | |
87 | * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms | |
88 | * 100 HZ: 0x0000000F: 4 jiffies = 40ms | |
89 | * reduce history for more aggressive entry into C3 | |
90 | */ | |
b6835052 | 91 | static unsigned int bm_history __read_mostly = |
4be44fcd | 92 | (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1)); |
1da177e4 | 93 | module_param(bm_history, uint, 0644); |
4f86d3a8 LB |
94 | |
95 | static int acpi_processor_set_power_policy(struct acpi_processor *pr); | |
96 | ||
97 | #endif | |
1da177e4 LT |
98 | |
99 | /* | |
100 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
101 | * For now disable this. Probably a bug somewhere else. | |
102 | * | |
103 | * To skip this limit, boot/load with a large max_cstate limit. | |
104 | */ | |
1855256c | 105 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
106 | { |
107 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
108 | return 0; | |
109 | ||
3d35600a | 110 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
111 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
112 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 113 | |
3d35600a | 114 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
115 | |
116 | return 0; | |
117 | } | |
118 | ||
7ded5689 AR |
119 | /* Actually this shouldn't be __cpuinitdata, would be better to fix the |
120 | callers to only run once -AK */ | |
121 | static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { | |
f831335d BS |
122 | { set_max_cstate, "IBM ThinkPad R40e", { |
123 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
124 | DMI_MATCH(DMI_BIOS_VERSION,"1SET70WW")}, (void *)1}, | |
876c184b TR |
125 | { set_max_cstate, "IBM ThinkPad R40e", { |
126 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
127 | DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1}, | |
128 | { set_max_cstate, "IBM ThinkPad R40e", { | |
129 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
130 | DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1}, | |
131 | { set_max_cstate, "IBM ThinkPad R40e", { | |
132 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
133 | DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1}, | |
134 | { set_max_cstate, "IBM ThinkPad R40e", { | |
135 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
136 | DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1}, | |
137 | { set_max_cstate, "IBM ThinkPad R40e", { | |
138 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
139 | DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1}, | |
140 | { set_max_cstate, "IBM ThinkPad R40e", { | |
141 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
142 | DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1}, | |
143 | { set_max_cstate, "IBM ThinkPad R40e", { | |
144 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
145 | DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1}, | |
146 | { set_max_cstate, "IBM ThinkPad R40e", { | |
147 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
148 | DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1}, | |
149 | { set_max_cstate, "IBM ThinkPad R40e", { | |
150 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
151 | DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1}, | |
152 | { set_max_cstate, "IBM ThinkPad R40e", { | |
153 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
154 | DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1}, | |
155 | { set_max_cstate, "IBM ThinkPad R40e", { | |
156 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
157 | DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1}, | |
158 | { set_max_cstate, "IBM ThinkPad R40e", { | |
159 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
160 | DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1}, | |
161 | { set_max_cstate, "IBM ThinkPad R40e", { | |
162 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
163 | DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1}, | |
164 | { set_max_cstate, "IBM ThinkPad R40e", { | |
165 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
166 | DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1}, | |
167 | { set_max_cstate, "IBM ThinkPad R40e", { | |
168 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
169 | DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1}, | |
170 | { set_max_cstate, "Medion 41700", { | |
171 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
172 | DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1}, | |
173 | { set_max_cstate, "Clevo 5600D", { | |
174 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
175 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 176 | (void *)2}, |
1da177e4 LT |
177 | {}, |
178 | }; | |
179 | ||
4be44fcd | 180 | static inline u32 ticks_elapsed(u32 t1, u32 t2) |
1da177e4 LT |
181 | { |
182 | if (t2 >= t1) | |
183 | return (t2 - t1); | |
cee324b1 | 184 | else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) |
1da177e4 LT |
185 | return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); |
186 | else | |
187 | return ((0xFFFFFFFF - t1) + t2); | |
188 | } | |
189 | ||
4f86d3a8 LB |
190 | static inline u32 ticks_elapsed_in_us(u32 t1, u32 t2) |
191 | { | |
192 | if (t2 >= t1) | |
193 | return PM_TIMER_TICKS_TO_US(t2 - t1); | |
194 | else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) | |
195 | return PM_TIMER_TICKS_TO_US(((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); | |
196 | else | |
197 | return PM_TIMER_TICKS_TO_US((0xFFFFFFFF - t1) + t2); | |
198 | } | |
199 | ||
ddc081a1 VP |
200 | static void acpi_safe_halt(void) |
201 | { | |
202 | current_thread_info()->status &= ~TS_POLLING; | |
203 | /* | |
204 | * TS_POLLING-cleared state must be visible before we | |
205 | * test NEED_RESCHED: | |
206 | */ | |
207 | smp_mb(); | |
208 | if (!need_resched()) | |
209 | safe_halt(); | |
210 | current_thread_info()->status |= TS_POLLING; | |
211 | } | |
212 | ||
4f86d3a8 LB |
213 | #ifndef CONFIG_CPU_IDLE |
214 | ||
1da177e4 | 215 | static void |
4be44fcd LB |
216 | acpi_processor_power_activate(struct acpi_processor *pr, |
217 | struct acpi_processor_cx *new) | |
1da177e4 | 218 | { |
4be44fcd | 219 | struct acpi_processor_cx *old; |
1da177e4 LT |
220 | |
221 | if (!pr || !new) | |
222 | return; | |
223 | ||
224 | old = pr->power.state; | |
225 | ||
226 | if (old) | |
227 | old->promotion.count = 0; | |
4be44fcd | 228 | new->demotion.count = 0; |
1da177e4 LT |
229 | |
230 | /* Cleanup from old state. */ | |
231 | if (old) { | |
232 | switch (old->type) { | |
233 | case ACPI_STATE_C3: | |
234 | /* Disable bus master reload */ | |
02df8b93 | 235 | if (new->type != ACPI_STATE_C3 && pr->flags.bm_check) |
d8c71b6d | 236 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); |
1da177e4 LT |
237 | break; |
238 | } | |
239 | } | |
240 | ||
241 | /* Prepare to use new state. */ | |
242 | switch (new->type) { | |
243 | case ACPI_STATE_C3: | |
244 | /* Enable bus master reload */ | |
02df8b93 | 245 | if (old->type != ACPI_STATE_C3 && pr->flags.bm_check) |
d8c71b6d | 246 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 LT |
247 | break; |
248 | } | |
249 | ||
250 | pr->power.state = new; | |
251 | ||
252 | return; | |
253 | } | |
254 | ||
4be44fcd | 255 | static atomic_t c3_cpu_count; |
1da177e4 | 256 | |
991528d7 VP |
257 | /* Common C-state entry for C2, C3, .. */ |
258 | static void acpi_cstate_enter(struct acpi_processor_cx *cstate) | |
259 | { | |
260 | if (cstate->space_id == ACPI_CSTATE_FFH) { | |
261 | /* Call into architectural FFH based C-state */ | |
262 | acpi_processor_ffh_cstate_enter(cstate); | |
263 | } else { | |
264 | int unused; | |
265 | /* IO port based C-state */ | |
266 | inb(cstate->address); | |
267 | /* Dummy wait op - must do something useless after P_LVL2 read | |
268 | because chipsets cannot guarantee that STPCLK# signal | |
269 | gets asserted in time to freeze execution properly. */ | |
cee324b1 | 270 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); |
991528d7 VP |
271 | } |
272 | } | |
4f86d3a8 | 273 | #endif /* !CONFIG_CPU_IDLE */ |
991528d7 | 274 | |
169a0abb TG |
275 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
276 | ||
277 | /* | |
278 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
279 | * This seems to be a common problem on AMD boxen, but other vendors |
280 | * are affected too. We pick the most conservative approach: we assume | |
281 | * that the local APIC stops in both C2 and C3. | |
169a0abb TG |
282 | */ |
283 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
284 | struct acpi_processor_cx *cx) | |
285 | { | |
286 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 287 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb TG |
288 | |
289 | /* | |
290 | * Check, if one of the previous states already marked the lapic | |
291 | * unstable | |
292 | */ | |
293 | if (pwr->timer_broadcast_on_state < state) | |
294 | return; | |
295 | ||
e585bef8 | 296 | if (cx->type >= type) |
296d93cd | 297 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
298 | } |
299 | ||
300 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) | |
301 | { | |
e9e2cdb4 TG |
302 | unsigned long reason; |
303 | ||
304 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
305 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
306 | ||
307 | clockevents_notify(reason, &pr->id); | |
e9e2cdb4 TG |
308 | } |
309 | ||
310 | /* Power(C) State timer broadcast control */ | |
311 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, | |
312 | struct acpi_processor_cx *cx, | |
313 | int broadcast) | |
314 | { | |
e9e2cdb4 TG |
315 | int state = cx - pr->power.states; |
316 | ||
317 | if (state >= pr->power.timer_broadcast_on_state) { | |
318 | unsigned long reason; | |
319 | ||
320 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
321 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
322 | clockevents_notify(reason, &pr->id); | |
323 | } | |
169a0abb TG |
324 | } |
325 | ||
326 | #else | |
327 | ||
328 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
329 | struct acpi_processor_cx *cstate) { } | |
330 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { } | |
e9e2cdb4 TG |
331 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, |
332 | struct acpi_processor_cx *cx, | |
333 | int broadcast) | |
334 | { | |
335 | } | |
169a0abb TG |
336 | |
337 | #endif | |
338 | ||
b04e7bdb TG |
339 | /* |
340 | * Suspend / resume control | |
341 | */ | |
342 | static int acpi_idle_suspend; | |
343 | ||
344 | int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) | |
345 | { | |
346 | acpi_idle_suspend = 1; | |
347 | return 0; | |
348 | } | |
349 | ||
350 | int acpi_processor_resume(struct acpi_device * device) | |
351 | { | |
352 | acpi_idle_suspend = 0; | |
353 | return 0; | |
354 | } | |
355 | ||
4f86d3a8 | 356 | #ifndef CONFIG_CPU_IDLE |
4be44fcd | 357 | static void acpi_processor_idle(void) |
1da177e4 | 358 | { |
4be44fcd | 359 | struct acpi_processor *pr = NULL; |
1da177e4 LT |
360 | struct acpi_processor_cx *cx = NULL; |
361 | struct acpi_processor_cx *next_state = NULL; | |
4be44fcd LB |
362 | int sleep_ticks = 0; |
363 | u32 t1, t2 = 0; | |
1da177e4 | 364 | |
1da177e4 LT |
365 | /* |
366 | * Interrupts must be disabled during bus mastering calculations and | |
367 | * for C2/C3 transitions. | |
368 | */ | |
369 | local_irq_disable(); | |
370 | ||
d5a3d32a VP |
371 | pr = processors[smp_processor_id()]; |
372 | if (!pr) { | |
373 | local_irq_enable(); | |
374 | return; | |
375 | } | |
376 | ||
1da177e4 LT |
377 | /* |
378 | * Check whether we truly need to go idle, or should | |
379 | * reschedule: | |
380 | */ | |
381 | if (unlikely(need_resched())) { | |
382 | local_irq_enable(); | |
383 | return; | |
384 | } | |
385 | ||
386 | cx = pr->power.state; | |
b04e7bdb | 387 | if (!cx || acpi_idle_suspend) { |
64c7c8f8 NP |
388 | if (pm_idle_save) |
389 | pm_idle_save(); | |
390 | else | |
391 | acpi_safe_halt(); | |
392 | return; | |
393 | } | |
1da177e4 LT |
394 | |
395 | /* | |
396 | * Check BM Activity | |
397 | * ----------------- | |
398 | * Check for bus mastering activity (if required), record, and check | |
399 | * for demotion. | |
400 | */ | |
401 | if (pr->flags.bm_check) { | |
4be44fcd LB |
402 | u32 bm_status = 0; |
403 | unsigned long diff = jiffies - pr->power.bm_check_timestamp; | |
1da177e4 | 404 | |
c5ab81ca DB |
405 | if (diff > 31) |
406 | diff = 31; | |
1da177e4 | 407 | |
c5ab81ca | 408 | pr->power.bm_activity <<= diff; |
1da177e4 | 409 | |
d8c71b6d | 410 | acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
1da177e4 | 411 | if (bm_status) { |
c5ab81ca | 412 | pr->power.bm_activity |= 0x1; |
d8c71b6d | 413 | acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
1da177e4 LT |
414 | } |
415 | /* | |
416 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
417 | * the true state of bus mastering activity; forcing us to | |
418 | * manually check the BMIDEA bit of each IDE channel. | |
419 | */ | |
420 | else if (errata.piix4.bmisx) { | |
421 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
4be44fcd | 422 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) |
c5ab81ca | 423 | pr->power.bm_activity |= 0x1; |
1da177e4 LT |
424 | } |
425 | ||
426 | pr->power.bm_check_timestamp = jiffies; | |
427 | ||
428 | /* | |
c4a001b1 | 429 | * If bus mastering is or was active this jiffy, demote |
1da177e4 LT |
430 | * to avoid a faulty transition. Note that the processor |
431 | * won't enter a low-power state during this call (to this | |
c4a001b1 | 432 | * function) but should upon the next. |
1da177e4 LT |
433 | * |
434 | * TBD: A better policy might be to fallback to the demotion | |
435 | * state (use it for this quantum only) istead of | |
436 | * demoting -- and rely on duration as our sole demotion | |
437 | * qualification. This may, however, introduce DMA | |
438 | * issues (e.g. floppy DMA transfer overrun/underrun). | |
439 | */ | |
c4a001b1 DB |
440 | if ((pr->power.bm_activity & 0x1) && |
441 | cx->demotion.threshold.bm) { | |
1da177e4 LT |
442 | local_irq_enable(); |
443 | next_state = cx->demotion.state; | |
444 | goto end; | |
445 | } | |
446 | } | |
447 | ||
4c033552 VP |
448 | #ifdef CONFIG_HOTPLUG_CPU |
449 | /* | |
450 | * Check for P_LVL2_UP flag before entering C2 and above on | |
451 | * an SMP system. We do it here instead of doing it at _CST/P_LVL | |
452 | * detection phase, to work cleanly with logical CPU hotplug. | |
453 | */ | |
4f86d3a8 | 454 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && |
cee324b1 | 455 | !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
1e483969 | 456 | cx = &pr->power.states[ACPI_STATE_C1]; |
4c033552 | 457 | #endif |
1e483969 | 458 | |
1da177e4 LT |
459 | /* |
460 | * Sleep: | |
461 | * ------ | |
462 | * Invoke the current Cx state to put the processor to sleep. | |
463 | */ | |
2a298a35 | 464 | if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) { |
495ab9c0 | 465 | current_thread_info()->status &= ~TS_POLLING; |
0888f06a IM |
466 | /* |
467 | * TS_POLLING-cleared state must be visible before we | |
468 | * test NEED_RESCHED: | |
469 | */ | |
470 | smp_mb(); | |
2a298a35 | 471 | if (need_resched()) { |
495ab9c0 | 472 | current_thread_info()->status |= TS_POLLING; |
af2eb17b | 473 | local_irq_enable(); |
2a298a35 NP |
474 | return; |
475 | } | |
476 | } | |
477 | ||
1da177e4 LT |
478 | switch (cx->type) { |
479 | ||
480 | case ACPI_STATE_C1: | |
481 | /* | |
482 | * Invoke C1. | |
483 | * Use the appropriate idle routine, the one that would | |
484 | * be used without acpi C-states. | |
485 | */ | |
486 | if (pm_idle_save) | |
487 | pm_idle_save(); | |
488 | else | |
64c7c8f8 NP |
489 | acpi_safe_halt(); |
490 | ||
1da177e4 | 491 | /* |
4be44fcd | 492 | * TBD: Can't get time duration while in C1, as resumes |
1da177e4 LT |
493 | * go to an ISR rather than here. Need to instrument |
494 | * base interrupt handler. | |
2aa44d05 IM |
495 | * |
496 | * Note: the TSC better not stop in C1, sched_clock() will | |
497 | * skew otherwise. | |
1da177e4 LT |
498 | */ |
499 | sleep_ticks = 0xFFFFFFFF; | |
500 | break; | |
501 | ||
502 | case ACPI_STATE_C2: | |
503 | /* Get start time (ticks) */ | |
cee324b1 | 504 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
2aa44d05 IM |
505 | /* Tell the scheduler that we are going deep-idle: */ |
506 | sched_clock_idle_sleep_event(); | |
1da177e4 | 507 | /* Invoke C2 */ |
e9e2cdb4 | 508 | acpi_state_timer_broadcast(pr, cx, 1); |
991528d7 | 509 | acpi_cstate_enter(cx); |
1da177e4 | 510 | /* Get end time (ticks) */ |
cee324b1 | 511 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
539eb11e | 512 | |
0aa366f3 | 513 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) |
539eb11e | 514 | /* TSC halts in C2, so notify users */ |
5a90cf20 | 515 | mark_tsc_unstable("possible TSC halt in C2"); |
539eb11e | 516 | #endif |
2aa44d05 IM |
517 | /* Compute time (ticks) that we were actually asleep */ |
518 | sleep_ticks = ticks_elapsed(t1, t2); | |
519 | ||
520 | /* Tell the scheduler how much we idled: */ | |
521 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
522 | ||
1da177e4 LT |
523 | /* Re-enable interrupts */ |
524 | local_irq_enable(); | |
2aa44d05 IM |
525 | /* Do not account our idle-switching overhead: */ |
526 | sleep_ticks -= cx->latency_ticks + C2_OVERHEAD; | |
527 | ||
495ab9c0 | 528 | current_thread_info()->status |= TS_POLLING; |
e9e2cdb4 | 529 | acpi_state_timer_broadcast(pr, cx, 0); |
1da177e4 LT |
530 | break; |
531 | ||
532 | case ACPI_STATE_C3: | |
e17bcb43 TG |
533 | /* |
534 | * Must be done before busmaster disable as we might | |
535 | * need to access HPET ! | |
536 | */ | |
537 | acpi_state_timer_broadcast(pr, cx, 1); | |
18eab855 VP |
538 | /* |
539 | * disable bus master | |
540 | * bm_check implies we need ARB_DIS | |
541 | * !bm_check implies we need cache flush | |
542 | * bm_control implies whether we can do ARB_DIS | |
543 | * | |
544 | * That leaves a case where bm_check is set and bm_control is | |
545 | * not set. In that case we cannot do much, we enter C3 | |
546 | * without doing anything. | |
547 | */ | |
548 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
02df8b93 | 549 | if (atomic_inc_return(&c3_cpu_count) == |
4be44fcd | 550 | num_online_cpus()) { |
02df8b93 VP |
551 | /* |
552 | * All CPUs are trying to go to C3 | |
553 | * Disable bus master arbitration | |
554 | */ | |
d8c71b6d | 555 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); |
02df8b93 | 556 | } |
18eab855 | 557 | } else if (!pr->flags.bm_check) { |
02df8b93 VP |
558 | /* SMP with no shared cache... Invalidate cache */ |
559 | ACPI_FLUSH_CPU_CACHE(); | |
560 | } | |
4be44fcd | 561 | |
1da177e4 | 562 | /* Get start time (ticks) */ |
cee324b1 | 563 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
1da177e4 | 564 | /* Invoke C3 */ |
2aa44d05 IM |
565 | /* Tell the scheduler that we are going deep-idle: */ |
566 | sched_clock_idle_sleep_event(); | |
991528d7 | 567 | acpi_cstate_enter(cx); |
1da177e4 | 568 | /* Get end time (ticks) */ |
cee324b1 | 569 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
18eab855 | 570 | if (pr->flags.bm_check && pr->flags.bm_control) { |
02df8b93 VP |
571 | /* Enable bus master arbitration */ |
572 | atomic_dec(&c3_cpu_count); | |
d8c71b6d | 573 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); |
02df8b93 VP |
574 | } |
575 | ||
0aa366f3 | 576 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) |
539eb11e | 577 | /* TSC halts in C3, so notify users */ |
5a90cf20 | 578 | mark_tsc_unstable("TSC halts in C3"); |
539eb11e | 579 | #endif |
2aa44d05 IM |
580 | /* Compute time (ticks) that we were actually asleep */ |
581 | sleep_ticks = ticks_elapsed(t1, t2); | |
582 | /* Tell the scheduler how much we idled: */ | |
583 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
584 | ||
1da177e4 LT |
585 | /* Re-enable interrupts */ |
586 | local_irq_enable(); | |
2aa44d05 IM |
587 | /* Do not account our idle-switching overhead: */ |
588 | sleep_ticks -= cx->latency_ticks + C3_OVERHEAD; | |
589 | ||
495ab9c0 | 590 | current_thread_info()->status |= TS_POLLING; |
e9e2cdb4 | 591 | acpi_state_timer_broadcast(pr, cx, 0); |
1da177e4 LT |
592 | break; |
593 | ||
594 | default: | |
595 | local_irq_enable(); | |
596 | return; | |
597 | } | |
a3c6598f DB |
598 | cx->usage++; |
599 | if ((cx->type != ACPI_STATE_C1) && (sleep_ticks > 0)) | |
600 | cx->time += sleep_ticks; | |
1da177e4 LT |
601 | |
602 | next_state = pr->power.state; | |
603 | ||
1e483969 DSL |
604 | #ifdef CONFIG_HOTPLUG_CPU |
605 | /* Don't do promotion/demotion */ | |
606 | if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
cee324b1 | 607 | !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) { |
1e483969 DSL |
608 | next_state = cx; |
609 | goto end; | |
610 | } | |
611 | #endif | |
612 | ||
1da177e4 LT |
613 | /* |
614 | * Promotion? | |
615 | * ---------- | |
616 | * Track the number of longs (time asleep is greater than threshold) | |
617 | * and promote when the count threshold is reached. Note that bus | |
618 | * mastering activity may prevent promotions. | |
619 | * Do not promote above max_cstate. | |
620 | */ | |
621 | if (cx->promotion.state && | |
622 | ((cx->promotion.state - pr->power.states) <= max_cstate)) { | |
5c87579e AV |
623 | if (sleep_ticks > cx->promotion.threshold.ticks && |
624 | cx->promotion.state->latency <= system_latency_constraint()) { | |
1da177e4 | 625 | cx->promotion.count++; |
4be44fcd LB |
626 | cx->demotion.count = 0; |
627 | if (cx->promotion.count >= | |
628 | cx->promotion.threshold.count) { | |
1da177e4 | 629 | if (pr->flags.bm_check) { |
4be44fcd LB |
630 | if (! |
631 | (pr->power.bm_activity & cx-> | |
632 | promotion.threshold.bm)) { | |
633 | next_state = | |
634 | cx->promotion.state; | |
1da177e4 LT |
635 | goto end; |
636 | } | |
4be44fcd | 637 | } else { |
1da177e4 LT |
638 | next_state = cx->promotion.state; |
639 | goto end; | |
640 | } | |
641 | } | |
642 | } | |
643 | } | |
644 | ||
645 | /* | |
646 | * Demotion? | |
647 | * --------- | |
648 | * Track the number of shorts (time asleep is less than time threshold) | |
649 | * and demote when the usage threshold is reached. | |
650 | */ | |
651 | if (cx->demotion.state) { | |
652 | if (sleep_ticks < cx->demotion.threshold.ticks) { | |
653 | cx->demotion.count++; | |
654 | cx->promotion.count = 0; | |
655 | if (cx->demotion.count >= cx->demotion.threshold.count) { | |
656 | next_state = cx->demotion.state; | |
657 | goto end; | |
658 | } | |
659 | } | |
660 | } | |
661 | ||
4be44fcd | 662 | end: |
1da177e4 LT |
663 | /* |
664 | * Demote if current state exceeds max_cstate | |
5c87579e | 665 | * or if the latency of the current state is unacceptable |
1da177e4 | 666 | */ |
5c87579e AV |
667 | if ((pr->power.state - pr->power.states) > max_cstate || |
668 | pr->power.state->latency > system_latency_constraint()) { | |
1da177e4 LT |
669 | if (cx->demotion.state) |
670 | next_state = cx->demotion.state; | |
671 | } | |
672 | ||
673 | /* | |
674 | * New Cx State? | |
675 | * ------------- | |
676 | * If we're going to start using a new Cx state we must clean up | |
677 | * from the previous and prepare to use the new. | |
678 | */ | |
679 | if (next_state != pr->power.state) | |
680 | acpi_processor_power_activate(pr, next_state); | |
1da177e4 LT |
681 | } |
682 | ||
4be44fcd | 683 | static int acpi_processor_set_power_policy(struct acpi_processor *pr) |
1da177e4 LT |
684 | { |
685 | unsigned int i; | |
686 | unsigned int state_is_set = 0; | |
687 | struct acpi_processor_cx *lower = NULL; | |
688 | struct acpi_processor_cx *higher = NULL; | |
689 | struct acpi_processor_cx *cx; | |
690 | ||
1da177e4 LT |
691 | |
692 | if (!pr) | |
d550d98d | 693 | return -EINVAL; |
1da177e4 LT |
694 | |
695 | /* | |
696 | * This function sets the default Cx state policy (OS idle handler). | |
697 | * Our scheme is to promote quickly to C2 but more conservatively | |
698 | * to C3. We're favoring C2 for its characteristics of low latency | |
699 | * (quick response), good power savings, and ability to allow bus | |
700 | * mastering activity. Note that the Cx state policy is completely | |
701 | * customizable and can be altered dynamically. | |
702 | */ | |
703 | ||
704 | /* startup state */ | |
4be44fcd | 705 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
706 | cx = &pr->power.states[i]; |
707 | if (!cx->valid) | |
708 | continue; | |
709 | ||
710 | if (!state_is_set) | |
711 | pr->power.state = cx; | |
712 | state_is_set++; | |
713 | break; | |
4be44fcd | 714 | } |
1da177e4 LT |
715 | |
716 | if (!state_is_set) | |
d550d98d | 717 | return -ENODEV; |
1da177e4 LT |
718 | |
719 | /* demotion */ | |
4be44fcd | 720 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
721 | cx = &pr->power.states[i]; |
722 | if (!cx->valid) | |
723 | continue; | |
724 | ||
725 | if (lower) { | |
726 | cx->demotion.state = lower; | |
727 | cx->demotion.threshold.ticks = cx->latency_ticks; | |
728 | cx->demotion.threshold.count = 1; | |
729 | if (cx->type == ACPI_STATE_C3) | |
730 | cx->demotion.threshold.bm = bm_history; | |
731 | } | |
732 | ||
733 | lower = cx; | |
734 | } | |
735 | ||
736 | /* promotion */ | |
737 | for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) { | |
738 | cx = &pr->power.states[i]; | |
739 | if (!cx->valid) | |
740 | continue; | |
741 | ||
742 | if (higher) { | |
4be44fcd | 743 | cx->promotion.state = higher; |
1da177e4 LT |
744 | cx->promotion.threshold.ticks = cx->latency_ticks; |
745 | if (cx->type >= ACPI_STATE_C2) | |
746 | cx->promotion.threshold.count = 4; | |
747 | else | |
748 | cx->promotion.threshold.count = 10; | |
749 | if (higher->type == ACPI_STATE_C3) | |
750 | cx->promotion.threshold.bm = bm_history; | |
751 | } | |
752 | ||
753 | higher = cx; | |
754 | } | |
755 | ||
d550d98d | 756 | return 0; |
1da177e4 | 757 | } |
4f86d3a8 | 758 | #endif /* !CONFIG_CPU_IDLE */ |
1da177e4 | 759 | |
4be44fcd | 760 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 761 | { |
1da177e4 LT |
762 | |
763 | if (!pr) | |
d550d98d | 764 | return -EINVAL; |
1da177e4 LT |
765 | |
766 | if (!pr->pblk) | |
d550d98d | 767 | return -ENODEV; |
1da177e4 | 768 | |
1da177e4 | 769 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
770 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
771 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
772 | ||
4c033552 VP |
773 | #ifndef CONFIG_HOTPLUG_CPU |
774 | /* | |
775 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 776 | * an SMP system. |
4c033552 | 777 | */ |
ad71860a | 778 | if ((num_online_cpus() > 1) && |
cee324b1 | 779 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 780 | return -ENODEV; |
4c033552 VP |
781 | #endif |
782 | ||
1da177e4 LT |
783 | /* determine C2 and C3 address from pblk */ |
784 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
785 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
786 | ||
787 | /* determine latencies from FADT */ | |
cee324b1 AS |
788 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; |
789 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; | |
1da177e4 LT |
790 | |
791 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
792 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
793 | pr->power.states[ACPI_STATE_C2].address, | |
794 | pr->power.states[ACPI_STATE_C3].address)); | |
795 | ||
d550d98d | 796 | return 0; |
1da177e4 LT |
797 | } |
798 | ||
991528d7 | 799 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 800 | { |
991528d7 VP |
801 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
802 | /* set the first C-State to C1 */ | |
803 | /* all processors need to support C1 */ | |
804 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
805 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
806 | } | |
807 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 808 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 809 | return 0; |
acf05f4b VP |
810 | } |
811 | ||
4be44fcd | 812 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 813 | { |
4be44fcd LB |
814 | acpi_status status = 0; |
815 | acpi_integer count; | |
cf824788 | 816 | int current_count; |
4be44fcd LB |
817 | int i; |
818 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
819 | union acpi_object *cst; | |
1da177e4 | 820 | |
1da177e4 | 821 | |
1da177e4 | 822 | if (nocst) |
d550d98d | 823 | return -ENODEV; |
1da177e4 | 824 | |
991528d7 | 825 | current_count = 0; |
1da177e4 LT |
826 | |
827 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
828 | if (ACPI_FAILURE(status)) { | |
829 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 830 | return -ENODEV; |
4be44fcd | 831 | } |
1da177e4 | 832 | |
50dd0969 | 833 | cst = buffer.pointer; |
1da177e4 LT |
834 | |
835 | /* There must be at least 2 elements */ | |
836 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 837 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
838 | status = -EFAULT; |
839 | goto end; | |
840 | } | |
841 | ||
842 | count = cst->package.elements[0].integer.value; | |
843 | ||
844 | /* Validate number of power states. */ | |
845 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 846 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
847 | status = -EFAULT; |
848 | goto end; | |
849 | } | |
850 | ||
1da177e4 LT |
851 | /* Tell driver that at least _CST is supported. */ |
852 | pr->flags.has_cst = 1; | |
853 | ||
854 | for (i = 1; i <= count; i++) { | |
855 | union acpi_object *element; | |
856 | union acpi_object *obj; | |
857 | struct acpi_power_register *reg; | |
858 | struct acpi_processor_cx cx; | |
859 | ||
860 | memset(&cx, 0, sizeof(cx)); | |
861 | ||
50dd0969 | 862 | element = &(cst->package.elements[i]); |
1da177e4 LT |
863 | if (element->type != ACPI_TYPE_PACKAGE) |
864 | continue; | |
865 | ||
866 | if (element->package.count != 4) | |
867 | continue; | |
868 | ||
50dd0969 | 869 | obj = &(element->package.elements[0]); |
1da177e4 LT |
870 | |
871 | if (obj->type != ACPI_TYPE_BUFFER) | |
872 | continue; | |
873 | ||
4be44fcd | 874 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
875 | |
876 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 877 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
878 | continue; |
879 | ||
1da177e4 | 880 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 881 | obj = &(element->package.elements[1]); |
1da177e4 LT |
882 | if (obj->type != ACPI_TYPE_INTEGER) |
883 | continue; | |
884 | ||
885 | cx.type = obj->integer.value; | |
991528d7 VP |
886 | /* |
887 | * Some buggy BIOSes won't list C1 in _CST - | |
888 | * Let acpi_processor_get_power_info_default() handle them later | |
889 | */ | |
890 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
891 | current_count++; | |
892 | ||
893 | cx.address = reg->address; | |
894 | cx.index = current_count + 1; | |
895 | ||
896 | cx.space_id = ACPI_CSTATE_SYSTEMIO; | |
897 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { | |
898 | if (acpi_processor_ffh_cstate_probe | |
899 | (pr->id, &cx, reg) == 0) { | |
900 | cx.space_id = ACPI_CSTATE_FFH; | |
901 | } else if (cx.type != ACPI_STATE_C1) { | |
902 | /* | |
903 | * C1 is a special case where FIXED_HARDWARE | |
904 | * can be handled in non-MWAIT way as well. | |
905 | * In that case, save this _CST entry info. | |
906 | * That is, we retain space_id of SYSTEM_IO for | |
907 | * halt based C1. | |
908 | * Otherwise, ignore this info and continue. | |
909 | */ | |
910 | continue; | |
911 | } | |
912 | } | |
1da177e4 | 913 | |
50dd0969 | 914 | obj = &(element->package.elements[2]); |
1da177e4 LT |
915 | if (obj->type != ACPI_TYPE_INTEGER) |
916 | continue; | |
917 | ||
918 | cx.latency = obj->integer.value; | |
919 | ||
50dd0969 | 920 | obj = &(element->package.elements[3]); |
1da177e4 LT |
921 | if (obj->type != ACPI_TYPE_INTEGER) |
922 | continue; | |
923 | ||
924 | cx.power = obj->integer.value; | |
925 | ||
cf824788 JM |
926 | current_count++; |
927 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
928 | ||
929 | /* | |
930 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
931 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
932 | */ | |
933 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
934 | printk(KERN_WARNING | |
935 | "Limiting number of power states to max (%d)\n", | |
936 | ACPI_PROCESSOR_MAX_POWER); | |
937 | printk(KERN_WARNING | |
938 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
939 | break; | |
940 | } | |
1da177e4 LT |
941 | } |
942 | ||
4be44fcd | 943 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 944 | current_count)); |
1da177e4 LT |
945 | |
946 | /* Validate number of power states discovered */ | |
cf824788 | 947 | if (current_count < 2) |
6d93c648 | 948 | status = -EFAULT; |
1da177e4 | 949 | |
4be44fcd | 950 | end: |
02438d87 | 951 | kfree(buffer.pointer); |
1da177e4 | 952 | |
d550d98d | 953 | return status; |
1da177e4 LT |
954 | } |
955 | ||
1da177e4 LT |
956 | static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx) |
957 | { | |
1da177e4 LT |
958 | |
959 | if (!cx->address) | |
d550d98d | 960 | return; |
1da177e4 LT |
961 | |
962 | /* | |
963 | * C2 latency must be less than or equal to 100 | |
964 | * microseconds. | |
965 | */ | |
966 | else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { | |
967 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 968 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 969 | return; |
1da177e4 LT |
970 | } |
971 | ||
1da177e4 LT |
972 | /* |
973 | * Otherwise we've met all of our C2 requirements. | |
974 | * Normalize the C2 latency to expidite policy | |
975 | */ | |
976 | cx->valid = 1; | |
4f86d3a8 LB |
977 | |
978 | #ifndef CONFIG_CPU_IDLE | |
1da177e4 | 979 | cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); |
4f86d3a8 LB |
980 | #else |
981 | cx->latency_ticks = cx->latency; | |
982 | #endif | |
1da177e4 | 983 | |
d550d98d | 984 | return; |
1da177e4 LT |
985 | } |
986 | ||
4be44fcd LB |
987 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
988 | struct acpi_processor_cx *cx) | |
1da177e4 | 989 | { |
02df8b93 VP |
990 | static int bm_check_flag; |
991 | ||
1da177e4 LT |
992 | |
993 | if (!cx->address) | |
d550d98d | 994 | return; |
1da177e4 LT |
995 | |
996 | /* | |
997 | * C3 latency must be less than or equal to 1000 | |
998 | * microseconds. | |
999 | */ | |
1000 | else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { | |
1001 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 1002 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 1003 | return; |
1da177e4 LT |
1004 | } |
1005 | ||
1da177e4 LT |
1006 | /* |
1007 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
1008 | * DMA transfers are used by any ISA device to avoid livelock. | |
1009 | * Note that we could disable Type-F DMA (as recommended by | |
1010 | * the erratum), but this is known to disrupt certain ISA | |
1011 | * devices thus we take the conservative approach. | |
1012 | */ | |
1013 | else if (errata.piix4.fdma) { | |
1014 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 1015 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 1016 | return; |
1da177e4 LT |
1017 | } |
1018 | ||
02df8b93 VP |
1019 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
1020 | if (!bm_check_flag) { | |
1021 | /* Determine whether bm_check is needed based on CPU */ | |
1022 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
1023 | bm_check_flag = pr->flags.bm_check; | |
1024 | } else { | |
1025 | pr->flags.bm_check = bm_check_flag; | |
1026 | } | |
1027 | ||
1028 | if (pr->flags.bm_check) { | |
02df8b93 | 1029 | if (!pr->flags.bm_control) { |
ed3110ef VP |
1030 | if (pr->flags.has_cst != 1) { |
1031 | /* bus mastering control is necessary */ | |
1032 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
1033 | "C3 support requires BM control\n")); | |
1034 | return; | |
1035 | } else { | |
1036 | /* Here we enter C3 without bus mastering */ | |
1037 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
1038 | "C3 support without BM control\n")); | |
1039 | } | |
02df8b93 VP |
1040 | } |
1041 | } else { | |
02df8b93 VP |
1042 | /* |
1043 | * WBINVD should be set in fadt, for C3 state to be | |
1044 | * supported on when bm_check is not required. | |
1045 | */ | |
cee324b1 | 1046 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 1047 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
1048 | "Cache invalidation should work properly" |
1049 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 1050 | return; |
02df8b93 | 1051 | } |
d8c71b6d | 1052 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); |
02df8b93 VP |
1053 | } |
1054 | ||
1da177e4 LT |
1055 | /* |
1056 | * Otherwise we've met all of our C3 requirements. | |
1057 | * Normalize the C3 latency to expidite policy. Enable | |
1058 | * checking of bus mastering status (bm_check) so we can | |
1059 | * use this in our C3 policy | |
1060 | */ | |
1061 | cx->valid = 1; | |
4f86d3a8 LB |
1062 | |
1063 | #ifndef CONFIG_CPU_IDLE | |
1da177e4 | 1064 | cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); |
4f86d3a8 LB |
1065 | #else |
1066 | cx->latency_ticks = cx->latency; | |
1067 | #endif | |
1da177e4 | 1068 | |
d550d98d | 1069 | return; |
1da177e4 LT |
1070 | } |
1071 | ||
1da177e4 LT |
1072 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
1073 | { | |
1074 | unsigned int i; | |
1075 | unsigned int working = 0; | |
6eb0a0fd | 1076 | |
169a0abb | 1077 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 1078 | |
4be44fcd | 1079 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
1080 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
1081 | ||
1082 | switch (cx->type) { | |
1083 | case ACPI_STATE_C1: | |
1084 | cx->valid = 1; | |
1085 | break; | |
1086 | ||
1087 | case ACPI_STATE_C2: | |
1088 | acpi_processor_power_verify_c2(cx); | |
296d93cd | 1089 | if (cx->valid) |
169a0abb | 1090 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
1091 | break; |
1092 | ||
1093 | case ACPI_STATE_C3: | |
1094 | acpi_processor_power_verify_c3(pr, cx); | |
296d93cd | 1095 | if (cx->valid) |
169a0abb | 1096 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
1097 | break; |
1098 | } | |
1099 | ||
1100 | if (cx->valid) | |
1101 | working++; | |
1102 | } | |
bd663347 | 1103 | |
169a0abb | 1104 | acpi_propagate_timer_broadcast(pr); |
1da177e4 LT |
1105 | |
1106 | return (working); | |
1107 | } | |
1108 | ||
4be44fcd | 1109 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
1110 | { |
1111 | unsigned int i; | |
1112 | int result; | |
1113 | ||
1da177e4 LT |
1114 | |
1115 | /* NOTE: the idle thread may not be running while calling | |
1116 | * this function */ | |
1117 | ||
991528d7 VP |
1118 | /* Zero initialize all the C-states info. */ |
1119 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
1120 | ||
1da177e4 | 1121 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 1122 | if (result == -ENODEV) |
c5a114f1 | 1123 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 1124 | |
991528d7 VP |
1125 | if (result) |
1126 | return result; | |
1127 | ||
1128 | acpi_processor_get_power_info_default(pr); | |
1129 | ||
cf824788 | 1130 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 1131 | |
4f86d3a8 | 1132 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
1133 | /* |
1134 | * Set Default Policy | |
1135 | * ------------------ | |
1136 | * Now that we know which states are supported, set the default | |
1137 | * policy. Note that this policy can be changed dynamically | |
1138 | * (e.g. encourage deeper sleeps to conserve battery life when | |
1139 | * not on AC). | |
1140 | */ | |
1141 | result = acpi_processor_set_power_policy(pr); | |
1142 | if (result) | |
d550d98d | 1143 | return result; |
4f86d3a8 | 1144 | #endif |
1da177e4 LT |
1145 | |
1146 | /* | |
1147 | * if one state of type C2 or C3 is available, mark this | |
1148 | * CPU as being "idle manageable" | |
1149 | */ | |
1150 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 1151 | if (pr->power.states[i].valid) { |
1da177e4 | 1152 | pr->power.count = i; |
2203d6ed LT |
1153 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
1154 | pr->flags.power = 1; | |
acf05f4b | 1155 | } |
1da177e4 LT |
1156 | } |
1157 | ||
d550d98d | 1158 | return 0; |
1da177e4 LT |
1159 | } |
1160 | ||
1da177e4 LT |
1161 | static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) |
1162 | { | |
50dd0969 | 1163 | struct acpi_processor *pr = seq->private; |
4be44fcd | 1164 | unsigned int i; |
1da177e4 | 1165 | |
1da177e4 LT |
1166 | |
1167 | if (!pr) | |
1168 | goto end; | |
1169 | ||
1170 | seq_printf(seq, "active state: C%zd\n" | |
4be44fcd | 1171 | "max_cstate: C%d\n" |
5c87579e AV |
1172 | "bus master activity: %08x\n" |
1173 | "maximum allowed latency: %d usec\n", | |
4be44fcd | 1174 | pr->power.state ? pr->power.state - pr->power.states : 0, |
5c87579e AV |
1175 | max_cstate, (unsigned)pr->power.bm_activity, |
1176 | system_latency_constraint()); | |
1da177e4 LT |
1177 | |
1178 | seq_puts(seq, "states:\n"); | |
1179 | ||
1180 | for (i = 1; i <= pr->power.count; i++) { | |
1181 | seq_printf(seq, " %cC%d: ", | |
4be44fcd LB |
1182 | (&pr->power.states[i] == |
1183 | pr->power.state ? '*' : ' '), i); | |
1da177e4 LT |
1184 | |
1185 | if (!pr->power.states[i].valid) { | |
1186 | seq_puts(seq, "<not supported>\n"); | |
1187 | continue; | |
1188 | } | |
1189 | ||
1190 | switch (pr->power.states[i].type) { | |
1191 | case ACPI_STATE_C1: | |
1192 | seq_printf(seq, "type[C1] "); | |
1193 | break; | |
1194 | case ACPI_STATE_C2: | |
1195 | seq_printf(seq, "type[C2] "); | |
1196 | break; | |
1197 | case ACPI_STATE_C3: | |
1198 | seq_printf(seq, "type[C3] "); | |
1199 | break; | |
1200 | default: | |
1201 | seq_printf(seq, "type[--] "); | |
1202 | break; | |
1203 | } | |
1204 | ||
1205 | if (pr->power.states[i].promotion.state) | |
1206 | seq_printf(seq, "promotion[C%zd] ", | |
4be44fcd LB |
1207 | (pr->power.states[i].promotion.state - |
1208 | pr->power.states)); | |
1da177e4 LT |
1209 | else |
1210 | seq_puts(seq, "promotion[--] "); | |
1211 | ||
1212 | if (pr->power.states[i].demotion.state) | |
1213 | seq_printf(seq, "demotion[C%zd] ", | |
4be44fcd LB |
1214 | (pr->power.states[i].demotion.state - |
1215 | pr->power.states)); | |
1da177e4 LT |
1216 | else |
1217 | seq_puts(seq, "demotion[--] "); | |
1218 | ||
a3c6598f | 1219 | seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", |
4be44fcd | 1220 | pr->power.states[i].latency, |
a3c6598f | 1221 | pr->power.states[i].usage, |
b0b7eaaf | 1222 | (unsigned long long)pr->power.states[i].time); |
1da177e4 LT |
1223 | } |
1224 | ||
4be44fcd | 1225 | end: |
d550d98d | 1226 | return 0; |
1da177e4 LT |
1227 | } |
1228 | ||
1229 | static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) | |
1230 | { | |
1231 | return single_open(file, acpi_processor_power_seq_show, | |
4be44fcd | 1232 | PDE(inode)->data); |
1da177e4 LT |
1233 | } |
1234 | ||
d7508032 | 1235 | static const struct file_operations acpi_processor_power_fops = { |
4be44fcd LB |
1236 | .open = acpi_processor_power_open_fs, |
1237 | .read = seq_read, | |
1238 | .llseek = seq_lseek, | |
1239 | .release = single_release, | |
1da177e4 LT |
1240 | }; |
1241 | ||
4f86d3a8 LB |
1242 | #ifndef CONFIG_CPU_IDLE |
1243 | ||
1244 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1245 | { | |
1246 | int result = 0; | |
1247 | ||
1248 | ||
1249 | if (!pr) | |
1250 | return -EINVAL; | |
1251 | ||
1252 | if (nocst) { | |
1253 | return -ENODEV; | |
1254 | } | |
1255 | ||
1256 | if (!pr->flags.power_setup_done) | |
1257 | return -ENODEV; | |
1258 | ||
1259 | /* Fall back to the default idle loop */ | |
1260 | pm_idle = pm_idle_save; | |
1261 | synchronize_sched(); /* Relies on interrupts forcing exit from idle. */ | |
1262 | ||
1263 | pr->flags.power = 0; | |
1264 | result = acpi_processor_get_power_info(pr); | |
1265 | if ((pr->flags.power == 1) && (pr->flags.power_setup_done)) | |
1266 | pm_idle = acpi_processor_idle; | |
1267 | ||
1268 | return result; | |
1269 | } | |
1270 | ||
1fec74a9 | 1271 | #ifdef CONFIG_SMP |
5c87579e AV |
1272 | static void smp_callback(void *v) |
1273 | { | |
1274 | /* we already woke the CPU up, nothing more to do */ | |
1275 | } | |
1276 | ||
1277 | /* | |
1278 | * This function gets called when a part of the kernel has a new latency | |
1279 | * requirement. This means we need to get all processors out of their C-state, | |
1280 | * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that | |
1281 | * wakes them all right up. | |
1282 | */ | |
1283 | static int acpi_processor_latency_notify(struct notifier_block *b, | |
1284 | unsigned long l, void *v) | |
1285 | { | |
1286 | smp_call_function(smp_callback, NULL, 0, 1); | |
1287 | return NOTIFY_OK; | |
1288 | } | |
1289 | ||
1290 | static struct notifier_block acpi_processor_latency_notifier = { | |
1291 | .notifier_call = acpi_processor_latency_notify, | |
1292 | }; | |
4f86d3a8 LB |
1293 | |
1294 | #endif | |
1295 | ||
1296 | #else /* CONFIG_CPU_IDLE */ | |
1297 | ||
1298 | /** | |
1299 | * acpi_idle_bm_check - checks if bus master activity was detected | |
1300 | */ | |
1301 | static int acpi_idle_bm_check(void) | |
1302 | { | |
1303 | u32 bm_status = 0; | |
1304 | ||
1305 | acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); | |
1306 | if (bm_status) | |
1307 | acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); | |
1308 | /* | |
1309 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
1310 | * the true state of bus mastering activity; forcing us to | |
1311 | * manually check the BMIDEA bit of each IDE channel. | |
1312 | */ | |
1313 | else if (errata.piix4.bmisx) { | |
1314 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
1315 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
1316 | bm_status = 1; | |
1317 | } | |
1318 | return bm_status; | |
1319 | } | |
1320 | ||
1321 | /** | |
1322 | * acpi_idle_update_bm_rld - updates the BM_RLD bit depending on target state | |
1323 | * @pr: the processor | |
1324 | * @target: the new target state | |
1325 | */ | |
1326 | static inline void acpi_idle_update_bm_rld(struct acpi_processor *pr, | |
1327 | struct acpi_processor_cx *target) | |
1328 | { | |
1329 | if (pr->flags.bm_rld_set && target->type != ACPI_STATE_C3) { | |
1330 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); | |
1331 | pr->flags.bm_rld_set = 0; | |
1332 | } | |
1333 | ||
1334 | if (!pr->flags.bm_rld_set && target->type == ACPI_STATE_C3) { | |
1335 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); | |
1336 | pr->flags.bm_rld_set = 1; | |
1337 | } | |
1338 | } | |
1339 | ||
1340 | /** | |
1341 | * acpi_idle_do_entry - a helper function that does C2 and C3 type entry | |
1342 | * @cx: cstate data | |
1343 | */ | |
1344 | static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) | |
1345 | { | |
1346 | if (cx->space_id == ACPI_CSTATE_FFH) { | |
1347 | /* Call into architectural FFH based C-state */ | |
1348 | acpi_processor_ffh_cstate_enter(cx); | |
1349 | } else { | |
1350 | int unused; | |
1351 | /* IO port based C-state */ | |
1352 | inb(cx->address); | |
1353 | /* Dummy wait op - must do something useless after P_LVL2 read | |
1354 | because chipsets cannot guarantee that STPCLK# signal | |
1355 | gets asserted in time to freeze execution properly. */ | |
1356 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
1357 | } | |
1358 | } | |
1359 | ||
1360 | /** | |
1361 | * acpi_idle_enter_c1 - enters an ACPI C1 state-type | |
1362 | * @dev: the target CPU | |
1363 | * @state: the state data | |
1364 | * | |
1365 | * This is equivalent to the HALT instruction. | |
1366 | */ | |
1367 | static int acpi_idle_enter_c1(struct cpuidle_device *dev, | |
1368 | struct cpuidle_state *state) | |
1369 | { | |
1370 | struct acpi_processor *pr; | |
1371 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
1372 | pr = processors[smp_processor_id()]; | |
1373 | ||
1374 | if (unlikely(!pr)) | |
1375 | return 0; | |
1376 | ||
1377 | if (pr->flags.bm_check) | |
1378 | acpi_idle_update_bm_rld(pr, cx); | |
1379 | ||
ddc081a1 | 1380 | acpi_safe_halt(); |
4f86d3a8 LB |
1381 | |
1382 | cx->usage++; | |
1383 | ||
1384 | return 0; | |
1385 | } | |
1386 | ||
1387 | /** | |
1388 | * acpi_idle_enter_simple - enters an ACPI state without BM handling | |
1389 | * @dev: the target CPU | |
1390 | * @state: the state data | |
1391 | */ | |
1392 | static int acpi_idle_enter_simple(struct cpuidle_device *dev, | |
1393 | struct cpuidle_state *state) | |
1394 | { | |
1395 | struct acpi_processor *pr; | |
1396 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
1397 | u32 t1, t2; | |
50629118 VP |
1398 | int sleep_ticks = 0; |
1399 | ||
4f86d3a8 LB |
1400 | pr = processors[smp_processor_id()]; |
1401 | ||
1402 | if (unlikely(!pr)) | |
1403 | return 0; | |
1404 | ||
e196441b LB |
1405 | if (acpi_idle_suspend) |
1406 | return(acpi_idle_enter_c1(dev, state)); | |
1407 | ||
4f86d3a8 LB |
1408 | local_irq_disable(); |
1409 | current_thread_info()->status &= ~TS_POLLING; | |
1410 | /* | |
1411 | * TS_POLLING-cleared state must be visible before we test | |
1412 | * NEED_RESCHED: | |
1413 | */ | |
1414 | smp_mb(); | |
1415 | ||
1416 | if (unlikely(need_resched())) { | |
1417 | current_thread_info()->status |= TS_POLLING; | |
1418 | local_irq_enable(); | |
1419 | return 0; | |
1420 | } | |
1421 | ||
e17bcb43 TG |
1422 | /* |
1423 | * Must be done before busmaster disable as we might need to | |
1424 | * access HPET ! | |
1425 | */ | |
1426 | acpi_state_timer_broadcast(pr, cx, 1); | |
1427 | ||
1428 | if (pr->flags.bm_check) | |
1429 | acpi_idle_update_bm_rld(pr, cx); | |
1430 | ||
4f86d3a8 LB |
1431 | if (cx->type == ACPI_STATE_C3) |
1432 | ACPI_FLUSH_CPU_CACHE(); | |
1433 | ||
1434 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
50629118 VP |
1435 | /* Tell the scheduler that we are going deep-idle: */ |
1436 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
1437 | acpi_idle_do_entry(cx); |
1438 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
1439 | ||
1440 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) | |
1441 | /* TSC could halt in idle, so notify users */ | |
1442 | mark_tsc_unstable("TSC halts in idle");; | |
1443 | #endif | |
50629118 VP |
1444 | sleep_ticks = ticks_elapsed(t1, t2); |
1445 | ||
1446 | /* Tell the scheduler how much we idled: */ | |
1447 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
1448 | |
1449 | local_irq_enable(); | |
1450 | current_thread_info()->status |= TS_POLLING; | |
1451 | ||
1452 | cx->usage++; | |
1453 | ||
1454 | acpi_state_timer_broadcast(pr, cx, 0); | |
50629118 | 1455 | cx->time += sleep_ticks; |
4f86d3a8 LB |
1456 | return ticks_elapsed_in_us(t1, t2); |
1457 | } | |
1458 | ||
1459 | static int c3_cpu_count; | |
1460 | static DEFINE_SPINLOCK(c3_lock); | |
1461 | ||
1462 | /** | |
1463 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
1464 | * @dev: the target CPU | |
1465 | * @state: the state data | |
1466 | * | |
1467 | * If BM is detected, the deepest non-C3 idle state is entered instead. | |
1468 | */ | |
1469 | static int acpi_idle_enter_bm(struct cpuidle_device *dev, | |
1470 | struct cpuidle_state *state) | |
1471 | { | |
1472 | struct acpi_processor *pr; | |
1473 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
1474 | u32 t1, t2; | |
50629118 VP |
1475 | int sleep_ticks = 0; |
1476 | ||
4f86d3a8 LB |
1477 | pr = processors[smp_processor_id()]; |
1478 | ||
1479 | if (unlikely(!pr)) | |
1480 | return 0; | |
1481 | ||
e196441b LB |
1482 | if (acpi_idle_suspend) |
1483 | return(acpi_idle_enter_c1(dev, state)); | |
1484 | ||
ddc081a1 VP |
1485 | if (acpi_idle_bm_check()) { |
1486 | if (dev->safe_state) { | |
1487 | return dev->safe_state->enter(dev, dev->safe_state); | |
1488 | } else { | |
1489 | acpi_safe_halt(); | |
1490 | return 0; | |
1491 | } | |
1492 | } | |
1493 | ||
4f86d3a8 LB |
1494 | local_irq_disable(); |
1495 | current_thread_info()->status &= ~TS_POLLING; | |
1496 | /* | |
1497 | * TS_POLLING-cleared state must be visible before we test | |
1498 | * NEED_RESCHED: | |
1499 | */ | |
1500 | smp_mb(); | |
1501 | ||
1502 | if (unlikely(need_resched())) { | |
1503 | current_thread_info()->status |= TS_POLLING; | |
1504 | local_irq_enable(); | |
1505 | return 0; | |
1506 | } | |
1507 | ||
50629118 VP |
1508 | /* Tell the scheduler that we are going deep-idle: */ |
1509 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
1510 | /* |
1511 | * Must be done before busmaster disable as we might need to | |
1512 | * access HPET ! | |
1513 | */ | |
1514 | acpi_state_timer_broadcast(pr, cx, 1); | |
1515 | ||
ddc081a1 | 1516 | acpi_idle_update_bm_rld(pr, cx); |
4f86d3a8 | 1517 | |
ddc081a1 VP |
1518 | /* |
1519 | * disable bus master | |
1520 | * bm_check implies we need ARB_DIS | |
1521 | * !bm_check implies we need cache flush | |
1522 | * bm_control implies whether we can do ARB_DIS | |
1523 | * | |
1524 | * That leaves a case where bm_check is set and bm_control is | |
1525 | * not set. In that case we cannot do much, we enter C3 | |
1526 | * without doing anything. | |
1527 | */ | |
1528 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 LB |
1529 | spin_lock(&c3_lock); |
1530 | c3_cpu_count++; | |
1531 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
1532 | if (c3_cpu_count == num_online_cpus()) | |
1533 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); | |
1534 | spin_unlock(&c3_lock); | |
ddc081a1 VP |
1535 | } else if (!pr->flags.bm_check) { |
1536 | ACPI_FLUSH_CPU_CACHE(); | |
1537 | } | |
4f86d3a8 | 1538 | |
ddc081a1 VP |
1539 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
1540 | acpi_idle_do_entry(cx); | |
1541 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
4f86d3a8 | 1542 | |
ddc081a1 VP |
1543 | /* Re-enable bus master arbitration */ |
1544 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 | 1545 | spin_lock(&c3_lock); |
ddc081a1 | 1546 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); |
4f86d3a8 LB |
1547 | c3_cpu_count--; |
1548 | spin_unlock(&c3_lock); | |
1549 | } | |
1550 | ||
1551 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) | |
1552 | /* TSC could halt in idle, so notify users */ | |
1553 | mark_tsc_unstable("TSC halts in idle"); | |
1554 | #endif | |
50629118 VP |
1555 | sleep_ticks = ticks_elapsed(t1, t2); |
1556 | /* Tell the scheduler how much we idled: */ | |
1557 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
1558 | |
1559 | local_irq_enable(); | |
1560 | current_thread_info()->status |= TS_POLLING; | |
1561 | ||
1562 | cx->usage++; | |
1563 | ||
1564 | acpi_state_timer_broadcast(pr, cx, 0); | |
50629118 | 1565 | cx->time += sleep_ticks; |
4f86d3a8 LB |
1566 | return ticks_elapsed_in_us(t1, t2); |
1567 | } | |
1568 | ||
1569 | struct cpuidle_driver acpi_idle_driver = { | |
1570 | .name = "acpi_idle", | |
1571 | .owner = THIS_MODULE, | |
1572 | }; | |
1573 | ||
1574 | /** | |
1575 | * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE | |
1576 | * @pr: the ACPI processor | |
1577 | */ | |
1578 | static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) | |
1579 | { | |
1580 | int i, count = 0; | |
1581 | struct acpi_processor_cx *cx; | |
1582 | struct cpuidle_state *state; | |
1583 | struct cpuidle_device *dev = &pr->power.dev; | |
1584 | ||
1585 | if (!pr->flags.power_setup_done) | |
1586 | return -EINVAL; | |
1587 | ||
1588 | if (pr->flags.power == 0) { | |
1589 | return -EINVAL; | |
1590 | } | |
1591 | ||
1592 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { | |
1593 | cx = &pr->power.states[i]; | |
1594 | state = &dev->states[count]; | |
1595 | ||
1596 | if (!cx->valid) | |
1597 | continue; | |
1598 | ||
1599 | #ifdef CONFIG_HOTPLUG_CPU | |
1600 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
1601 | !pr->flags.has_cst && | |
1602 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
1603 | continue; | |
1fec74a9 | 1604 | #endif |
4f86d3a8 LB |
1605 | cpuidle_set_statedata(state, cx); |
1606 | ||
1607 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); | |
1608 | state->exit_latency = cx->latency; | |
1609 | state->target_residency = cx->latency * 6; | |
1610 | state->power_usage = cx->power; | |
1611 | ||
1612 | state->flags = 0; | |
1613 | switch (cx->type) { | |
1614 | case ACPI_STATE_C1: | |
1615 | state->flags |= CPUIDLE_FLAG_SHALLOW; | |
1616 | state->enter = acpi_idle_enter_c1; | |
ddc081a1 | 1617 | dev->safe_state = state; |
4f86d3a8 LB |
1618 | break; |
1619 | ||
1620 | case ACPI_STATE_C2: | |
1621 | state->flags |= CPUIDLE_FLAG_BALANCED; | |
1622 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1623 | state->enter = acpi_idle_enter_simple; | |
ddc081a1 | 1624 | dev->safe_state = state; |
4f86d3a8 LB |
1625 | break; |
1626 | ||
1627 | case ACPI_STATE_C3: | |
1628 | state->flags |= CPUIDLE_FLAG_DEEP; | |
1629 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1630 | state->flags |= CPUIDLE_FLAG_CHECK_BM; | |
1631 | state->enter = pr->flags.bm_check ? | |
1632 | acpi_idle_enter_bm : | |
1633 | acpi_idle_enter_simple; | |
1634 | break; | |
1635 | } | |
1636 | ||
1637 | count++; | |
1638 | } | |
1639 | ||
1640 | dev->state_count = count; | |
1641 | ||
1642 | if (!count) | |
1643 | return -EINVAL; | |
1644 | ||
4f86d3a8 LB |
1645 | return 0; |
1646 | } | |
1647 | ||
1648 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1649 | { | |
1650 | int ret; | |
1651 | ||
1652 | if (!pr) | |
1653 | return -EINVAL; | |
1654 | ||
1655 | if (nocst) { | |
1656 | return -ENODEV; | |
1657 | } | |
1658 | ||
1659 | if (!pr->flags.power_setup_done) | |
1660 | return -ENODEV; | |
1661 | ||
1662 | cpuidle_pause_and_lock(); | |
1663 | cpuidle_disable_device(&pr->power.dev); | |
1664 | acpi_processor_get_power_info(pr); | |
1665 | acpi_processor_setup_cpuidle(pr); | |
1666 | ret = cpuidle_enable_device(&pr->power.dev); | |
1667 | cpuidle_resume_and_unlock(); | |
1668 | ||
1669 | return ret; | |
1670 | } | |
1671 | ||
1672 | #endif /* CONFIG_CPU_IDLE */ | |
5c87579e | 1673 | |
7af8b660 | 1674 | int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, |
4be44fcd | 1675 | struct acpi_device *device) |
1da177e4 | 1676 | { |
4be44fcd | 1677 | acpi_status status = 0; |
b6835052 | 1678 | static int first_run; |
4be44fcd | 1679 | struct proc_dir_entry *entry = NULL; |
1da177e4 LT |
1680 | unsigned int i; |
1681 | ||
1da177e4 LT |
1682 | |
1683 | if (!first_run) { | |
1684 | dmi_check_system(processor_power_dmi_table); | |
c1c30634 | 1685 | max_cstate = acpi_processor_cstate_check(max_cstate); |
1da177e4 | 1686 | if (max_cstate < ACPI_C_STATES_MAX) |
4be44fcd LB |
1687 | printk(KERN_NOTICE |
1688 | "ACPI: processor limited to max C-state %d\n", | |
1689 | max_cstate); | |
1da177e4 | 1690 | first_run++; |
4f86d3a8 | 1691 | #if !defined (CONFIG_CPU_IDLE) && defined (CONFIG_SMP) |
5c87579e | 1692 | register_latency_notifier(&acpi_processor_latency_notifier); |
1fec74a9 | 1693 | #endif |
1da177e4 LT |
1694 | } |
1695 | ||
02df8b93 | 1696 | if (!pr) |
d550d98d | 1697 | return -EINVAL; |
02df8b93 | 1698 | |
cee324b1 | 1699 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1700 | status = |
cee324b1 | 1701 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1702 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1703 | ACPI_EXCEPTION((AE_INFO, status, |
1704 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1705 | } |
1706 | } | |
1707 | ||
1708 | acpi_processor_get_power_info(pr); | |
4f86d3a8 | 1709 | pr->flags.power_setup_done = 1; |
1da177e4 LT |
1710 | |
1711 | /* | |
1712 | * Install the idle handler if processor power management is supported. | |
1713 | * Note that we use previously set idle handler will be used on | |
1714 | * platforms that only support C1. | |
1715 | */ | |
1716 | if ((pr->flags.power) && (!boot_option_idle_override)) { | |
4f86d3a8 LB |
1717 | #ifdef CONFIG_CPU_IDLE |
1718 | acpi_processor_setup_cpuidle(pr); | |
1719 | pr->power.dev.cpu = pr->id; | |
1720 | if (cpuidle_register_device(&pr->power.dev)) | |
1721 | return -EIO; | |
1722 | #endif | |
1723 | ||
1da177e4 LT |
1724 | printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id); |
1725 | for (i = 1; i <= pr->power.count; i++) | |
1726 | if (pr->power.states[i].valid) | |
4be44fcd LB |
1727 | printk(" C%d[C%d]", i, |
1728 | pr->power.states[i].type); | |
1da177e4 LT |
1729 | printk(")\n"); |
1730 | ||
4f86d3a8 | 1731 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
1732 | if (pr->id == 0) { |
1733 | pm_idle_save = pm_idle; | |
1734 | pm_idle = acpi_processor_idle; | |
1735 | } | |
4f86d3a8 | 1736 | #endif |
1da177e4 LT |
1737 | } |
1738 | ||
1739 | /* 'power' [R] */ | |
1740 | entry = create_proc_entry(ACPI_PROCESSOR_FILE_POWER, | |
4be44fcd | 1741 | S_IRUGO, acpi_device_dir(device)); |
1da177e4 | 1742 | if (!entry) |
a6fc6720 | 1743 | return -EIO; |
1da177e4 LT |
1744 | else { |
1745 | entry->proc_fops = &acpi_processor_power_fops; | |
1746 | entry->data = acpi_driver_data(device); | |
1747 | entry->owner = THIS_MODULE; | |
1748 | } | |
1749 | ||
d550d98d | 1750 | return 0; |
1da177e4 LT |
1751 | } |
1752 | ||
4be44fcd LB |
1753 | int acpi_processor_power_exit(struct acpi_processor *pr, |
1754 | struct acpi_device *device) | |
1da177e4 | 1755 | { |
4f86d3a8 LB |
1756 | #ifdef CONFIG_CPU_IDLE |
1757 | if ((pr->flags.power) && (!boot_option_idle_override)) | |
1758 | cpuidle_unregister_device(&pr->power.dev); | |
1759 | #endif | |
1da177e4 LT |
1760 | pr->flags.power_setup_done = 0; |
1761 | ||
1762 | if (acpi_device_dir(device)) | |
4be44fcd LB |
1763 | remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, |
1764 | acpi_device_dir(device)); | |
1da177e4 | 1765 | |
4f86d3a8 LB |
1766 | #ifndef CONFIG_CPU_IDLE |
1767 | ||
1da177e4 LT |
1768 | /* Unregister the idle handler when processor #0 is removed. */ |
1769 | if (pr->id == 0) { | |
1770 | pm_idle = pm_idle_save; | |
1771 | ||
1772 | /* | |
1773 | * We are about to unload the current idle thread pm callback | |
1774 | * (pm_idle), Wait for all processors to update cached/local | |
1775 | * copies of pm_idle before proceeding. | |
1776 | */ | |
1777 | cpu_idle_wait(); | |
1fec74a9 | 1778 | #ifdef CONFIG_SMP |
5c87579e | 1779 | unregister_latency_notifier(&acpi_processor_latency_notifier); |
1fec74a9 | 1780 | #endif |
1da177e4 | 1781 | } |
4f86d3a8 | 1782 | #endif |
1da177e4 | 1783 | |
d550d98d | 1784 | return 0; |
1da177e4 | 1785 | } |