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1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/cpufreq.h> | |
35 | #include <linux/proc_fs.h> | |
36 | #include <linux/seq_file.h> | |
37 | #include <linux/acpi.h> | |
38 | #include <linux/dmi.h> | |
39 | #include <linux/moduleparam.h> | |
4e57b681 | 40 | #include <linux/sched.h> /* need_resched() */ |
5c87579e | 41 | #include <linux/latency.h> |
e9e2cdb4 | 42 | #include <linux/clockchips.h> |
4f86d3a8 | 43 | #include <linux/cpuidle.h> |
1da177e4 | 44 | |
3434933b TG |
45 | /* |
46 | * Include the apic definitions for x86 to have the APIC timer related defines | |
47 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
48 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
49 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
50 | */ | |
51 | #ifdef CONFIG_X86 | |
52 | #include <asm/apic.h> | |
53 | #endif | |
54 | ||
1da177e4 LT |
55 | #include <asm/io.h> |
56 | #include <asm/uaccess.h> | |
57 | ||
58 | #include <acpi/acpi_bus.h> | |
59 | #include <acpi/processor.h> | |
60 | ||
61 | #define ACPI_PROCESSOR_COMPONENT 0x01000000 | |
62 | #define ACPI_PROCESSOR_CLASS "processor" | |
1da177e4 | 63 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 64 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 65 | #define ACPI_PROCESSOR_FILE_POWER "power" |
1da177e4 | 66 | #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000) |
2aa44d05 | 67 | #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) |
4f86d3a8 | 68 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
69 | #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */ |
70 | #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */ | |
b6835052 | 71 | static void (*pm_idle_save) (void) __read_mostly; |
4f86d3a8 LB |
72 | #else |
73 | #define C2_OVERHEAD 1 /* 1us */ | |
74 | #define C3_OVERHEAD 1 /* 1us */ | |
75 | #endif | |
76 | #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) | |
1da177e4 | 77 | |
4f86d3a8 LB |
78 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
79 | module_param(max_cstate, uint, 0000); | |
b6835052 | 80 | static unsigned int nocst __read_mostly; |
1da177e4 LT |
81 | module_param(nocst, uint, 0000); |
82 | ||
4f86d3a8 | 83 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
84 | /* |
85 | * bm_history -- bit-mask with a bit per jiffy of bus-master activity | |
86 | * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms | |
87 | * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms | |
88 | * 100 HZ: 0x0000000F: 4 jiffies = 40ms | |
89 | * reduce history for more aggressive entry into C3 | |
90 | */ | |
b6835052 | 91 | static unsigned int bm_history __read_mostly = |
4be44fcd | 92 | (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1)); |
1da177e4 | 93 | module_param(bm_history, uint, 0644); |
4f86d3a8 LB |
94 | |
95 | static int acpi_processor_set_power_policy(struct acpi_processor *pr); | |
96 | ||
4963f620 LB |
97 | #else /* CONFIG_CPU_IDLE */ |
98 | static unsigned int latency_factor __read_mostly = 6; | |
99 | module_param(latency_factor, uint, 0644); | |
4f86d3a8 | 100 | #endif |
1da177e4 LT |
101 | |
102 | /* | |
103 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
104 | * For now disable this. Probably a bug somewhere else. | |
105 | * | |
106 | * To skip this limit, boot/load with a large max_cstate limit. | |
107 | */ | |
1855256c | 108 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
109 | { |
110 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
111 | return 0; | |
112 | ||
3d35600a | 113 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
114 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
115 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 116 | |
3d35600a | 117 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
118 | |
119 | return 0; | |
120 | } | |
121 | ||
7ded5689 AR |
122 | /* Actually this shouldn't be __cpuinitdata, would be better to fix the |
123 | callers to only run once -AK */ | |
124 | static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { | |
f831335d BS |
125 | { set_max_cstate, "IBM ThinkPad R40e", { |
126 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
127 | DMI_MATCH(DMI_BIOS_VERSION,"1SET70WW")}, (void *)1}, | |
876c184b TR |
128 | { set_max_cstate, "IBM ThinkPad R40e", { |
129 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
130 | DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1}, | |
131 | { set_max_cstate, "IBM ThinkPad R40e", { | |
132 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
133 | DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1}, | |
134 | { set_max_cstate, "IBM ThinkPad R40e", { | |
135 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
136 | DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1}, | |
137 | { set_max_cstate, "IBM ThinkPad R40e", { | |
138 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
139 | DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1}, | |
140 | { set_max_cstate, "IBM ThinkPad R40e", { | |
141 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
142 | DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1}, | |
143 | { set_max_cstate, "IBM ThinkPad R40e", { | |
144 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
145 | DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1}, | |
146 | { set_max_cstate, "IBM ThinkPad R40e", { | |
147 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
148 | DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1}, | |
149 | { set_max_cstate, "IBM ThinkPad R40e", { | |
150 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
151 | DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1}, | |
152 | { set_max_cstate, "IBM ThinkPad R40e", { | |
153 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
154 | DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1}, | |
155 | { set_max_cstate, "IBM ThinkPad R40e", { | |
156 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
157 | DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1}, | |
158 | { set_max_cstate, "IBM ThinkPad R40e", { | |
159 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
160 | DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1}, | |
161 | { set_max_cstate, "IBM ThinkPad R40e", { | |
162 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
163 | DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1}, | |
164 | { set_max_cstate, "IBM ThinkPad R40e", { | |
165 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
166 | DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1}, | |
167 | { set_max_cstate, "IBM ThinkPad R40e", { | |
168 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
169 | DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1}, | |
170 | { set_max_cstate, "IBM ThinkPad R40e", { | |
171 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
172 | DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1}, | |
173 | { set_max_cstate, "Medion 41700", { | |
174 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
175 | DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1}, | |
176 | { set_max_cstate, "Clevo 5600D", { | |
177 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
178 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 179 | (void *)2}, |
1da177e4 LT |
180 | {}, |
181 | }; | |
182 | ||
4be44fcd | 183 | static inline u32 ticks_elapsed(u32 t1, u32 t2) |
1da177e4 LT |
184 | { |
185 | if (t2 >= t1) | |
186 | return (t2 - t1); | |
cee324b1 | 187 | else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) |
1da177e4 LT |
188 | return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); |
189 | else | |
190 | return ((0xFFFFFFFF - t1) + t2); | |
191 | } | |
192 | ||
4f86d3a8 LB |
193 | static inline u32 ticks_elapsed_in_us(u32 t1, u32 t2) |
194 | { | |
195 | if (t2 >= t1) | |
196 | return PM_TIMER_TICKS_TO_US(t2 - t1); | |
197 | else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) | |
198 | return PM_TIMER_TICKS_TO_US(((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); | |
199 | else | |
200 | return PM_TIMER_TICKS_TO_US((0xFFFFFFFF - t1) + t2); | |
201 | } | |
202 | ||
203 | #ifndef CONFIG_CPU_IDLE | |
204 | ||
1da177e4 | 205 | static void |
4be44fcd LB |
206 | acpi_processor_power_activate(struct acpi_processor *pr, |
207 | struct acpi_processor_cx *new) | |
1da177e4 | 208 | { |
4be44fcd | 209 | struct acpi_processor_cx *old; |
1da177e4 LT |
210 | |
211 | if (!pr || !new) | |
212 | return; | |
213 | ||
214 | old = pr->power.state; | |
215 | ||
216 | if (old) | |
217 | old->promotion.count = 0; | |
4be44fcd | 218 | new->demotion.count = 0; |
1da177e4 LT |
219 | |
220 | /* Cleanup from old state. */ | |
221 | if (old) { | |
222 | switch (old->type) { | |
223 | case ACPI_STATE_C3: | |
224 | /* Disable bus master reload */ | |
02df8b93 | 225 | if (new->type != ACPI_STATE_C3 && pr->flags.bm_check) |
d8c71b6d | 226 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); |
1da177e4 LT |
227 | break; |
228 | } | |
229 | } | |
230 | ||
231 | /* Prepare to use new state. */ | |
232 | switch (new->type) { | |
233 | case ACPI_STATE_C3: | |
234 | /* Enable bus master reload */ | |
02df8b93 | 235 | if (old->type != ACPI_STATE_C3 && pr->flags.bm_check) |
d8c71b6d | 236 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 LT |
237 | break; |
238 | } | |
239 | ||
240 | pr->power.state = new; | |
241 | ||
242 | return; | |
243 | } | |
244 | ||
64c7c8f8 NP |
245 | static void acpi_safe_halt(void) |
246 | { | |
495ab9c0 | 247 | current_thread_info()->status &= ~TS_POLLING; |
0888f06a IM |
248 | /* |
249 | * TS_POLLING-cleared state must be visible before we | |
250 | * test NEED_RESCHED: | |
251 | */ | |
252 | smp_mb(); | |
64c7c8f8 NP |
253 | if (!need_resched()) |
254 | safe_halt(); | |
495ab9c0 | 255 | current_thread_info()->status |= TS_POLLING; |
64c7c8f8 NP |
256 | } |
257 | ||
4be44fcd | 258 | static atomic_t c3_cpu_count; |
1da177e4 | 259 | |
991528d7 VP |
260 | /* Common C-state entry for C2, C3, .. */ |
261 | static void acpi_cstate_enter(struct acpi_processor_cx *cstate) | |
262 | { | |
263 | if (cstate->space_id == ACPI_CSTATE_FFH) { | |
264 | /* Call into architectural FFH based C-state */ | |
265 | acpi_processor_ffh_cstate_enter(cstate); | |
266 | } else { | |
267 | int unused; | |
268 | /* IO port based C-state */ | |
269 | inb(cstate->address); | |
270 | /* Dummy wait op - must do something useless after P_LVL2 read | |
271 | because chipsets cannot guarantee that STPCLK# signal | |
272 | gets asserted in time to freeze execution properly. */ | |
cee324b1 | 273 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); |
991528d7 VP |
274 | } |
275 | } | |
4f86d3a8 | 276 | #endif /* !CONFIG_CPU_IDLE */ |
991528d7 | 277 | |
169a0abb TG |
278 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
279 | ||
280 | /* | |
281 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
282 | * This seems to be a common problem on AMD boxen, but other vendors |
283 | * are affected too. We pick the most conservative approach: we assume | |
284 | * that the local APIC stops in both C2 and C3. | |
169a0abb TG |
285 | */ |
286 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
287 | struct acpi_processor_cx *cx) | |
288 | { | |
289 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 290 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb TG |
291 | |
292 | /* | |
293 | * Check, if one of the previous states already marked the lapic | |
294 | * unstable | |
295 | */ | |
296 | if (pwr->timer_broadcast_on_state < state) | |
297 | return; | |
298 | ||
e585bef8 | 299 | if (cx->type >= type) |
296d93cd | 300 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
301 | } |
302 | ||
303 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) | |
304 | { | |
e9e2cdb4 TG |
305 | unsigned long reason; |
306 | ||
307 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
308 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
309 | ||
310 | clockevents_notify(reason, &pr->id); | |
e9e2cdb4 TG |
311 | } |
312 | ||
313 | /* Power(C) State timer broadcast control */ | |
314 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, | |
315 | struct acpi_processor_cx *cx, | |
316 | int broadcast) | |
317 | { | |
e9e2cdb4 TG |
318 | int state = cx - pr->power.states; |
319 | ||
320 | if (state >= pr->power.timer_broadcast_on_state) { | |
321 | unsigned long reason; | |
322 | ||
323 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
324 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
325 | clockevents_notify(reason, &pr->id); | |
326 | } | |
169a0abb TG |
327 | } |
328 | ||
329 | #else | |
330 | ||
331 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
332 | struct acpi_processor_cx *cstate) { } | |
333 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { } | |
e9e2cdb4 TG |
334 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, |
335 | struct acpi_processor_cx *cx, | |
336 | int broadcast) | |
337 | { | |
338 | } | |
169a0abb TG |
339 | |
340 | #endif | |
341 | ||
b04e7bdb TG |
342 | /* |
343 | * Suspend / resume control | |
344 | */ | |
345 | static int acpi_idle_suspend; | |
346 | ||
347 | int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) | |
348 | { | |
349 | acpi_idle_suspend = 1; | |
350 | return 0; | |
351 | } | |
352 | ||
353 | int acpi_processor_resume(struct acpi_device * device) | |
354 | { | |
355 | acpi_idle_suspend = 0; | |
356 | return 0; | |
357 | } | |
358 | ||
4f86d3a8 | 359 | #ifndef CONFIG_CPU_IDLE |
4be44fcd | 360 | static void acpi_processor_idle(void) |
1da177e4 | 361 | { |
4be44fcd | 362 | struct acpi_processor *pr = NULL; |
1da177e4 LT |
363 | struct acpi_processor_cx *cx = NULL; |
364 | struct acpi_processor_cx *next_state = NULL; | |
4be44fcd LB |
365 | int sleep_ticks = 0; |
366 | u32 t1, t2 = 0; | |
1da177e4 | 367 | |
1da177e4 LT |
368 | /* |
369 | * Interrupts must be disabled during bus mastering calculations and | |
370 | * for C2/C3 transitions. | |
371 | */ | |
372 | local_irq_disable(); | |
373 | ||
d5a3d32a VP |
374 | pr = processors[smp_processor_id()]; |
375 | if (!pr) { | |
376 | local_irq_enable(); | |
377 | return; | |
378 | } | |
379 | ||
1da177e4 LT |
380 | /* |
381 | * Check whether we truly need to go idle, or should | |
382 | * reschedule: | |
383 | */ | |
384 | if (unlikely(need_resched())) { | |
385 | local_irq_enable(); | |
386 | return; | |
387 | } | |
388 | ||
389 | cx = pr->power.state; | |
b04e7bdb | 390 | if (!cx || acpi_idle_suspend) { |
64c7c8f8 NP |
391 | if (pm_idle_save) |
392 | pm_idle_save(); | |
393 | else | |
394 | acpi_safe_halt(); | |
395 | return; | |
396 | } | |
1da177e4 LT |
397 | |
398 | /* | |
399 | * Check BM Activity | |
400 | * ----------------- | |
401 | * Check for bus mastering activity (if required), record, and check | |
402 | * for demotion. | |
403 | */ | |
404 | if (pr->flags.bm_check) { | |
4be44fcd LB |
405 | u32 bm_status = 0; |
406 | unsigned long diff = jiffies - pr->power.bm_check_timestamp; | |
1da177e4 | 407 | |
c5ab81ca DB |
408 | if (diff > 31) |
409 | diff = 31; | |
1da177e4 | 410 | |
c5ab81ca | 411 | pr->power.bm_activity <<= diff; |
1da177e4 | 412 | |
d8c71b6d | 413 | acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
1da177e4 | 414 | if (bm_status) { |
c5ab81ca | 415 | pr->power.bm_activity |= 0x1; |
d8c71b6d | 416 | acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
1da177e4 LT |
417 | } |
418 | /* | |
419 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
420 | * the true state of bus mastering activity; forcing us to | |
421 | * manually check the BMIDEA bit of each IDE channel. | |
422 | */ | |
423 | else if (errata.piix4.bmisx) { | |
424 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
4be44fcd | 425 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) |
c5ab81ca | 426 | pr->power.bm_activity |= 0x1; |
1da177e4 LT |
427 | } |
428 | ||
429 | pr->power.bm_check_timestamp = jiffies; | |
430 | ||
431 | /* | |
c4a001b1 | 432 | * If bus mastering is or was active this jiffy, demote |
1da177e4 LT |
433 | * to avoid a faulty transition. Note that the processor |
434 | * won't enter a low-power state during this call (to this | |
c4a001b1 | 435 | * function) but should upon the next. |
1da177e4 LT |
436 | * |
437 | * TBD: A better policy might be to fallback to the demotion | |
438 | * state (use it for this quantum only) istead of | |
439 | * demoting -- and rely on duration as our sole demotion | |
440 | * qualification. This may, however, introduce DMA | |
441 | * issues (e.g. floppy DMA transfer overrun/underrun). | |
442 | */ | |
c4a001b1 DB |
443 | if ((pr->power.bm_activity & 0x1) && |
444 | cx->demotion.threshold.bm) { | |
1da177e4 LT |
445 | local_irq_enable(); |
446 | next_state = cx->demotion.state; | |
447 | goto end; | |
448 | } | |
449 | } | |
450 | ||
4c033552 VP |
451 | #ifdef CONFIG_HOTPLUG_CPU |
452 | /* | |
453 | * Check for P_LVL2_UP flag before entering C2 and above on | |
454 | * an SMP system. We do it here instead of doing it at _CST/P_LVL | |
455 | * detection phase, to work cleanly with logical CPU hotplug. | |
456 | */ | |
4f86d3a8 | 457 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && |
cee324b1 | 458 | !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
1e483969 | 459 | cx = &pr->power.states[ACPI_STATE_C1]; |
4c033552 | 460 | #endif |
1e483969 | 461 | |
1da177e4 LT |
462 | /* |
463 | * Sleep: | |
464 | * ------ | |
465 | * Invoke the current Cx state to put the processor to sleep. | |
466 | */ | |
2a298a35 | 467 | if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) { |
495ab9c0 | 468 | current_thread_info()->status &= ~TS_POLLING; |
0888f06a IM |
469 | /* |
470 | * TS_POLLING-cleared state must be visible before we | |
471 | * test NEED_RESCHED: | |
472 | */ | |
473 | smp_mb(); | |
2a298a35 | 474 | if (need_resched()) { |
495ab9c0 | 475 | current_thread_info()->status |= TS_POLLING; |
af2eb17b | 476 | local_irq_enable(); |
2a298a35 NP |
477 | return; |
478 | } | |
479 | } | |
480 | ||
1da177e4 LT |
481 | switch (cx->type) { |
482 | ||
483 | case ACPI_STATE_C1: | |
484 | /* | |
485 | * Invoke C1. | |
486 | * Use the appropriate idle routine, the one that would | |
487 | * be used without acpi C-states. | |
488 | */ | |
489 | if (pm_idle_save) | |
490 | pm_idle_save(); | |
491 | else | |
64c7c8f8 NP |
492 | acpi_safe_halt(); |
493 | ||
1da177e4 | 494 | /* |
4be44fcd | 495 | * TBD: Can't get time duration while in C1, as resumes |
1da177e4 LT |
496 | * go to an ISR rather than here. Need to instrument |
497 | * base interrupt handler. | |
2aa44d05 IM |
498 | * |
499 | * Note: the TSC better not stop in C1, sched_clock() will | |
500 | * skew otherwise. | |
1da177e4 LT |
501 | */ |
502 | sleep_ticks = 0xFFFFFFFF; | |
503 | break; | |
504 | ||
505 | case ACPI_STATE_C2: | |
506 | /* Get start time (ticks) */ | |
cee324b1 | 507 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
2aa44d05 IM |
508 | /* Tell the scheduler that we are going deep-idle: */ |
509 | sched_clock_idle_sleep_event(); | |
1da177e4 | 510 | /* Invoke C2 */ |
e9e2cdb4 | 511 | acpi_state_timer_broadcast(pr, cx, 1); |
991528d7 | 512 | acpi_cstate_enter(cx); |
1da177e4 | 513 | /* Get end time (ticks) */ |
cee324b1 | 514 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
539eb11e | 515 | |
0aa366f3 | 516 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) |
539eb11e | 517 | /* TSC halts in C2, so notify users */ |
5a90cf20 | 518 | mark_tsc_unstable("possible TSC halt in C2"); |
539eb11e | 519 | #endif |
2aa44d05 IM |
520 | /* Compute time (ticks) that we were actually asleep */ |
521 | sleep_ticks = ticks_elapsed(t1, t2); | |
522 | ||
523 | /* Tell the scheduler how much we idled: */ | |
524 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
525 | ||
1da177e4 LT |
526 | /* Re-enable interrupts */ |
527 | local_irq_enable(); | |
2aa44d05 IM |
528 | /* Do not account our idle-switching overhead: */ |
529 | sleep_ticks -= cx->latency_ticks + C2_OVERHEAD; | |
530 | ||
495ab9c0 | 531 | current_thread_info()->status |= TS_POLLING; |
e9e2cdb4 | 532 | acpi_state_timer_broadcast(pr, cx, 0); |
1da177e4 LT |
533 | break; |
534 | ||
535 | case ACPI_STATE_C3: | |
18eab855 VP |
536 | /* |
537 | * disable bus master | |
538 | * bm_check implies we need ARB_DIS | |
539 | * !bm_check implies we need cache flush | |
540 | * bm_control implies whether we can do ARB_DIS | |
541 | * | |
542 | * That leaves a case where bm_check is set and bm_control is | |
543 | * not set. In that case we cannot do much, we enter C3 | |
544 | * without doing anything. | |
545 | */ | |
546 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
02df8b93 | 547 | if (atomic_inc_return(&c3_cpu_count) == |
4be44fcd | 548 | num_online_cpus()) { |
02df8b93 VP |
549 | /* |
550 | * All CPUs are trying to go to C3 | |
551 | * Disable bus master arbitration | |
552 | */ | |
d8c71b6d | 553 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); |
02df8b93 | 554 | } |
18eab855 | 555 | } else if (!pr->flags.bm_check) { |
02df8b93 VP |
556 | /* SMP with no shared cache... Invalidate cache */ |
557 | ACPI_FLUSH_CPU_CACHE(); | |
558 | } | |
4be44fcd | 559 | |
1da177e4 | 560 | /* Get start time (ticks) */ |
cee324b1 | 561 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
1da177e4 | 562 | /* Invoke C3 */ |
e9e2cdb4 | 563 | acpi_state_timer_broadcast(pr, cx, 1); |
2aa44d05 IM |
564 | /* Tell the scheduler that we are going deep-idle: */ |
565 | sched_clock_idle_sleep_event(); | |
991528d7 | 566 | acpi_cstate_enter(cx); |
1da177e4 | 567 | /* Get end time (ticks) */ |
cee324b1 | 568 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
18eab855 | 569 | if (pr->flags.bm_check && pr->flags.bm_control) { |
02df8b93 VP |
570 | /* Enable bus master arbitration */ |
571 | atomic_dec(&c3_cpu_count); | |
d8c71b6d | 572 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); |
02df8b93 VP |
573 | } |
574 | ||
0aa366f3 | 575 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) |
539eb11e | 576 | /* TSC halts in C3, so notify users */ |
5a90cf20 | 577 | mark_tsc_unstable("TSC halts in C3"); |
539eb11e | 578 | #endif |
2aa44d05 IM |
579 | /* Compute time (ticks) that we were actually asleep */ |
580 | sleep_ticks = ticks_elapsed(t1, t2); | |
581 | /* Tell the scheduler how much we idled: */ | |
582 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
583 | ||
1da177e4 LT |
584 | /* Re-enable interrupts */ |
585 | local_irq_enable(); | |
2aa44d05 IM |
586 | /* Do not account our idle-switching overhead: */ |
587 | sleep_ticks -= cx->latency_ticks + C3_OVERHEAD; | |
588 | ||
495ab9c0 | 589 | current_thread_info()->status |= TS_POLLING; |
e9e2cdb4 | 590 | acpi_state_timer_broadcast(pr, cx, 0); |
1da177e4 LT |
591 | break; |
592 | ||
593 | default: | |
594 | local_irq_enable(); | |
595 | return; | |
596 | } | |
a3c6598f DB |
597 | cx->usage++; |
598 | if ((cx->type != ACPI_STATE_C1) && (sleep_ticks > 0)) | |
599 | cx->time += sleep_ticks; | |
1da177e4 LT |
600 | |
601 | next_state = pr->power.state; | |
602 | ||
1e483969 DSL |
603 | #ifdef CONFIG_HOTPLUG_CPU |
604 | /* Don't do promotion/demotion */ | |
605 | if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
cee324b1 | 606 | !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) { |
1e483969 DSL |
607 | next_state = cx; |
608 | goto end; | |
609 | } | |
610 | #endif | |
611 | ||
1da177e4 LT |
612 | /* |
613 | * Promotion? | |
614 | * ---------- | |
615 | * Track the number of longs (time asleep is greater than threshold) | |
616 | * and promote when the count threshold is reached. Note that bus | |
617 | * mastering activity may prevent promotions. | |
618 | * Do not promote above max_cstate. | |
619 | */ | |
620 | if (cx->promotion.state && | |
621 | ((cx->promotion.state - pr->power.states) <= max_cstate)) { | |
5c87579e AV |
622 | if (sleep_ticks > cx->promotion.threshold.ticks && |
623 | cx->promotion.state->latency <= system_latency_constraint()) { | |
1da177e4 | 624 | cx->promotion.count++; |
4be44fcd LB |
625 | cx->demotion.count = 0; |
626 | if (cx->promotion.count >= | |
627 | cx->promotion.threshold.count) { | |
1da177e4 | 628 | if (pr->flags.bm_check) { |
4be44fcd LB |
629 | if (! |
630 | (pr->power.bm_activity & cx-> | |
631 | promotion.threshold.bm)) { | |
632 | next_state = | |
633 | cx->promotion.state; | |
1da177e4 LT |
634 | goto end; |
635 | } | |
4be44fcd | 636 | } else { |
1da177e4 LT |
637 | next_state = cx->promotion.state; |
638 | goto end; | |
639 | } | |
640 | } | |
641 | } | |
642 | } | |
643 | ||
644 | /* | |
645 | * Demotion? | |
646 | * --------- | |
647 | * Track the number of shorts (time asleep is less than time threshold) | |
648 | * and demote when the usage threshold is reached. | |
649 | */ | |
650 | if (cx->demotion.state) { | |
651 | if (sleep_ticks < cx->demotion.threshold.ticks) { | |
652 | cx->demotion.count++; | |
653 | cx->promotion.count = 0; | |
654 | if (cx->demotion.count >= cx->demotion.threshold.count) { | |
655 | next_state = cx->demotion.state; | |
656 | goto end; | |
657 | } | |
658 | } | |
659 | } | |
660 | ||
4be44fcd | 661 | end: |
1da177e4 LT |
662 | /* |
663 | * Demote if current state exceeds max_cstate | |
5c87579e | 664 | * or if the latency of the current state is unacceptable |
1da177e4 | 665 | */ |
5c87579e AV |
666 | if ((pr->power.state - pr->power.states) > max_cstate || |
667 | pr->power.state->latency > system_latency_constraint()) { | |
1da177e4 LT |
668 | if (cx->demotion.state) |
669 | next_state = cx->demotion.state; | |
670 | } | |
671 | ||
672 | /* | |
673 | * New Cx State? | |
674 | * ------------- | |
675 | * If we're going to start using a new Cx state we must clean up | |
676 | * from the previous and prepare to use the new. | |
677 | */ | |
678 | if (next_state != pr->power.state) | |
679 | acpi_processor_power_activate(pr, next_state); | |
1da177e4 LT |
680 | } |
681 | ||
4be44fcd | 682 | static int acpi_processor_set_power_policy(struct acpi_processor *pr) |
1da177e4 LT |
683 | { |
684 | unsigned int i; | |
685 | unsigned int state_is_set = 0; | |
686 | struct acpi_processor_cx *lower = NULL; | |
687 | struct acpi_processor_cx *higher = NULL; | |
688 | struct acpi_processor_cx *cx; | |
689 | ||
1da177e4 LT |
690 | |
691 | if (!pr) | |
d550d98d | 692 | return -EINVAL; |
1da177e4 LT |
693 | |
694 | /* | |
695 | * This function sets the default Cx state policy (OS idle handler). | |
696 | * Our scheme is to promote quickly to C2 but more conservatively | |
697 | * to C3. We're favoring C2 for its characteristics of low latency | |
698 | * (quick response), good power savings, and ability to allow bus | |
699 | * mastering activity. Note that the Cx state policy is completely | |
700 | * customizable and can be altered dynamically. | |
701 | */ | |
702 | ||
703 | /* startup state */ | |
4be44fcd | 704 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
705 | cx = &pr->power.states[i]; |
706 | if (!cx->valid) | |
707 | continue; | |
708 | ||
709 | if (!state_is_set) | |
710 | pr->power.state = cx; | |
711 | state_is_set++; | |
712 | break; | |
4be44fcd | 713 | } |
1da177e4 LT |
714 | |
715 | if (!state_is_set) | |
d550d98d | 716 | return -ENODEV; |
1da177e4 LT |
717 | |
718 | /* demotion */ | |
4be44fcd | 719 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
720 | cx = &pr->power.states[i]; |
721 | if (!cx->valid) | |
722 | continue; | |
723 | ||
724 | if (lower) { | |
725 | cx->demotion.state = lower; | |
726 | cx->demotion.threshold.ticks = cx->latency_ticks; | |
727 | cx->demotion.threshold.count = 1; | |
728 | if (cx->type == ACPI_STATE_C3) | |
729 | cx->demotion.threshold.bm = bm_history; | |
730 | } | |
731 | ||
732 | lower = cx; | |
733 | } | |
734 | ||
735 | /* promotion */ | |
736 | for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) { | |
737 | cx = &pr->power.states[i]; | |
738 | if (!cx->valid) | |
739 | continue; | |
740 | ||
741 | if (higher) { | |
4be44fcd | 742 | cx->promotion.state = higher; |
1da177e4 LT |
743 | cx->promotion.threshold.ticks = cx->latency_ticks; |
744 | if (cx->type >= ACPI_STATE_C2) | |
745 | cx->promotion.threshold.count = 4; | |
746 | else | |
747 | cx->promotion.threshold.count = 10; | |
748 | if (higher->type == ACPI_STATE_C3) | |
749 | cx->promotion.threshold.bm = bm_history; | |
750 | } | |
751 | ||
752 | higher = cx; | |
753 | } | |
754 | ||
d550d98d | 755 | return 0; |
1da177e4 | 756 | } |
4f86d3a8 | 757 | #endif /* !CONFIG_CPU_IDLE */ |
1da177e4 | 758 | |
4be44fcd | 759 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 760 | { |
1da177e4 LT |
761 | |
762 | if (!pr) | |
d550d98d | 763 | return -EINVAL; |
1da177e4 LT |
764 | |
765 | if (!pr->pblk) | |
d550d98d | 766 | return -ENODEV; |
1da177e4 | 767 | |
1da177e4 | 768 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
769 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
770 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
771 | ||
4c033552 VP |
772 | #ifndef CONFIG_HOTPLUG_CPU |
773 | /* | |
774 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 775 | * an SMP system. |
4c033552 | 776 | */ |
ad71860a | 777 | if ((num_online_cpus() > 1) && |
cee324b1 | 778 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 779 | return -ENODEV; |
4c033552 VP |
780 | #endif |
781 | ||
1da177e4 LT |
782 | /* determine C2 and C3 address from pblk */ |
783 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
784 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
785 | ||
786 | /* determine latencies from FADT */ | |
cee324b1 AS |
787 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; |
788 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; | |
1da177e4 LT |
789 | |
790 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
791 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
792 | pr->power.states[ACPI_STATE_C2].address, | |
793 | pr->power.states[ACPI_STATE_C3].address)); | |
794 | ||
d550d98d | 795 | return 0; |
1da177e4 LT |
796 | } |
797 | ||
991528d7 | 798 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 799 | { |
991528d7 VP |
800 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
801 | /* set the first C-State to C1 */ | |
802 | /* all processors need to support C1 */ | |
803 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
804 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
805 | } | |
806 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 807 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 808 | return 0; |
acf05f4b VP |
809 | } |
810 | ||
4be44fcd | 811 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 812 | { |
4be44fcd LB |
813 | acpi_status status = 0; |
814 | acpi_integer count; | |
cf824788 | 815 | int current_count; |
4be44fcd LB |
816 | int i; |
817 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
818 | union acpi_object *cst; | |
1da177e4 | 819 | |
1da177e4 | 820 | |
1da177e4 | 821 | if (nocst) |
d550d98d | 822 | return -ENODEV; |
1da177e4 | 823 | |
991528d7 | 824 | current_count = 0; |
1da177e4 LT |
825 | |
826 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
827 | if (ACPI_FAILURE(status)) { | |
828 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 829 | return -ENODEV; |
4be44fcd | 830 | } |
1da177e4 | 831 | |
50dd0969 | 832 | cst = buffer.pointer; |
1da177e4 LT |
833 | |
834 | /* There must be at least 2 elements */ | |
835 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 836 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
837 | status = -EFAULT; |
838 | goto end; | |
839 | } | |
840 | ||
841 | count = cst->package.elements[0].integer.value; | |
842 | ||
843 | /* Validate number of power states. */ | |
844 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 845 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
846 | status = -EFAULT; |
847 | goto end; | |
848 | } | |
849 | ||
1da177e4 LT |
850 | /* Tell driver that at least _CST is supported. */ |
851 | pr->flags.has_cst = 1; | |
852 | ||
853 | for (i = 1; i <= count; i++) { | |
854 | union acpi_object *element; | |
855 | union acpi_object *obj; | |
856 | struct acpi_power_register *reg; | |
857 | struct acpi_processor_cx cx; | |
858 | ||
859 | memset(&cx, 0, sizeof(cx)); | |
860 | ||
50dd0969 | 861 | element = &(cst->package.elements[i]); |
1da177e4 LT |
862 | if (element->type != ACPI_TYPE_PACKAGE) |
863 | continue; | |
864 | ||
865 | if (element->package.count != 4) | |
866 | continue; | |
867 | ||
50dd0969 | 868 | obj = &(element->package.elements[0]); |
1da177e4 LT |
869 | |
870 | if (obj->type != ACPI_TYPE_BUFFER) | |
871 | continue; | |
872 | ||
4be44fcd | 873 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
874 | |
875 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 876 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
877 | continue; |
878 | ||
1da177e4 | 879 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 880 | obj = &(element->package.elements[1]); |
1da177e4 LT |
881 | if (obj->type != ACPI_TYPE_INTEGER) |
882 | continue; | |
883 | ||
884 | cx.type = obj->integer.value; | |
991528d7 VP |
885 | /* |
886 | * Some buggy BIOSes won't list C1 in _CST - | |
887 | * Let acpi_processor_get_power_info_default() handle them later | |
888 | */ | |
889 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
890 | current_count++; | |
891 | ||
892 | cx.address = reg->address; | |
893 | cx.index = current_count + 1; | |
894 | ||
895 | cx.space_id = ACPI_CSTATE_SYSTEMIO; | |
896 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { | |
897 | if (acpi_processor_ffh_cstate_probe | |
898 | (pr->id, &cx, reg) == 0) { | |
899 | cx.space_id = ACPI_CSTATE_FFH; | |
900 | } else if (cx.type != ACPI_STATE_C1) { | |
901 | /* | |
902 | * C1 is a special case where FIXED_HARDWARE | |
903 | * can be handled in non-MWAIT way as well. | |
904 | * In that case, save this _CST entry info. | |
905 | * That is, we retain space_id of SYSTEM_IO for | |
906 | * halt based C1. | |
907 | * Otherwise, ignore this info and continue. | |
908 | */ | |
909 | continue; | |
910 | } | |
911 | } | |
1da177e4 | 912 | |
50dd0969 | 913 | obj = &(element->package.elements[2]); |
1da177e4 LT |
914 | if (obj->type != ACPI_TYPE_INTEGER) |
915 | continue; | |
916 | ||
917 | cx.latency = obj->integer.value; | |
918 | ||
50dd0969 | 919 | obj = &(element->package.elements[3]); |
1da177e4 LT |
920 | if (obj->type != ACPI_TYPE_INTEGER) |
921 | continue; | |
922 | ||
923 | cx.power = obj->integer.value; | |
924 | ||
cf824788 JM |
925 | current_count++; |
926 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
927 | ||
928 | /* | |
929 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
930 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
931 | */ | |
932 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
933 | printk(KERN_WARNING | |
934 | "Limiting number of power states to max (%d)\n", | |
935 | ACPI_PROCESSOR_MAX_POWER); | |
936 | printk(KERN_WARNING | |
937 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
938 | break; | |
939 | } | |
1da177e4 LT |
940 | } |
941 | ||
4be44fcd | 942 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 943 | current_count)); |
1da177e4 LT |
944 | |
945 | /* Validate number of power states discovered */ | |
cf824788 | 946 | if (current_count < 2) |
6d93c648 | 947 | status = -EFAULT; |
1da177e4 | 948 | |
4be44fcd | 949 | end: |
02438d87 | 950 | kfree(buffer.pointer); |
1da177e4 | 951 | |
d550d98d | 952 | return status; |
1da177e4 LT |
953 | } |
954 | ||
1da177e4 LT |
955 | static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx) |
956 | { | |
1da177e4 LT |
957 | |
958 | if (!cx->address) | |
d550d98d | 959 | return; |
1da177e4 LT |
960 | |
961 | /* | |
962 | * C2 latency must be less than or equal to 100 | |
963 | * microseconds. | |
964 | */ | |
965 | else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { | |
966 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 967 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 968 | return; |
1da177e4 LT |
969 | } |
970 | ||
1da177e4 LT |
971 | /* |
972 | * Otherwise we've met all of our C2 requirements. | |
973 | * Normalize the C2 latency to expidite policy | |
974 | */ | |
975 | cx->valid = 1; | |
4f86d3a8 LB |
976 | |
977 | #ifndef CONFIG_CPU_IDLE | |
1da177e4 | 978 | cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); |
4f86d3a8 LB |
979 | #else |
980 | cx->latency_ticks = cx->latency; | |
981 | #endif | |
1da177e4 | 982 | |
d550d98d | 983 | return; |
1da177e4 LT |
984 | } |
985 | ||
4be44fcd LB |
986 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
987 | struct acpi_processor_cx *cx) | |
1da177e4 | 988 | { |
02df8b93 VP |
989 | static int bm_check_flag; |
990 | ||
1da177e4 LT |
991 | |
992 | if (!cx->address) | |
d550d98d | 993 | return; |
1da177e4 LT |
994 | |
995 | /* | |
996 | * C3 latency must be less than or equal to 1000 | |
997 | * microseconds. | |
998 | */ | |
999 | else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { | |
1000 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 1001 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 1002 | return; |
1da177e4 LT |
1003 | } |
1004 | ||
1da177e4 LT |
1005 | /* |
1006 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
1007 | * DMA transfers are used by any ISA device to avoid livelock. | |
1008 | * Note that we could disable Type-F DMA (as recommended by | |
1009 | * the erratum), but this is known to disrupt certain ISA | |
1010 | * devices thus we take the conservative approach. | |
1011 | */ | |
1012 | else if (errata.piix4.fdma) { | |
1013 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 1014 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 1015 | return; |
1da177e4 LT |
1016 | } |
1017 | ||
02df8b93 VP |
1018 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
1019 | if (!bm_check_flag) { | |
1020 | /* Determine whether bm_check is needed based on CPU */ | |
1021 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
1022 | bm_check_flag = pr->flags.bm_check; | |
1023 | } else { | |
1024 | pr->flags.bm_check = bm_check_flag; | |
1025 | } | |
1026 | ||
1027 | if (pr->flags.bm_check) { | |
02df8b93 | 1028 | if (!pr->flags.bm_control) { |
ed3110ef VP |
1029 | if (pr->flags.has_cst != 1) { |
1030 | /* bus mastering control is necessary */ | |
1031 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
1032 | "C3 support requires BM control\n")); | |
1033 | return; | |
1034 | } else { | |
1035 | /* Here we enter C3 without bus mastering */ | |
1036 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
1037 | "C3 support without BM control\n")); | |
1038 | } | |
02df8b93 VP |
1039 | } |
1040 | } else { | |
02df8b93 VP |
1041 | /* |
1042 | * WBINVD should be set in fadt, for C3 state to be | |
1043 | * supported on when bm_check is not required. | |
1044 | */ | |
cee324b1 | 1045 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 1046 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
1047 | "Cache invalidation should work properly" |
1048 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 1049 | return; |
02df8b93 | 1050 | } |
d8c71b6d | 1051 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); |
02df8b93 VP |
1052 | } |
1053 | ||
1da177e4 LT |
1054 | /* |
1055 | * Otherwise we've met all of our C3 requirements. | |
1056 | * Normalize the C3 latency to expidite policy. Enable | |
1057 | * checking of bus mastering status (bm_check) so we can | |
1058 | * use this in our C3 policy | |
1059 | */ | |
1060 | cx->valid = 1; | |
4f86d3a8 LB |
1061 | |
1062 | #ifndef CONFIG_CPU_IDLE | |
1da177e4 | 1063 | cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); |
4f86d3a8 LB |
1064 | #else |
1065 | cx->latency_ticks = cx->latency; | |
1066 | #endif | |
1da177e4 | 1067 | |
d550d98d | 1068 | return; |
1da177e4 LT |
1069 | } |
1070 | ||
1da177e4 LT |
1071 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
1072 | { | |
1073 | unsigned int i; | |
1074 | unsigned int working = 0; | |
6eb0a0fd | 1075 | |
169a0abb | 1076 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 1077 | |
4be44fcd | 1078 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
1079 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
1080 | ||
1081 | switch (cx->type) { | |
1082 | case ACPI_STATE_C1: | |
1083 | cx->valid = 1; | |
1084 | break; | |
1085 | ||
1086 | case ACPI_STATE_C2: | |
1087 | acpi_processor_power_verify_c2(cx); | |
296d93cd | 1088 | if (cx->valid) |
169a0abb | 1089 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
1090 | break; |
1091 | ||
1092 | case ACPI_STATE_C3: | |
1093 | acpi_processor_power_verify_c3(pr, cx); | |
296d93cd | 1094 | if (cx->valid) |
169a0abb | 1095 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
1096 | break; |
1097 | } | |
1098 | ||
1099 | if (cx->valid) | |
1100 | working++; | |
1101 | } | |
bd663347 | 1102 | |
169a0abb | 1103 | acpi_propagate_timer_broadcast(pr); |
1da177e4 LT |
1104 | |
1105 | return (working); | |
1106 | } | |
1107 | ||
4be44fcd | 1108 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
1109 | { |
1110 | unsigned int i; | |
1111 | int result; | |
1112 | ||
1da177e4 LT |
1113 | |
1114 | /* NOTE: the idle thread may not be running while calling | |
1115 | * this function */ | |
1116 | ||
991528d7 VP |
1117 | /* Zero initialize all the C-states info. */ |
1118 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
1119 | ||
1da177e4 | 1120 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 1121 | if (result == -ENODEV) |
c5a114f1 | 1122 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 1123 | |
991528d7 VP |
1124 | if (result) |
1125 | return result; | |
1126 | ||
1127 | acpi_processor_get_power_info_default(pr); | |
1128 | ||
cf824788 | 1129 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 1130 | |
4f86d3a8 | 1131 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
1132 | /* |
1133 | * Set Default Policy | |
1134 | * ------------------ | |
1135 | * Now that we know which states are supported, set the default | |
1136 | * policy. Note that this policy can be changed dynamically | |
1137 | * (e.g. encourage deeper sleeps to conserve battery life when | |
1138 | * not on AC). | |
1139 | */ | |
1140 | result = acpi_processor_set_power_policy(pr); | |
1141 | if (result) | |
d550d98d | 1142 | return result; |
4f86d3a8 | 1143 | #endif |
1da177e4 LT |
1144 | |
1145 | /* | |
1146 | * if one state of type C2 or C3 is available, mark this | |
1147 | * CPU as being "idle manageable" | |
1148 | */ | |
1149 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 1150 | if (pr->power.states[i].valid) { |
1da177e4 | 1151 | pr->power.count = i; |
2203d6ed LT |
1152 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
1153 | pr->flags.power = 1; | |
acf05f4b | 1154 | } |
1da177e4 LT |
1155 | } |
1156 | ||
d550d98d | 1157 | return 0; |
1da177e4 LT |
1158 | } |
1159 | ||
1da177e4 LT |
1160 | static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) |
1161 | { | |
50dd0969 | 1162 | struct acpi_processor *pr = seq->private; |
4be44fcd | 1163 | unsigned int i; |
1da177e4 | 1164 | |
1da177e4 LT |
1165 | |
1166 | if (!pr) | |
1167 | goto end; | |
1168 | ||
1169 | seq_printf(seq, "active state: C%zd\n" | |
4be44fcd | 1170 | "max_cstate: C%d\n" |
5c87579e AV |
1171 | "bus master activity: %08x\n" |
1172 | "maximum allowed latency: %d usec\n", | |
4be44fcd | 1173 | pr->power.state ? pr->power.state - pr->power.states : 0, |
5c87579e AV |
1174 | max_cstate, (unsigned)pr->power.bm_activity, |
1175 | system_latency_constraint()); | |
1da177e4 LT |
1176 | |
1177 | seq_puts(seq, "states:\n"); | |
1178 | ||
1179 | for (i = 1; i <= pr->power.count; i++) { | |
1180 | seq_printf(seq, " %cC%d: ", | |
4be44fcd LB |
1181 | (&pr->power.states[i] == |
1182 | pr->power.state ? '*' : ' '), i); | |
1da177e4 LT |
1183 | |
1184 | if (!pr->power.states[i].valid) { | |
1185 | seq_puts(seq, "<not supported>\n"); | |
1186 | continue; | |
1187 | } | |
1188 | ||
1189 | switch (pr->power.states[i].type) { | |
1190 | case ACPI_STATE_C1: | |
1191 | seq_printf(seq, "type[C1] "); | |
1192 | break; | |
1193 | case ACPI_STATE_C2: | |
1194 | seq_printf(seq, "type[C2] "); | |
1195 | break; | |
1196 | case ACPI_STATE_C3: | |
1197 | seq_printf(seq, "type[C3] "); | |
1198 | break; | |
1199 | default: | |
1200 | seq_printf(seq, "type[--] "); | |
1201 | break; | |
1202 | } | |
1203 | ||
1204 | if (pr->power.states[i].promotion.state) | |
1205 | seq_printf(seq, "promotion[C%zd] ", | |
4be44fcd LB |
1206 | (pr->power.states[i].promotion.state - |
1207 | pr->power.states)); | |
1da177e4 LT |
1208 | else |
1209 | seq_puts(seq, "promotion[--] "); | |
1210 | ||
1211 | if (pr->power.states[i].demotion.state) | |
1212 | seq_printf(seq, "demotion[C%zd] ", | |
4be44fcd LB |
1213 | (pr->power.states[i].demotion.state - |
1214 | pr->power.states)); | |
1da177e4 LT |
1215 | else |
1216 | seq_puts(seq, "demotion[--] "); | |
1217 | ||
a3c6598f | 1218 | seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", |
4be44fcd | 1219 | pr->power.states[i].latency, |
a3c6598f | 1220 | pr->power.states[i].usage, |
b0b7eaaf | 1221 | (unsigned long long)pr->power.states[i].time); |
1da177e4 LT |
1222 | } |
1223 | ||
4be44fcd | 1224 | end: |
d550d98d | 1225 | return 0; |
1da177e4 LT |
1226 | } |
1227 | ||
1228 | static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) | |
1229 | { | |
1230 | return single_open(file, acpi_processor_power_seq_show, | |
4be44fcd | 1231 | PDE(inode)->data); |
1da177e4 LT |
1232 | } |
1233 | ||
d7508032 | 1234 | static const struct file_operations acpi_processor_power_fops = { |
4be44fcd LB |
1235 | .open = acpi_processor_power_open_fs, |
1236 | .read = seq_read, | |
1237 | .llseek = seq_lseek, | |
1238 | .release = single_release, | |
1da177e4 LT |
1239 | }; |
1240 | ||
4f86d3a8 LB |
1241 | #ifndef CONFIG_CPU_IDLE |
1242 | ||
1243 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1244 | { | |
1245 | int result = 0; | |
1246 | ||
1247 | ||
1248 | if (!pr) | |
1249 | return -EINVAL; | |
1250 | ||
1251 | if (nocst) { | |
1252 | return -ENODEV; | |
1253 | } | |
1254 | ||
1255 | if (!pr->flags.power_setup_done) | |
1256 | return -ENODEV; | |
1257 | ||
1258 | /* Fall back to the default idle loop */ | |
1259 | pm_idle = pm_idle_save; | |
1260 | synchronize_sched(); /* Relies on interrupts forcing exit from idle. */ | |
1261 | ||
1262 | pr->flags.power = 0; | |
1263 | result = acpi_processor_get_power_info(pr); | |
1264 | if ((pr->flags.power == 1) && (pr->flags.power_setup_done)) | |
1265 | pm_idle = acpi_processor_idle; | |
1266 | ||
1267 | return result; | |
1268 | } | |
1269 | ||
1fec74a9 | 1270 | #ifdef CONFIG_SMP |
5c87579e AV |
1271 | static void smp_callback(void *v) |
1272 | { | |
1273 | /* we already woke the CPU up, nothing more to do */ | |
1274 | } | |
1275 | ||
1276 | /* | |
1277 | * This function gets called when a part of the kernel has a new latency | |
1278 | * requirement. This means we need to get all processors out of their C-state, | |
1279 | * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that | |
1280 | * wakes them all right up. | |
1281 | */ | |
1282 | static int acpi_processor_latency_notify(struct notifier_block *b, | |
1283 | unsigned long l, void *v) | |
1284 | { | |
1285 | smp_call_function(smp_callback, NULL, 0, 1); | |
1286 | return NOTIFY_OK; | |
1287 | } | |
1288 | ||
1289 | static struct notifier_block acpi_processor_latency_notifier = { | |
1290 | .notifier_call = acpi_processor_latency_notify, | |
1291 | }; | |
4f86d3a8 LB |
1292 | |
1293 | #endif | |
1294 | ||
1295 | #else /* CONFIG_CPU_IDLE */ | |
1296 | ||
1297 | /** | |
1298 | * acpi_idle_bm_check - checks if bus master activity was detected | |
1299 | */ | |
1300 | static int acpi_idle_bm_check(void) | |
1301 | { | |
1302 | u32 bm_status = 0; | |
1303 | ||
1304 | acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); | |
1305 | if (bm_status) | |
1306 | acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); | |
1307 | /* | |
1308 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
1309 | * the true state of bus mastering activity; forcing us to | |
1310 | * manually check the BMIDEA bit of each IDE channel. | |
1311 | */ | |
1312 | else if (errata.piix4.bmisx) { | |
1313 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
1314 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
1315 | bm_status = 1; | |
1316 | } | |
1317 | return bm_status; | |
1318 | } | |
1319 | ||
1320 | /** | |
1321 | * acpi_idle_update_bm_rld - updates the BM_RLD bit depending on target state | |
1322 | * @pr: the processor | |
1323 | * @target: the new target state | |
1324 | */ | |
1325 | static inline void acpi_idle_update_bm_rld(struct acpi_processor *pr, | |
1326 | struct acpi_processor_cx *target) | |
1327 | { | |
1328 | if (pr->flags.bm_rld_set && target->type != ACPI_STATE_C3) { | |
1329 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); | |
1330 | pr->flags.bm_rld_set = 0; | |
1331 | } | |
1332 | ||
1333 | if (!pr->flags.bm_rld_set && target->type == ACPI_STATE_C3) { | |
1334 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); | |
1335 | pr->flags.bm_rld_set = 1; | |
1336 | } | |
1337 | } | |
1338 | ||
1339 | /** | |
1340 | * acpi_idle_do_entry - a helper function that does C2 and C3 type entry | |
1341 | * @cx: cstate data | |
1342 | */ | |
1343 | static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) | |
1344 | { | |
1345 | if (cx->space_id == ACPI_CSTATE_FFH) { | |
1346 | /* Call into architectural FFH based C-state */ | |
1347 | acpi_processor_ffh_cstate_enter(cx); | |
1348 | } else { | |
1349 | int unused; | |
1350 | /* IO port based C-state */ | |
1351 | inb(cx->address); | |
1352 | /* Dummy wait op - must do something useless after P_LVL2 read | |
1353 | because chipsets cannot guarantee that STPCLK# signal | |
1354 | gets asserted in time to freeze execution properly. */ | |
1355 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
1356 | } | |
1357 | } | |
1358 | ||
1359 | /** | |
1360 | * acpi_idle_enter_c1 - enters an ACPI C1 state-type | |
1361 | * @dev: the target CPU | |
1362 | * @state: the state data | |
1363 | * | |
1364 | * This is equivalent to the HALT instruction. | |
1365 | */ | |
1366 | static int acpi_idle_enter_c1(struct cpuidle_device *dev, | |
1367 | struct cpuidle_state *state) | |
1368 | { | |
1369 | struct acpi_processor *pr; | |
1370 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
1371 | pr = processors[smp_processor_id()]; | |
1372 | ||
1373 | if (unlikely(!pr)) | |
1374 | return 0; | |
1375 | ||
1376 | if (pr->flags.bm_check) | |
1377 | acpi_idle_update_bm_rld(pr, cx); | |
1378 | ||
1379 | current_thread_info()->status &= ~TS_POLLING; | |
1380 | /* | |
1381 | * TS_POLLING-cleared state must be visible before we test | |
1382 | * NEED_RESCHED: | |
1383 | */ | |
1384 | smp_mb(); | |
1385 | if (!need_resched()) | |
1386 | safe_halt(); | |
1387 | current_thread_info()->status |= TS_POLLING; | |
1388 | ||
1389 | cx->usage++; | |
1390 | ||
1391 | return 0; | |
1392 | } | |
1393 | ||
1394 | /** | |
1395 | * acpi_idle_enter_simple - enters an ACPI state without BM handling | |
1396 | * @dev: the target CPU | |
1397 | * @state: the state data | |
1398 | */ | |
1399 | static int acpi_idle_enter_simple(struct cpuidle_device *dev, | |
1400 | struct cpuidle_state *state) | |
1401 | { | |
1402 | struct acpi_processor *pr; | |
1403 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
1404 | u32 t1, t2; | |
1405 | pr = processors[smp_processor_id()]; | |
1406 | ||
1407 | if (unlikely(!pr)) | |
1408 | return 0; | |
1409 | ||
e196441b LB |
1410 | if (acpi_idle_suspend) |
1411 | return(acpi_idle_enter_c1(dev, state)); | |
1412 | ||
4f86d3a8 LB |
1413 | if (pr->flags.bm_check) |
1414 | acpi_idle_update_bm_rld(pr, cx); | |
1415 | ||
1416 | local_irq_disable(); | |
1417 | current_thread_info()->status &= ~TS_POLLING; | |
1418 | /* | |
1419 | * TS_POLLING-cleared state must be visible before we test | |
1420 | * NEED_RESCHED: | |
1421 | */ | |
1422 | smp_mb(); | |
1423 | ||
1424 | if (unlikely(need_resched())) { | |
1425 | current_thread_info()->status |= TS_POLLING; | |
1426 | local_irq_enable(); | |
1427 | return 0; | |
1428 | } | |
1429 | ||
1430 | if (cx->type == ACPI_STATE_C3) | |
1431 | ACPI_FLUSH_CPU_CACHE(); | |
1432 | ||
1433 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
1434 | acpi_state_timer_broadcast(pr, cx, 1); | |
1435 | acpi_idle_do_entry(cx); | |
1436 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
1437 | ||
1438 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) | |
1439 | /* TSC could halt in idle, so notify users */ | |
1440 | mark_tsc_unstable("TSC halts in idle");; | |
1441 | #endif | |
1442 | ||
1443 | local_irq_enable(); | |
1444 | current_thread_info()->status |= TS_POLLING; | |
1445 | ||
1446 | cx->usage++; | |
1447 | ||
1448 | acpi_state_timer_broadcast(pr, cx, 0); | |
1449 | cx->time += ticks_elapsed(t1, t2); | |
1450 | return ticks_elapsed_in_us(t1, t2); | |
1451 | } | |
1452 | ||
1453 | static int c3_cpu_count; | |
1454 | static DEFINE_SPINLOCK(c3_lock); | |
1455 | ||
1456 | /** | |
1457 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
1458 | * @dev: the target CPU | |
1459 | * @state: the state data | |
1460 | * | |
1461 | * If BM is detected, the deepest non-C3 idle state is entered instead. | |
1462 | */ | |
1463 | static int acpi_idle_enter_bm(struct cpuidle_device *dev, | |
1464 | struct cpuidle_state *state) | |
1465 | { | |
1466 | struct acpi_processor *pr; | |
1467 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
1468 | u32 t1, t2; | |
1469 | pr = processors[smp_processor_id()]; | |
1470 | ||
1471 | if (unlikely(!pr)) | |
1472 | return 0; | |
1473 | ||
e196441b LB |
1474 | if (acpi_idle_suspend) |
1475 | return(acpi_idle_enter_c1(dev, state)); | |
1476 | ||
4f86d3a8 LB |
1477 | local_irq_disable(); |
1478 | current_thread_info()->status &= ~TS_POLLING; | |
1479 | /* | |
1480 | * TS_POLLING-cleared state must be visible before we test | |
1481 | * NEED_RESCHED: | |
1482 | */ | |
1483 | smp_mb(); | |
1484 | ||
1485 | if (unlikely(need_resched())) { | |
1486 | current_thread_info()->status |= TS_POLLING; | |
1487 | local_irq_enable(); | |
1488 | return 0; | |
1489 | } | |
1490 | ||
1491 | /* | |
1492 | * Must be done before busmaster disable as we might need to | |
1493 | * access HPET ! | |
1494 | */ | |
1495 | acpi_state_timer_broadcast(pr, cx, 1); | |
1496 | ||
1497 | if (acpi_idle_bm_check()) { | |
1498 | cx = pr->power.bm_state; | |
1499 | ||
1500 | acpi_idle_update_bm_rld(pr, cx); | |
1501 | ||
1502 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
1503 | acpi_idle_do_entry(cx); | |
1504 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
1505 | } else { | |
1506 | acpi_idle_update_bm_rld(pr, cx); | |
1507 | ||
1508 | spin_lock(&c3_lock); | |
1509 | c3_cpu_count++; | |
1510 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
1511 | if (c3_cpu_count == num_online_cpus()) | |
1512 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); | |
1513 | spin_unlock(&c3_lock); | |
1514 | ||
1515 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
1516 | acpi_idle_do_entry(cx); | |
1517 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
1518 | ||
1519 | spin_lock(&c3_lock); | |
1520 | /* Re-enable bus master arbitration */ | |
1521 | if (c3_cpu_count == num_online_cpus()) | |
1522 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); | |
1523 | c3_cpu_count--; | |
1524 | spin_unlock(&c3_lock); | |
1525 | } | |
1526 | ||
1527 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) | |
1528 | /* TSC could halt in idle, so notify users */ | |
1529 | mark_tsc_unstable("TSC halts in idle"); | |
1530 | #endif | |
1531 | ||
1532 | local_irq_enable(); | |
1533 | current_thread_info()->status |= TS_POLLING; | |
1534 | ||
1535 | cx->usage++; | |
1536 | ||
1537 | acpi_state_timer_broadcast(pr, cx, 0); | |
1538 | cx->time += ticks_elapsed(t1, t2); | |
1539 | return ticks_elapsed_in_us(t1, t2); | |
1540 | } | |
1541 | ||
1542 | struct cpuidle_driver acpi_idle_driver = { | |
1543 | .name = "acpi_idle", | |
1544 | .owner = THIS_MODULE, | |
1545 | }; | |
1546 | ||
1547 | /** | |
1548 | * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE | |
1549 | * @pr: the ACPI processor | |
1550 | */ | |
1551 | static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) | |
1552 | { | |
1553 | int i, count = 0; | |
1554 | struct acpi_processor_cx *cx; | |
1555 | struct cpuidle_state *state; | |
1556 | struct cpuidle_device *dev = &pr->power.dev; | |
1557 | ||
1558 | if (!pr->flags.power_setup_done) | |
1559 | return -EINVAL; | |
1560 | ||
1561 | if (pr->flags.power == 0) { | |
1562 | return -EINVAL; | |
1563 | } | |
1564 | ||
1565 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { | |
1566 | cx = &pr->power.states[i]; | |
1567 | state = &dev->states[count]; | |
1568 | ||
1569 | if (!cx->valid) | |
1570 | continue; | |
1571 | ||
1572 | #ifdef CONFIG_HOTPLUG_CPU | |
1573 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
1574 | !pr->flags.has_cst && | |
1575 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
1576 | continue; | |
1fec74a9 | 1577 | #endif |
4f86d3a8 LB |
1578 | cpuidle_set_statedata(state, cx); |
1579 | ||
1580 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); | |
1581 | state->exit_latency = cx->latency; | |
4963f620 | 1582 | state->target_residency = cx->latency * latency_factor; |
4f86d3a8 LB |
1583 | state->power_usage = cx->power; |
1584 | ||
1585 | state->flags = 0; | |
1586 | switch (cx->type) { | |
1587 | case ACPI_STATE_C1: | |
1588 | state->flags |= CPUIDLE_FLAG_SHALLOW; | |
1589 | state->enter = acpi_idle_enter_c1; | |
1590 | break; | |
1591 | ||
1592 | case ACPI_STATE_C2: | |
1593 | state->flags |= CPUIDLE_FLAG_BALANCED; | |
1594 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1595 | state->enter = acpi_idle_enter_simple; | |
1596 | break; | |
1597 | ||
1598 | case ACPI_STATE_C3: | |
1599 | state->flags |= CPUIDLE_FLAG_DEEP; | |
1600 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1601 | state->flags |= CPUIDLE_FLAG_CHECK_BM; | |
1602 | state->enter = pr->flags.bm_check ? | |
1603 | acpi_idle_enter_bm : | |
1604 | acpi_idle_enter_simple; | |
1605 | break; | |
1606 | } | |
1607 | ||
1608 | count++; | |
1609 | } | |
1610 | ||
1611 | dev->state_count = count; | |
1612 | ||
1613 | if (!count) | |
1614 | return -EINVAL; | |
1615 | ||
1616 | /* find the deepest state that can handle active BM */ | |
1617 | if (pr->flags.bm_check) { | |
1618 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) | |
1619 | if (pr->power.states[i].type == ACPI_STATE_C3) | |
1620 | break; | |
1621 | pr->power.bm_state = &pr->power.states[i-1]; | |
1622 | } | |
1623 | ||
1624 | return 0; | |
1625 | } | |
1626 | ||
1627 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1628 | { | |
1629 | int ret; | |
1630 | ||
1631 | if (!pr) | |
1632 | return -EINVAL; | |
1633 | ||
1634 | if (nocst) { | |
1635 | return -ENODEV; | |
1636 | } | |
1637 | ||
1638 | if (!pr->flags.power_setup_done) | |
1639 | return -ENODEV; | |
1640 | ||
1641 | cpuidle_pause_and_lock(); | |
1642 | cpuidle_disable_device(&pr->power.dev); | |
1643 | acpi_processor_get_power_info(pr); | |
1644 | acpi_processor_setup_cpuidle(pr); | |
1645 | ret = cpuidle_enable_device(&pr->power.dev); | |
1646 | cpuidle_resume_and_unlock(); | |
1647 | ||
1648 | return ret; | |
1649 | } | |
1650 | ||
1651 | #endif /* CONFIG_CPU_IDLE */ | |
5c87579e | 1652 | |
7af8b660 | 1653 | int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, |
4be44fcd | 1654 | struct acpi_device *device) |
1da177e4 | 1655 | { |
4be44fcd | 1656 | acpi_status status = 0; |
b6835052 | 1657 | static int first_run; |
4be44fcd | 1658 | struct proc_dir_entry *entry = NULL; |
1da177e4 LT |
1659 | unsigned int i; |
1660 | ||
1da177e4 LT |
1661 | |
1662 | if (!first_run) { | |
1663 | dmi_check_system(processor_power_dmi_table); | |
1664 | if (max_cstate < ACPI_C_STATES_MAX) | |
4be44fcd LB |
1665 | printk(KERN_NOTICE |
1666 | "ACPI: processor limited to max C-state %d\n", | |
1667 | max_cstate); | |
1da177e4 | 1668 | first_run++; |
4f86d3a8 | 1669 | #if !defined (CONFIG_CPU_IDLE) && defined (CONFIG_SMP) |
5c87579e | 1670 | register_latency_notifier(&acpi_processor_latency_notifier); |
1fec74a9 | 1671 | #endif |
1da177e4 LT |
1672 | } |
1673 | ||
02df8b93 | 1674 | if (!pr) |
d550d98d | 1675 | return -EINVAL; |
02df8b93 | 1676 | |
cee324b1 | 1677 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1678 | status = |
cee324b1 | 1679 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1680 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1681 | ACPI_EXCEPTION((AE_INFO, status, |
1682 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1683 | } |
1684 | } | |
1685 | ||
1686 | acpi_processor_get_power_info(pr); | |
4f86d3a8 | 1687 | pr->flags.power_setup_done = 1; |
1da177e4 LT |
1688 | |
1689 | /* | |
1690 | * Install the idle handler if processor power management is supported. | |
1691 | * Note that we use previously set idle handler will be used on | |
1692 | * platforms that only support C1. | |
1693 | */ | |
1694 | if ((pr->flags.power) && (!boot_option_idle_override)) { | |
4f86d3a8 LB |
1695 | #ifdef CONFIG_CPU_IDLE |
1696 | acpi_processor_setup_cpuidle(pr); | |
1697 | pr->power.dev.cpu = pr->id; | |
1698 | if (cpuidle_register_device(&pr->power.dev)) | |
1699 | return -EIO; | |
1700 | #endif | |
1701 | ||
1da177e4 LT |
1702 | printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id); |
1703 | for (i = 1; i <= pr->power.count; i++) | |
1704 | if (pr->power.states[i].valid) | |
4be44fcd LB |
1705 | printk(" C%d[C%d]", i, |
1706 | pr->power.states[i].type); | |
1da177e4 LT |
1707 | printk(")\n"); |
1708 | ||
4f86d3a8 | 1709 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
1710 | if (pr->id == 0) { |
1711 | pm_idle_save = pm_idle; | |
1712 | pm_idle = acpi_processor_idle; | |
1713 | } | |
4f86d3a8 | 1714 | #endif |
1da177e4 LT |
1715 | } |
1716 | ||
1717 | /* 'power' [R] */ | |
1718 | entry = create_proc_entry(ACPI_PROCESSOR_FILE_POWER, | |
4be44fcd | 1719 | S_IRUGO, acpi_device_dir(device)); |
1da177e4 | 1720 | if (!entry) |
a6fc6720 | 1721 | return -EIO; |
1da177e4 LT |
1722 | else { |
1723 | entry->proc_fops = &acpi_processor_power_fops; | |
1724 | entry->data = acpi_driver_data(device); | |
1725 | entry->owner = THIS_MODULE; | |
1726 | } | |
1727 | ||
d550d98d | 1728 | return 0; |
1da177e4 LT |
1729 | } |
1730 | ||
4be44fcd LB |
1731 | int acpi_processor_power_exit(struct acpi_processor *pr, |
1732 | struct acpi_device *device) | |
1da177e4 | 1733 | { |
4f86d3a8 LB |
1734 | #ifdef CONFIG_CPU_IDLE |
1735 | if ((pr->flags.power) && (!boot_option_idle_override)) | |
1736 | cpuidle_unregister_device(&pr->power.dev); | |
1737 | #endif | |
1da177e4 LT |
1738 | pr->flags.power_setup_done = 0; |
1739 | ||
1740 | if (acpi_device_dir(device)) | |
4be44fcd LB |
1741 | remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, |
1742 | acpi_device_dir(device)); | |
1da177e4 | 1743 | |
4f86d3a8 LB |
1744 | #ifndef CONFIG_CPU_IDLE |
1745 | ||
1da177e4 LT |
1746 | /* Unregister the idle handler when processor #0 is removed. */ |
1747 | if (pr->id == 0) { | |
1748 | pm_idle = pm_idle_save; | |
1749 | ||
1750 | /* | |
1751 | * We are about to unload the current idle thread pm callback | |
1752 | * (pm_idle), Wait for all processors to update cached/local | |
1753 | * copies of pm_idle before proceeding. | |
1754 | */ | |
1755 | cpu_idle_wait(); | |
1fec74a9 | 1756 | #ifdef CONFIG_SMP |
5c87579e | 1757 | unregister_latency_notifier(&acpi_processor_latency_notifier); |
1fec74a9 | 1758 | #endif |
1da177e4 | 1759 | } |
4f86d3a8 | 1760 | #endif |
1da177e4 | 1761 | |
d550d98d | 1762 | return 0; |
1da177e4 | 1763 | } |