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Merge tag 'for-linus-5.15b-rc2-tag' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-jammy-kernel.git] / drivers / ata / ahci.c
CommitLineData
c82ee6d3 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 * ahci.c - AHCI SATA support
4 *
8c3d3d4b 5 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
af36d7f0 11 * libata documentation is available via 'make {ps|pdf}docs',
19285f3c 12 * as Documentation/driver-api/libata.rst
af36d7f0
JG		 13 *
14 * AHCI hardware documentation:
1da177e4 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
1da177e4
LT		 22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
87507cfd 25#include <linux/dma-mapping.h>
a9524a76 26#include <linux/device.h>
edc93052 27#include <linux/dmi.h>
5a0e3ad6 28#include <linux/gfp.h>
ee2aad42 29#include <linux/msi.h>
1da177e4 30#include <scsi/scsi_host.h>
193515d5 31#include <scsi/scsi_cmnd.h>
1da177e4 32#include <linux/libata.h>
aecec8b6
CH		 33#include <linux/ahci-remap.h>
34#include <linux/io-64-nonatomic-lo-hi.h>
365cfa1e 35#include "ahci.h"
1da177e4
LT		 36
37#define DRV_NAME "ahci"
7d50b60b 38#define DRV_VERSION "3.0"
1da177e4 39
1da177e4 40enum {
318893e1 41 AHCI_PCI_BAR_STA2X11 = 0,
b7ae128d 42 AHCI_PCI_BAR_CAVIUM = 0,
e49bd683 43 AHCI_PCI_BAR_LOONGSON = 0,
7f9c9f8e 44 AHCI_PCI_BAR_ENMOTUS = 2,
b1314e3f 45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
318893e1 46 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 47};
48
49enum board_ids {
50 /* board IDs by feature in alphabetical order */
51 board_ahci,
52 board_ahci_ign_iferr,
ebb82e3c 53 board_ahci_mobile,
66a7cbc3 54 board_ahci_nomsi,
67809f85 55 board_ahci_noncq,
441577ef 56 board_ahci_nosntf,
5f173107 57 board_ahci_yes_fbs,
1da177e4 58
441577ef 59 /* board IDs for specific chipsets in alphabetical order */
7d523bdc 60 board_ahci_al,
dbfe8ef5 61 board_ahci_avn,
441577ef 62 board_ahci_mcp65,
83f2b963
TH		 63 board_ahci_mcp77,
64 board_ahci_mcp89,
441577ef
TH		 65 board_ahci_mv,
66 board_ahci_sb600,
67 board_ahci_sb700, /* for SB700 and SB800 */
68 board_ahci_vt8251,
69
c312ef17
DW		 70 /*
71 * board IDs for Intel chipsets that support more than 6 ports
72 * *and* end up needing the PCS quirk.
73 */
74 board_ahci_pcs7,
75
441577ef
TH		 76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 80 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 81};
82
2dcb407e 83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
02e53293 84static void ahci_remove_one(struct pci_dev *dev);
10a663a1 85static void ahci_shutdown_one(struct pci_dev *dev);
a1efdaba
TH		 86static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
dbfe8ef5
DW		 88static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
cb85696d
JL		 90static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
91static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 92static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
02e53293
MW		 94#ifdef CONFIG_PM
95static int ahci_pci_device_runtime_suspend(struct device *dev);
96static int ahci_pci_device_runtime_resume(struct device *dev);
f1d848f9
MW		 97#ifdef CONFIG_PM_SLEEP
98static int ahci_pci_device_suspend(struct device *dev);
99static int ahci_pci_device_resume(struct device *dev);
438ac6d5 100#endif
02e53293 101#endif /* CONFIG_PM */
ad616ffb 102
fad16e7a
TH		 103static struct scsi_host_template ahci_sht = {
104 AHCI_SHT("ahci"),
105};
106
029cfd6b
TH		 107static struct ata_port_operations ahci_vt8251_ops = {
108 .inherits = &ahci_ops,
a1efdaba 109 .hardreset = ahci_vt8251_hardreset,
029cfd6b 110};
edc93052 111
029cfd6b
TH		 112static struct ata_port_operations ahci_p5wdh_ops = {
113 .inherits = &ahci_ops,
a1efdaba 114 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 115};
116
dbfe8ef5
DW		 117static struct ata_port_operations ahci_avn_ops = {
118 .inherits = &ahci_ops,
119 .hardreset = ahci_avn_hardreset,
120};
121
98ac62de 122static const struct ata_port_info ahci_port_info[] = {
441577ef 123 /* by features */
facb8fa6 124 [board_ahci] = {
1188c0d8 125 .flags = AHCI_FLAG_COMMON,
14bdef98 126 .pio_mask = ATA_PIO4,
469248ab 127 .udma_mask = ATA_UDMA6,
1da177e4
LT		 128 .port_ops = &ahci_ops,
129 },
facb8fa6 130 [board_ahci_ign_iferr] = {
441577ef 131 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 132 .flags = AHCI_FLAG_COMMON,
14bdef98 133 .pio_mask = ATA_PIO4,
469248ab 134 .udma_mask = ATA_UDMA6,
441577ef 135 .port_ops = &ahci_ops,
bf2af2a2 136 },
ebb82e3c
HG		 137 [board_ahci_mobile] = {
138 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
66a7cbc3
TH		 144 [board_ahci_nomsi] = {
145 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
67809f85
LK		 151 [board_ahci_noncq] = {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
facb8fa6 158 [board_ahci_nosntf] = {
441577ef 159 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 160 .flags = AHCI_FLAG_COMMON,
14bdef98 161 .pio_mask = ATA_PIO4,
469248ab 162 .udma_mask = ATA_UDMA6,
41669553
TH		 163 .port_ops = &ahci_ops,
164 },
facb8fa6 165 [board_ahci_yes_fbs] = {
5f173107
TH		 166 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
167 .flags = AHCI_FLAG_COMMON,
168 .pio_mask = ATA_PIO4,
169 .udma_mask = ATA_UDMA6,
170 .port_ops = &ahci_ops,
171 },
441577ef 172 /* by chipsets */
7d523bdc
HH		 173 [board_ahci_al] = {
174 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
175 .flags = AHCI_FLAG_COMMON,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
179 },
dbfe8ef5
DW		 180 [board_ahci_avn] = {
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_avn_ops,
185 },
facb8fa6 186 [board_ahci_mcp65] = {
83f2b963
TH		 187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
188 AHCI_HFLAG_YES_NCQ),
ae01b249 189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_ops,
193 },
facb8fa6 194 [board_ahci_mcp77] = {
83f2b963
TH		 195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_ops,
200 },
facb8fa6 201 [board_ahci_mcp89] = {
83f2b963 202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 203 .flags = AHCI_FLAG_COMMON,
14bdef98 204 .pio_mask = ATA_PIO4,
469248ab 205 .udma_mask = ATA_UDMA6,
441577ef 206 .port_ops = &ahci_ops,
55a61604 207 },
facb8fa6 208 [board_ahci_mv] = {
417a1a6d 209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 212 .pio_mask = ATA_PIO4,
cd70c266
JG		 213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
215 },
facb8fa6 216 [board_ahci_sb600] = {
441577ef
TH		 217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
219 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 220 .flags = AHCI_FLAG_COMMON,
14bdef98 221 .pio_mask = ATA_PIO4,
e39fc8c9 222 .udma_mask = ATA_UDMA6,
345347c5 223 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 224 },
facb8fa6 225 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 227 .flags = AHCI_FLAG_COMMON,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
345347c5 230 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 231 },
facb8fa6 232 [board_ahci_vt8251] = {
441577ef 233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 234 .flags = AHCI_FLAG_COMMON,
235 .pio_mask = ATA_PIO4,
236 .udma_mask = ATA_UDMA6,
441577ef 237 .port_ops = &ahci_vt8251_ops,
1b677afd 238 },
c312ef17
DW		 239 [board_ahci_pcs7] = {
240 .flags = AHCI_FLAG_COMMON,
241 .pio_mask = ATA_PIO4,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &ahci_ops,
244 },
1da177e4
LT		 245};
246
3b7d697d 247static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 248 /* Intel */
5e125d13 249 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
54bb3a94
JG		 250 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
251 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
252 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
253 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
254 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 255 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 256 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
257 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
258 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
259 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 260 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 261 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 262 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
263 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
264 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
265 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
266 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
267 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
268 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
269 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
ebb82e3c
HG		 270 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
271 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
272 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
273 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
274 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
7a234aff 275 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
ebb82e3c 276 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
d4155e6f
JG		 277 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
278 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 279 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 280 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 281 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 282 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
283 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 284 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 285 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
ebb82e3c 286 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
adcb5308 287 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
ebb82e3c 288 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
c1f57d9b 289 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
c312ef17
DW		 290 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
5623cab8 310 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
ebb82e3c 311 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
5623cab8 312 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
ebb82e3c 313 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
5623cab8
SH		 314 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
315 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 316 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
317 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
318 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 319 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 320 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea 321 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
ebb82e3c 322 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
181e3cea
SH		 323 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
324 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
325 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
ebb82e3c 326 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
2cab7a4c 327 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66 328 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
ebb82e3c 329 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
ea4ace66 330 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
ebb82e3c 331 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
ea4ace66 332 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
ebb82e3c 333 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
ea4ace66 334 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
ebb82e3c
HG		 335 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
336 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
337 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
338 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
339 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
340 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
341 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
342 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
343 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
4544e403 344 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
29e674dd
SH		 345 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
346 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
347 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
348 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
349 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
350 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
351 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
352 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
dbfe8ef5
DW		 353 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
354 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
355 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
356 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
360 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
efda332c
JR		 361 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
362 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
8e85f605
MW		 363 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
364 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
365 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
366 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
151743fd
JR		 367 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
368 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
369 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
370 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
371 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
372 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
373 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
374 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 375 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
ebb82e3c
HG		 376 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
377 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
378 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
379 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
1b071a09 380 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
ebb82e3c 381 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
1b071a09 382 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
ebb82e3c 383 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
1b071a09 384 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
ebb82e3c 385 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
1b071a09 386 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
ebb82e3c
HG		 387 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
388 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
389 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
390 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
c5967b79 391 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
ebb82e3c 392 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
690000b9 393 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
c5967b79 394 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
ebb82e3c 395 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
690000b9 396 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
4d92f009 397 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
f5bdd66c 398 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
4d92f009 399 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
f5bdd66c 400 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
4d92f009 401 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
4d92f009 402 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
f5bdd66c
AY		 403 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
404 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
4d92f009 405 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
4d92f009 406 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
f5bdd66c
AY		 407 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
408 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
f919dde0 409 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
32d25454 410 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
58c42b0b 411 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
ebb82e3c
HG		 412 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
413 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
414 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
415 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
ba445791 416 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
1f2ef049 417 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */
7667e63c 418 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */
fe7fa31a 419
e34bb370
TH		 420 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
421 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
422 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 423 /* JMicron 362B and 362C have an AHCI function with IDE class code */
424 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
425 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
91f15fb3 426 /* May need to update quirk_jmicron_async_suspend() for additions */
fe7fa31a
JG		 427
428 /* ATI */
c65ec1c2 429 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 430 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
431 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
435 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 436
7d523bdc
HH		 437 /* Amazon's Annapurna Labs support */
438 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
439 .class = PCI_CLASS_STORAGE_SATA_AHCI,
440 .class_mask = 0xffffff,
441 board_ahci_al },
e2dd90b1 442 /* AMD */
5deab536 443 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 444 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 445 /* AMD is using RAID class only for ahci controllers */
446 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
447 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
9c54cd10
CR		 448
449 /* Dell S140/S150 */
450 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
451 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
e2dd90b1 452
fe7fa31a 453 /* VIA */
54bb3a94 454 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 455 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 456
457 /* NVIDIA */
e297d99e
TH		 458 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
459 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
460 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
461 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
462 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
463 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
464 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
465 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 466 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
470 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
471 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
472 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
473 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
474 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
475 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
476 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
477 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
478 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
479 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
480 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
481 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
482 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
483 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
484 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
485 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
486 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
487 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
488 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
489 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
490 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
491 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
492 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
493 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
494 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
495 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
496 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
497 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
498 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
499 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
500 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
501 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
502 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
503 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
504 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
505 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
506 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
507 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
508 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
509 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
510 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
511 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
512 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
513 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
514 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
515 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
516 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
517 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
518 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
519 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
520 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
521 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
522 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
523 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
524 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
525 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
526 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
527 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
528 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
529 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
530 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
531 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
532 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
533 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
534 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
535 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
536 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
537 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
538 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
539 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
540 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
541 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 542
95916edd 543 /* SiS */
20e2de4a
TH		 544 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
545 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
546 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 547
318893e1
AR		 548 /* ST Microelectronics */
549 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
550
cd70c266
JG		 551 /* Marvell */
552 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 553 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 554 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 555 .class = PCI_CLASS_STORAGE_SATA_AHCI,
556 .class_mask = 0xffffff,
5f173107 557 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 558 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 559 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 560 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
561 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
562 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 564 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35 565 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
c5edfff9
MK		 566 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
567 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
fcce9a35 568 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 569 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 570 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
754a292f
AS		 571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
572 .driver_data = board_ahci_yes_fbs },
a40cf3f3
JT		 573 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
574 .driver_data = board_ahci_yes_fbs },
69fd3157 575 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 576 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 577 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
578 .driver_data = board_ahci_yes_fbs },
28b2182d
HG		 579 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
580 .driver_data = board_ahci_yes_fbs },
581 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
d2518365 582 .driver_data = board_ahci_yes_fbs },
cd70c266 583
c77a036b
MN		 584 /* Promise */
585 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
b32bfc06 586 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
c77a036b 587
c9703765 588 /* Asmedia */
7b4f6eca
AC		 589 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
590 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
591 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
592 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
0ce968f3
SL		 593 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
594 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
c9703765 595
67809f85 596 /*
66a7cbc3
TH		 597 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
598 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
67809f85 599 */
66a7cbc3 600 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
2b21ef0a 601 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
67809f85 602
7f9c9f8e
HD		 603 /* Enmotus */
604 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
605
e49bd683
TY		 606 /* Loongson */
607 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
608
415ae2b5
JG		 609 /* Generic, PCI class code for AHCI */
610 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 611 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 612
1da177e4
LT		 613 { } /* terminate list */
614};
615
f1d848f9
MW		 616static const struct dev_pm_ops ahci_pci_pm_ops = {
617 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
02e53293
MW		 618 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
619 ahci_pci_device_runtime_resume, NULL)
f1d848f9 620};
1da177e4
LT		 621
622static struct pci_driver ahci_pci_driver = {
623 .name = DRV_NAME,
624 .id_table = ahci_pci_tbl,
625 .probe = ahci_init_one,
02e53293 626 .remove = ahci_remove_one,
10a663a1 627 .shutdown = ahci_shutdown_one,
f1d848f9
MW		 628 .driver = {
629 .pm = &ahci_pci_pm_ops,
630 },
365cfa1e 631};
1da177e4 632
5219d653 633#if IS_ENABLED(CONFIG_PATA_MARVELL)
365cfa1e
AV		 634static int marvell_enable;
635#else
636static int marvell_enable = 1;
637#endif
638module_param(marvell_enable, int, 0644);
639MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 640
b1a9585c 641static int mobile_lpm_policy = -1;
ebb82e3c
HG		 642module_param(mobile_lpm_policy, int, 0644);
643MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
1da177e4 644
365cfa1e
AV		 645static void ahci_pci_save_initial_config(struct pci_dev *pdev,
646 struct ahci_host_priv *hpriv)
647{
365cfa1e
AV		 648 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
649 dev_info(&pdev->dev, "JMB361 has only one port\n");
9a23c1d6 650 hpriv->force_port_map = 1;
1da177e4
LT		 651 }
652
365cfa1e
AV		 653 /*
654 * Temporary Marvell 6145 hack: PATA port presence
655 * is asserted through the standard AHCI port
656 * presence register, as bit 4 (counting from 0)
d28f87aa 657 */
365cfa1e
AV		 658 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
659 if (pdev->device == 0x6121)
9a23c1d6 660 hpriv->mask_port_map = 0x3;
365cfa1e 661 else
9a23c1d6 662 hpriv->mask_port_map = 0xf;
365cfa1e
AV		 663 dev_info(&pdev->dev,
664 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
665 }
1da177e4 666
725c7b57 667 ahci_save_initial_config(&pdev->dev, hpriv);
1da177e4
LT		 668}
669
365cfa1e 670static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 671{
365cfa1e
AV		 672 struct ahci_host_priv *hpriv = host->private_data;
673 struct pci_dev *pdev = to_pci_dev(host->dev);
674 void __iomem *port_mmio;
78cd52d0 675 u32 tmp;
365cfa1e 676 int mv;
78cd52d0 677
365cfa1e
AV		 678 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
679 if (pdev->device == 0x6121)
680 mv = 2;
681 else
682 mv = 4;
683 port_mmio = __ahci_port_base(host, mv);
78cd52d0 684
365cfa1e 685 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 686
365cfa1e
AV		 687 /* clear port IRQ */
688 tmp = readl(port_mmio + PORT_IRQ_STAT);
689 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
690 if (tmp)
691 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 692 }
693
365cfa1e 694 ahci_init_controller(host);
edc93052
TH		 695}
696
365cfa1e
AV		 697static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
698 unsigned long deadline)
d6ef3153 699{
365cfa1e 700 struct ata_port *ap = link->ap;
039ece38 701 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 702 bool online;
d6ef3153
SH		 703 int rc;
704
365cfa1e 705 DPRINTK("ENTER\n");
d6ef3153 706
fa89f53b 707 hpriv->stop_engine(ap);
d6ef3153 708
365cfa1e
AV		 709 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
710 deadline, &online, NULL);
d6ef3153 711
039ece38 712 hpriv->start_engine(ap);
d6ef3153 713
365cfa1e 714 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 715
365cfa1e
AV		 716 /* vt8251 doesn't clear BSY on signature FIS reception,
717 * request follow-up softreset.
718 */
719 return online ? -EAGAIN : rc;
7d50b60b
TH		 720}
721
365cfa1e
AV		 722static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
723 unsigned long deadline)
7d50b60b 724{
365cfa1e 725 struct ata_port *ap = link->ap;
1c954a4d 726 struct ahci_port_priv *pp = ap->private_data;
039ece38 727 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 728 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
729 struct ata_taskfile tf;
730 bool online;
731 int rc;
7d50b60b 732
fa89f53b 733 hpriv->stop_engine(ap);
028a2596 734
365cfa1e
AV		 735 /* clear D2H reception area to properly wait for D2H FIS */
736 ata_tf_init(link->device, &tf);
9bbb1b0e 737 tf.command = ATA_BUSY;
365cfa1e 738 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 739
365cfa1e
AV		 740 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
741 deadline, &online, NULL);
028a2596 742
039ece38 743 hpriv->start_engine(ap);
c1332875 744
365cfa1e
AV		 745 /* The pseudo configuration device on SIMG4726 attached to
746 * ASUS P5W-DH Deluxe doesn't send signature FIS after
747 * hardreset if no device is attached to the first downstream
748 * port && the pseudo device locks up on SRST w/ PMP==0. To
749 * work around this, wait for !BSY only briefly. If BSY isn't
750 * cleared, perform CLO and proceed to IDENTIFY (achieved by
751 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
752 *
753 * Wait for two seconds. Devices attached to downstream port
754 * which can't process the following IDENTIFY after this will
755 * have to be reset again. For most cases, this should
756 * suffice while making probing snappish enough.
757 */
758 if (online) {
759 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
760 ahci_check_ready);
761 if (rc)
762 ahci_kick_engine(ap);
c1332875 763 }
c1332875
TH		 764 return rc;
765}
766
dbfe8ef5
DW		 767/*
768 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
769 *
770 * It has been observed with some SSDs that the timing of events in the
771 * link synchronization phase can leave the port in a state that can not
772 * be recovered by a SATA-hard-reset alone. The failing signature is
773 * SStatus.DET stuck at 1 ("Device presence detected but Phy
774 * communication not established"). It was found that unloading and
775 * reloading the driver when this problem occurs allows the drive
776 * connection to be recovered (DET advanced to 0x3). The critical
777 * component of reloading the driver is that the port state machines are
778 * reset by bouncing "port enable" in the AHCI PCS configuration
779 * register. So, reproduce that effect by bouncing a port whenever we
780 * see DET==1 after a reset.
781 */
782static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
783 unsigned long deadline)
784{
785 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
786 struct ata_port *ap = link->ap;
787 struct ahci_port_priv *pp = ap->private_data;
788 struct ahci_host_priv *hpriv = ap->host->private_data;
789 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
790 unsigned long tmo = deadline - jiffies;
791 struct ata_taskfile tf;
792 bool online;
793 int rc, i;
794
795 DPRINTK("ENTER\n");
796
fa89f53b 797 hpriv->stop_engine(ap);
dbfe8ef5
DW		 798
799 for (i = 0; i < 2; i++) {
800 u16 val;
801 u32 sstatus;
802 int port = ap->port_no;
803 struct ata_host *host = ap->host;
804 struct pci_dev *pdev = to_pci_dev(host->dev);
805
806 /* clear D2H reception area to properly wait for D2H FIS */
807 ata_tf_init(link->device, &tf);
808 tf.command = ATA_BUSY;
809 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
810
811 rc = sata_link_hardreset(link, timing, deadline, &online,
812 ahci_check_ready);
813
814 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
815 (sstatus & 0xf) != 1)
816 break;
817
e276c9bd 818 ata_link_info(link, "avn bounce port%d\n", port);
dbfe8ef5
DW		 819
820 pci_read_config_word(pdev, 0x92, &val);
821 val &= ~(1 << port);
822 pci_write_config_word(pdev, 0x92, val);
823 ata_msleep(ap, 1000);
824 val |= 1 << port;
825 pci_write_config_word(pdev, 0x92, val);
826 deadline += tmo;
827 }
828
829 hpriv->start_engine(ap);
830
831 if (online)
832 *class = ahci_dev_classify(ap);
833
834 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
835 return rc;
836}
837
838
02e53293
MW		 839#ifdef CONFIG_PM
840static void ahci_pci_disable_interrupts(struct ata_host *host)
c1332875 841{
9b10ae86 842 struct ahci_host_priv *hpriv = host->private_data;
d8993349 843 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 844 u32 ctl;
845
f1d848f9
MW		 846 /* AHCI spec rev1.1 section 8.3.3:
847 * Software must disable interrupts prior to requesting a
848 * transition of the HBA to D3 state.
849 */
850 ctl = readl(mmio + HOST_CTL);
851 ctl &= ~HOST_IRQ_EN;
852 writel(ctl, mmio + HOST_CTL);
853 readl(mmio + HOST_CTL); /* flush */
02e53293
MW		 854}
855
856static int ahci_pci_device_runtime_suspend(struct device *dev)
857{
858 struct pci_dev *pdev = to_pci_dev(dev);
859 struct ata_host *host = pci_get_drvdata(pdev);
c1332875 860
02e53293
MW		 861 ahci_pci_disable_interrupts(host);
862 return 0;
863}
864
865static int ahci_pci_device_runtime_resume(struct device *dev)
866{
867 struct pci_dev *pdev = to_pci_dev(dev);
868 struct ata_host *host = pci_get_drvdata(pdev);
869 int rc;
870
c312ef17 871 rc = ahci_reset_controller(host);
02e53293
MW		 872 if (rc)
873 return rc;
874 ahci_pci_init_controller(host);
875 return 0;
876}
877
878#ifdef CONFIG_PM_SLEEP
879static int ahci_pci_device_suspend(struct device *dev)
880{
881 struct pci_dev *pdev = to_pci_dev(dev);
882 struct ata_host *host = pci_get_drvdata(pdev);
883 struct ahci_host_priv *hpriv = host->private_data;
884
885 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
886 dev_err(&pdev->dev,
887 "BIOS update required for suspend/resume\n");
888 return -EIO;
889 }
890
891 ahci_pci_disable_interrupts(host);
f1d848f9 892 return ata_host_suspend(host, PMSG_SUSPEND);
c1332875
TH		 893}
894
f1d848f9 895static int ahci_pci_device_resume(struct device *dev)
c1332875 896{
f1d848f9 897 struct pci_dev *pdev = to_pci_dev(dev);
0a86e1c8 898 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 899 int rc;
900
cb85696d
JL		 901 /* Apple BIOS helpfully mangles the registers on resume */
902 if (is_mcp89_apple(pdev))
903 ahci_mcp89_apple_enable(pdev);
904
c1332875 905 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
c312ef17 906 rc = ahci_reset_controller(host);
c1332875
TH		 907 if (rc)
908 return rc;
909
781d6550 910 ahci_pci_init_controller(host);
c1332875
TH		 911 }
912
cca3974e 913 ata_host_resume(host);
c1332875
TH		 914
915 return 0;
916}
438ac6d5 917#endif
c1332875 918
02e53293
MW		 919#endif /* CONFIG_PM */
920
4447d351 921static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 922{
b1716871 923 const int dma_bits = using_dac ? 64 : 32;
1da177e4 924 int rc;
1da177e4 925
318893e1
AR		 926 /*
927 * If the device fixup already set the dma_mask to some non-standard
928 * value, don't extend it here. This happens on STA2X11, for example.
b1716871
CH		 929 *
930 * XXX: manipulating the DMA mask from platform code is completely
a7ba70f1 931 * bogus, platform code should use dev->bus_dma_limit instead..
318893e1
AR		 932 */
933 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
934 return 0;
935
b1716871
CH		 936 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
937 if (rc)
938 dev_err(&pdev->dev, "DMA enable failed\n");
939 return rc;
1da177e4
LT		 940}
941
439fcaec
AV		 942static void ahci_pci_print_info(struct ata_host *host)
943{
944 struct pci_dev *pdev = to_pci_dev(host->dev);
945 u16 cc;
946 const char *scc_s;
947
948 pci_read_config_word(pdev, 0x0a, &cc);
949 if (cc == PCI_CLASS_STORAGE_IDE)
950 scc_s = "IDE";
951 else if (cc == PCI_CLASS_STORAGE_SATA)
952 scc_s = "SATA";
953 else if (cc == PCI_CLASS_STORAGE_RAID)
954 scc_s = "RAID";
955 else
956 scc_s = "unknown";
957
958 ahci_print_info(host, scc_s);
959}
960
edc93052
TH		 961/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
962 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
963 * support PMP and the 4726 either directly exports the device
964 * attached to the first downstream port or acts as a hardware storage
965 * controller and emulate a single ATA device (can be RAID 0/1 or some
966 * other configuration).
967 *
968 * When there's no device attached to the first downstream port of the
969 * 4726, "Config Disk" appears, which is a pseudo ATA device to
970 * configure the 4726. However, ATA emulation of the device is very
971 * lame. It doesn't send signature D2H Reg FIS after the initial
972 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
973 *
974 * The following function works around the problem by always using
975 * hardreset on the port and not depending on receiving signature FIS
976 * afterward. If signature FIS isn't received soon, ATA class is
977 * assumed without follow-up softreset.
978 */
979static void ahci_p5wdh_workaround(struct ata_host *host)
980{
1bd06867 981 static const struct dmi_system_id sysids[] = {
edc93052
TH		 982 {
983 .ident = "P5W DH Deluxe",
984 .matches = {
985 DMI_MATCH(DMI_SYS_VENDOR,
986 "ASUSTEK COMPUTER INC"),
987 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
988 },
989 },
990 { }
991 };
992 struct pci_dev *pdev = to_pci_dev(host->dev);
993
994 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
995 dmi_check_system(sysids)) {
996 struct ata_port *ap = host->ports[1];
997
a44fec1f
JP		 998 dev_info(&pdev->dev,
999 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 1000
1001 ap->ops = &ahci_p5wdh_ops;
1002 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1003 }
1004}
1005
cb85696d
JL		 1006/*
1007 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1008 * booting in BIOS compatibility mode. We restore the registers but not ID.
1009 */
1010static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1011{
1012 u32 val;
1013
1014 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1015
1016 pci_read_config_dword(pdev, 0xf8, &val);
1017 val |= 1 << 0x1b;
1018 /* the following changes the device ID, but appears not to affect function */
1019 /* val = (val & ~0xf0000000) | 0x80000000; */
1020 pci_write_config_dword(pdev, 0xf8, val);
1021
1022 pci_read_config_dword(pdev, 0x54c, &val);
1023 val |= 1 << 0xc;
1024 pci_write_config_dword(pdev, 0x54c, val);
1025
1026 pci_read_config_dword(pdev, 0x4a4, &val);
1027 val &= 0xff;
1028 val |= 0x01060100;
1029 pci_write_config_dword(pdev, 0x4a4, val);
1030
1031 pci_read_config_dword(pdev, 0x54c, &val);
1032 val &= ~(1 << 0xc);
1033 pci_write_config_dword(pdev, 0x54c, val);
1034
1035 pci_read_config_dword(pdev, 0xf8, &val);
1036 val &= ~(1 << 0x1b);
1037 pci_write_config_dword(pdev, 0xf8, val);
1038}
1039
1040static bool is_mcp89_apple(struct pci_dev *pdev)
1041{
1042 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1043 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1044 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1045 pdev->subsystem_device == 0xcb89;
1046}
1047
2fcad9d2
TH		 1048/* only some SB600 ahci controllers can do 64bit DMA */
1049static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 1050{
1051 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 1052 /*
1053 * The oldest version known to be broken is 0901 and
1054 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 1055 * Enable 64bit DMA on 1501 and anything newer.
1056 *
03d783bf
TH		 1057 * Please read bko#9412 for more info.
1058 */
58a09b38
SH		 1059 {
1060 .ident = "ASUS M2A-VM",
1061 .matches = {
1062 DMI_MATCH(DMI_BOARD_VENDOR,
1063 "ASUSTeK Computer INC."),
1064 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1065 },
03d783bf 1066 .driver_data = "20071026", /* yyyymmdd */
58a09b38 1067 },
e65cc194
MN		 1068 /*
1069 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1070 * support 64bit DMA.
1071 *
1072 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1073 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1074 * This spelling mistake was fixed in BIOS version 1.5, so
1075 * 1.5 and later have the Manufacturer as
1076 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1077 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1078 *
1079 * BIOS versions earlier than 1.9 had a Board Product Name
1080 * DMI field of "MS-7376". This was changed to be
1081 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1082 * match on DMI_BOARD_NAME of "MS-7376".
1083 */
1084 {
1085 .ident = "MSI K9A2 Platinum",
1086 .matches = {
1087 DMI_MATCH(DMI_BOARD_VENDOR,
1088 "MICRO-STAR INTER"),
1089 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1090 },
1091 },
ff0173c1
MN		 1092 /*
1093 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1094 * 64bit DMA.
1095 *
1096 * This board also had the typo mentioned above in the
1097 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1098 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1099 */
1100 {
1101 .ident = "MSI K9AGM2",
1102 .matches = {
1103 DMI_MATCH(DMI_BOARD_VENDOR,
1104 "MICRO-STAR INTER"),
1105 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1106 },
1107 },
3c4aa91f
MN		 1108 /*
1109 * All BIOS versions for the Asus M3A support 64bit DMA.
1110 * (all release versions from 0301 to 1206 were tested)
1111 */
1112 {
1113 .ident = "ASUS M3A",
1114 .matches = {
1115 DMI_MATCH(DMI_BOARD_VENDOR,
1116 "ASUSTeK Computer INC."),
1117 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1118 },
1119 },
58a09b38
SH		 1120 { }
1121 };
03d783bf 1122 const struct dmi_system_id *match;
2fcad9d2
TH		 1123 int year, month, date;
1124 char buf[9];
58a09b38 1125
03d783bf 1126 match = dmi_first_match(sysids);
58a09b38 1127 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 1128 !match)
58a09b38
SH		 1129 return false;
1130
e65cc194
MN		 1131 if (!match->driver_data)
1132 goto enable_64bit;
1133
2fcad9d2
TH		 1134 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1135 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 1136
e65cc194
MN		 1137 if (strcmp(buf, match->driver_data) >= 0)
1138 goto enable_64bit;
1139 else {
a44fec1f
JP		 1140 dev_warn(&pdev->dev,
1141 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1142 match->ident);
2fcad9d2
TH		 1143 return false;
1144 }
e65cc194
MN		 1145
1146enable_64bit:
a44fec1f 1147 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 1148 return true;
58a09b38
SH		 1149}
1150
1fd68434
RW		 1151static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1152{
1153 static const struct dmi_system_id broken_systems[] = {
1154 {
1155 .ident = "HP Compaq nx6310",
1156 .matches = {
1157 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1158 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1159 },
1160 /* PCI slot number of the controller */
1161 .driver_data = (void *)0x1FUL,
1162 },
d2f9c061
MR		 1163 {
1164 .ident = "HP Compaq 6720s",
1165 .matches = {
1166 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1167 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1168 },
1169 /* PCI slot number of the controller */
1170 .driver_data = (void *)0x1FUL,
1171 },
1fd68434
RW		 1172
1173 { } /* terminate list */
1174 };
1175 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1176
1177 if (dmi) {
1178 unsigned long slot = (unsigned long)dmi->driver_data;
1179 /* apply the quirk only to on-board controllers */
1180 return slot == PCI_SLOT(pdev->devfn);
1181 }
1182
1183 return false;
1184}
1185
9b10ae86
TH		 1186static bool ahci_broken_suspend(struct pci_dev *pdev)
1187{
1188 static const struct dmi_system_id sysids[] = {
1189 /*
1190 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1191 * to the harddisk doesn't become online after
1192 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 1193 *
1194 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1195 *
1196 * Use dates instead of versions to match as HP is
1197 * apparently recycling both product and version
1198 * strings.
1199 *
1200 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 1201 */
1202 {
1203 .ident = "dv4",
1204 .matches = {
1205 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1206 DMI_MATCH(DMI_PRODUCT_NAME,
1207 "HP Pavilion dv4 Notebook PC"),
1208 },
9deb3431 1209 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1210 },
1211 {
1212 .ident = "dv5",
1213 .matches = {
1214 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1215 DMI_MATCH(DMI_PRODUCT_NAME,
1216 "HP Pavilion dv5 Notebook PC"),
1217 },
9deb3431 1218 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1219 },
1220 {
1221 .ident = "dv6",
1222 .matches = {
1223 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1224 DMI_MATCH(DMI_PRODUCT_NAME,
1225 "HP Pavilion dv6 Notebook PC"),
1226 },
9deb3431 1227 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1228 },
1229 {
1230 .ident = "HDX18",
1231 .matches = {
1232 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1233 DMI_MATCH(DMI_PRODUCT_NAME,
1234 "HP HDX18 Notebook PC"),
1235 },
9deb3431 1236 .driver_data = "20090430", /* F.23 */
9b10ae86 1237 },
cedc9bf9
TH		 1238 /*
1239 * Acer eMachines G725 has the same problem. BIOS
1240 * V1.03 is known to be broken. V3.04 is known to
25985edc 1241 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1242 * that we don't have much idea about. For now,
1243 * blacklist anything older than V3.04.
9deb3431
TH		 1244 *
1245 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1246 */
1247 {
1248 .ident = "G725",
1249 .matches = {
1250 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1251 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1252 },
9deb3431 1253 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1254 },
9b10ae86
TH		 1255 { } /* terminate list */
1256 };
1257 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1258 int year, month, date;
1259 char buf[9];
9b10ae86
TH		 1260
1261 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1262 return false;
1263
9deb3431
TH		 1264 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1265 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1266
9deb3431 1267 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1268}
1269
240630e6
HG		 1270static bool ahci_broken_lpm(struct pci_dev *pdev)
1271{
1272 static const struct dmi_system_id sysids[] = {
1273 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1274 {
1275 .matches = {
1276 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1277 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1278 },
1279 .driver_data = "20180406", /* 1.31 */
1280 },
1281 {
1282 .matches = {
1283 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1284 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1285 },
1286 .driver_data = "20180420", /* 1.28 */
1287 },
1288 {
1289 .matches = {
1290 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1291 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1292 },
1293 .driver_data = "20180315", /* 1.33 */
1294 },
1295 {
1296 .matches = {
1297 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1298 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1299 },
1300 /*
1301 * Note date based on release notes, 2.35 has been
1302 * reported to be good, but I've been unable to get
1303 * a hold of the reporter to get the DMI BIOS date.
1304 * TODO: fix this.
1305 */
1306 .driver_data = "20180310", /* 2.35 */
1307 },
1308 { } /* terminate list */
1309 };
1310 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1311 int year, month, date;
1312 char buf[9];
1313
1314 if (!dmi)
1315 return false;
1316
1317 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1318 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1319
1320 return strcmp(buf, dmi->driver_data) < 0;
1321}
1322
5594639a
TH		 1323static bool ahci_broken_online(struct pci_dev *pdev)
1324{
1325#define ENCODE_BUSDEVFN(bus, slot, func) \
1326 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1327 static const struct dmi_system_id sysids[] = {
1328 /*
1329 * There are several gigabyte boards which use
1330 * SIMG5723s configured as hardware RAID. Certain
1331 * 5723 firmware revisions shipped there keep the link
1332 * online but fail to answer properly to SRST or
1333 * IDENTIFY when no device is attached downstream
1334 * causing libata to retry quite a few times leading
1335 * to excessive detection delay.
1336 *
1337 * As these firmwares respond to the second reset try
1338 * with invalid device signature, considering unknown
1339 * sig as offline works around the problem acceptably.
1340 */
1341 {
1342 .ident = "EP45-DQ6",
1343 .matches = {
1344 DMI_MATCH(DMI_BOARD_VENDOR,
1345 "Gigabyte Technology Co., Ltd."),
1346 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1347 },
1348 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1349 },
1350 {
1351 .ident = "EP45-DS5",
1352 .matches = {
1353 DMI_MATCH(DMI_BOARD_VENDOR,
1354 "Gigabyte Technology Co., Ltd."),
1355 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1356 },
1357 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1358 },
1359 { } /* terminate list */
1360 };
1361#undef ENCODE_BUSDEVFN
1362 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1363 unsigned int val;
1364
1365 if (!dmi)
1366 return false;
1367
1368 val = (unsigned long)dmi->driver_data;
1369
1370 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1371}
1372
0cf4a7d6
JP		 1373static bool ahci_broken_devslp(struct pci_dev *pdev)
1374{
1375 /* device with broken DEVSLP but still showing SDS capability */
1376 static const struct pci_device_id ids[] = {
1377 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1378 {}
1379 };
1380
1381 return pci_match_id(ids, pdev);
1382}
1383
8e513217 1384#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1385static void ahci_gtf_filter_workaround(struct ata_host *host)
1386{
1387 static const struct dmi_system_id sysids[] = {
1388 /*
1389 * Aspire 3810T issues a bunch of SATA enable commands
1390 * via _GTF including an invalid one and one which is
1391 * rejected by the device. Among the successful ones
1392 * is FPDMA non-zero offset enable which when enabled
1393 * only on the drive side leads to NCQ command
1394 * failures. Filter it out.
1395 */
1396 {
1397 .ident = "Aspire 3810T",
1398 .matches = {
1399 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1400 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1401 },
1402 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1403 },
1404 { }
1405 };
1406 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1407 unsigned int filter;
1408 int i;
1409
1410 if (!dmi)
1411 return;
1412
1413 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1414 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1415 filter, dmi->ident);
f80ae7e4
TH		 1416
1417 for (i = 0; i < host->n_ports; i++) {
1418 struct ata_port *ap = host->ports[i];
1419 struct ata_link *link;
1420 struct ata_device *dev;
1421
1422 ata_for_each_link(link, ap, EDGE)
1423 ata_for_each_dev(dev, link, ALL)
1424 dev->gtf_filter |= filter;
1425 }
1426}
8e513217
MT		 1427#else
1428static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1429{}
1430#endif
f80ae7e4 1431
8bfd1743
SC		 1432/*
1433 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1434 * as DUMMY, or detected but eventually get a "link down" and never get up
1435 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1436 * port_map may hold a value of 0x00.
1437 *
1438 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1439 * and can significantly reduce the occurrence of the problem.
1440 *
1441 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1442 */
1443static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1444 struct pci_dev *pdev)
1445{
1446 static const struct dmi_system_id sysids[] = {
1447 {
1448 .ident = "Acer Switch Alpha 12",
1449 .matches = {
1450 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1451 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1452 },
1453 },
1454 { }
1455 };
1456
1457 if (dmi_check_system(sysids)) {
1458 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1459 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1460 hpriv->port_map = 0x7;
1461 hpriv->cap = 0xC734FF02;
1462 }
1463 }
1464}
1465
d243bed3
TC		 1466#ifdef CONFIG_ARM64
1467/*
1468 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1469 * Workaround is to make sure all pending IRQs are served before leaving
1470 * handler.
1471 */
1472static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1473{
1474 struct ata_host *host = dev_instance;
1475 struct ahci_host_priv *hpriv;
1476 unsigned int rc = 0;
1477 void __iomem *mmio;
1478 u32 irq_stat, irq_masked;
1479 unsigned int handled = 1;
1480
1481 VPRINTK("ENTER\n");
1482 hpriv = host->private_data;
1483 mmio = hpriv->mmio;
1484 irq_stat = readl(mmio + HOST_IRQ_STAT);
1485 if (!irq_stat)
1486 return IRQ_NONE;
1487
1488 do {
1489 irq_masked = irq_stat & hpriv->port_map;
1490 spin_lock(&host->lock);
1491 rc = ahci_handle_port_intr(host, irq_masked);
1492 if (!rc)
1493 handled = 0;
1494 writel(irq_stat, mmio + HOST_IRQ_STAT);
1495 irq_stat = readl(mmio + HOST_IRQ_STAT);
1496 spin_unlock(&host->lock);
1497 } while (irq_stat);
1498 VPRINTK("EXIT\n");
1499
1500 return IRQ_RETVAL(handled);
1501}
1502#endif
1503
aecec8b6
CH		 1504static void ahci_remap_check(struct pci_dev *pdev, int bar,
1505 struct ahci_host_priv *hpriv)
1506{
894fba7f 1507 int i;
aecec8b6
CH		 1508 u32 cap;
1509
1510 /*
1511 * Check if this device might have remapped nvme devices.
1512 */
1513 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1514 pci_resource_len(pdev, bar) < SZ_512K ||
1515 bar != AHCI_PCI_BAR_STANDARD ||
1516 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1517 return;
1518
1519 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1520 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1521 if ((cap & (1 << i)) == 0)
1522 continue;
1523 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1524 != PCI_CLASS_STORAGE_EXPRESS)
1525 continue;
1526
1527 /* We've found a remapped device */
894fba7f 1528 hpriv->remapped_nvme++;
aecec8b6
CH		 1529 }
1530
894fba7f 1531 if (!hpriv->remapped_nvme)
aecec8b6
CH		 1532 return;
1533
894fba7f
KHF		 1534 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1535 hpriv->remapped_nvme);
f723fa4e
CH		 1536 dev_warn(&pdev->dev,
1537 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1538
1539 /*
1540 * Don't rely on the msi-x capability in the remap case,
1541 * share the legacy interrupt across ahci and remapped devices.
1542 */
1543 hpriv->flags |= AHCI_HFLAG_NO_MSI;
aecec8b6
CH		 1544}
1545
0b9e2988 1546static int ahci_get_irq_vector(struct ata_host *host, int port)
5ca72c4f 1547{
0b9e2988 1548 return pci_irq_vector(to_pci_dev(host->dev), port);
ee2aad42
RR		 1549}
1550
a1c82311
RR		 1551static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1552 struct ahci_host_priv *hpriv)
5ca72c4f 1553{
0b9e2988 1554 int nvec;
5ca72c4f 1555
7b92b4f6 1556 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
a1c82311 1557 return -ENODEV;
7b92b4f6 1558
7b92b4f6
AG		 1559 /*
1560 * If number of MSIs is less than number of ports then Sharing Last
1561 * Message mode could be enforced. In this case assume that advantage
1562 * of multipe MSIs is negated and use single MSI mode instead.
1563 */
17a51f12
CH		 1564 if (n_ports > 1) {
1565 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1566 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1567 if (nvec > 0) {
1568 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1569 hpriv->get_irq_vector = ahci_get_irq_vector;
1570 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1571 return nvec;
1572 }
5ca72c4f 1573
17a51f12
CH		 1574 /*
1575 * Fallback to single MSI mode if the controller
1576 * enforced MRSM mode.
1577 */
1578 printk(KERN_INFO
1579 "ahci: MRSM is on, fallback to single MSI\n");
1580 pci_free_irq_vectors(pdev);
1581 }
a478b097 1582 }
d684a90d 1583
0b9e2988
CH		 1584 /*
1585 * If the host is not capable of supporting per-port vectors, fall
1586 * back to single MSI before finally attempting single MSI-X.
1587 */
1588 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1589 if (nvec == 1)
ee2aad42 1590 return nvec;
0b9e2988 1591 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
5ca72c4f
AG		 1592}
1593
b1a9585c
SP		 1594static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1595 struct ahci_host_priv *hpriv)
1596{
1597 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1598
1599
1600 /* Ignore processing for non mobile platforms */
1601 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1602 return;
1603
1604 /* user modified policy via module param */
1605 if (mobile_lpm_policy != -1) {
1606 policy = mobile_lpm_policy;
1607 goto update_policy;
1608 }
1609
1610#ifdef CONFIG_ACPI
1611 if (policy > ATA_LPM_MED_POWER &&
1612 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1613 if (hpriv->cap & HOST_CAP_PART)
1614 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1615 else if (hpriv->cap & HOST_CAP_SSC)
1616 policy = ATA_LPM_MIN_POWER;
1617 }
1618#endif
1619
1620update_policy:
1621 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1622 ap->target_lpm_policy = policy;
1623}
1624
c312ef17
DW		 1625static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1626{
1627 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1628 u16 tmp16;
1629
1630 /*
1631 * Only apply the 6-port PCS quirk for known legacy platforms.
1632 */
1633 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1634 return;
09d6ac8d
DW		 1635
1636 /* Skip applying the quirk on Denverton and beyond */
1637 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
c312ef17
DW		 1638 return;
1639
1640 /*
1641 * port_map is determined from PORTS_IMPL PCI register which is
1642 * implemented as write or write-once register. If the register
1643 * isn't programmed, ahci automatically generates it from number
1644 * of ports, which is good enough for PCS programming. It is
1645 * otherwise expected that platform firmware enables the ports
1646 * before the OS boots.
1647 */
1648 pci_read_config_word(pdev, PCS_6, &tmp16);
1649 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1650 tmp16 |= hpriv->port_map;
1651 pci_write_config_word(pdev, PCS_6, tmp16);
1652 }
1653}
1654
894fba7f
KHF		 1655static ssize_t remapped_nvme_show(struct device *dev,
1656 struct device_attribute *attr,
1657 char *buf)
1658{
1659 struct ata_host *host = dev_get_drvdata(dev);
1660 struct ahci_host_priv *hpriv = host->private_data;
1661
1662 return sprintf(buf, "%u\n", hpriv->remapped_nvme);
1663}
1664
1665static DEVICE_ATTR_RO(remapped_nvme);
1666
24dc5f33 1667static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1668{
e297d99e
TH		 1669 unsigned int board_id = ent->driver_data;
1670 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1671 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1672 struct device *dev = &pdev->dev;
1da177e4 1673 struct ahci_host_priv *hpriv;
4447d351 1674 struct ata_host *host;
c3ebd6a9 1675 int n_ports, i, rc;
318893e1 1676 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1677
1678 VPRINTK("ENTER\n");
1679
b429dd59 1680 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1681
06296a1e 1682 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1683
5b66c829
AC		 1684 /* The AHCI driver can only drive the SATA ports, the PATA driver
1685 can drive them all so if both drivers are selected make sure
1686 AHCI stays out of the way */
1687 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1688 return -ENODEV;
1689
cb85696d
JL		 1690 /* Apple BIOS on MCP89 prevents us using AHCI */
1691 if (is_mcp89_apple(pdev))
1692 ahci_mcp89_apple_enable(pdev);
c6353b45 1693
7a02267e
MN		 1694 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1695 * At the moment, we can only use the AHCI mode. Let the users know
1696 * that for SAS drives they're out of luck.
1697 */
1698 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1699 dev_info(&pdev->dev,
1700 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1701
b7ae128d 1702 /* Some devices use non-standard BARs */
318893e1
AR		 1703 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1704 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1705 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1706 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
b1314e3f
RMC		 1707 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1708 if (pdev->device == 0xa01c)
1709 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1710 if (pdev->device == 0xa084)
1711 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
e49bd683
TY		 1712 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1713 if (pdev->device == 0x7a08)
1714 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
b1314e3f 1715 }
318893e1 1716
4447d351 1717 /* acquire resources */
24dc5f33 1718 rc = pcim_enable_device(pdev);
1da177e4
LT		 1719 if (rc)
1720 return rc;
1721
c4f7792c
TH		 1722 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1723 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1724 u8 map;
1725
1726 /* ICH6s share the same PCI ID for both piix and ahci
1727 * modes. Enabling ahci mode while MAP indicates
1728 * combined mode is a bad idea. Yield to ata_piix.
1729 */
1730 pci_read_config_byte(pdev, ICH_MAP, &map);
1731 if (map & 0x3) {
a44fec1f
JP		 1732 dev_info(&pdev->dev,
1733 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1734 return -ENODEV;
1735 }
1736 }
1737
6fec8871
PB		 1738 /* AHCI controllers often implement SFF compatible interface.
1739 * Grab all PCI BARs just in case.
1740 */
1741 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1742 if (rc == -EBUSY)
1743 pcim_pin_device(pdev);
1744 if (rc)
1745 return rc;
1746
24dc5f33
TH		 1747 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1748 if (!hpriv)
1749 return -ENOMEM;
417a1a6d
TH		 1750 hpriv->flags |= (unsigned long)pi.private_data;
1751
e297d99e
TH		 1752 /* MCP65 revision A1 and A2 can't do MSI */
1753 if (board_id == board_ahci_mcp65 &&
1754 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1755 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1756
e427fe04
SH		 1757 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1758 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1759 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1760
2fcad9d2
TH		 1761 /* only some SB600s can do 64bit DMA */
1762 if (ahci_sb600_enable_64bit(pdev))
1763 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1764
318893e1 1765 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1766
aecec8b6
CH		 1767 /* detect remapped nvme devices */
1768 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1769
894fba7f
KHF		 1770 sysfs_add_file_to_group(&pdev->dev.kobj,
1771 &dev_attr_remapped_nvme.attr,
1772 NULL);
1773
0cf4a7d6
JP		 1774 /* must set flag prior to save config in order to take effect */
1775 if (ahci_broken_devslp(pdev))
1776 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1777
d243bed3 1778#ifdef CONFIG_ARM64
234e6d2c
XY		 1779 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1780 pdev->device == 0xa235 &&
1781 pdev->revision < 0x30)
1782 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1783
d243bed3
TC		 1784 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1785 hpriv->irq_handler = ahci_thunderx_irq_handler;
1786#endif
1787
4447d351 1788 /* save initial config */
394d6e53 1789 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1790
c312ef17
DW		 1791 /*
1792 * If platform firmware failed to enable ports, try to enable
1793 * them here.
1794 */
1795 ahci_intel_pcs_quirk(pdev, hpriv);
1796
4447d351 1797 /* prepare host */
453d3131
RH		 1798 if (hpriv->cap & HOST_CAP_NCQ) {
1799 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1800 /*
1801 * Auto-activate optimization is supposed to be
1802 * supported on all AHCI controllers indicating NCQ
1803 * capability, but it seems to be broken on some
1804 * chipsets including NVIDIAs.
1805 */
1806 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1807 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1808
1809 /*
1810 * All AHCI controllers should be forward-compatible
1811 * with the new auxiliary field. This code should be
1812 * conditionalized if any buggy AHCI controllers are
1813 * encountered.
1814 */
1815 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1816 }
1da177e4 1817
7d50b60b
TH		 1818 if (hpriv->cap & HOST_CAP_PMP)
1819 pi.flags |= ATA_FLAG_PMP;
1820
0cbb0e77 1821 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1822
1fd68434
RW		 1823 if (ahci_broken_system_poweroff(pdev)) {
1824 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1825 dev_info(&pdev->dev,
1826 "quirky BIOS, skipping spindown on poweroff\n");
1827 }
1828
240630e6
HG		 1829 if (ahci_broken_lpm(pdev)) {
1830 pi.flags |= ATA_FLAG_NO_LPM;
1831 dev_warn(&pdev->dev,
1832 "BIOS update required for Link Power Management support\n");
1833 }
1834
9b10ae86
TH		 1835 if (ahci_broken_suspend(pdev)) {
1836 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1837 dev_warn(&pdev->dev,
1838 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1839 }
1840
5594639a
TH		 1841 if (ahci_broken_online(pdev)) {
1842 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1843 dev_info(&pdev->dev,
1844 "online status unreliable, applying workaround\n");
1845 }
1846
8bfd1743
SC		 1847
1848 /* Acer SA5-271 workaround modifies private_data */
1849 acer_sa5_271_workaround(hpriv, pdev);
1850
837f5f8f
TH		 1851 /* CAP.NP sometimes indicate the index of the last enabled
1852 * port, at other times, that of the last possible port, so
1853 * determining the maximum port number requires looking at
1854 * both CAP.NP and port_map.
1855 */
1856 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1857
1858 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1859 if (!host)
1860 return -ENOMEM;
4447d351 1861 host->private_data = hpriv;
0b9e2988
CH		 1862
1863 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1864 /* legacy intx interrupts */
1865 pci_intx(pdev, 1);
1866 }
0ce57f8a 1867 hpriv->irq = pci_irq_vector(pdev, 0);
21bfd1aa 1868
f3d7f23f 1869 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1870 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1871 else
d2782d96 1872 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1873
18f7ba4c
KCA		 1874 if (pi.flags & ATA_FLAG_EM)
1875 ahci_reset_em(host);
1876
4447d351 1877 for (i = 0; i < host->n_ports; i++) {
dab632e8 1878 struct ata_port *ap = host->ports[i];
4447d351 1879
318893e1
AR		 1880 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1881 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1882 0x100 + ap->port_no * 0x80, "port");
1883
18f7ba4c
KCA		 1884 /* set enclosure management message type */
1885 if (ap->flags & ATA_FLAG_EM)
008dbd61 1886 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c 1887
b1a9585c 1888 ahci_update_initial_lpm_policy(ap, hpriv);
18f7ba4c 1889
dab632e8 1890 /* disabled/not-implemented port */
350756f6 1891 if (!(hpriv->port_map & (1 << i)))
dab632e8 1892 ap->ops = &ata_dummy_port_ops;
4447d351 1893 }
d447df14 1894
edc93052
TH		 1895 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1896 ahci_p5wdh_workaround(host);
1897
f80ae7e4
TH		 1898 /* apply gtf filter quirk */
1899 ahci_gtf_filter_workaround(host);
1900
4447d351
TH		 1901 /* initialize adapter */
1902 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1903 if (rc)
24dc5f33 1904 return rc;
1da177e4 1905
c312ef17 1906 rc = ahci_reset_controller(host);
4447d351
TH		 1907 if (rc)
1908 return rc;
1da177e4 1909
781d6550 1910 ahci_pci_init_controller(host);
439fcaec 1911 ahci_pci_print_info(host);
1da177e4 1912
4447d351 1913 pci_set_master(pdev);
5ca72c4f 1914
02e53293
MW		 1915 rc = ahci_host_activate(host, &ahci_sht);
1916 if (rc)
1917 return rc;
1918
1919 pm_runtime_put_noidle(&pdev->dev);
1920 return 0;
1921}
1922
10a663a1
PK		 1923static void ahci_shutdown_one(struct pci_dev *pdev)
1924{
1925 ata_pci_shutdown_one(pdev);
1926}
1927
02e53293
MW		 1928static void ahci_remove_one(struct pci_dev *pdev)
1929{
894fba7f
KHF		 1930 sysfs_remove_file_from_group(&pdev->dev.kobj,
1931 &dev_attr_remapped_nvme.attr,
1932 NULL);
02e53293
MW		 1933 pm_runtime_get_noresume(&pdev->dev);
1934 ata_pci_remove_one(pdev);
907f4678 1935}
1da177e4 1936
2fc75da0 1937module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1938
1939MODULE_AUTHOR("Jeff Garzik");
1940MODULE_DESCRIPTION("AHCI SATA low-level driver");
1941MODULE_LICENSE("GPL");
1942MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1943MODULE_VERSION(DRV_VERSION);
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