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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
87507cfd | 42 | #include <linux/dma-mapping.h> |
a9524a76 | 43 | #include <linux/device.h> |
edc93052 | 44 | #include <linux/dmi.h> |
1da177e4 | 45 | #include <scsi/scsi_host.h> |
193515d5 | 46 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 47 | #include <linux/libata.h> |
1da177e4 LT |
48 | |
49 | #define DRV_NAME "ahci" | |
7d50b60b | 50 | #define DRV_VERSION "3.0" |
1da177e4 | 51 | |
a22e6444 TH |
52 | static int ahci_skip_host_reset; |
53 | module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); | |
54 | MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); | |
55 | ||
31556594 KCA |
56 | static int ahci_enable_alpm(struct ata_port *ap, |
57 | enum link_pm policy); | |
58 | static void ahci_disable_alpm(struct ata_port *ap); | |
1da177e4 LT |
59 | |
60 | enum { | |
61 | AHCI_PCI_BAR = 5, | |
648a88be | 62 | AHCI_MAX_PORTS = 32, |
1da177e4 LT |
63 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
64 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
12fad3f9 | 65 | AHCI_MAX_CMDS = 32, |
dd410ff1 | 66 | AHCI_CMD_SZ = 32, |
12fad3f9 | 67 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
1da177e4 | 68 | AHCI_RX_FIS_SZ = 256, |
a0ea7328 | 69 | AHCI_CMD_TBL_CDB = 0x40, |
dd410ff1 TH |
70 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
71 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), | |
72 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, | |
73 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + | |
1da177e4 LT |
74 | AHCI_RX_FIS_SZ, |
75 | AHCI_IRQ_ON_SG = (1 << 31), | |
76 | AHCI_CMD_ATAPI = (1 << 5), | |
77 | AHCI_CMD_WRITE = (1 << 6), | |
4b10e559 | 78 | AHCI_CMD_PREFETCH = (1 << 7), |
22b49985 TH |
79 | AHCI_CMD_RESET = (1 << 8), |
80 | AHCI_CMD_CLR_BUSY = (1 << 10), | |
1da177e4 LT |
81 | |
82 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
0291f95f | 83 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
78cd52d0 | 84 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
1da177e4 LT |
85 | |
86 | board_ahci = 0, | |
7a234aff TH |
87 | board_ahci_vt8251 = 1, |
88 | board_ahci_ign_iferr = 2, | |
89 | board_ahci_sb600 = 3, | |
90 | board_ahci_mv = 4, | |
e39fc8c9 | 91 | board_ahci_sb700 = 5, |
e297d99e | 92 | board_ahci_mcp65 = 6, |
9a3b103c | 93 | board_ahci_nopmp = 7, |
1da177e4 LT |
94 | |
95 | /* global controller registers */ | |
96 | HOST_CAP = 0x00, /* host capabilities */ | |
97 | HOST_CTL = 0x04, /* global host control */ | |
98 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
99 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
100 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
101 | ||
102 | /* HOST_CTL bits */ | |
103 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
104 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
105 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
106 | ||
107 | /* HOST_CAP bits */ | |
0be0aa98 | 108 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
7d50b60b | 109 | HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ |
22b49985 | 110 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
31556594 | 111 | HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ |
0be0aa98 | 112 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
203ef6c4 | 113 | HOST_CAP_SNTF = (1 << 29), /* SNotification register */ |
979db803 | 114 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
dd410ff1 | 115 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
1da177e4 LT |
116 | |
117 | /* registers for each SATA port */ | |
118 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
119 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
120 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
121 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
122 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
123 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
124 | PORT_CMD = 0x18, /* port command */ | |
125 | PORT_TFDATA = 0x20, /* taskfile data */ | |
126 | PORT_SIG = 0x24, /* device TF signature */ | |
127 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
1da177e4 LT |
128 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
129 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
130 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
131 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
203ef6c4 | 132 | PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ |
1da177e4 LT |
133 | |
134 | /* PORT_IRQ_{STAT,MASK} bits */ | |
135 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
136 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
137 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
138 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
139 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
140 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
141 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
142 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
143 | ||
144 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
145 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
146 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
147 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
148 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
149 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
150 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
151 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
152 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
153 | ||
78cd52d0 TH |
154 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
155 | PORT_IRQ_IF_ERR | | |
156 | PORT_IRQ_CONNECT | | |
4296971d | 157 | PORT_IRQ_PHYRDY | |
7d50b60b TH |
158 | PORT_IRQ_UNK_FIS | |
159 | PORT_IRQ_BAD_PMP, | |
78cd52d0 TH |
160 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
161 | PORT_IRQ_TF_ERR | | |
162 | PORT_IRQ_HBUS_DATA_ERR, | |
163 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | | |
164 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | | |
165 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, | |
1da177e4 LT |
166 | |
167 | /* PORT_CMD bits */ | |
31556594 KCA |
168 | PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ |
169 | PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ | |
02eaa666 | 170 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
7d50b60b | 171 | PORT_CMD_PMP = (1 << 17), /* PMP attached */ |
1da177e4 LT |
172 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
173 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
174 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
22b49985 | 175 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
1da177e4 LT |
176 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
177 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
178 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
179 | ||
0be0aa98 | 180 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
1da177e4 LT |
181 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
182 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
183 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 | 184 | |
417a1a6d TH |
185 | /* hpriv->flags bits */ |
186 | AHCI_HFLAG_NO_NCQ = (1 << 0), | |
187 | AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ | |
188 | AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ | |
189 | AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ | |
190 | AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ | |
191 | AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ | |
6949b914 | 192 | AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ |
31556594 | 193 | AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */ |
a878539e | 194 | AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ |
e297d99e | 195 | AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ |
417a1a6d | 196 | |
bf2af2a2 | 197 | /* ap->flags bits */ |
1188c0d8 TH |
198 | |
199 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
200 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
31556594 KCA |
201 | ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | |
202 | ATA_FLAG_IPM, | |
c4f7792c TH |
203 | |
204 | ICH_MAP = 0x90, /* ICH MAP register */ | |
1da177e4 LT |
205 | }; |
206 | ||
207 | struct ahci_cmd_hdr { | |
4ca4e439 AV |
208 | __le32 opts; |
209 | __le32 status; | |
210 | __le32 tbl_addr; | |
211 | __le32 tbl_addr_hi; | |
212 | __le32 reserved[4]; | |
1da177e4 LT |
213 | }; |
214 | ||
215 | struct ahci_sg { | |
4ca4e439 AV |
216 | __le32 addr; |
217 | __le32 addr_hi; | |
218 | __le32 reserved; | |
219 | __le32 flags_size; | |
1da177e4 LT |
220 | }; |
221 | ||
222 | struct ahci_host_priv { | |
417a1a6d | 223 | unsigned int flags; /* AHCI_HFLAG_* */ |
d447df14 TH |
224 | u32 cap; /* cap to use */ |
225 | u32 port_map; /* port map to use */ | |
226 | u32 saved_cap; /* saved initial cap */ | |
227 | u32 saved_port_map; /* saved initial port_map */ | |
1da177e4 LT |
228 | }; |
229 | ||
230 | struct ahci_port_priv { | |
7d50b60b | 231 | struct ata_link *active_link; |
1da177e4 LT |
232 | struct ahci_cmd_hdr *cmd_slot; |
233 | dma_addr_t cmd_slot_dma; | |
234 | void *cmd_tbl; | |
235 | dma_addr_t cmd_tbl_dma; | |
1da177e4 LT |
236 | void *rx_fis; |
237 | dma_addr_t rx_fis_dma; | |
0291f95f | 238 | /* for NCQ spurious interrupt analysis */ |
0291f95f TH |
239 | unsigned int ncq_saw_d2h:1; |
240 | unsigned int ncq_saw_dmas:1; | |
afb2d552 | 241 | unsigned int ncq_saw_sdb:1; |
a7384925 | 242 | u32 intr_mask; /* interrupts to enable */ |
1da177e4 LT |
243 | }; |
244 | ||
da3dbb17 TH |
245 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
246 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); | |
2dcb407e | 247 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
9a3d9eb0 | 248 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
4c9bf4e7 | 249 | static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); |
1da177e4 LT |
250 | static int ahci_port_start(struct ata_port *ap); |
251 | static void ahci_port_stop(struct ata_port *ap); | |
1da177e4 | 252 | static void ahci_qc_prep(struct ata_queued_cmd *qc); |
78cd52d0 TH |
253 | static void ahci_freeze(struct ata_port *ap); |
254 | static void ahci_thaw(struct ata_port *ap); | |
7d50b60b TH |
255 | static void ahci_pmp_attach(struct ata_port *ap); |
256 | static void ahci_pmp_detach(struct ata_port *ap); | |
a1efdaba TH |
257 | static int ahci_softreset(struct ata_link *link, unsigned int *class, |
258 | unsigned long deadline); | |
bd17243a SH |
259 | static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class, |
260 | unsigned long deadline); | |
a1efdaba TH |
261 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
262 | unsigned long deadline); | |
263 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, | |
264 | unsigned long deadline); | |
265 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, | |
266 | unsigned long deadline); | |
267 | static void ahci_postreset(struct ata_link *link, unsigned int *class); | |
78cd52d0 TH |
268 | static void ahci_error_handler(struct ata_port *ap); |
269 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); | |
df69c9c5 | 270 | static int ahci_port_resume(struct ata_port *ap); |
a878539e | 271 | static void ahci_dev_config(struct ata_device *dev); |
dab632e8 JG |
272 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl); |
273 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, | |
274 | u32 opts); | |
438ac6d5 | 275 | #ifdef CONFIG_PM |
c1332875 | 276 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
c1332875 TH |
277 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
278 | static int ahci_pci_device_resume(struct pci_dev *pdev); | |
438ac6d5 | 279 | #endif |
1da177e4 | 280 | |
ee959b00 TJ |
281 | static struct device_attribute *ahci_shost_attrs[] = { |
282 | &dev_attr_link_power_management_policy, | |
31556594 KCA |
283 | NULL |
284 | }; | |
285 | ||
193515d5 | 286 | static struct scsi_host_template ahci_sht = { |
68d1d07b | 287 | ATA_NCQ_SHT(DRV_NAME), |
12fad3f9 | 288 | .can_queue = AHCI_MAX_CMDS - 1, |
1da177e4 | 289 | .sg_tablesize = AHCI_MAX_SG, |
1da177e4 | 290 | .dma_boundary = AHCI_DMA_BOUNDARY, |
31556594 | 291 | .shost_attrs = ahci_shost_attrs, |
1da177e4 LT |
292 | }; |
293 | ||
029cfd6b TH |
294 | static struct ata_port_operations ahci_ops = { |
295 | .inherits = &sata_pmp_port_ops, | |
296 | ||
7d50b60b | 297 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
1da177e4 LT |
298 | .qc_prep = ahci_qc_prep, |
299 | .qc_issue = ahci_qc_issue, | |
4c9bf4e7 | 300 | .qc_fill_rtf = ahci_qc_fill_rtf, |
1da177e4 | 301 | |
78cd52d0 TH |
302 | .freeze = ahci_freeze, |
303 | .thaw = ahci_thaw, | |
a1efdaba TH |
304 | .softreset = ahci_softreset, |
305 | .hardreset = ahci_hardreset, | |
306 | .postreset = ahci_postreset, | |
071f44b1 | 307 | .pmp_softreset = ahci_softreset, |
78cd52d0 TH |
308 | .error_handler = ahci_error_handler, |
309 | .post_internal_cmd = ahci_post_internal_cmd, | |
6bd99b4e TH |
310 | .dev_config = ahci_dev_config, |
311 | ||
ad616ffb TH |
312 | .scr_read = ahci_scr_read, |
313 | .scr_write = ahci_scr_write, | |
7d50b60b TH |
314 | .pmp_attach = ahci_pmp_attach, |
315 | .pmp_detach = ahci_pmp_detach, | |
7d50b60b | 316 | |
029cfd6b TH |
317 | .enable_pm = ahci_enable_alpm, |
318 | .disable_pm = ahci_disable_alpm, | |
438ac6d5 | 319 | #ifdef CONFIG_PM |
ad616ffb TH |
320 | .port_suspend = ahci_port_suspend, |
321 | .port_resume = ahci_port_resume, | |
438ac6d5 | 322 | #endif |
ad616ffb TH |
323 | .port_start = ahci_port_start, |
324 | .port_stop = ahci_port_stop, | |
325 | }; | |
326 | ||
029cfd6b TH |
327 | static struct ata_port_operations ahci_vt8251_ops = { |
328 | .inherits = &ahci_ops, | |
a1efdaba | 329 | .hardreset = ahci_vt8251_hardreset, |
029cfd6b | 330 | }; |
edc93052 | 331 | |
029cfd6b TH |
332 | static struct ata_port_operations ahci_p5wdh_ops = { |
333 | .inherits = &ahci_ops, | |
a1efdaba | 334 | .hardreset = ahci_p5wdh_hardreset, |
edc93052 TH |
335 | }; |
336 | ||
bd17243a SH |
337 | static struct ata_port_operations ahci_sb600_ops = { |
338 | .inherits = &ahci_ops, | |
339 | .softreset = ahci_sb600_softreset, | |
340 | .pmp_softreset = ahci_sb600_softreset, | |
341 | }; | |
342 | ||
417a1a6d TH |
343 | #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) |
344 | ||
98ac62de | 345 | static const struct ata_port_info ahci_port_info[] = { |
1da177e4 LT |
346 | /* board_ahci */ |
347 | { | |
1188c0d8 | 348 | .flags = AHCI_FLAG_COMMON, |
7da79312 | 349 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 350 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
351 | .port_ops = &ahci_ops, |
352 | }, | |
bf2af2a2 BJ |
353 | /* board_ahci_vt8251 */ |
354 | { | |
6949b914 | 355 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
417a1a6d | 356 | .flags = AHCI_FLAG_COMMON, |
bf2af2a2 | 357 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 358 | .udma_mask = ATA_UDMA6, |
ad616ffb | 359 | .port_ops = &ahci_vt8251_ops, |
bf2af2a2 | 360 | }, |
41669553 TH |
361 | /* board_ahci_ign_iferr */ |
362 | { | |
417a1a6d TH |
363 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
364 | .flags = AHCI_FLAG_COMMON, | |
41669553 | 365 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 366 | .udma_mask = ATA_UDMA6, |
41669553 TH |
367 | .port_ops = &ahci_ops, |
368 | }, | |
55a61604 CH |
369 | /* board_ahci_sb600 */ |
370 | { | |
417a1a6d | 371 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
22b5e7a7 | 372 | AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI | |
bd17243a | 373 | AHCI_HFLAG_SECT255), |
417a1a6d | 374 | .flags = AHCI_FLAG_COMMON, |
55a61604 | 375 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 376 | .udma_mask = ATA_UDMA6, |
bd17243a | 377 | .port_ops = &ahci_sb600_ops, |
55a61604 | 378 | }, |
cd70c266 JG |
379 | /* board_ahci_mv */ |
380 | { | |
417a1a6d TH |
381 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
382 | AHCI_HFLAG_MV_PATA), | |
cd70c266 | 383 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
417a1a6d | 384 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, |
cd70c266 JG |
385 | .pio_mask = 0x1f, /* pio0-4 */ |
386 | .udma_mask = ATA_UDMA6, | |
387 | .port_ops = &ahci_ops, | |
388 | }, | |
e39fc8c9 SH |
389 | /* board_ahci_sb700 */ |
390 | { | |
bd17243a | 391 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), |
e39fc8c9 | 392 | .flags = AHCI_FLAG_COMMON, |
e39fc8c9 SH |
393 | .pio_mask = 0x1f, /* pio0-4 */ |
394 | .udma_mask = ATA_UDMA6, | |
bd17243a | 395 | .port_ops = &ahci_sb600_ops, |
e39fc8c9 | 396 | }, |
e297d99e TH |
397 | /* board_ahci_mcp65 */ |
398 | { | |
399 | AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ), | |
400 | .flags = AHCI_FLAG_COMMON, | |
401 | .pio_mask = 0x1f, /* pio0-4 */ | |
402 | .udma_mask = ATA_UDMA6, | |
403 | .port_ops = &ahci_ops, | |
404 | }, | |
9a3b103c TH |
405 | /* board_ahci_nopmp */ |
406 | { | |
407 | AHCI_HFLAGS (AHCI_HFLAG_NO_PMP), | |
408 | .flags = AHCI_FLAG_COMMON, | |
409 | .pio_mask = 0x1f, /* pio0-4 */ | |
410 | .udma_mask = ATA_UDMA6, | |
411 | .port_ops = &ahci_ops, | |
412 | }, | |
1da177e4 LT |
413 | }; |
414 | ||
3b7d697d | 415 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 416 | /* Intel */ |
54bb3a94 JG |
417 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
418 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
419 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
420 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
421 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 422 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
423 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
424 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
425 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
426 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
7a234aff TH |
427 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
428 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */ | |
429 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ | |
430 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ | |
431 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ | |
432 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ | |
433 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ | |
434 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ | |
435 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ | |
436 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ | |
437 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ | |
438 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ | |
439 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ | |
440 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ | |
441 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ | |
442 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ | |
443 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ | |
d4155e6f JG |
444 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
445 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ | |
16ad1ad9 JG |
446 | { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ |
447 | { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ | |
fe7fa31a | 448 | |
e34bb370 TH |
449 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
450 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
451 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
fe7fa31a JG |
452 | |
453 | /* ATI */ | |
c65ec1c2 | 454 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
e39fc8c9 SH |
455 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ |
456 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ | |
457 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ | |
458 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ | |
459 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ | |
460 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ | |
fe7fa31a JG |
461 | |
462 | /* VIA */ | |
54bb3a94 | 463 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
bf335542 | 464 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
465 | |
466 | /* NVIDIA */ | |
e297d99e TH |
467 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ |
468 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ | |
469 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ | |
470 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ | |
471 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ | |
472 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ | |
473 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ | |
474 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ | |
6fbf5ba4 PC |
475 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ |
476 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ | |
477 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ | |
478 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ | |
895663cd PC |
479 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
480 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ | |
481 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ | |
482 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ | |
483 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ | |
484 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ | |
485 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ | |
486 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ | |
0522b286 PC |
487 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */ |
488 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */ | |
489 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */ | |
490 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */ | |
491 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */ | |
492 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */ | |
493 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */ | |
494 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */ | |
495 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */ | |
496 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */ | |
497 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */ | |
498 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */ | |
499 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ | |
500 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ | |
501 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ | |
502 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ | |
503 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ | |
504 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ | |
505 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ | |
506 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ | |
507 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ | |
508 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ | |
509 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ | |
510 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ | |
6ba86958 | 511 | { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */ |
512 | { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */ | |
513 | { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */ | |
514 | { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */ | |
7100819f PC |
515 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */ |
516 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */ | |
517 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */ | |
518 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */ | |
519 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */ | |
520 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ | |
521 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ | |
522 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ | |
70d562cf | 523 | { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */ |
524 | { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */ | |
525 | { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */ | |
526 | { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */ | |
527 | { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */ | |
528 | { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */ | |
529 | { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */ | |
530 | { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */ | |
3072c379 | 531 | { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */ |
532 | { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */ | |
533 | { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */ | |
534 | { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */ | |
fe7fa31a | 535 | |
95916edd | 536 | /* SiS */ |
9a3b103c TH |
537 | { PCI_VDEVICE(SI, 0x1184), board_ahci_nopmp }, /* SiS 966 */ |
538 | { PCI_VDEVICE(SI, 0x1185), board_ahci_nopmp }, /* SiS 968 */ | |
539 | { PCI_VDEVICE(SI, 0x0186), board_ahci_nopmp }, /* SiS 968 */ | |
95916edd | 540 | |
cd70c266 JG |
541 | /* Marvell */ |
542 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ | |
c40e7cb8 | 543 | { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ |
cd70c266 | 544 | |
415ae2b5 JG |
545 | /* Generic, PCI class code for AHCI */ |
546 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 547 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 548 | |
1da177e4 LT |
549 | { } /* terminate list */ |
550 | }; | |
551 | ||
552 | ||
553 | static struct pci_driver ahci_pci_driver = { | |
554 | .name = DRV_NAME, | |
555 | .id_table = ahci_pci_tbl, | |
556 | .probe = ahci_init_one, | |
24dc5f33 | 557 | .remove = ata_pci_remove_one, |
438ac6d5 | 558 | #ifdef CONFIG_PM |
c1332875 TH |
559 | .suspend = ahci_pci_device_suspend, |
560 | .resume = ahci_pci_device_resume, | |
438ac6d5 | 561 | #endif |
1da177e4 LT |
562 | }; |
563 | ||
564 | ||
98fa4b60 TH |
565 | static inline int ahci_nr_ports(u32 cap) |
566 | { | |
567 | return (cap & 0x1f) + 1; | |
568 | } | |
569 | ||
dab632e8 JG |
570 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
571 | unsigned int port_no) | |
1da177e4 | 572 | { |
dab632e8 | 573 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
4447d351 | 574 | |
dab632e8 JG |
575 | return mmio + 0x100 + (port_no * 0x80); |
576 | } | |
577 | ||
578 | static inline void __iomem *ahci_port_base(struct ata_port *ap) | |
579 | { | |
580 | return __ahci_port_base(ap->host, ap->port_no); | |
1da177e4 LT |
581 | } |
582 | ||
b710a1f4 TH |
583 | static void ahci_enable_ahci(void __iomem *mmio) |
584 | { | |
15fe982e | 585 | int i; |
b710a1f4 TH |
586 | u32 tmp; |
587 | ||
588 | /* turn on AHCI_EN */ | |
589 | tmp = readl(mmio + HOST_CTL); | |
15fe982e TH |
590 | if (tmp & HOST_AHCI_EN) |
591 | return; | |
592 | ||
593 | /* Some controllers need AHCI_EN to be written multiple times. | |
594 | * Try a few times before giving up. | |
595 | */ | |
596 | for (i = 0; i < 5; i++) { | |
b710a1f4 TH |
597 | tmp |= HOST_AHCI_EN; |
598 | writel(tmp, mmio + HOST_CTL); | |
599 | tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ | |
15fe982e TH |
600 | if (tmp & HOST_AHCI_EN) |
601 | return; | |
602 | msleep(10); | |
b710a1f4 | 603 | } |
15fe982e TH |
604 | |
605 | WARN_ON(1); | |
b710a1f4 TH |
606 | } |
607 | ||
d447df14 TH |
608 | /** |
609 | * ahci_save_initial_config - Save and fixup initial config values | |
4447d351 | 610 | * @pdev: target PCI device |
4447d351 | 611 | * @hpriv: host private area to store config values |
d447df14 TH |
612 | * |
613 | * Some registers containing configuration info might be setup by | |
614 | * BIOS and might be cleared on reset. This function saves the | |
615 | * initial values of those registers into @hpriv such that they | |
616 | * can be restored after controller reset. | |
617 | * | |
618 | * If inconsistent, config values are fixed up by this function. | |
619 | * | |
620 | * LOCKING: | |
621 | * None. | |
622 | */ | |
4447d351 | 623 | static void ahci_save_initial_config(struct pci_dev *pdev, |
4447d351 | 624 | struct ahci_host_priv *hpriv) |
d447df14 | 625 | { |
4447d351 | 626 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
d447df14 | 627 | u32 cap, port_map; |
17199b18 | 628 | int i; |
c40e7cb8 | 629 | int mv; |
d447df14 | 630 | |
b710a1f4 TH |
631 | /* make sure AHCI mode is enabled before accessing CAP */ |
632 | ahci_enable_ahci(mmio); | |
633 | ||
d447df14 TH |
634 | /* Values prefixed with saved_ are written back to host after |
635 | * reset. Values without are used for driver operation. | |
636 | */ | |
637 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); | |
638 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); | |
639 | ||
274c1fde | 640 | /* some chips have errata preventing 64bit use */ |
417a1a6d | 641 | if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { |
c7a42156 TH |
642 | dev_printk(KERN_INFO, &pdev->dev, |
643 | "controller can't do 64bit DMA, forcing 32bit\n"); | |
644 | cap &= ~HOST_CAP_64; | |
645 | } | |
646 | ||
417a1a6d | 647 | if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { |
274c1fde TH |
648 | dev_printk(KERN_INFO, &pdev->dev, |
649 | "controller can't do NCQ, turning off CAP_NCQ\n"); | |
650 | cap &= ~HOST_CAP_NCQ; | |
651 | } | |
652 | ||
e297d99e TH |
653 | if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { |
654 | dev_printk(KERN_INFO, &pdev->dev, | |
655 | "controller can do NCQ, turning on CAP_NCQ\n"); | |
656 | cap |= HOST_CAP_NCQ; | |
657 | } | |
658 | ||
258cd846 | 659 | if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { |
6949b914 TH |
660 | dev_printk(KERN_INFO, &pdev->dev, |
661 | "controller can't do PMP, turning off CAP_PMP\n"); | |
662 | cap &= ~HOST_CAP_PMP; | |
663 | } | |
664 | ||
d799e083 TH |
665 | if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 && |
666 | port_map != 1) { | |
667 | dev_printk(KERN_INFO, &pdev->dev, | |
668 | "JMB361 has only one port, port_map 0x%x -> 0x%x\n", | |
669 | port_map, 1); | |
670 | port_map = 1; | |
671 | } | |
672 | ||
cd70c266 JG |
673 | /* |
674 | * Temporary Marvell 6145 hack: PATA port presence | |
675 | * is asserted through the standard AHCI port | |
676 | * presence register, as bit 4 (counting from 0) | |
677 | */ | |
417a1a6d | 678 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
c40e7cb8 JAR |
679 | if (pdev->device == 0x6121) |
680 | mv = 0x3; | |
681 | else | |
682 | mv = 0xf; | |
cd70c266 JG |
683 | dev_printk(KERN_ERR, &pdev->dev, |
684 | "MV_AHCI HACK: port_map %x -> %x\n", | |
c40e7cb8 JAR |
685 | port_map, |
686 | port_map & mv); | |
cd70c266 | 687 | |
c40e7cb8 | 688 | port_map &= mv; |
cd70c266 JG |
689 | } |
690 | ||
17199b18 | 691 | /* cross check port_map and cap.n_ports */ |
7a234aff | 692 | if (port_map) { |
837f5f8f | 693 | int map_ports = 0; |
17199b18 | 694 | |
837f5f8f TH |
695 | for (i = 0; i < AHCI_MAX_PORTS; i++) |
696 | if (port_map & (1 << i)) | |
697 | map_ports++; | |
17199b18 | 698 | |
837f5f8f TH |
699 | /* If PI has more ports than n_ports, whine, clear |
700 | * port_map and let it be generated from n_ports. | |
17199b18 | 701 | */ |
837f5f8f | 702 | if (map_ports > ahci_nr_ports(cap)) { |
4447d351 | 703 | dev_printk(KERN_WARNING, &pdev->dev, |
837f5f8f TH |
704 | "implemented port map (0x%x) contains more " |
705 | "ports than nr_ports (%u), using nr_ports\n", | |
706 | port_map, ahci_nr_ports(cap)); | |
7a234aff TH |
707 | port_map = 0; |
708 | } | |
709 | } | |
710 | ||
711 | /* fabricate port_map from cap.nr_ports */ | |
712 | if (!port_map) { | |
17199b18 | 713 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
7a234aff TH |
714 | dev_printk(KERN_WARNING, &pdev->dev, |
715 | "forcing PORTS_IMPL to 0x%x\n", port_map); | |
716 | ||
717 | /* write the fixed up value to the PI register */ | |
718 | hpriv->saved_port_map = port_map; | |
17199b18 TH |
719 | } |
720 | ||
d447df14 TH |
721 | /* record values to use during operation */ |
722 | hpriv->cap = cap; | |
723 | hpriv->port_map = port_map; | |
724 | } | |
725 | ||
726 | /** | |
727 | * ahci_restore_initial_config - Restore initial config | |
4447d351 | 728 | * @host: target ATA host |
d447df14 TH |
729 | * |
730 | * Restore initial config stored by ahci_save_initial_config(). | |
731 | * | |
732 | * LOCKING: | |
733 | * None. | |
734 | */ | |
4447d351 | 735 | static void ahci_restore_initial_config(struct ata_host *host) |
d447df14 | 736 | { |
4447d351 TH |
737 | struct ahci_host_priv *hpriv = host->private_data; |
738 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
739 | ||
d447df14 TH |
740 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
741 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); | |
742 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | |
743 | } | |
744 | ||
203ef6c4 | 745 | static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) |
1da177e4 | 746 | { |
203ef6c4 TH |
747 | static const int offset[] = { |
748 | [SCR_STATUS] = PORT_SCR_STAT, | |
749 | [SCR_CONTROL] = PORT_SCR_CTL, | |
750 | [SCR_ERROR] = PORT_SCR_ERR, | |
751 | [SCR_ACTIVE] = PORT_SCR_ACT, | |
752 | [SCR_NOTIFICATION] = PORT_SCR_NTF, | |
753 | }; | |
754 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1da177e4 | 755 | |
203ef6c4 TH |
756 | if (sc_reg < ARRAY_SIZE(offset) && |
757 | (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) | |
758 | return offset[sc_reg]; | |
da3dbb17 | 759 | return 0; |
1da177e4 LT |
760 | } |
761 | ||
203ef6c4 | 762 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 | 763 | { |
203ef6c4 TH |
764 | void __iomem *port_mmio = ahci_port_base(ap); |
765 | int offset = ahci_scr_offset(ap, sc_reg); | |
766 | ||
767 | if (offset) { | |
768 | *val = readl(port_mmio + offset); | |
769 | return 0; | |
1da177e4 | 770 | } |
203ef6c4 TH |
771 | return -EINVAL; |
772 | } | |
1da177e4 | 773 | |
203ef6c4 TH |
774 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
775 | { | |
776 | void __iomem *port_mmio = ahci_port_base(ap); | |
777 | int offset = ahci_scr_offset(ap, sc_reg); | |
778 | ||
779 | if (offset) { | |
780 | writel(val, port_mmio + offset); | |
781 | return 0; | |
782 | } | |
783 | return -EINVAL; | |
1da177e4 LT |
784 | } |
785 | ||
4447d351 | 786 | static void ahci_start_engine(struct ata_port *ap) |
7c76d1e8 | 787 | { |
4447d351 | 788 | void __iomem *port_mmio = ahci_port_base(ap); |
7c76d1e8 TH |
789 | u32 tmp; |
790 | ||
d8fcd116 | 791 | /* start DMA */ |
9f592056 | 792 | tmp = readl(port_mmio + PORT_CMD); |
7c76d1e8 TH |
793 | tmp |= PORT_CMD_START; |
794 | writel(tmp, port_mmio + PORT_CMD); | |
795 | readl(port_mmio + PORT_CMD); /* flush */ | |
796 | } | |
797 | ||
4447d351 | 798 | static int ahci_stop_engine(struct ata_port *ap) |
254950cd | 799 | { |
4447d351 | 800 | void __iomem *port_mmio = ahci_port_base(ap); |
254950cd TH |
801 | u32 tmp; |
802 | ||
803 | tmp = readl(port_mmio + PORT_CMD); | |
804 | ||
d8fcd116 | 805 | /* check if the HBA is idle */ |
254950cd TH |
806 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
807 | return 0; | |
808 | ||
d8fcd116 | 809 | /* setting HBA to idle */ |
254950cd TH |
810 | tmp &= ~PORT_CMD_START; |
811 | writel(tmp, port_mmio + PORT_CMD); | |
812 | ||
d8fcd116 | 813 | /* wait for engine to stop. This could be as long as 500 msec */ |
254950cd | 814 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
2dcb407e | 815 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); |
d8fcd116 | 816 | if (tmp & PORT_CMD_LIST_ON) |
254950cd TH |
817 | return -EIO; |
818 | ||
819 | return 0; | |
820 | } | |
821 | ||
4447d351 | 822 | static void ahci_start_fis_rx(struct ata_port *ap) |
0be0aa98 | 823 | { |
4447d351 TH |
824 | void __iomem *port_mmio = ahci_port_base(ap); |
825 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
826 | struct ahci_port_priv *pp = ap->private_data; | |
0be0aa98 TH |
827 | u32 tmp; |
828 | ||
829 | /* set FIS registers */ | |
4447d351 TH |
830 | if (hpriv->cap & HOST_CAP_64) |
831 | writel((pp->cmd_slot_dma >> 16) >> 16, | |
832 | port_mmio + PORT_LST_ADDR_HI); | |
833 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
0be0aa98 | 834 | |
4447d351 TH |
835 | if (hpriv->cap & HOST_CAP_64) |
836 | writel((pp->rx_fis_dma >> 16) >> 16, | |
837 | port_mmio + PORT_FIS_ADDR_HI); | |
838 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
0be0aa98 TH |
839 | |
840 | /* enable FIS reception */ | |
841 | tmp = readl(port_mmio + PORT_CMD); | |
842 | tmp |= PORT_CMD_FIS_RX; | |
843 | writel(tmp, port_mmio + PORT_CMD); | |
844 | ||
845 | /* flush */ | |
846 | readl(port_mmio + PORT_CMD); | |
847 | } | |
848 | ||
4447d351 | 849 | static int ahci_stop_fis_rx(struct ata_port *ap) |
0be0aa98 | 850 | { |
4447d351 | 851 | void __iomem *port_mmio = ahci_port_base(ap); |
0be0aa98 TH |
852 | u32 tmp; |
853 | ||
854 | /* disable FIS reception */ | |
855 | tmp = readl(port_mmio + PORT_CMD); | |
856 | tmp &= ~PORT_CMD_FIS_RX; | |
857 | writel(tmp, port_mmio + PORT_CMD); | |
858 | ||
859 | /* wait for completion, spec says 500ms, give it 1000 */ | |
860 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, | |
861 | PORT_CMD_FIS_ON, 10, 1000); | |
862 | if (tmp & PORT_CMD_FIS_ON) | |
863 | return -EBUSY; | |
864 | ||
865 | return 0; | |
866 | } | |
867 | ||
4447d351 | 868 | static void ahci_power_up(struct ata_port *ap) |
0be0aa98 | 869 | { |
4447d351 TH |
870 | struct ahci_host_priv *hpriv = ap->host->private_data; |
871 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
872 | u32 cmd; |
873 | ||
874 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
875 | ||
876 | /* spin up device */ | |
4447d351 | 877 | if (hpriv->cap & HOST_CAP_SSS) { |
0be0aa98 TH |
878 | cmd |= PORT_CMD_SPIN_UP; |
879 | writel(cmd, port_mmio + PORT_CMD); | |
880 | } | |
881 | ||
882 | /* wake up link */ | |
883 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); | |
884 | } | |
885 | ||
31556594 KCA |
886 | static void ahci_disable_alpm(struct ata_port *ap) |
887 | { | |
888 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
889 | void __iomem *port_mmio = ahci_port_base(ap); | |
890 | u32 cmd; | |
891 | struct ahci_port_priv *pp = ap->private_data; | |
892 | ||
893 | /* IPM bits should be disabled by libata-core */ | |
894 | /* get the existing command bits */ | |
895 | cmd = readl(port_mmio + PORT_CMD); | |
896 | ||
897 | /* disable ALPM and ASP */ | |
898 | cmd &= ~PORT_CMD_ASP; | |
899 | cmd &= ~PORT_CMD_ALPE; | |
900 | ||
901 | /* force the interface back to active */ | |
902 | cmd |= PORT_CMD_ICC_ACTIVE; | |
903 | ||
904 | /* write out new cmd value */ | |
905 | writel(cmd, port_mmio + PORT_CMD); | |
906 | cmd = readl(port_mmio + PORT_CMD); | |
907 | ||
908 | /* wait 10ms to be sure we've come out of any low power state */ | |
909 | msleep(10); | |
910 | ||
911 | /* clear out any PhyRdy stuff from interrupt status */ | |
912 | writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT); | |
913 | ||
914 | /* go ahead and clean out PhyRdy Change from Serror too */ | |
915 | ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18))); | |
916 | ||
917 | /* | |
918 | * Clear flag to indicate that we should ignore all PhyRdy | |
919 | * state changes | |
920 | */ | |
921 | hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG; | |
922 | ||
923 | /* | |
924 | * Enable interrupts on Phy Ready. | |
925 | */ | |
926 | pp->intr_mask |= PORT_IRQ_PHYRDY; | |
927 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
928 | ||
929 | /* | |
930 | * don't change the link pm policy - we can be called | |
931 | * just to turn of link pm temporarily | |
932 | */ | |
933 | } | |
934 | ||
935 | static int ahci_enable_alpm(struct ata_port *ap, | |
936 | enum link_pm policy) | |
937 | { | |
938 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
939 | void __iomem *port_mmio = ahci_port_base(ap); | |
940 | u32 cmd; | |
941 | struct ahci_port_priv *pp = ap->private_data; | |
942 | u32 asp; | |
943 | ||
944 | /* Make sure the host is capable of link power management */ | |
945 | if (!(hpriv->cap & HOST_CAP_ALPM)) | |
946 | return -EINVAL; | |
947 | ||
948 | switch (policy) { | |
949 | case MAX_PERFORMANCE: | |
950 | case NOT_AVAILABLE: | |
951 | /* | |
952 | * if we came here with NOT_AVAILABLE, | |
953 | * it just means this is the first time we | |
954 | * have tried to enable - default to max performance, | |
955 | * and let the user go to lower power modes on request. | |
956 | */ | |
957 | ahci_disable_alpm(ap); | |
958 | return 0; | |
959 | case MIN_POWER: | |
960 | /* configure HBA to enter SLUMBER */ | |
961 | asp = PORT_CMD_ASP; | |
962 | break; | |
963 | case MEDIUM_POWER: | |
964 | /* configure HBA to enter PARTIAL */ | |
965 | asp = 0; | |
966 | break; | |
967 | default: | |
968 | return -EINVAL; | |
969 | } | |
970 | ||
971 | /* | |
972 | * Disable interrupts on Phy Ready. This keeps us from | |
973 | * getting woken up due to spurious phy ready interrupts | |
974 | * TBD - Hot plug should be done via polling now, is | |
975 | * that even supported? | |
976 | */ | |
977 | pp->intr_mask &= ~PORT_IRQ_PHYRDY; | |
978 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
979 | ||
980 | /* | |
981 | * Set a flag to indicate that we should ignore all PhyRdy | |
982 | * state changes since these can happen now whenever we | |
983 | * change link state | |
984 | */ | |
985 | hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG; | |
986 | ||
987 | /* get the existing command bits */ | |
988 | cmd = readl(port_mmio + PORT_CMD); | |
989 | ||
990 | /* | |
991 | * Set ASP based on Policy | |
992 | */ | |
993 | cmd |= asp; | |
994 | ||
995 | /* | |
996 | * Setting this bit will instruct the HBA to aggressively | |
997 | * enter a lower power link state when it's appropriate and | |
998 | * based on the value set above for ASP | |
999 | */ | |
1000 | cmd |= PORT_CMD_ALPE; | |
1001 | ||
1002 | /* write out new cmd value */ | |
1003 | writel(cmd, port_mmio + PORT_CMD); | |
1004 | cmd = readl(port_mmio + PORT_CMD); | |
1005 | ||
1006 | /* IPM bits should be set by libata-core */ | |
1007 | return 0; | |
1008 | } | |
1009 | ||
438ac6d5 | 1010 | #ifdef CONFIG_PM |
4447d351 | 1011 | static void ahci_power_down(struct ata_port *ap) |
0be0aa98 | 1012 | { |
4447d351 TH |
1013 | struct ahci_host_priv *hpriv = ap->host->private_data; |
1014 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
1015 | u32 cmd, scontrol; |
1016 | ||
4447d351 | 1017 | if (!(hpriv->cap & HOST_CAP_SSS)) |
07c53dac | 1018 | return; |
0be0aa98 | 1019 | |
07c53dac TH |
1020 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
1021 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
1022 | scontrol &= ~0xf; | |
1023 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
0be0aa98 | 1024 | |
07c53dac TH |
1025 | /* then set PxCMD.SUD to 0 */ |
1026 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
1027 | cmd &= ~PORT_CMD_SPIN_UP; | |
1028 | writel(cmd, port_mmio + PORT_CMD); | |
0be0aa98 | 1029 | } |
438ac6d5 | 1030 | #endif |
0be0aa98 | 1031 | |
df69c9c5 | 1032 | static void ahci_start_port(struct ata_port *ap) |
0be0aa98 | 1033 | { |
0be0aa98 | 1034 | /* enable FIS reception */ |
4447d351 | 1035 | ahci_start_fis_rx(ap); |
0be0aa98 TH |
1036 | |
1037 | /* enable DMA */ | |
4447d351 | 1038 | ahci_start_engine(ap); |
0be0aa98 TH |
1039 | } |
1040 | ||
4447d351 | 1041 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
0be0aa98 TH |
1042 | { |
1043 | int rc; | |
1044 | ||
1045 | /* disable DMA */ | |
4447d351 | 1046 | rc = ahci_stop_engine(ap); |
0be0aa98 TH |
1047 | if (rc) { |
1048 | *emsg = "failed to stop engine"; | |
1049 | return rc; | |
1050 | } | |
1051 | ||
1052 | /* disable FIS reception */ | |
4447d351 | 1053 | rc = ahci_stop_fis_rx(ap); |
0be0aa98 TH |
1054 | if (rc) { |
1055 | *emsg = "failed stop FIS RX"; | |
1056 | return rc; | |
1057 | } | |
1058 | ||
0be0aa98 TH |
1059 | return 0; |
1060 | } | |
1061 | ||
4447d351 | 1062 | static int ahci_reset_controller(struct ata_host *host) |
d91542c1 | 1063 | { |
4447d351 | 1064 | struct pci_dev *pdev = to_pci_dev(host->dev); |
49f29090 | 1065 | struct ahci_host_priv *hpriv = host->private_data; |
4447d351 | 1066 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
d447df14 | 1067 | u32 tmp; |
d91542c1 | 1068 | |
3cc3eb11 JG |
1069 | /* we must be in AHCI mode, before using anything |
1070 | * AHCI-specific, such as HOST_RESET. | |
1071 | */ | |
b710a1f4 | 1072 | ahci_enable_ahci(mmio); |
3cc3eb11 JG |
1073 | |
1074 | /* global controller reset */ | |
a22e6444 TH |
1075 | if (!ahci_skip_host_reset) { |
1076 | tmp = readl(mmio + HOST_CTL); | |
1077 | if ((tmp & HOST_RESET) == 0) { | |
1078 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
1079 | readl(mmio + HOST_CTL); /* flush */ | |
1080 | } | |
d91542c1 | 1081 | |
a22e6444 TH |
1082 | /* reset must complete within 1 second, or |
1083 | * the hardware should be considered fried. | |
1084 | */ | |
1085 | ssleep(1); | |
d91542c1 | 1086 | |
a22e6444 TH |
1087 | tmp = readl(mmio + HOST_CTL); |
1088 | if (tmp & HOST_RESET) { | |
1089 | dev_printk(KERN_ERR, host->dev, | |
1090 | "controller reset failed (0x%x)\n", tmp); | |
1091 | return -EIO; | |
1092 | } | |
d91542c1 | 1093 | |
a22e6444 TH |
1094 | /* turn on AHCI mode */ |
1095 | ahci_enable_ahci(mmio); | |
98fa4b60 | 1096 | |
a22e6444 TH |
1097 | /* Some registers might be cleared on reset. Restore |
1098 | * initial values. | |
1099 | */ | |
1100 | ahci_restore_initial_config(host); | |
1101 | } else | |
1102 | dev_printk(KERN_INFO, host->dev, | |
1103 | "skipping global host reset\n"); | |
d91542c1 TH |
1104 | |
1105 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { | |
1106 | u16 tmp16; | |
1107 | ||
1108 | /* configure PCS */ | |
1109 | pci_read_config_word(pdev, 0x92, &tmp16); | |
49f29090 TH |
1110 | if ((tmp16 & hpriv->port_map) != hpriv->port_map) { |
1111 | tmp16 |= hpriv->port_map; | |
1112 | pci_write_config_word(pdev, 0x92, tmp16); | |
1113 | } | |
d91542c1 TH |
1114 | } |
1115 | ||
1116 | return 0; | |
1117 | } | |
1118 | ||
2bcd866b JG |
1119 | static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, |
1120 | int port_no, void __iomem *mmio, | |
1121 | void __iomem *port_mmio) | |
1122 | { | |
1123 | const char *emsg = NULL; | |
1124 | int rc; | |
1125 | u32 tmp; | |
1126 | ||
1127 | /* make sure port is not active */ | |
1128 | rc = ahci_deinit_port(ap, &emsg); | |
1129 | if (rc) | |
1130 | dev_printk(KERN_WARNING, &pdev->dev, | |
1131 | "%s (%d)\n", emsg, rc); | |
1132 | ||
1133 | /* clear SError */ | |
1134 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
1135 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
1136 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
1137 | ||
1138 | /* clear port IRQ */ | |
1139 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1140 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1141 | if (tmp) | |
1142 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1143 | ||
1144 | writel(1 << port_no, mmio + HOST_IRQ_STAT); | |
1145 | } | |
1146 | ||
4447d351 | 1147 | static void ahci_init_controller(struct ata_host *host) |
d91542c1 | 1148 | { |
417a1a6d | 1149 | struct ahci_host_priv *hpriv = host->private_data; |
4447d351 TH |
1150 | struct pci_dev *pdev = to_pci_dev(host->dev); |
1151 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
2bcd866b | 1152 | int i; |
cd70c266 | 1153 | void __iomem *port_mmio; |
d91542c1 | 1154 | u32 tmp; |
c40e7cb8 | 1155 | int mv; |
d91542c1 | 1156 | |
417a1a6d | 1157 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
c40e7cb8 JAR |
1158 | if (pdev->device == 0x6121) |
1159 | mv = 2; | |
1160 | else | |
1161 | mv = 4; | |
1162 | port_mmio = __ahci_port_base(host, mv); | |
cd70c266 JG |
1163 | |
1164 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1165 | ||
1166 | /* clear port IRQ */ | |
1167 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1168 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1169 | if (tmp) | |
1170 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1171 | } | |
1172 | ||
4447d351 TH |
1173 | for (i = 0; i < host->n_ports; i++) { |
1174 | struct ata_port *ap = host->ports[i]; | |
d91542c1 | 1175 | |
cd70c266 | 1176 | port_mmio = ahci_port_base(ap); |
4447d351 | 1177 | if (ata_port_is_dummy(ap)) |
d91542c1 | 1178 | continue; |
d91542c1 | 1179 | |
2bcd866b | 1180 | ahci_port_init(pdev, ap, i, mmio, port_mmio); |
d91542c1 TH |
1181 | } |
1182 | ||
1183 | tmp = readl(mmio + HOST_CTL); | |
1184 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1185 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
1186 | tmp = readl(mmio + HOST_CTL); | |
1187 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1188 | } | |
1189 | ||
a878539e JG |
1190 | static void ahci_dev_config(struct ata_device *dev) |
1191 | { | |
1192 | struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; | |
1193 | ||
4cde32fc | 1194 | if (hpriv->flags & AHCI_HFLAG_SECT255) { |
a878539e | 1195 | dev->max_sectors = 255; |
4cde32fc JG |
1196 | ata_dev_printk(dev, KERN_INFO, |
1197 | "SB600 AHCI: limiting to 255 sectors per cmd\n"); | |
1198 | } | |
a878539e JG |
1199 | } |
1200 | ||
422b7595 | 1201 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
1da177e4 | 1202 | { |
4447d351 | 1203 | void __iomem *port_mmio = ahci_port_base(ap); |
1da177e4 | 1204 | struct ata_taskfile tf; |
422b7595 TH |
1205 | u32 tmp; |
1206 | ||
1207 | tmp = readl(port_mmio + PORT_SIG); | |
1208 | tf.lbah = (tmp >> 24) & 0xff; | |
1209 | tf.lbam = (tmp >> 16) & 0xff; | |
1210 | tf.lbal = (tmp >> 8) & 0xff; | |
1211 | tf.nsect = (tmp) & 0xff; | |
1212 | ||
1213 | return ata_dev_classify(&tf); | |
1214 | } | |
1215 | ||
12fad3f9 TH |
1216 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
1217 | u32 opts) | |
cc9278ed | 1218 | { |
12fad3f9 TH |
1219 | dma_addr_t cmd_tbl_dma; |
1220 | ||
1221 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
1222 | ||
1223 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
1224 | pp->cmd_slot[tag].status = 0; | |
1225 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
1226 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
cc9278ed TH |
1227 | } |
1228 | ||
d2e75dff | 1229 | static int ahci_kick_engine(struct ata_port *ap, int force_restart) |
4658f79b | 1230 | { |
350756f6 | 1231 | void __iomem *port_mmio = ahci_port_base(ap); |
cca3974e | 1232 | struct ahci_host_priv *hpriv = ap->host->private_data; |
520d06f9 | 1233 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; |
bf2af2a2 | 1234 | u32 tmp; |
d2e75dff | 1235 | int busy, rc; |
bf2af2a2 | 1236 | |
d2e75dff | 1237 | /* do we need to kick the port? */ |
520d06f9 | 1238 | busy = status & (ATA_BUSY | ATA_DRQ); |
d2e75dff TH |
1239 | if (!busy && !force_restart) |
1240 | return 0; | |
1241 | ||
1242 | /* stop engine */ | |
1243 | rc = ahci_stop_engine(ap); | |
1244 | if (rc) | |
1245 | goto out_restart; | |
1246 | ||
1247 | /* need to do CLO? */ | |
1248 | if (!busy) { | |
1249 | rc = 0; | |
1250 | goto out_restart; | |
1251 | } | |
1252 | ||
1253 | if (!(hpriv->cap & HOST_CAP_CLO)) { | |
1254 | rc = -EOPNOTSUPP; | |
1255 | goto out_restart; | |
1256 | } | |
bf2af2a2 | 1257 | |
d2e75dff | 1258 | /* perform CLO */ |
bf2af2a2 BJ |
1259 | tmp = readl(port_mmio + PORT_CMD); |
1260 | tmp |= PORT_CMD_CLO; | |
1261 | writel(tmp, port_mmio + PORT_CMD); | |
1262 | ||
d2e75dff | 1263 | rc = 0; |
bf2af2a2 BJ |
1264 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
1265 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); | |
1266 | if (tmp & PORT_CMD_CLO) | |
d2e75dff | 1267 | rc = -EIO; |
bf2af2a2 | 1268 | |
d2e75dff TH |
1269 | /* restart engine */ |
1270 | out_restart: | |
1271 | ahci_start_engine(ap); | |
1272 | return rc; | |
bf2af2a2 BJ |
1273 | } |
1274 | ||
91c4a2e0 TH |
1275 | static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, |
1276 | struct ata_taskfile *tf, int is_cmd, u16 flags, | |
1277 | unsigned long timeout_msec) | |
bf2af2a2 | 1278 | { |
91c4a2e0 | 1279 | const u32 cmd_fis_len = 5; /* five dwords */ |
4658f79b | 1280 | struct ahci_port_priv *pp = ap->private_data; |
4447d351 | 1281 | void __iomem *port_mmio = ahci_port_base(ap); |
91c4a2e0 TH |
1282 | u8 *fis = pp->cmd_tbl; |
1283 | u32 tmp; | |
1284 | ||
1285 | /* prep the command */ | |
1286 | ata_tf_to_fis(tf, pmp, is_cmd, fis); | |
1287 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); | |
1288 | ||
1289 | /* issue & wait */ | |
1290 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
1291 | ||
1292 | if (timeout_msec) { | |
1293 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, | |
1294 | 1, timeout_msec); | |
1295 | if (tmp & 0x1) { | |
1296 | ahci_kick_engine(ap, 1); | |
1297 | return -EBUSY; | |
1298 | } | |
1299 | } else | |
1300 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
1301 | ||
1302 | return 0; | |
1303 | } | |
1304 | ||
bd17243a SH |
1305 | static int ahci_do_softreset(struct ata_link *link, unsigned int *class, |
1306 | int pmp, unsigned long deadline, | |
1307 | int (*check_ready)(struct ata_link *link)) | |
91c4a2e0 | 1308 | { |
cc0680a5 | 1309 | struct ata_port *ap = link->ap; |
4658f79b | 1310 | const char *reason = NULL; |
2cbb79eb | 1311 | unsigned long now, msecs; |
4658f79b | 1312 | struct ata_taskfile tf; |
4658f79b TH |
1313 | int rc; |
1314 | ||
1315 | DPRINTK("ENTER\n"); | |
1316 | ||
1317 | /* prepare for SRST (AHCI-1.1 10.4.1) */ | |
d2e75dff | 1318 | rc = ahci_kick_engine(ap, 1); |
994056d7 | 1319 | if (rc && rc != -EOPNOTSUPP) |
cc0680a5 | 1320 | ata_link_printk(link, KERN_WARNING, |
994056d7 | 1321 | "failed to reset engine (errno=%d)\n", rc); |
4658f79b | 1322 | |
cc0680a5 | 1323 | ata_tf_init(link->device, &tf); |
4658f79b TH |
1324 | |
1325 | /* issue the first D2H Register FIS */ | |
2cbb79eb TH |
1326 | msecs = 0; |
1327 | now = jiffies; | |
1328 | if (time_after(now, deadline)) | |
1329 | msecs = jiffies_to_msecs(deadline - now); | |
1330 | ||
4658f79b | 1331 | tf.ctl |= ATA_SRST; |
a9cf5e85 | 1332 | if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, |
91c4a2e0 | 1333 | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { |
4658f79b TH |
1334 | rc = -EIO; |
1335 | reason = "1st FIS failed"; | |
1336 | goto fail; | |
1337 | } | |
1338 | ||
1339 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
1340 | msleep(1); | |
1341 | ||
1342 | /* issue the second D2H Register FIS */ | |
4658f79b | 1343 | tf.ctl &= ~ATA_SRST; |
a9cf5e85 | 1344 | ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); |
4658f79b | 1345 | |
705e76be | 1346 | /* wait for link to become ready */ |
bd17243a | 1347 | rc = ata_wait_after_reset(link, deadline, check_ready); |
9b89391c TH |
1348 | /* link occupied, -ENODEV too is an error */ |
1349 | if (rc) { | |
1350 | reason = "device not ready"; | |
1351 | goto fail; | |
4658f79b | 1352 | } |
9b89391c | 1353 | *class = ahci_dev_classify(ap); |
4658f79b TH |
1354 | |
1355 | DPRINTK("EXIT, class=%u\n", *class); | |
1356 | return 0; | |
1357 | ||
4658f79b | 1358 | fail: |
cc0680a5 | 1359 | ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); |
4658f79b TH |
1360 | return rc; |
1361 | } | |
1362 | ||
bd17243a SH |
1363 | static int ahci_check_ready(struct ata_link *link) |
1364 | { | |
1365 | void __iomem *port_mmio = ahci_port_base(link->ap); | |
1366 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; | |
1367 | ||
1368 | return ata_check_ready(status); | |
1369 | } | |
1370 | ||
1371 | static int ahci_softreset(struct ata_link *link, unsigned int *class, | |
1372 | unsigned long deadline) | |
1373 | { | |
1374 | int pmp = sata_srst_pmp(link); | |
1375 | ||
1376 | DPRINTK("ENTER\n"); | |
1377 | ||
1378 | return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); | |
1379 | } | |
1380 | ||
1381 | static int ahci_sb600_check_ready(struct ata_link *link) | |
1382 | { | |
1383 | void __iomem *port_mmio = ahci_port_base(link->ap); | |
1384 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; | |
1385 | u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); | |
1386 | ||
1387 | /* | |
1388 | * There is no need to check TFDATA if BAD PMP is found due to HW bug, | |
1389 | * which can save timeout delay. | |
1390 | */ | |
1391 | if (irq_status & PORT_IRQ_BAD_PMP) | |
1392 | return -EIO; | |
1393 | ||
1394 | return ata_check_ready(status); | |
1395 | } | |
1396 | ||
1397 | static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class, | |
1398 | unsigned long deadline) | |
1399 | { | |
1400 | struct ata_port *ap = link->ap; | |
1401 | void __iomem *port_mmio = ahci_port_base(ap); | |
1402 | int pmp = sata_srst_pmp(link); | |
1403 | int rc; | |
1404 | u32 irq_sts; | |
1405 | ||
1406 | DPRINTK("ENTER\n"); | |
1407 | ||
1408 | rc = ahci_do_softreset(link, class, pmp, deadline, | |
1409 | ahci_sb600_check_ready); | |
1410 | ||
1411 | /* | |
1412 | * Soft reset fails on some ATI chips with IPMS set when PMP | |
1413 | * is enabled but SATA HDD/ODD is connected to SATA port, | |
1414 | * do soft reset again to port 0. | |
1415 | */ | |
1416 | if (rc == -EIO) { | |
1417 | irq_sts = readl(port_mmio + PORT_IRQ_STAT); | |
1418 | if (irq_sts & PORT_IRQ_BAD_PMP) { | |
1419 | ata_link_printk(link, KERN_WARNING, | |
1420 | "failed due to HW bug, retry pmp=0\n"); | |
1421 | rc = ahci_do_softreset(link, class, 0, deadline, | |
1422 | ahci_check_ready); | |
1423 | } | |
1424 | } | |
1425 | ||
1426 | return rc; | |
1427 | } | |
1428 | ||
cc0680a5 | 1429 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1430 | unsigned long deadline) |
422b7595 | 1431 | { |
9dadd45b | 1432 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); |
cc0680a5 | 1433 | struct ata_port *ap = link->ap; |
4296971d TH |
1434 | struct ahci_port_priv *pp = ap->private_data; |
1435 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1436 | struct ata_taskfile tf; | |
9dadd45b | 1437 | bool online; |
4bd00f6a TH |
1438 | int rc; |
1439 | ||
1440 | DPRINTK("ENTER\n"); | |
1da177e4 | 1441 | |
4447d351 | 1442 | ahci_stop_engine(ap); |
4296971d TH |
1443 | |
1444 | /* clear D2H reception area to properly wait for D2H FIS */ | |
cc0680a5 | 1445 | ata_tf_init(link->device, &tf); |
dfd7a3db | 1446 | tf.command = 0x80; |
9977126c | 1447 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
4296971d | 1448 | |
9dadd45b TH |
1449 | rc = sata_link_hardreset(link, timing, deadline, &online, |
1450 | ahci_check_ready); | |
4296971d | 1451 | |
4447d351 | 1452 | ahci_start_engine(ap); |
1da177e4 | 1453 | |
9dadd45b | 1454 | if (online) |
4bd00f6a | 1455 | *class = ahci_dev_classify(ap); |
1da177e4 | 1456 | |
4bd00f6a TH |
1457 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
1458 | return rc; | |
1459 | } | |
1460 | ||
cc0680a5 | 1461 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1462 | unsigned long deadline) |
ad616ffb | 1463 | { |
cc0680a5 | 1464 | struct ata_port *ap = link->ap; |
9dadd45b | 1465 | bool online; |
ad616ffb TH |
1466 | int rc; |
1467 | ||
1468 | DPRINTK("ENTER\n"); | |
1469 | ||
4447d351 | 1470 | ahci_stop_engine(ap); |
ad616ffb | 1471 | |
cc0680a5 | 1472 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
9dadd45b | 1473 | deadline, &online, NULL); |
ad616ffb | 1474 | |
4447d351 | 1475 | ahci_start_engine(ap); |
ad616ffb TH |
1476 | |
1477 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
1478 | ||
1479 | /* vt8251 doesn't clear BSY on signature FIS reception, | |
1480 | * request follow-up softreset. | |
1481 | */ | |
9dadd45b | 1482 | return online ? -EAGAIN : rc; |
ad616ffb TH |
1483 | } |
1484 | ||
edc93052 TH |
1485 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
1486 | unsigned long deadline) | |
1487 | { | |
1488 | struct ata_port *ap = link->ap; | |
1489 | struct ahci_port_priv *pp = ap->private_data; | |
1490 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1491 | struct ata_taskfile tf; | |
9dadd45b | 1492 | bool online; |
edc93052 TH |
1493 | int rc; |
1494 | ||
1495 | ahci_stop_engine(ap); | |
1496 | ||
1497 | /* clear D2H reception area to properly wait for D2H FIS */ | |
1498 | ata_tf_init(link->device, &tf); | |
1499 | tf.command = 0x80; | |
1500 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); | |
1501 | ||
1502 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), | |
9dadd45b | 1503 | deadline, &online, NULL); |
edc93052 TH |
1504 | |
1505 | ahci_start_engine(ap); | |
1506 | ||
edc93052 TH |
1507 | /* The pseudo configuration device on SIMG4726 attached to |
1508 | * ASUS P5W-DH Deluxe doesn't send signature FIS after | |
1509 | * hardreset if no device is attached to the first downstream | |
1510 | * port && the pseudo device locks up on SRST w/ PMP==0. To | |
1511 | * work around this, wait for !BSY only briefly. If BSY isn't | |
1512 | * cleared, perform CLO and proceed to IDENTIFY (achieved by | |
1513 | * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). | |
1514 | * | |
1515 | * Wait for two seconds. Devices attached to downstream port | |
1516 | * which can't process the following IDENTIFY after this will | |
1517 | * have to be reset again. For most cases, this should | |
1518 | * suffice while making probing snappish enough. | |
1519 | */ | |
9dadd45b TH |
1520 | if (online) { |
1521 | rc = ata_wait_after_reset(link, jiffies + 2 * HZ, | |
1522 | ahci_check_ready); | |
1523 | if (rc) | |
1524 | ahci_kick_engine(ap, 0); | |
1525 | } | |
9dadd45b | 1526 | return rc; |
edc93052 TH |
1527 | } |
1528 | ||
cc0680a5 | 1529 | static void ahci_postreset(struct ata_link *link, unsigned int *class) |
4bd00f6a | 1530 | { |
cc0680a5 | 1531 | struct ata_port *ap = link->ap; |
4447d351 | 1532 | void __iomem *port_mmio = ahci_port_base(ap); |
4bd00f6a TH |
1533 | u32 new_tmp, tmp; |
1534 | ||
203c75b8 | 1535 | ata_std_postreset(link, class); |
02eaa666 JG |
1536 | |
1537 | /* Make sure port's ATAPI bit is set appropriately */ | |
1538 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
4bd00f6a | 1539 | if (*class == ATA_DEV_ATAPI) |
02eaa666 JG |
1540 | new_tmp |= PORT_CMD_ATAPI; |
1541 | else | |
1542 | new_tmp &= ~PORT_CMD_ATAPI; | |
1543 | if (new_tmp != tmp) { | |
1544 | writel(new_tmp, port_mmio + PORT_CMD); | |
1545 | readl(port_mmio + PORT_CMD); /* flush */ | |
1546 | } | |
1da177e4 LT |
1547 | } |
1548 | ||
12fad3f9 | 1549 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
1da177e4 | 1550 | { |
cedc9a47 | 1551 | struct scatterlist *sg; |
ff2aeb1e TH |
1552 | struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
1553 | unsigned int si; | |
1da177e4 LT |
1554 | |
1555 | VPRINTK("ENTER\n"); | |
1556 | ||
1557 | /* | |
1558 | * Next, the S/G list. | |
1559 | */ | |
ff2aeb1e | 1560 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
cedc9a47 JG |
1561 | dma_addr_t addr = sg_dma_address(sg); |
1562 | u32 sg_len = sg_dma_len(sg); | |
1563 | ||
ff2aeb1e TH |
1564 | ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); |
1565 | ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
1566 | ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); | |
1da177e4 | 1567 | } |
828d09de | 1568 | |
ff2aeb1e | 1569 | return si; |
1da177e4 LT |
1570 | } |
1571 | ||
1572 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
1573 | { | |
a0ea7328 JG |
1574 | struct ata_port *ap = qc->ap; |
1575 | struct ahci_port_priv *pp = ap->private_data; | |
405e66b3 | 1576 | int is_atapi = ata_is_atapi(qc->tf.protocol); |
12fad3f9 | 1577 | void *cmd_tbl; |
1da177e4 LT |
1578 | u32 opts; |
1579 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 1580 | unsigned int n_elem; |
1da177e4 | 1581 | |
1da177e4 LT |
1582 | /* |
1583 | * Fill in command table information. First, the header, | |
1584 | * a SATA Register - Host to Device command FIS. | |
1585 | */ | |
12fad3f9 TH |
1586 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
1587 | ||
7d50b60b | 1588 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); |
cc9278ed | 1589 | if (is_atapi) { |
12fad3f9 TH |
1590 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
1591 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
a0ea7328 | 1592 | } |
1da177e4 | 1593 | |
cc9278ed TH |
1594 | n_elem = 0; |
1595 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
12fad3f9 | 1596 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
1da177e4 | 1597 | |
cc9278ed TH |
1598 | /* |
1599 | * Fill in command slot information. | |
1600 | */ | |
7d50b60b | 1601 | opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); |
cc9278ed TH |
1602 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
1603 | opts |= AHCI_CMD_WRITE; | |
1604 | if (is_atapi) | |
4b10e559 | 1605 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
828d09de | 1606 | |
12fad3f9 | 1607 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
1da177e4 LT |
1608 | } |
1609 | ||
78cd52d0 | 1610 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 1611 | { |
417a1a6d | 1612 | struct ahci_host_priv *hpriv = ap->host->private_data; |
78cd52d0 | 1613 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1614 | struct ata_eh_info *host_ehi = &ap->link.eh_info; |
1615 | struct ata_link *link = NULL; | |
1616 | struct ata_queued_cmd *active_qc; | |
1617 | struct ata_eh_info *active_ehi; | |
78cd52d0 | 1618 | u32 serror; |
1da177e4 | 1619 | |
7d50b60b TH |
1620 | /* determine active link */ |
1621 | ata_port_for_each_link(link, ap) | |
1622 | if (ata_link_active(link)) | |
1623 | break; | |
1624 | if (!link) | |
1625 | link = &ap->link; | |
1626 | ||
1627 | active_qc = ata_qc_from_tag(ap, link->active_tag); | |
1628 | active_ehi = &link->eh_info; | |
1629 | ||
1630 | /* record irq stat */ | |
1631 | ata_ehi_clear_desc(host_ehi); | |
1632 | ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); | |
1da177e4 | 1633 | |
78cd52d0 | 1634 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
da3dbb17 | 1635 | ahci_scr_read(ap, SCR_ERROR, &serror); |
78cd52d0 | 1636 | ahci_scr_write(ap, SCR_ERROR, serror); |
7d50b60b | 1637 | host_ehi->serror |= serror; |
78cd52d0 | 1638 | |
41669553 | 1639 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
417a1a6d | 1640 | if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) |
41669553 TH |
1641 | irq_stat &= ~PORT_IRQ_IF_ERR; |
1642 | ||
55a61604 | 1643 | if (irq_stat & PORT_IRQ_TF_ERR) { |
7d50b60b TH |
1644 | /* If qc is active, charge it; otherwise, the active |
1645 | * link. There's no active qc on NCQ errors. It will | |
1646 | * be determined by EH by reading log page 10h. | |
1647 | */ | |
1648 | if (active_qc) | |
1649 | active_qc->err_mask |= AC_ERR_DEV; | |
1650 | else | |
1651 | active_ehi->err_mask |= AC_ERR_DEV; | |
1652 | ||
417a1a6d | 1653 | if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) |
7d50b60b TH |
1654 | host_ehi->serror &= ~SERR_INTERNAL; |
1655 | } | |
1656 | ||
1657 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
1658 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); | |
1659 | ||
1660 | active_ehi->err_mask |= AC_ERR_HSM; | |
cf480626 | 1661 | active_ehi->action |= ATA_EH_RESET; |
7d50b60b TH |
1662 | ata_ehi_push_desc(active_ehi, |
1663 | "unknown FIS %08x %08x %08x %08x" , | |
1664 | unk[0], unk[1], unk[2], unk[3]); | |
1665 | } | |
1666 | ||
071f44b1 | 1667 | if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { |
7d50b60b | 1668 | active_ehi->err_mask |= AC_ERR_HSM; |
cf480626 | 1669 | active_ehi->action |= ATA_EH_RESET; |
7d50b60b | 1670 | ata_ehi_push_desc(active_ehi, "incorrect PMP"); |
55a61604 | 1671 | } |
78cd52d0 TH |
1672 | |
1673 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
7d50b60b | 1674 | host_ehi->err_mask |= AC_ERR_HOST_BUS; |
cf480626 | 1675 | host_ehi->action |= ATA_EH_RESET; |
7d50b60b | 1676 | ata_ehi_push_desc(host_ehi, "host bus error"); |
1da177e4 LT |
1677 | } |
1678 | ||
78cd52d0 | 1679 | if (irq_stat & PORT_IRQ_IF_ERR) { |
7d50b60b | 1680 | host_ehi->err_mask |= AC_ERR_ATA_BUS; |
cf480626 | 1681 | host_ehi->action |= ATA_EH_RESET; |
7d50b60b | 1682 | ata_ehi_push_desc(host_ehi, "interface fatal error"); |
78cd52d0 | 1683 | } |
1da177e4 | 1684 | |
78cd52d0 | 1685 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
7d50b60b TH |
1686 | ata_ehi_hotplugged(host_ehi); |
1687 | ata_ehi_push_desc(host_ehi, "%s", | |
1688 | irq_stat & PORT_IRQ_CONNECT ? | |
78cd52d0 TH |
1689 | "connection status changed" : "PHY RDY changed"); |
1690 | } | |
1691 | ||
78cd52d0 | 1692 | /* okay, let's hand over to EH */ |
a72ec4ce | 1693 | |
78cd52d0 TH |
1694 | if (irq_stat & PORT_IRQ_FREEZE) |
1695 | ata_port_freeze(ap); | |
1696 | else | |
1697 | ata_port_abort(ap); | |
1da177e4 LT |
1698 | } |
1699 | ||
df69c9c5 | 1700 | static void ahci_port_intr(struct ata_port *ap) |
1da177e4 | 1701 | { |
350756f6 | 1702 | void __iomem *port_mmio = ahci_port_base(ap); |
9af5c9c9 | 1703 | struct ata_eh_info *ehi = &ap->link.eh_info; |
0291f95f | 1704 | struct ahci_port_priv *pp = ap->private_data; |
5f226c6b | 1705 | struct ahci_host_priv *hpriv = ap->host->private_data; |
b06ce3e5 | 1706 | int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); |
12fad3f9 | 1707 | u32 status, qc_active; |
459ad688 | 1708 | int rc; |
1da177e4 LT |
1709 | |
1710 | status = readl(port_mmio + PORT_IRQ_STAT); | |
1711 | writel(status, port_mmio + PORT_IRQ_STAT); | |
1712 | ||
b06ce3e5 TH |
1713 | /* ignore BAD_PMP while resetting */ |
1714 | if (unlikely(resetting)) | |
1715 | status &= ~PORT_IRQ_BAD_PMP; | |
1716 | ||
31556594 KCA |
1717 | /* If we are getting PhyRdy, this is |
1718 | * just a power state change, we should | |
1719 | * clear out this, plus the PhyRdy/Comm | |
1720 | * Wake bits from Serror | |
1721 | */ | |
1722 | if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) && | |
1723 | (status & PORT_IRQ_PHYRDY)) { | |
1724 | status &= ~PORT_IRQ_PHYRDY; | |
1725 | ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18))); | |
1726 | } | |
1727 | ||
78cd52d0 TH |
1728 | if (unlikely(status & PORT_IRQ_ERROR)) { |
1729 | ahci_error_intr(ap, status); | |
1730 | return; | |
1da177e4 LT |
1731 | } |
1732 | ||
2f294968 | 1733 | if (status & PORT_IRQ_SDB_FIS) { |
5f226c6b TH |
1734 | /* If SNotification is available, leave notification |
1735 | * handling to sata_async_notification(). If not, | |
1736 | * emulate it by snooping SDB FIS RX area. | |
1737 | * | |
1738 | * Snooping FIS RX area is probably cheaper than | |
1739 | * poking SNotification but some constrollers which | |
1740 | * implement SNotification, ICH9 for example, don't | |
1741 | * store AN SDB FIS into receive area. | |
2f294968 | 1742 | */ |
5f226c6b | 1743 | if (hpriv->cap & HOST_CAP_SNTF) |
7d77b247 | 1744 | sata_async_notification(ap); |
5f226c6b TH |
1745 | else { |
1746 | /* If the 'N' bit in word 0 of the FIS is set, | |
1747 | * we just received asynchronous notification. | |
1748 | * Tell libata about it. | |
1749 | */ | |
1750 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; | |
1751 | u32 f0 = le32_to_cpu(f[0]); | |
1752 | ||
1753 | if (f0 & (1 << 15)) | |
1754 | sata_async_notification(ap); | |
1755 | } | |
2f294968 KCA |
1756 | } |
1757 | ||
7d50b60b TH |
1758 | /* pp->active_link is valid iff any command is in flight */ |
1759 | if (ap->qc_active && pp->active_link->sactive) | |
12fad3f9 TH |
1760 | qc_active = readl(port_mmio + PORT_SCR_ACT); |
1761 | else | |
1762 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
1763 | ||
79f97dad | 1764 | rc = ata_qc_complete_multiple(ap, qc_active); |
b06ce3e5 | 1765 | |
459ad688 TH |
1766 | /* while resetting, invalid completions are expected */ |
1767 | if (unlikely(rc < 0 && !resetting)) { | |
12fad3f9 | 1768 | ehi->err_mask |= AC_ERR_HSM; |
cf480626 | 1769 | ehi->action |= ATA_EH_RESET; |
12fad3f9 | 1770 | ata_port_freeze(ap); |
1da177e4 | 1771 | } |
1da177e4 LT |
1772 | } |
1773 | ||
7d12e780 | 1774 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
1da177e4 | 1775 | { |
cca3974e | 1776 | struct ata_host *host = dev_instance; |
1da177e4 LT |
1777 | struct ahci_host_priv *hpriv; |
1778 | unsigned int i, handled = 0; | |
ea6ba10b | 1779 | void __iomem *mmio; |
d28f87aa | 1780 | u32 irq_stat, irq_masked; |
1da177e4 LT |
1781 | |
1782 | VPRINTK("ENTER\n"); | |
1783 | ||
cca3974e | 1784 | hpriv = host->private_data; |
0d5ff566 | 1785 | mmio = host->iomap[AHCI_PCI_BAR]; |
1da177e4 LT |
1786 | |
1787 | /* sigh. 0xffffffff is a valid return from h/w */ | |
1788 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1da177e4 LT |
1789 | if (!irq_stat) |
1790 | return IRQ_NONE; | |
1791 | ||
d28f87aa TH |
1792 | irq_masked = irq_stat & hpriv->port_map; |
1793 | ||
2dcb407e | 1794 | spin_lock(&host->lock); |
1da177e4 | 1795 | |
2dcb407e | 1796 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 1797 | struct ata_port *ap; |
1da177e4 | 1798 | |
d28f87aa | 1799 | if (!(irq_masked & (1 << i))) |
67846b30 JG |
1800 | continue; |
1801 | ||
cca3974e | 1802 | ap = host->ports[i]; |
67846b30 | 1803 | if (ap) { |
df69c9c5 | 1804 | ahci_port_intr(ap); |
67846b30 JG |
1805 | VPRINTK("port %u\n", i); |
1806 | } else { | |
1807 | VPRINTK("port %u (no irq)\n", i); | |
6971ed1f | 1808 | if (ata_ratelimit()) |
cca3974e | 1809 | dev_printk(KERN_WARNING, host->dev, |
a9524a76 | 1810 | "interrupt on disabled port %u\n", i); |
1da177e4 | 1811 | } |
67846b30 | 1812 | |
1da177e4 LT |
1813 | handled = 1; |
1814 | } | |
1815 | ||
d28f87aa TH |
1816 | /* HOST_IRQ_STAT behaves as level triggered latch meaning that |
1817 | * it should be cleared after all the port events are cleared; | |
1818 | * otherwise, it will raise a spurious interrupt after each | |
1819 | * valid one. Please read section 10.6.2 of ahci 1.1 for more | |
1820 | * information. | |
1821 | * | |
1822 | * Also, use the unmasked value to clear interrupt as spurious | |
1823 | * pending event on a dummy port might cause screaming IRQ. | |
1824 | */ | |
ea0c62f7 TH |
1825 | writel(irq_stat, mmio + HOST_IRQ_STAT); |
1826 | ||
cca3974e | 1827 | spin_unlock(&host->lock); |
1da177e4 LT |
1828 | |
1829 | VPRINTK("EXIT\n"); | |
1830 | ||
1831 | return IRQ_RETVAL(handled); | |
1832 | } | |
1833 | ||
9a3d9eb0 | 1834 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
1835 | { |
1836 | struct ata_port *ap = qc->ap; | |
4447d351 | 1837 | void __iomem *port_mmio = ahci_port_base(ap); |
7d50b60b TH |
1838 | struct ahci_port_priv *pp = ap->private_data; |
1839 | ||
1840 | /* Keep track of the currently active link. It will be used | |
1841 | * in completion path to determine whether NCQ phase is in | |
1842 | * progress. | |
1843 | */ | |
1844 | pp->active_link = qc->dev->link; | |
1da177e4 | 1845 | |
12fad3f9 TH |
1846 | if (qc->tf.protocol == ATA_PROT_NCQ) |
1847 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | |
1848 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); | |
1da177e4 LT |
1849 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
1850 | ||
1851 | return 0; | |
1852 | } | |
1853 | ||
4c9bf4e7 TH |
1854 | static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) |
1855 | { | |
1856 | struct ahci_port_priv *pp = qc->ap->private_data; | |
1857 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1858 | ||
1859 | ata_tf_from_fis(d2h_fis, &qc->result_tf); | |
1860 | return true; | |
1861 | } | |
1862 | ||
78cd52d0 TH |
1863 | static void ahci_freeze(struct ata_port *ap) |
1864 | { | |
4447d351 | 1865 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 TH |
1866 | |
1867 | /* turn IRQ off */ | |
1868 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1869 | } | |
1870 | ||
1871 | static void ahci_thaw(struct ata_port *ap) | |
1872 | { | |
0d5ff566 | 1873 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
4447d351 | 1874 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 | 1875 | u32 tmp; |
a7384925 | 1876 | struct ahci_port_priv *pp = ap->private_data; |
78cd52d0 TH |
1877 | |
1878 | /* clear IRQ */ | |
1879 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1880 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
a718728f | 1881 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
78cd52d0 | 1882 | |
1c954a4d TH |
1883 | /* turn IRQ back on */ |
1884 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
78cd52d0 TH |
1885 | } |
1886 | ||
1887 | static void ahci_error_handler(struct ata_port *ap) | |
1888 | { | |
b51e9e5d | 1889 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
78cd52d0 | 1890 | /* restart engine */ |
4447d351 TH |
1891 | ahci_stop_engine(ap); |
1892 | ahci_start_engine(ap); | |
78cd52d0 TH |
1893 | } |
1894 | ||
a1efdaba | 1895 | sata_pmp_error_handler(ap); |
edc93052 TH |
1896 | } |
1897 | ||
78cd52d0 TH |
1898 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
1899 | { | |
1900 | struct ata_port *ap = qc->ap; | |
1901 | ||
d2e75dff TH |
1902 | /* make DMA engine forget about the failed command */ |
1903 | if (qc->flags & ATA_QCFLAG_FAILED) | |
1904 | ahci_kick_engine(ap, 1); | |
78cd52d0 TH |
1905 | } |
1906 | ||
7d50b60b TH |
1907 | static void ahci_pmp_attach(struct ata_port *ap) |
1908 | { | |
1909 | void __iomem *port_mmio = ahci_port_base(ap); | |
1c954a4d | 1910 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1911 | u32 cmd; |
1912 | ||
1913 | cmd = readl(port_mmio + PORT_CMD); | |
1914 | cmd |= PORT_CMD_PMP; | |
1915 | writel(cmd, port_mmio + PORT_CMD); | |
1c954a4d TH |
1916 | |
1917 | pp->intr_mask |= PORT_IRQ_BAD_PMP; | |
1918 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
7d50b60b TH |
1919 | } |
1920 | ||
1921 | static void ahci_pmp_detach(struct ata_port *ap) | |
1922 | { | |
1923 | void __iomem *port_mmio = ahci_port_base(ap); | |
1c954a4d | 1924 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1925 | u32 cmd; |
1926 | ||
1927 | cmd = readl(port_mmio + PORT_CMD); | |
1928 | cmd &= ~PORT_CMD_PMP; | |
1929 | writel(cmd, port_mmio + PORT_CMD); | |
1c954a4d TH |
1930 | |
1931 | pp->intr_mask &= ~PORT_IRQ_BAD_PMP; | |
1932 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
7d50b60b TH |
1933 | } |
1934 | ||
028a2596 AD |
1935 | static int ahci_port_resume(struct ata_port *ap) |
1936 | { | |
1937 | ahci_power_up(ap); | |
1938 | ahci_start_port(ap); | |
1939 | ||
071f44b1 | 1940 | if (sata_pmp_attached(ap)) |
7d50b60b TH |
1941 | ahci_pmp_attach(ap); |
1942 | else | |
1943 | ahci_pmp_detach(ap); | |
1944 | ||
028a2596 AD |
1945 | return 0; |
1946 | } | |
1947 | ||
438ac6d5 | 1948 | #ifdef CONFIG_PM |
c1332875 TH |
1949 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
1950 | { | |
c1332875 TH |
1951 | const char *emsg = NULL; |
1952 | int rc; | |
1953 | ||
4447d351 | 1954 | rc = ahci_deinit_port(ap, &emsg); |
8e16f941 | 1955 | if (rc == 0) |
4447d351 | 1956 | ahci_power_down(ap); |
8e16f941 | 1957 | else { |
c1332875 | 1958 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
df69c9c5 | 1959 | ahci_start_port(ap); |
c1332875 TH |
1960 | } |
1961 | ||
1962 | return rc; | |
1963 | } | |
1964 | ||
c1332875 TH |
1965 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
1966 | { | |
cca3974e | 1967 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
0d5ff566 | 1968 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1969 | u32 ctl; |
1970 | ||
3a2d5b70 | 1971 | if (mesg.event & PM_EVENT_SLEEP) { |
c1332875 TH |
1972 | /* AHCI spec rev1.1 section 8.3.3: |
1973 | * Software must disable interrupts prior to requesting a | |
1974 | * transition of the HBA to D3 state. | |
1975 | */ | |
1976 | ctl = readl(mmio + HOST_CTL); | |
1977 | ctl &= ~HOST_IRQ_EN; | |
1978 | writel(ctl, mmio + HOST_CTL); | |
1979 | readl(mmio + HOST_CTL); /* flush */ | |
1980 | } | |
1981 | ||
1982 | return ata_pci_device_suspend(pdev, mesg); | |
1983 | } | |
1984 | ||
1985 | static int ahci_pci_device_resume(struct pci_dev *pdev) | |
1986 | { | |
cca3974e | 1987 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
c1332875 TH |
1988 | int rc; |
1989 | ||
553c4aa6 TH |
1990 | rc = ata_pci_device_do_resume(pdev); |
1991 | if (rc) | |
1992 | return rc; | |
c1332875 TH |
1993 | |
1994 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
4447d351 | 1995 | rc = ahci_reset_controller(host); |
c1332875 TH |
1996 | if (rc) |
1997 | return rc; | |
1998 | ||
4447d351 | 1999 | ahci_init_controller(host); |
c1332875 TH |
2000 | } |
2001 | ||
cca3974e | 2002 | ata_host_resume(host); |
c1332875 TH |
2003 | |
2004 | return 0; | |
2005 | } | |
438ac6d5 | 2006 | #endif |
c1332875 | 2007 | |
254950cd TH |
2008 | static int ahci_port_start(struct ata_port *ap) |
2009 | { | |
cca3974e | 2010 | struct device *dev = ap->host->dev; |
254950cd | 2011 | struct ahci_port_priv *pp; |
254950cd TH |
2012 | void *mem; |
2013 | dma_addr_t mem_dma; | |
254950cd | 2014 | |
24dc5f33 | 2015 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
254950cd TH |
2016 | if (!pp) |
2017 | return -ENOMEM; | |
254950cd | 2018 | |
24dc5f33 TH |
2019 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
2020 | GFP_KERNEL); | |
2021 | if (!mem) | |
254950cd | 2022 | return -ENOMEM; |
254950cd TH |
2023 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
2024 | ||
2025 | /* | |
2026 | * First item in chunk of DMA memory: 32-slot command table, | |
2027 | * 32 bytes each in size | |
2028 | */ | |
2029 | pp->cmd_slot = mem; | |
2030 | pp->cmd_slot_dma = mem_dma; | |
2031 | ||
2032 | mem += AHCI_CMD_SLOT_SZ; | |
2033 | mem_dma += AHCI_CMD_SLOT_SZ; | |
2034 | ||
2035 | /* | |
2036 | * Second item: Received-FIS area | |
2037 | */ | |
2038 | pp->rx_fis = mem; | |
2039 | pp->rx_fis_dma = mem_dma; | |
2040 | ||
2041 | mem += AHCI_RX_FIS_SZ; | |
2042 | mem_dma += AHCI_RX_FIS_SZ; | |
2043 | ||
2044 | /* | |
2045 | * Third item: data area for storing a single command | |
2046 | * and its scatter-gather table | |
2047 | */ | |
2048 | pp->cmd_tbl = mem; | |
2049 | pp->cmd_tbl_dma = mem_dma; | |
2050 | ||
a7384925 | 2051 | /* |
2dcb407e JG |
2052 | * Save off initial list of interrupts to be enabled. |
2053 | * This could be changed later | |
2054 | */ | |
a7384925 KCA |
2055 | pp->intr_mask = DEF_PORT_IRQ; |
2056 | ||
254950cd TH |
2057 | ap->private_data = pp; |
2058 | ||
df69c9c5 JG |
2059 | /* engage engines, captain */ |
2060 | return ahci_port_resume(ap); | |
254950cd TH |
2061 | } |
2062 | ||
2063 | static void ahci_port_stop(struct ata_port *ap) | |
2064 | { | |
0be0aa98 TH |
2065 | const char *emsg = NULL; |
2066 | int rc; | |
254950cd | 2067 | |
0be0aa98 | 2068 | /* de-initialize port */ |
4447d351 | 2069 | rc = ahci_deinit_port(ap, &emsg); |
0be0aa98 TH |
2070 | if (rc) |
2071 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | |
254950cd TH |
2072 | } |
2073 | ||
4447d351 | 2074 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
1da177e4 | 2075 | { |
1da177e4 | 2076 | int rc; |
1da177e4 | 2077 | |
1da177e4 LT |
2078 | if (using_dac && |
2079 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
2080 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
2081 | if (rc) { | |
2082 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
2083 | if (rc) { | |
a9524a76 JG |
2084 | dev_printk(KERN_ERR, &pdev->dev, |
2085 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
2086 | return rc; |
2087 | } | |
2088 | } | |
1da177e4 LT |
2089 | } else { |
2090 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
2091 | if (rc) { | |
a9524a76 JG |
2092 | dev_printk(KERN_ERR, &pdev->dev, |
2093 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
2094 | return rc; |
2095 | } | |
2096 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
2097 | if (rc) { | |
a9524a76 JG |
2098 | dev_printk(KERN_ERR, &pdev->dev, |
2099 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
2100 | return rc; |
2101 | } | |
2102 | } | |
1da177e4 LT |
2103 | return 0; |
2104 | } | |
2105 | ||
4447d351 | 2106 | static void ahci_print_info(struct ata_host *host) |
1da177e4 | 2107 | { |
4447d351 TH |
2108 | struct ahci_host_priv *hpriv = host->private_data; |
2109 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
2110 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
1da177e4 LT |
2111 | u32 vers, cap, impl, speed; |
2112 | const char *speed_s; | |
2113 | u16 cc; | |
2114 | const char *scc_s; | |
2115 | ||
2116 | vers = readl(mmio + HOST_VERSION); | |
2117 | cap = hpriv->cap; | |
2118 | impl = hpriv->port_map; | |
2119 | ||
2120 | speed = (cap >> 20) & 0xf; | |
2121 | if (speed == 1) | |
2122 | speed_s = "1.5"; | |
2123 | else if (speed == 2) | |
2124 | speed_s = "3"; | |
2125 | else | |
2126 | speed_s = "?"; | |
2127 | ||
2128 | pci_read_config_word(pdev, 0x0a, &cc); | |
c9f89475 | 2129 | if (cc == PCI_CLASS_STORAGE_IDE) |
1da177e4 | 2130 | scc_s = "IDE"; |
c9f89475 | 2131 | else if (cc == PCI_CLASS_STORAGE_SATA) |
1da177e4 | 2132 | scc_s = "SATA"; |
c9f89475 | 2133 | else if (cc == PCI_CLASS_STORAGE_RAID) |
1da177e4 LT |
2134 | scc_s = "RAID"; |
2135 | else | |
2136 | scc_s = "unknown"; | |
2137 | ||
a9524a76 JG |
2138 | dev_printk(KERN_INFO, &pdev->dev, |
2139 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 | 2140 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
2dcb407e | 2141 | , |
1da177e4 | 2142 | |
2dcb407e JG |
2143 | (vers >> 24) & 0xff, |
2144 | (vers >> 16) & 0xff, | |
2145 | (vers >> 8) & 0xff, | |
2146 | vers & 0xff, | |
1da177e4 LT |
2147 | |
2148 | ((cap >> 8) & 0x1f) + 1, | |
2149 | (cap & 0x1f) + 1, | |
2150 | speed_s, | |
2151 | impl, | |
2152 | scc_s); | |
2153 | ||
a9524a76 JG |
2154 | dev_printk(KERN_INFO, &pdev->dev, |
2155 | "flags: " | |
203ef6c4 TH |
2156 | "%s%s%s%s%s%s%s" |
2157 | "%s%s%s%s%s%s%s\n" | |
2dcb407e | 2158 | , |
1da177e4 LT |
2159 | |
2160 | cap & (1 << 31) ? "64bit " : "", | |
2161 | cap & (1 << 30) ? "ncq " : "", | |
203ef6c4 | 2162 | cap & (1 << 29) ? "sntf " : "", |
1da177e4 LT |
2163 | cap & (1 << 28) ? "ilck " : "", |
2164 | cap & (1 << 27) ? "stag " : "", | |
2165 | cap & (1 << 26) ? "pm " : "", | |
2166 | cap & (1 << 25) ? "led " : "", | |
2167 | ||
2168 | cap & (1 << 24) ? "clo " : "", | |
2169 | cap & (1 << 19) ? "nz " : "", | |
2170 | cap & (1 << 18) ? "only " : "", | |
2171 | cap & (1 << 17) ? "pmp " : "", | |
2172 | cap & (1 << 15) ? "pio " : "", | |
2173 | cap & (1 << 14) ? "slum " : "", | |
2174 | cap & (1 << 13) ? "part " : "" | |
2175 | ); | |
2176 | } | |
2177 | ||
edc93052 TH |
2178 | /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is |
2179 | * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't | |
2180 | * support PMP and the 4726 either directly exports the device | |
2181 | * attached to the first downstream port or acts as a hardware storage | |
2182 | * controller and emulate a single ATA device (can be RAID 0/1 or some | |
2183 | * other configuration). | |
2184 | * | |
2185 | * When there's no device attached to the first downstream port of the | |
2186 | * 4726, "Config Disk" appears, which is a pseudo ATA device to | |
2187 | * configure the 4726. However, ATA emulation of the device is very | |
2188 | * lame. It doesn't send signature D2H Reg FIS after the initial | |
2189 | * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. | |
2190 | * | |
2191 | * The following function works around the problem by always using | |
2192 | * hardreset on the port and not depending on receiving signature FIS | |
2193 | * afterward. If signature FIS isn't received soon, ATA class is | |
2194 | * assumed without follow-up softreset. | |
2195 | */ | |
2196 | static void ahci_p5wdh_workaround(struct ata_host *host) | |
2197 | { | |
2198 | static struct dmi_system_id sysids[] = { | |
2199 | { | |
2200 | .ident = "P5W DH Deluxe", | |
2201 | .matches = { | |
2202 | DMI_MATCH(DMI_SYS_VENDOR, | |
2203 | "ASUSTEK COMPUTER INC"), | |
2204 | DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), | |
2205 | }, | |
2206 | }, | |
2207 | { } | |
2208 | }; | |
2209 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
2210 | ||
2211 | if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && | |
2212 | dmi_check_system(sysids)) { | |
2213 | struct ata_port *ap = host->ports[1]; | |
2214 | ||
2215 | dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH " | |
2216 | "Deluxe on-board SIMG4726 workaround\n"); | |
2217 | ||
2218 | ap->ops = &ahci_p5wdh_ops; | |
2219 | ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; | |
2220 | } | |
2221 | } | |
2222 | ||
24dc5f33 | 2223 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
2224 | { |
2225 | static int printed_version; | |
e297d99e TH |
2226 | unsigned int board_id = ent->driver_data; |
2227 | struct ata_port_info pi = ahci_port_info[board_id]; | |
4447d351 | 2228 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
24dc5f33 | 2229 | struct device *dev = &pdev->dev; |
1da177e4 | 2230 | struct ahci_host_priv *hpriv; |
4447d351 | 2231 | struct ata_host *host; |
837f5f8f | 2232 | int n_ports, i, rc; |
1da177e4 LT |
2233 | |
2234 | VPRINTK("ENTER\n"); | |
2235 | ||
12fad3f9 TH |
2236 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
2237 | ||
1da177e4 | 2238 | if (!printed_version++) |
a9524a76 | 2239 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 2240 | |
4447d351 | 2241 | /* acquire resources */ |
24dc5f33 | 2242 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
2243 | if (rc) |
2244 | return rc; | |
2245 | ||
dea55137 TH |
2246 | /* AHCI controllers often implement SFF compatible interface. |
2247 | * Grab all PCI BARs just in case. | |
2248 | */ | |
2249 | rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); | |
0d5ff566 | 2250 | if (rc == -EBUSY) |
24dc5f33 | 2251 | pcim_pin_device(pdev); |
0d5ff566 | 2252 | if (rc) |
24dc5f33 | 2253 | return rc; |
1da177e4 | 2254 | |
c4f7792c TH |
2255 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
2256 | (pdev->device == 0x2652 || pdev->device == 0x2653)) { | |
2257 | u8 map; | |
2258 | ||
2259 | /* ICH6s share the same PCI ID for both piix and ahci | |
2260 | * modes. Enabling ahci mode while MAP indicates | |
2261 | * combined mode is a bad idea. Yield to ata_piix. | |
2262 | */ | |
2263 | pci_read_config_byte(pdev, ICH_MAP, &map); | |
2264 | if (map & 0x3) { | |
2265 | dev_printk(KERN_INFO, &pdev->dev, "controller is in " | |
2266 | "combined mode, can't enable AHCI mode\n"); | |
2267 | return -ENODEV; | |
2268 | } | |
2269 | } | |
2270 | ||
24dc5f33 TH |
2271 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
2272 | if (!hpriv) | |
2273 | return -ENOMEM; | |
417a1a6d TH |
2274 | hpriv->flags |= (unsigned long)pi.private_data; |
2275 | ||
e297d99e TH |
2276 | /* MCP65 revision A1 and A2 can't do MSI */ |
2277 | if (board_id == board_ahci_mcp65 && | |
2278 | (pdev->revision == 0xa1 || pdev->revision == 0xa2)) | |
2279 | hpriv->flags |= AHCI_HFLAG_NO_MSI; | |
2280 | ||
417a1a6d TH |
2281 | if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev)) |
2282 | pci_intx(pdev, 1); | |
1da177e4 | 2283 | |
4447d351 | 2284 | /* save initial config */ |
417a1a6d | 2285 | ahci_save_initial_config(pdev, hpriv); |
1da177e4 | 2286 | |
4447d351 | 2287 | /* prepare host */ |
274c1fde | 2288 | if (hpriv->cap & HOST_CAP_NCQ) |
4447d351 | 2289 | pi.flags |= ATA_FLAG_NCQ; |
1da177e4 | 2290 | |
7d50b60b TH |
2291 | if (hpriv->cap & HOST_CAP_PMP) |
2292 | pi.flags |= ATA_FLAG_PMP; | |
2293 | ||
837f5f8f TH |
2294 | /* CAP.NP sometimes indicate the index of the last enabled |
2295 | * port, at other times, that of the last possible port, so | |
2296 | * determining the maximum port number requires looking at | |
2297 | * both CAP.NP and port_map. | |
2298 | */ | |
2299 | n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); | |
2300 | ||
2301 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
4447d351 TH |
2302 | if (!host) |
2303 | return -ENOMEM; | |
2304 | host->iomap = pcim_iomap_table(pdev); | |
2305 | host->private_data = hpriv; | |
2306 | ||
2307 | for (i = 0; i < host->n_ports; i++) { | |
dab632e8 | 2308 | struct ata_port *ap = host->ports[i]; |
4447d351 | 2309 | |
cbcdd875 TH |
2310 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); |
2311 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, | |
2312 | 0x100 + ap->port_no * 0x80, "port"); | |
2313 | ||
31556594 KCA |
2314 | /* set initial link pm policy */ |
2315 | ap->pm_policy = NOT_AVAILABLE; | |
2316 | ||
dab632e8 | 2317 | /* disabled/not-implemented port */ |
350756f6 | 2318 | if (!(hpriv->port_map & (1 << i))) |
dab632e8 | 2319 | ap->ops = &ata_dummy_port_ops; |
4447d351 | 2320 | } |
d447df14 | 2321 | |
edc93052 TH |
2322 | /* apply workaround for ASUS P5W DH Deluxe mainboard */ |
2323 | ahci_p5wdh_workaround(host); | |
2324 | ||
4447d351 TH |
2325 | /* initialize adapter */ |
2326 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
1da177e4 | 2327 | if (rc) |
24dc5f33 | 2328 | return rc; |
1da177e4 | 2329 | |
4447d351 TH |
2330 | rc = ahci_reset_controller(host); |
2331 | if (rc) | |
2332 | return rc; | |
1da177e4 | 2333 | |
4447d351 TH |
2334 | ahci_init_controller(host); |
2335 | ahci_print_info(host); | |
1da177e4 | 2336 | |
4447d351 TH |
2337 | pci_set_master(pdev); |
2338 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, | |
2339 | &ahci_sht); | |
907f4678 | 2340 | } |
1da177e4 LT |
2341 | |
2342 | static int __init ahci_init(void) | |
2343 | { | |
b7887196 | 2344 | return pci_register_driver(&ahci_pci_driver); |
1da177e4 LT |
2345 | } |
2346 | ||
1da177e4 LT |
2347 | static void __exit ahci_exit(void) |
2348 | { | |
2349 | pci_unregister_driver(&ahci_pci_driver); | |
2350 | } | |
2351 | ||
2352 | ||
2353 | MODULE_AUTHOR("Jeff Garzik"); | |
2354 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
2355 | MODULE_LICENSE("GPL"); | |
2356 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 2357 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
2358 | |
2359 | module_init(ahci_init); | |
2360 | module_exit(ahci_exit); |