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1da177e4 | 1 | /* |
af36d7f0 JG |
2 | * ata_piix.c - Intel PATA/SATA controllers |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * | |
9 | * Copyright 2003-2005 Red Hat Inc | |
10 | * Copyright 2003-2005 Jeff Garzik | |
11 | * | |
12 | * | |
13 | * Copyright header from piix.c: | |
14 | * | |
15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
17 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
18 | * | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2, or (at your option) | |
23 | * any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; see the file COPYING. If not, write to | |
32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
33 | * | |
34 | * | |
35 | * libata documentation is available via 'make {ps|pdf}docs', | |
36 | * as Documentation/DocBook/libata.* | |
37 | * | |
38 | * Hardware documentation available at http://developer.intel.com/ | |
39 | * | |
d96212ed AC |
40 | * Documentation |
41 | * Publically available from Intel web site. Errata documentation | |
42 | * is also publically available. As an aide to anyone hacking on this | |
2c5ff671 | 43 | * driver the list of errata that are relevant is below, going back to |
d96212ed AC |
44 | * PIIX4. Older device documentation is now a bit tricky to find. |
45 | * | |
46 | * The chipsets all follow very much the same design. The orginal Triton | |
47 | * series chipsets do _not_ support independant device timings, but this | |
48 | * is fixed in Triton II. With the odd mobile exception the chips then | |
49 | * change little except in gaining more modes until SATA arrives. This | |
50 | * driver supports only the chips with independant timing (that is those | |
51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix | |
52 | * for the early chip drivers. | |
53 | * | |
54 | * Errata of note: | |
55 | * | |
56 | * Unfixable | |
57 | * PIIX4 errata #9 - Only on ultra obscure hw | |
58 | * ICH3 errata #13 - Not observed to affect real hw | |
59 | * by Intel | |
60 | * | |
61 | * Things we must deal with | |
62 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
63 | * (must stop/start dma to recover) | |
64 | * 440MX errata #15 - As PIIX4 errata #10 | |
65 | * PIIX4 errata #15 - Must not read control registers | |
66 | * during a PIO transfer | |
67 | * 440MX errata #13 - As PIIX4 errata #15 | |
68 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
69 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
70 | * ICH2 spec c #9 - Extra operations needed to handle | |
71 | * drive hotswap [NOT YET SUPPORTED] | |
72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
73 | * and must be dword aligned | |
74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
75 | * | |
76 | * Should have been BIOS fixed: | |
77 | * 450NX: errata #19 - DMA hangs on old 450NX | |
78 | * 450NX: errata #20 - DMA hangs on old 450NX | |
79 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
80 | * ICH3 errata #15 - IDE deadlock under high load | |
81 | * (BIOS must set dev 31 fn 0 bit 23) | |
82 | * ICH3 errata #18 - Don't use native mode | |
1da177e4 LT |
83 | */ |
84 | ||
85 | #include <linux/kernel.h> | |
86 | #include <linux/module.h> | |
87 | #include <linux/pci.h> | |
88 | #include <linux/init.h> | |
89 | #include <linux/blkdev.h> | |
90 | #include <linux/delay.h> | |
6248e647 | 91 | #include <linux/device.h> |
1da177e4 LT |
92 | #include <scsi/scsi_host.h> |
93 | #include <linux/libata.h> | |
b8b275ef | 94 | #include <linux/dmi.h> |
1da177e4 LT |
95 | |
96 | #define DRV_NAME "ata_piix" | |
2a3103ce | 97 | #define DRV_VERSION "2.12" |
1da177e4 LT |
98 | |
99 | enum { | |
100 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ | |
101 | ICH5_PMR = 0x90, /* port mapping register */ | |
102 | ICH5_PCS = 0x92, /* port control and status */ | |
7b6dbd68 | 103 | PIIX_SCC = 0x0A, /* sub-class code register */ |
1da177e4 | 104 | |
ff0fc146 TH |
105 | PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */ |
106 | PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ | |
1da177e4 | 107 | |
800b3996 TH |
108 | PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, |
109 | PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, | |
b3362f88 | 110 | |
1da177e4 LT |
111 | PIIX_80C_PRI = (1 << 5) | (1 << 4), |
112 | PIIX_80C_SEC = (1 << 7) | (1 << 6), | |
113 | ||
d33f58b8 TH |
114 | /* constants for mapping table */ |
115 | P0 = 0, /* port 0 */ | |
116 | P1 = 1, /* port 1 */ | |
117 | P2 = 2, /* port 2 */ | |
118 | P3 = 3, /* port 3 */ | |
119 | IDE = -1, /* IDE */ | |
120 | NA = -2, /* not avaliable */ | |
121 | RV = -3, /* reserved */ | |
122 | ||
7b6dbd68 | 123 | PIIX_AHCI_DEVICE = 6, |
b8b275ef TH |
124 | |
125 | /* host->flags bits */ | |
126 | PIIX_HOST_BROKEN_SUSPEND = (1 << 24), | |
1da177e4 LT |
127 | }; |
128 | ||
9cde9ed1 TH |
129 | enum piix_controller_ids { |
130 | /* controller IDs */ | |
131 | piix_pata_mwdma, /* PIIX3 MWDMA only */ | |
132 | piix_pata_33, /* PIIX4 at 33Mhz */ | |
133 | ich_pata_33, /* ICH up to UDMA 33 only */ | |
134 | ich_pata_66, /* ICH up to 66 Mhz */ | |
135 | ich_pata_100, /* ICH up to UDMA 100 */ | |
136 | ich5_sata, | |
137 | ich6_sata, | |
138 | ich6_sata_ahci, | |
139 | ich6m_sata_ahci, | |
140 | ich8_sata_ahci, | |
141 | ich8_2port_sata, | |
142 | ich8m_apple_sata_ahci, /* locks up on second port enable */ | |
143 | tolapai_sata_ahci, | |
144 | piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ | |
145 | }; | |
146 | ||
d33f58b8 TH |
147 | struct piix_map_db { |
148 | const u32 mask; | |
73291a1c | 149 | const u16 port_enable; |
d33f58b8 TH |
150 | const int map[][4]; |
151 | }; | |
152 | ||
d96715c1 TH |
153 | struct piix_host_priv { |
154 | const int *map; | |
155 | }; | |
156 | ||
2dcb407e JG |
157 | static int piix_init_one(struct pci_dev *pdev, |
158 | const struct pci_device_id *ent); | |
ccc4672a | 159 | static void piix_pata_error_handler(struct ata_port *ap); |
2dcb407e JG |
160 | static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); |
161 | static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); | |
162 | static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); | |
eb4a2c7f | 163 | static int ich_pata_cable_detect(struct ata_port *ap); |
25f98131 | 164 | static u8 piix_vmw_bmdma_status(struct ata_port *ap); |
b8b275ef TH |
165 | #ifdef CONFIG_PM |
166 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); | |
167 | static int piix_pci_device_resume(struct pci_dev *pdev); | |
168 | #endif | |
1da177e4 LT |
169 | |
170 | static unsigned int in_module_init = 1; | |
171 | ||
3b7d697d | 172 | static const struct pci_device_id piix_pci_tbl[] = { |
d2cdfc0d AC |
173 | /* Intel PIIX3 for the 430HX etc */ |
174 | { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, | |
25f98131 TH |
175 | /* VMware ICH4 */ |
176 | { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw }, | |
669a5db4 JG |
177 | /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ |
178 | /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ | |
179 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
669a5db4 JG |
180 | /* Intel PIIX4 */ |
181 | { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
182 | /* Intel PIIX4 */ | |
183 | { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
184 | /* Intel PIIX */ | |
185 | { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
186 | /* Intel ICH (i810, i815, i840) UDMA 66*/ | |
187 | { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, | |
188 | /* Intel ICH0 : UDMA 33*/ | |
189 | { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, | |
190 | /* Intel ICH2M */ | |
191 | { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
192 | /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ | |
193 | { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
194 | /* Intel ICH3M */ | |
195 | { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
196 | /* Intel ICH3 (E7500/1) UDMA 100 */ | |
197 | { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
198 | /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ | |
199 | { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
200 | { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
201 | /* Intel ICH5 */ | |
2eb829e9 | 202 | { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
669a5db4 JG |
203 | /* C-ICH (i810E2) */ |
204 | { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
85cd7251 | 205 | /* ESB (855GME/875P + 6300ESB) UDMA 100 */ |
669a5db4 JG |
206 | { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
207 | /* ICH6 (and 6) (i915) UDMA 100 */ | |
208 | { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
209 | /* ICH7/7-R (i945, i975) UDMA 100*/ | |
2eb829e9 | 210 | { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
669a5db4 | 211 | { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
c1e6f28c CL |
212 | /* ICH8 Mobile PATA Controller */ |
213 | { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
1da177e4 LT |
214 | |
215 | /* NOTE: The following PCI ids must be kept in sync with the | |
216 | * list in drivers/pci/quirks.c. | |
217 | */ | |
218 | ||
1d076e5b | 219 | /* 82801EB (ICH5) */ |
1da177e4 | 220 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 221 | /* 82801EB (ICH5) */ |
1da177e4 | 222 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 223 | /* 6300ESB (ICH5 variant with broken PCS present bits) */ |
5e56a37c | 224 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 225 | /* 6300ESB pretending RAID */ |
5e56a37c | 226 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 227 | /* 82801FB/FW (ICH6/ICH6W) */ |
1da177e4 | 228 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
1d076e5b | 229 | /* 82801FR/FRW (ICH6R/ICH6RW) */ |
1c24a412 | 230 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
1d076e5b TH |
231 | /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ |
232 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, | |
233 | /* 82801GB/GR/GH (ICH7, identical to ICH6) */ | |
1c24a412 | 234 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
1d076e5b | 235 | /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
c6446a4c | 236 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, |
f98b6573 | 237 | /* Enterprise Southbridge 2 (631xESB/632xESB) */ |
1c24a412 | 238 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
f98b6573 | 239 | /* SATA Controller 1 IDE (ICH8) */ |
08f12edc | 240 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
f98b6573 | 241 | /* SATA Controller 2 IDE (ICH8) */ |
00242ec8 | 242 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 243 | /* Mobile SATA Controller IDE (ICH8M) */ |
08f12edc | 244 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
8d8ef2fb TR |
245 | /* Mobile SATA Controller IDE (ICH8M), Apple */ |
246 | { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci }, | |
f98b6573 JG |
247 | /* SATA Controller IDE (ICH9) */ |
248 | { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | |
249 | /* SATA Controller IDE (ICH9) */ | |
00242ec8 | 250 | { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 251 | /* SATA Controller IDE (ICH9) */ |
00242ec8 | 252 | { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 253 | /* SATA Controller IDE (ICH9M) */ |
00242ec8 | 254 | { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 255 | /* SATA Controller IDE (ICH9M) */ |
00242ec8 | 256 | { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 JG |
257 | /* SATA Controller IDE (ICH9M) */ |
258 | { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | |
c5cf0ffa JG |
259 | /* SATA Controller IDE (Tolapai) */ |
260 | { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci }, | |
1da177e4 LT |
261 | |
262 | { } /* terminate list */ | |
263 | }; | |
264 | ||
265 | static struct pci_driver piix_pci_driver = { | |
266 | .name = DRV_NAME, | |
267 | .id_table = piix_pci_tbl, | |
268 | .probe = piix_init_one, | |
269 | .remove = ata_pci_remove_one, | |
438ac6d5 | 270 | #ifdef CONFIG_PM |
b8b275ef TH |
271 | .suspend = piix_pci_device_suspend, |
272 | .resume = piix_pci_device_resume, | |
438ac6d5 | 273 | #endif |
1da177e4 LT |
274 | }; |
275 | ||
193515d5 | 276 | static struct scsi_host_template piix_sht = { |
1da177e4 LT |
277 | .module = THIS_MODULE, |
278 | .name = DRV_NAME, | |
279 | .ioctl = ata_scsi_ioctl, | |
280 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
281 | .can_queue = ATA_DEF_QUEUE, |
282 | .this_id = ATA_SHT_THIS_ID, | |
283 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
284 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
285 | .emulated = ATA_SHT_EMULATED, | |
286 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
287 | .proc_name = DRV_NAME, | |
288 | .dma_boundary = ATA_DMA_BOUNDARY, | |
289 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 290 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 291 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
292 | }; |
293 | ||
057ace5e | 294 | static const struct ata_port_operations piix_pata_ops = { |
1da177e4 LT |
295 | .set_piomode = piix_set_piomode, |
296 | .set_dmamode = piix_set_dmamode, | |
89bad589 | 297 | .mode_filter = ata_pci_default_filter, |
1da177e4 LT |
298 | |
299 | .tf_load = ata_tf_load, | |
300 | .tf_read = ata_tf_read, | |
301 | .check_status = ata_check_status, | |
302 | .exec_command = ata_exec_command, | |
303 | .dev_select = ata_std_dev_select, | |
304 | ||
1da177e4 LT |
305 | .bmdma_setup = ata_bmdma_setup, |
306 | .bmdma_start = ata_bmdma_start, | |
307 | .bmdma_stop = ata_bmdma_stop, | |
308 | .bmdma_status = ata_bmdma_status, | |
309 | .qc_prep = ata_qc_prep, | |
310 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 311 | .data_xfer = ata_data_xfer, |
1da177e4 | 312 | |
3f037db0 TH |
313 | .freeze = ata_bmdma_freeze, |
314 | .thaw = ata_bmdma_thaw, | |
ccc4672a | 315 | .error_handler = piix_pata_error_handler, |
3f037db0 | 316 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
eb4a2c7f | 317 | .cable_detect = ata_cable_40wire, |
1da177e4 | 318 | |
1da177e4 | 319 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 | 320 | .irq_on = ata_irq_on, |
1da177e4 LT |
321 | |
322 | .port_start = ata_port_start, | |
1da177e4 LT |
323 | }; |
324 | ||
669a5db4 | 325 | static const struct ata_port_operations ich_pata_ops = { |
669a5db4 JG |
326 | .set_piomode = piix_set_piomode, |
327 | .set_dmamode = ich_set_dmamode, | |
328 | .mode_filter = ata_pci_default_filter, | |
329 | ||
330 | .tf_load = ata_tf_load, | |
331 | .tf_read = ata_tf_read, | |
332 | .check_status = ata_check_status, | |
333 | .exec_command = ata_exec_command, | |
334 | .dev_select = ata_std_dev_select, | |
335 | ||
336 | .bmdma_setup = ata_bmdma_setup, | |
337 | .bmdma_start = ata_bmdma_start, | |
338 | .bmdma_stop = ata_bmdma_stop, | |
339 | .bmdma_status = ata_bmdma_status, | |
340 | .qc_prep = ata_qc_prep, | |
341 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 342 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
343 | |
344 | .freeze = ata_bmdma_freeze, | |
345 | .thaw = ata_bmdma_thaw, | |
eb4a2c7f | 346 | .error_handler = piix_pata_error_handler, |
669a5db4 | 347 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
eb4a2c7f | 348 | .cable_detect = ich_pata_cable_detect, |
669a5db4 | 349 | |
669a5db4 | 350 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 | 351 | .irq_on = ata_irq_on, |
669a5db4 JG |
352 | |
353 | .port_start = ata_port_start, | |
669a5db4 JG |
354 | }; |
355 | ||
057ace5e | 356 | static const struct ata_port_operations piix_sata_ops = { |
1da177e4 LT |
357 | .tf_load = ata_tf_load, |
358 | .tf_read = ata_tf_read, | |
359 | .check_status = ata_check_status, | |
360 | .exec_command = ata_exec_command, | |
361 | .dev_select = ata_std_dev_select, | |
362 | ||
1da177e4 LT |
363 | .bmdma_setup = ata_bmdma_setup, |
364 | .bmdma_start = ata_bmdma_start, | |
365 | .bmdma_stop = ata_bmdma_stop, | |
366 | .bmdma_status = ata_bmdma_status, | |
367 | .qc_prep = ata_qc_prep, | |
368 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 369 | .data_xfer = ata_data_xfer, |
1da177e4 | 370 | |
3f037db0 TH |
371 | .freeze = ata_bmdma_freeze, |
372 | .thaw = ata_bmdma_thaw, | |
2f91d81d | 373 | .error_handler = ata_bmdma_error_handler, |
3f037db0 | 374 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
1da177e4 | 375 | |
1da177e4 | 376 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 | 377 | .irq_on = ata_irq_on, |
1da177e4 LT |
378 | |
379 | .port_start = ata_port_start, | |
1da177e4 LT |
380 | }; |
381 | ||
25f98131 TH |
382 | static const struct ata_port_operations piix_vmw_ops = { |
383 | .set_piomode = piix_set_piomode, | |
384 | .set_dmamode = piix_set_dmamode, | |
385 | .mode_filter = ata_pci_default_filter, | |
386 | ||
387 | .tf_load = ata_tf_load, | |
388 | .tf_read = ata_tf_read, | |
389 | .check_status = ata_check_status, | |
390 | .exec_command = ata_exec_command, | |
391 | .dev_select = ata_std_dev_select, | |
392 | ||
393 | .bmdma_setup = ata_bmdma_setup, | |
394 | .bmdma_start = ata_bmdma_start, | |
395 | .bmdma_stop = ata_bmdma_stop, | |
396 | .bmdma_status = piix_vmw_bmdma_status, | |
397 | .qc_prep = ata_qc_prep, | |
398 | .qc_issue = ata_qc_issue_prot, | |
399 | .data_xfer = ata_data_xfer, | |
400 | ||
401 | .freeze = ata_bmdma_freeze, | |
402 | .thaw = ata_bmdma_thaw, | |
403 | .error_handler = piix_pata_error_handler, | |
404 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
405 | .cable_detect = ata_cable_40wire, | |
406 | ||
407 | .irq_handler = ata_interrupt, | |
408 | .irq_clear = ata_bmdma_irq_clear, | |
409 | .irq_on = ata_irq_on, | |
410 | ||
411 | .port_start = ata_port_start, | |
412 | }; | |
413 | ||
d96715c1 | 414 | static const struct piix_map_db ich5_map_db = { |
d33f58b8 | 415 | .mask = 0x7, |
ea35d29e | 416 | .port_enable = 0x3, |
d33f58b8 TH |
417 | .map = { |
418 | /* PM PS SM SS MAP */ | |
419 | { P0, NA, P1, NA }, /* 000b */ | |
420 | { P1, NA, P0, NA }, /* 001b */ | |
421 | { RV, RV, RV, RV }, | |
422 | { RV, RV, RV, RV }, | |
423 | { P0, P1, IDE, IDE }, /* 100b */ | |
424 | { P1, P0, IDE, IDE }, /* 101b */ | |
425 | { IDE, IDE, P0, P1 }, /* 110b */ | |
426 | { IDE, IDE, P1, P0 }, /* 111b */ | |
427 | }, | |
428 | }; | |
429 | ||
d96715c1 | 430 | static const struct piix_map_db ich6_map_db = { |
d33f58b8 | 431 | .mask = 0x3, |
ea35d29e | 432 | .port_enable = 0xf, |
d33f58b8 TH |
433 | .map = { |
434 | /* PM PS SM SS MAP */ | |
79ea24e7 | 435 | { P0, P2, P1, P3 }, /* 00b */ |
d33f58b8 TH |
436 | { IDE, IDE, P1, P3 }, /* 01b */ |
437 | { P0, P2, IDE, IDE }, /* 10b */ | |
438 | { RV, RV, RV, RV }, | |
439 | }, | |
440 | }; | |
441 | ||
d96715c1 | 442 | static const struct piix_map_db ich6m_map_db = { |
d33f58b8 | 443 | .mask = 0x3, |
ea35d29e | 444 | .port_enable = 0x5, |
67083741 TH |
445 | |
446 | /* Map 01b isn't specified in the doc but some notebooks use | |
c6446a4c TH |
447 | * it anyway. MAP 01b have been spotted on both ICH6M and |
448 | * ICH7M. | |
67083741 TH |
449 | */ |
450 | .map = { | |
451 | /* PM PS SM SS MAP */ | |
e04b3b9d | 452 | { P0, P2, NA, NA }, /* 00b */ |
67083741 TH |
453 | { IDE, IDE, P1, P3 }, /* 01b */ |
454 | { P0, P2, IDE, IDE }, /* 10b */ | |
455 | { RV, RV, RV, RV }, | |
456 | }, | |
457 | }; | |
458 | ||
08f12edc JG |
459 | static const struct piix_map_db ich8_map_db = { |
460 | .mask = 0x3, | |
a0ce9aca | 461 | .port_enable = 0xf, |
08f12edc JG |
462 | .map = { |
463 | /* PM PS SM SS MAP */ | |
158f30c8 | 464 | { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ |
08f12edc | 465 | { RV, RV, RV, RV }, |
ac2b0437 | 466 | { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ |
08f12edc JG |
467 | { RV, RV, RV, RV }, |
468 | }, | |
469 | }; | |
470 | ||
00242ec8 | 471 | static const struct piix_map_db ich8_2port_map_db = { |
e2d352af JG |
472 | .mask = 0x3, |
473 | .port_enable = 0x3, | |
474 | .map = { | |
475 | /* PM PS SM SS MAP */ | |
476 | { P0, NA, P1, NA }, /* 00b */ | |
477 | { RV, RV, RV, RV }, /* 01b */ | |
478 | { RV, RV, RV, RV }, /* 10b */ | |
479 | { RV, RV, RV, RV }, | |
480 | }, | |
c5cf0ffa JG |
481 | }; |
482 | ||
8d8ef2fb TR |
483 | static const struct piix_map_db ich8m_apple_map_db = { |
484 | .mask = 0x3, | |
485 | .port_enable = 0x1, | |
486 | .map = { | |
487 | /* PM PS SM SS MAP */ | |
488 | { P0, NA, NA, NA }, /* 00b */ | |
489 | { RV, RV, RV, RV }, | |
490 | { P0, P2, IDE, IDE }, /* 10b */ | |
491 | { RV, RV, RV, RV }, | |
492 | }, | |
493 | }; | |
494 | ||
00242ec8 | 495 | static const struct piix_map_db tolapai_map_db = { |
8f73a688 JG |
496 | .mask = 0x3, |
497 | .port_enable = 0x3, | |
498 | .map = { | |
499 | /* PM PS SM SS MAP */ | |
500 | { P0, NA, P1, NA }, /* 00b */ | |
501 | { RV, RV, RV, RV }, /* 01b */ | |
502 | { RV, RV, RV, RV }, /* 10b */ | |
503 | { RV, RV, RV, RV }, | |
504 | }, | |
505 | }; | |
506 | ||
d96715c1 TH |
507 | static const struct piix_map_db *piix_map_db_table[] = { |
508 | [ich5_sata] = &ich5_map_db, | |
d96715c1 TH |
509 | [ich6_sata] = &ich6_map_db, |
510 | [ich6_sata_ahci] = &ich6_map_db, | |
511 | [ich6m_sata_ahci] = &ich6m_map_db, | |
08f12edc | 512 | [ich8_sata_ahci] = &ich8_map_db, |
00242ec8 | 513 | [ich8_2port_sata] = &ich8_2port_map_db, |
8d8ef2fb | 514 | [ich8m_apple_sata_ahci] = &ich8m_apple_map_db, |
c5cf0ffa | 515 | [tolapai_sata_ahci] = &tolapai_map_db, |
d96715c1 TH |
516 | }; |
517 | ||
1da177e4 | 518 | static struct ata_port_info piix_port_info[] = { |
00242ec8 TH |
519 | [piix_pata_mwdma] = /* PIIX3 MWDMA only */ |
520 | { | |
00242ec8 TH |
521 | .flags = PIIX_PATA_FLAGS, |
522 | .pio_mask = 0x1f, /* pio0-4 */ | |
523 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | |
524 | .port_ops = &piix_pata_ops, | |
525 | }, | |
526 | ||
ec300d99 | 527 | [piix_pata_33] = /* PIIX4 at 33MHz */ |
1d076e5b | 528 | { |
b3362f88 | 529 | .flags = PIIX_PATA_FLAGS, |
1d076e5b | 530 | .pio_mask = 0x1f, /* pio0-4 */ |
669a5db4 | 531 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ |
1d076e5b TH |
532 | .udma_mask = ATA_UDMA_MASK_40C, |
533 | .port_ops = &piix_pata_ops, | |
534 | }, | |
535 | ||
ec300d99 | 536 | [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ |
669a5db4 | 537 | { |
b3362f88 | 538 | .flags = PIIX_PATA_FLAGS, |
669a5db4 JG |
539 | .pio_mask = 0x1f, /* pio 0-4 */ |
540 | .mwdma_mask = 0x06, /* Check: maybe 0x07 */ | |
541 | .udma_mask = ATA_UDMA2, /* UDMA33 */ | |
542 | .port_ops = &ich_pata_ops, | |
543 | }, | |
ec300d99 JG |
544 | |
545 | [ich_pata_66] = /* ICH controllers up to 66MHz */ | |
1da177e4 | 546 | { |
b3362f88 | 547 | .flags = PIIX_PATA_FLAGS, |
669a5db4 JG |
548 | .pio_mask = 0x1f, /* pio 0-4 */ |
549 | .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ | |
550 | .udma_mask = ATA_UDMA4, | |
551 | .port_ops = &ich_pata_ops, | |
552 | }, | |
85cd7251 | 553 | |
ec300d99 | 554 | [ich_pata_100] = |
669a5db4 | 555 | { |
b3362f88 | 556 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, |
1da177e4 | 557 | .pio_mask = 0x1f, /* pio0-4 */ |
1da177e4 | 558 | .mwdma_mask = 0x06, /* mwdma1-2 */ |
669a5db4 JG |
559 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
560 | .port_ops = &ich_pata_ops, | |
1da177e4 LT |
561 | }, |
562 | ||
ec300d99 | 563 | [ich5_sata] = |
1da177e4 | 564 | { |
228c1590 | 565 | .flags = PIIX_SATA_FLAGS, |
1da177e4 LT |
566 | .pio_mask = 0x1f, /* pio0-4 */ |
567 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 568 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
569 | .port_ops = &piix_sata_ops, |
570 | }, | |
571 | ||
ec300d99 | 572 | [ich6_sata] = |
1da177e4 | 573 | { |
723159c5 | 574 | .flags = PIIX_SATA_FLAGS, |
1da177e4 LT |
575 | .pio_mask = 0x1f, /* pio0-4 */ |
576 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 577 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
578 | .port_ops = &piix_sata_ops, |
579 | }, | |
580 | ||
ec300d99 | 581 | [ich6_sata_ahci] = |
c368ca4e | 582 | { |
723159c5 | 583 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI, |
c368ca4e JG |
584 | .pio_mask = 0x1f, /* pio0-4 */ |
585 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 586 | .udma_mask = ATA_UDMA6, |
c368ca4e JG |
587 | .port_ops = &piix_sata_ops, |
588 | }, | |
1d076e5b | 589 | |
ec300d99 | 590 | [ich6m_sata_ahci] = |
1d076e5b | 591 | { |
723159c5 | 592 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI, |
1d076e5b TH |
593 | .pio_mask = 0x1f, /* pio0-4 */ |
594 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 595 | .udma_mask = ATA_UDMA6, |
1d076e5b TH |
596 | .port_ops = &piix_sata_ops, |
597 | }, | |
08f12edc | 598 | |
ec300d99 | 599 | [ich8_sata_ahci] = |
08f12edc | 600 | { |
723159c5 | 601 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI, |
08f12edc JG |
602 | .pio_mask = 0x1f, /* pio0-4 */ |
603 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 604 | .udma_mask = ATA_UDMA6, |
08f12edc JG |
605 | .port_ops = &piix_sata_ops, |
606 | }, | |
669a5db4 | 607 | |
00242ec8 | 608 | [ich8_2port_sata] = |
c5cf0ffa | 609 | { |
723159c5 | 610 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI, |
c5cf0ffa JG |
611 | .pio_mask = 0x1f, /* pio0-4 */ |
612 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
613 | .udma_mask = ATA_UDMA6, | |
614 | .port_ops = &piix_sata_ops, | |
615 | }, | |
8f73a688 | 616 | |
00242ec8 | 617 | [tolapai_sata_ahci] = |
8f73a688 | 618 | { |
723159c5 | 619 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI, |
8f73a688 JG |
620 | .pio_mask = 0x1f, /* pio0-4 */ |
621 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
622 | .udma_mask = ATA_UDMA6, | |
623 | .port_ops = &piix_sata_ops, | |
624 | }, | |
8d8ef2fb TR |
625 | |
626 | [ich8m_apple_sata_ahci] = | |
627 | { | |
723159c5 | 628 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI, |
8d8ef2fb TR |
629 | .pio_mask = 0x1f, /* pio0-4 */ |
630 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
631 | .udma_mask = ATA_UDMA6, | |
632 | .port_ops = &piix_sata_ops, | |
633 | }, | |
634 | ||
25f98131 TH |
635 | [piix_pata_vmw] = |
636 | { | |
637 | .sht = &piix_sht, | |
638 | .flags = PIIX_PATA_FLAGS, | |
639 | .pio_mask = 0x1f, /* pio0-4 */ | |
640 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | |
641 | .udma_mask = ATA_UDMA_MASK_40C, | |
642 | .port_ops = &piix_vmw_ops, | |
643 | }, | |
644 | ||
1da177e4 LT |
645 | }; |
646 | ||
647 | static struct pci_bits piix_enable_bits[] = { | |
648 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ | |
649 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ | |
650 | }; | |
651 | ||
652 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); | |
653 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); | |
654 | MODULE_LICENSE("GPL"); | |
655 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
656 | MODULE_VERSION(DRV_VERSION); | |
657 | ||
fc085150 AC |
658 | struct ich_laptop { |
659 | u16 device; | |
660 | u16 subvendor; | |
661 | u16 subdevice; | |
662 | }; | |
663 | ||
664 | /* | |
665 | * List of laptops that use short cables rather than 80 wire | |
666 | */ | |
667 | ||
668 | static const struct ich_laptop ich_laptop[] = { | |
669 | /* devid, subvendor, subdev */ | |
670 | { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ | |
2655e2ce | 671 | { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ |
babfb682 | 672 | { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ |
12340106 | 673 | { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ |
54174db3 | 674 | { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ |
b33620f9 | 675 | { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ |
fc085150 AC |
676 | /* end marker */ |
677 | { 0, } | |
678 | }; | |
679 | ||
1da177e4 | 680 | /** |
eb4a2c7f | 681 | * ich_pata_cable_detect - Probe host controller cable detect info |
1da177e4 LT |
682 | * @ap: Port for which cable detect info is desired |
683 | * | |
684 | * Read 80c cable indicator from ATA PCI device's PCI config | |
685 | * register. This register is normally set by firmware (BIOS). | |
686 | * | |
687 | * LOCKING: | |
688 | * None (inherited from caller). | |
689 | */ | |
669a5db4 | 690 | |
eb4a2c7f | 691 | static int ich_pata_cable_detect(struct ata_port *ap) |
1da177e4 | 692 | { |
cca3974e | 693 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
fc085150 | 694 | const struct ich_laptop *lap = &ich_laptop[0]; |
1da177e4 LT |
695 | u8 tmp, mask; |
696 | ||
fc085150 AC |
697 | /* Check for specials - Acer Aspire 5602WLMi */ |
698 | while (lap->device) { | |
699 | if (lap->device == pdev->device && | |
700 | lap->subvendor == pdev->subsystem_vendor && | |
2dcb407e | 701 | lap->subdevice == pdev->subsystem_device) |
eb4a2c7f | 702 | return ATA_CBL_PATA40_SHORT; |
2dcb407e | 703 | |
fc085150 AC |
704 | lap++; |
705 | } | |
706 | ||
1da177e4 | 707 | /* check BIOS cable detect results */ |
2a88d1ac | 708 | mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; |
1da177e4 LT |
709 | pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); |
710 | if ((tmp & mask) == 0) | |
eb4a2c7f AC |
711 | return ATA_CBL_PATA40; |
712 | return ATA_CBL_PATA80; | |
1da177e4 LT |
713 | } |
714 | ||
715 | /** | |
ccc4672a | 716 | * piix_pata_prereset - prereset for PATA host controller |
cc0680a5 | 717 | * @link: Target link |
d4b2bab4 | 718 | * @deadline: deadline jiffies for the operation |
1da177e4 | 719 | * |
573db6b8 TH |
720 | * LOCKING: |
721 | * None (inherited from caller). | |
722 | */ | |
cc0680a5 | 723 | static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) |
1da177e4 | 724 | { |
cc0680a5 | 725 | struct ata_port *ap = link->ap; |
cca3974e | 726 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
1da177e4 | 727 | |
c961922b AC |
728 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) |
729 | return -ENOENT; | |
cc0680a5 | 730 | return ata_std_prereset(link, deadline); |
ccc4672a TH |
731 | } |
732 | ||
733 | static void piix_pata_error_handler(struct ata_port *ap) | |
734 | { | |
735 | ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL, | |
736 | ata_std_postreset); | |
1da177e4 LT |
737 | } |
738 | ||
1da177e4 LT |
739 | /** |
740 | * piix_set_piomode - Initialize host controller PATA PIO timings | |
741 | * @ap: Port whose timings we are configuring | |
742 | * @adev: um | |
1da177e4 LT |
743 | * |
744 | * Set PIO mode for device, in host controller PCI config space. | |
745 | * | |
746 | * LOCKING: | |
747 | * None (inherited from caller). | |
748 | */ | |
749 | ||
2dcb407e | 750 | static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) |
1da177e4 LT |
751 | { |
752 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
cca3974e | 753 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
1da177e4 | 754 | unsigned int is_slave = (adev->devno != 0); |
2a88d1ac | 755 | unsigned int master_port= ap->port_no ? 0x42 : 0x40; |
1da177e4 LT |
756 | unsigned int slave_port = 0x44; |
757 | u16 master_data; | |
758 | u8 slave_data; | |
669a5db4 JG |
759 | u8 udma_enable; |
760 | int control = 0; | |
85cd7251 | 761 | |
669a5db4 JG |
762 | /* |
763 | * See Intel Document 298600-004 for the timing programing rules | |
764 | * for ICH controllers. | |
765 | */ | |
1da177e4 LT |
766 | |
767 | static const /* ISP RTC */ | |
768 | u8 timings[][2] = { { 0, 0 }, | |
769 | { 0, 0 }, | |
770 | { 1, 0 }, | |
771 | { 2, 1 }, | |
772 | { 2, 3 }, }; | |
773 | ||
669a5db4 JG |
774 | if (pio >= 2) |
775 | control |= 1; /* TIME1 enable */ | |
776 | if (ata_pio_need_iordy(adev)) | |
777 | control |= 2; /* IE enable */ | |
778 | ||
85cd7251 | 779 | /* Intel specifies that the PPE functionality is for disk only */ |
669a5db4 JG |
780 | if (adev->class == ATA_DEV_ATA) |
781 | control |= 4; /* PPE enable */ | |
782 | ||
a5bf5f5a TH |
783 | /* PIO configuration clears DTE unconditionally. It will be |
784 | * programmed in set_dmamode which is guaranteed to be called | |
785 | * after set_piomode if any DMA mode is available. | |
786 | */ | |
1da177e4 LT |
787 | pci_read_config_word(dev, master_port, &master_data); |
788 | if (is_slave) { | |
a5bf5f5a TH |
789 | /* clear TIME1|IE1|PPE1|DTE1 */ |
790 | master_data &= 0xff0f; | |
669a5db4 | 791 | /* Enable SITRE (seperate slave timing register) */ |
1da177e4 | 792 | master_data |= 0x4000; |
669a5db4 JG |
793 | /* enable PPE1, IE1 and TIME1 as needed */ |
794 | master_data |= (control << 4); | |
1da177e4 | 795 | pci_read_config_byte(dev, slave_port, &slave_data); |
2a88d1ac | 796 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db4 | 797 | /* Load the timing nibble for this slave */ |
a5bf5f5a TH |
798 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) |
799 | << (ap->port_no ? 4 : 0); | |
1da177e4 | 800 | } else { |
a5bf5f5a TH |
801 | /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ |
802 | master_data &= 0xccf0; | |
669a5db4 JG |
803 | /* Enable PPE, IE and TIME as appropriate */ |
804 | master_data |= control; | |
a5bf5f5a | 805 | /* load ISP and RCT */ |
1da177e4 LT |
806 | master_data |= |
807 | (timings[pio][0] << 12) | | |
808 | (timings[pio][1] << 8); | |
809 | } | |
810 | pci_write_config_word(dev, master_port, master_data); | |
811 | if (is_slave) | |
812 | pci_write_config_byte(dev, slave_port, slave_data); | |
669a5db4 JG |
813 | |
814 | /* Ensure the UDMA bit is off - it will be turned back on if | |
815 | UDMA is selected */ | |
85cd7251 | 816 | |
669a5db4 JG |
817 | if (ap->udma_mask) { |
818 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
819 | udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); | |
820 | pci_write_config_byte(dev, 0x48, udma_enable); | |
821 | } | |
1da177e4 LT |
822 | } |
823 | ||
824 | /** | |
669a5db4 | 825 | * do_pata_set_dmamode - Initialize host controller PATA PIO timings |
1da177e4 | 826 | * @ap: Port whose timings we are configuring |
669a5db4 | 827 | * @adev: Drive in question |
1da177e4 | 828 | * @udma: udma mode, 0 - 6 |
c32a8fd7 | 829 | * @isich: set if the chip is an ICH device |
1da177e4 LT |
830 | * |
831 | * Set UDMA mode for device, in host controller PCI config space. | |
832 | * | |
833 | * LOCKING: | |
834 | * None (inherited from caller). | |
835 | */ | |
836 | ||
2dcb407e | 837 | static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) |
1da177e4 | 838 | { |
cca3974e | 839 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
669a5db4 JG |
840 | u8 master_port = ap->port_no ? 0x42 : 0x40; |
841 | u16 master_data; | |
842 | u8 speed = adev->dma_mode; | |
843 | int devid = adev->devno + 2 * ap->port_no; | |
dedf61db | 844 | u8 udma_enable = 0; |
85cd7251 | 845 | |
669a5db4 JG |
846 | static const /* ISP RTC */ |
847 | u8 timings[][2] = { { 0, 0 }, | |
848 | { 0, 0 }, | |
849 | { 1, 0 }, | |
850 | { 2, 1 }, | |
851 | { 2, 3 }, }; | |
852 | ||
853 | pci_read_config_word(dev, master_port, &master_data); | |
d2cdfc0d AC |
854 | if (ap->udma_mask) |
855 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
1da177e4 LT |
856 | |
857 | if (speed >= XFER_UDMA_0) { | |
669a5db4 JG |
858 | unsigned int udma = adev->dma_mode - XFER_UDMA_0; |
859 | u16 udma_timing; | |
860 | u16 ideconf; | |
861 | int u_clock, u_speed; | |
85cd7251 | 862 | |
669a5db4 | 863 | /* |
2dcb407e | 864 | * UDMA is handled by a combination of clock switching and |
85cd7251 JG |
865 | * selection of dividers |
866 | * | |
669a5db4 | 867 | * Handy rule: Odd modes are UDMATIMx 01, even are 02 |
85cd7251 | 868 | * except UDMA0 which is 00 |
669a5db4 JG |
869 | */ |
870 | u_speed = min(2 - (udma & 1), udma); | |
871 | if (udma == 5) | |
872 | u_clock = 0x1000; /* 100Mhz */ | |
873 | else if (udma > 2) | |
874 | u_clock = 1; /* 66Mhz */ | |
875 | else | |
876 | u_clock = 0; /* 33Mhz */ | |
85cd7251 | 877 | |
669a5db4 | 878 | udma_enable |= (1 << devid); |
85cd7251 | 879 | |
669a5db4 JG |
880 | /* Load the CT/RP selection */ |
881 | pci_read_config_word(dev, 0x4A, &udma_timing); | |
882 | udma_timing &= ~(3 << (4 * devid)); | |
883 | udma_timing |= u_speed << (4 * devid); | |
884 | pci_write_config_word(dev, 0x4A, udma_timing); | |
885 | ||
85cd7251 | 886 | if (isich) { |
669a5db4 JG |
887 | /* Select a 33/66/100Mhz clock */ |
888 | pci_read_config_word(dev, 0x54, &ideconf); | |
889 | ideconf &= ~(0x1001 << devid); | |
890 | ideconf |= u_clock << devid; | |
891 | /* For ICH or later we should set bit 10 for better | |
892 | performance (WR_PingPong_En) */ | |
893 | pci_write_config_word(dev, 0x54, ideconf); | |
1da177e4 | 894 | } |
1da177e4 | 895 | } else { |
669a5db4 JG |
896 | /* |
897 | * MWDMA is driven by the PIO timings. We must also enable | |
898 | * IORDY unconditionally along with TIME1. PPE has already | |
899 | * been set when the PIO timing was set. | |
900 | */ | |
901 | unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; | |
902 | unsigned int control; | |
903 | u8 slave_data; | |
904 | const unsigned int needed_pio[3] = { | |
905 | XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 | |
906 | }; | |
907 | int pio = needed_pio[mwdma] - XFER_PIO_0; | |
85cd7251 | 908 | |
669a5db4 | 909 | control = 3; /* IORDY|TIME1 */ |
85cd7251 | 910 | |
669a5db4 JG |
911 | /* If the drive MWDMA is faster than it can do PIO then |
912 | we must force PIO into PIO0 */ | |
85cd7251 | 913 | |
669a5db4 JG |
914 | if (adev->pio_mode < needed_pio[mwdma]) |
915 | /* Enable DMA timing only */ | |
916 | control |= 8; /* PIO cycles in PIO0 */ | |
917 | ||
918 | if (adev->devno) { /* Slave */ | |
919 | master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ | |
920 | master_data |= control << 4; | |
921 | pci_read_config_byte(dev, 0x44, &slave_data); | |
a5bf5f5a | 922 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db4 JG |
923 | /* Load the matching timing */ |
924 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); | |
925 | pci_write_config_byte(dev, 0x44, slave_data); | |
926 | } else { /* Master */ | |
85cd7251 | 927 | master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY |
669a5db4 JG |
928 | and master timing bits */ |
929 | master_data |= control; | |
930 | master_data |= | |
931 | (timings[pio][0] << 12) | | |
932 | (timings[pio][1] << 8); | |
933 | } | |
a5bf5f5a TH |
934 | |
935 | if (ap->udma_mask) { | |
936 | udma_enable &= ~(1 << devid); | |
937 | pci_write_config_word(dev, master_port, master_data); | |
938 | } | |
1da177e4 | 939 | } |
669a5db4 JG |
940 | /* Don't scribble on 0x48 if the controller does not support UDMA */ |
941 | if (ap->udma_mask) | |
942 | pci_write_config_byte(dev, 0x48, udma_enable); | |
943 | } | |
944 | ||
945 | /** | |
946 | * piix_set_dmamode - Initialize host controller PATA DMA timings | |
947 | * @ap: Port whose timings we are configuring | |
948 | * @adev: um | |
949 | * | |
950 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
951 | * | |
952 | * LOCKING: | |
953 | * None (inherited from caller). | |
954 | */ | |
955 | ||
2dcb407e | 956 | static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 JG |
957 | { |
958 | do_pata_set_dmamode(ap, adev, 0); | |
959 | } | |
960 | ||
961 | /** | |
962 | * ich_set_dmamode - Initialize host controller PATA DMA timings | |
963 | * @ap: Port whose timings we are configuring | |
964 | * @adev: um | |
965 | * | |
966 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
967 | * | |
968 | * LOCKING: | |
969 | * None (inherited from caller). | |
970 | */ | |
971 | ||
2dcb407e | 972 | static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 JG |
973 | { |
974 | do_pata_set_dmamode(ap, adev, 1); | |
1da177e4 LT |
975 | } |
976 | ||
b8b275ef | 977 | #ifdef CONFIG_PM |
8c3832eb TH |
978 | static int piix_broken_suspend(void) |
979 | { | |
1855256c | 980 | static const struct dmi_system_id sysids[] = { |
4c74d4ec TH |
981 | { |
982 | .ident = "TECRA M3", | |
983 | .matches = { | |
984 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
985 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), | |
986 | }, | |
987 | }, | |
04d86d6f PS |
988 | { |
989 | .ident = "TECRA M3", | |
990 | .matches = { | |
991 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
992 | DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), | |
993 | }, | |
994 | }, | |
d1aa690a PS |
995 | { |
996 | .ident = "TECRA M4", | |
997 | .matches = { | |
998 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
999 | DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), | |
1000 | }, | |
1001 | }, | |
8c3832eb TH |
1002 | { |
1003 | .ident = "TECRA M5", | |
1004 | .matches = { | |
1005 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1006 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), | |
1007 | }, | |
b8b275ef | 1008 | }, |
ffe188dd PS |
1009 | { |
1010 | .ident = "TECRA M6", | |
1011 | .matches = { | |
1012 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1013 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), | |
1014 | }, | |
1015 | }, | |
5c08ea01 TH |
1016 | { |
1017 | .ident = "TECRA M7", | |
1018 | .matches = { | |
1019 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1020 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), | |
1021 | }, | |
1022 | }, | |
04d86d6f PS |
1023 | { |
1024 | .ident = "TECRA A8", | |
1025 | .matches = { | |
1026 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1027 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), | |
1028 | }, | |
1029 | }, | |
ffe188dd PS |
1030 | { |
1031 | .ident = "Satellite R20", | |
1032 | .matches = { | |
1033 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1034 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), | |
1035 | }, | |
1036 | }, | |
04d86d6f PS |
1037 | { |
1038 | .ident = "Satellite R25", | |
1039 | .matches = { | |
1040 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1041 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), | |
1042 | }, | |
1043 | }, | |
3cc0b9d3 TH |
1044 | { |
1045 | .ident = "Satellite U200", | |
1046 | .matches = { | |
1047 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1048 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), | |
1049 | }, | |
1050 | }, | |
04d86d6f PS |
1051 | { |
1052 | .ident = "Satellite U200", | |
1053 | .matches = { | |
1054 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1055 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), | |
1056 | }, | |
1057 | }, | |
62320e23 YC |
1058 | { |
1059 | .ident = "Satellite Pro U200", | |
1060 | .matches = { | |
1061 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1062 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), | |
1063 | }, | |
1064 | }, | |
8c3832eb TH |
1065 | { |
1066 | .ident = "Satellite U205", | |
1067 | .matches = { | |
1068 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1069 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), | |
1070 | }, | |
b8b275ef | 1071 | }, |
de753e5e TH |
1072 | { |
1073 | .ident = "SATELLITE U205", | |
1074 | .matches = { | |
1075 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1076 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), | |
1077 | }, | |
1078 | }, | |
8c3832eb TH |
1079 | { |
1080 | .ident = "Portege M500", | |
1081 | .matches = { | |
1082 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1083 | DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), | |
1084 | }, | |
b8b275ef | 1085 | }, |
7d051548 JG |
1086 | |
1087 | { } /* terminate list */ | |
8c3832eb | 1088 | }; |
7abe79c3 TH |
1089 | static const char *oemstrs[] = { |
1090 | "Tecra M3,", | |
1091 | }; | |
1092 | int i; | |
8c3832eb TH |
1093 | |
1094 | if (dmi_check_system(sysids)) | |
1095 | return 1; | |
1096 | ||
7abe79c3 TH |
1097 | for (i = 0; i < ARRAY_SIZE(oemstrs); i++) |
1098 | if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) | |
1099 | return 1; | |
1100 | ||
8c3832eb TH |
1101 | return 0; |
1102 | } | |
b8b275ef TH |
1103 | |
1104 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | |
1105 | { | |
1106 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1107 | unsigned long flags; | |
1108 | int rc = 0; | |
1109 | ||
1110 | rc = ata_host_suspend(host, mesg); | |
1111 | if (rc) | |
1112 | return rc; | |
1113 | ||
1114 | /* Some braindamaged ACPI suspend implementations expect the | |
1115 | * controller to be awake on entry; otherwise, it burns cpu | |
1116 | * cycles and power trying to do something to the sleeping | |
1117 | * beauty. | |
1118 | */ | |
8c3832eb | 1119 | if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) { |
b8b275ef TH |
1120 | pci_save_state(pdev); |
1121 | ||
1122 | /* mark its power state as "unknown", since we don't | |
1123 | * know if e.g. the BIOS will change its device state | |
1124 | * when we suspend. | |
1125 | */ | |
1126 | if (pdev->current_state == PCI_D0) | |
1127 | pdev->current_state = PCI_UNKNOWN; | |
1128 | ||
1129 | /* tell resume that it's waking up from broken suspend */ | |
1130 | spin_lock_irqsave(&host->lock, flags); | |
1131 | host->flags |= PIIX_HOST_BROKEN_SUSPEND; | |
1132 | spin_unlock_irqrestore(&host->lock, flags); | |
1133 | } else | |
1134 | ata_pci_device_do_suspend(pdev, mesg); | |
1135 | ||
1136 | return 0; | |
1137 | } | |
1138 | ||
1139 | static int piix_pci_device_resume(struct pci_dev *pdev) | |
1140 | { | |
1141 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1142 | unsigned long flags; | |
1143 | int rc; | |
1144 | ||
1145 | if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { | |
1146 | spin_lock_irqsave(&host->lock, flags); | |
1147 | host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; | |
1148 | spin_unlock_irqrestore(&host->lock, flags); | |
1149 | ||
1150 | pci_set_power_state(pdev, PCI_D0); | |
1151 | pci_restore_state(pdev); | |
1152 | ||
1153 | /* PCI device wasn't disabled during suspend. Use | |
0b62e13b TH |
1154 | * pci_reenable_device() to avoid affecting the enable |
1155 | * count. | |
b8b275ef | 1156 | */ |
0b62e13b | 1157 | rc = pci_reenable_device(pdev); |
b8b275ef TH |
1158 | if (rc) |
1159 | dev_printk(KERN_ERR, &pdev->dev, "failed to enable " | |
1160 | "device after resume (%d)\n", rc); | |
1161 | } else | |
1162 | rc = ata_pci_device_do_resume(pdev); | |
1163 | ||
1164 | if (rc == 0) | |
1165 | ata_host_resume(host); | |
1166 | ||
1167 | return rc; | |
1168 | } | |
1169 | #endif | |
1170 | ||
25f98131 TH |
1171 | static u8 piix_vmw_bmdma_status(struct ata_port *ap) |
1172 | { | |
1173 | return ata_bmdma_status(ap) & ~ATA_DMA_ERR; | |
1174 | } | |
1175 | ||
1da177e4 LT |
1176 | #define AHCI_PCI_BAR 5 |
1177 | #define AHCI_GLOBAL_CTL 0x04 | |
1178 | #define AHCI_ENABLE (1 << 31) | |
1179 | static int piix_disable_ahci(struct pci_dev *pdev) | |
1180 | { | |
ea6ba10b | 1181 | void __iomem *mmio; |
1da177e4 LT |
1182 | u32 tmp; |
1183 | int rc = 0; | |
1184 | ||
1185 | /* BUG: pci_enable_device has not yet been called. This | |
1186 | * works because this device is usually set up by BIOS. | |
1187 | */ | |
1188 | ||
374b1873 JG |
1189 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
1190 | !pci_resource_len(pdev, AHCI_PCI_BAR)) | |
1da177e4 | 1191 | return 0; |
7b6dbd68 | 1192 | |
374b1873 | 1193 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
1da177e4 LT |
1194 | if (!mmio) |
1195 | return -ENOMEM; | |
7b6dbd68 | 1196 | |
c47a631f | 1197 | tmp = ioread32(mmio + AHCI_GLOBAL_CTL); |
1da177e4 LT |
1198 | if (tmp & AHCI_ENABLE) { |
1199 | tmp &= ~AHCI_ENABLE; | |
c47a631f | 1200 | iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); |
1da177e4 | 1201 | |
c47a631f | 1202 | tmp = ioread32(mmio + AHCI_GLOBAL_CTL); |
1da177e4 LT |
1203 | if (tmp & AHCI_ENABLE) |
1204 | rc = -EIO; | |
1205 | } | |
7b6dbd68 | 1206 | |
374b1873 | 1207 | pci_iounmap(pdev, mmio); |
1da177e4 LT |
1208 | return rc; |
1209 | } | |
1210 | ||
c621b140 AC |
1211 | /** |
1212 | * piix_check_450nx_errata - Check for problem 450NX setup | |
c893a3ae | 1213 | * @ata_dev: the PCI device to check |
2e9edbf8 | 1214 | * |
c621b140 AC |
1215 | * Check for the present of 450NX errata #19 and errata #25. If |
1216 | * they are found return an error code so we can turn off DMA | |
1217 | */ | |
1218 | ||
1219 | static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) | |
1220 | { | |
1221 | struct pci_dev *pdev = NULL; | |
1222 | u16 cfg; | |
c621b140 | 1223 | int no_piix_dma = 0; |
2e9edbf8 | 1224 | |
2dcb407e | 1225 | while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { |
c621b140 AC |
1226 | /* Look for 450NX PXB. Check for problem configurations |
1227 | A PCI quirk checks bit 6 already */ | |
c621b140 AC |
1228 | pci_read_config_word(pdev, 0x41, &cfg); |
1229 | /* Only on the original revision: IDE DMA can hang */ | |
44c10138 | 1230 | if (pdev->revision == 0x00) |
c621b140 AC |
1231 | no_piix_dma = 1; |
1232 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
44c10138 | 1233 | else if (cfg & (1<<14) && pdev->revision < 5) |
c621b140 AC |
1234 | no_piix_dma = 2; |
1235 | } | |
31a34fe7 | 1236 | if (no_piix_dma) |
c621b140 | 1237 | dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); |
31a34fe7 | 1238 | if (no_piix_dma == 2) |
c621b140 AC |
1239 | dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); |
1240 | return no_piix_dma; | |
2e9edbf8 | 1241 | } |
c621b140 | 1242 | |
8b09f0da | 1243 | static void __devinit piix_init_pcs(struct ata_host *host, |
ea35d29e JG |
1244 | const struct piix_map_db *map_db) |
1245 | { | |
8b09f0da | 1246 | struct pci_dev *pdev = to_pci_dev(host->dev); |
ea35d29e JG |
1247 | u16 pcs, new_pcs; |
1248 | ||
1249 | pci_read_config_word(pdev, ICH5_PCS, &pcs); | |
1250 | ||
1251 | new_pcs = pcs | map_db->port_enable; | |
1252 | ||
1253 | if (new_pcs != pcs) { | |
1254 | DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); | |
1255 | pci_write_config_word(pdev, ICH5_PCS, new_pcs); | |
1256 | msleep(150); | |
1257 | } | |
1258 | } | |
1259 | ||
8b09f0da TH |
1260 | static const int *__devinit piix_init_sata_map(struct pci_dev *pdev, |
1261 | struct ata_port_info *pinfo, | |
1262 | const struct piix_map_db *map_db) | |
d33f58b8 | 1263 | { |
b4482a4b | 1264 | const int *map; |
d33f58b8 TH |
1265 | int i, invalid_map = 0; |
1266 | u8 map_value; | |
1267 | ||
1268 | pci_read_config_byte(pdev, ICH5_PMR, &map_value); | |
1269 | ||
1270 | map = map_db->map[map_value & map_db->mask]; | |
1271 | ||
1272 | dev_printk(KERN_INFO, &pdev->dev, "MAP ["); | |
1273 | for (i = 0; i < 4; i++) { | |
1274 | switch (map[i]) { | |
1275 | case RV: | |
1276 | invalid_map = 1; | |
1277 | printk(" XX"); | |
1278 | break; | |
1279 | ||
1280 | case NA: | |
1281 | printk(" --"); | |
1282 | break; | |
1283 | ||
1284 | case IDE: | |
1285 | WARN_ON((i & 1) || map[i + 1] != IDE); | |
669a5db4 | 1286 | pinfo[i / 2] = piix_port_info[ich_pata_100]; |
d33f58b8 TH |
1287 | i++; |
1288 | printk(" IDE IDE"); | |
1289 | break; | |
1290 | ||
1291 | default: | |
1292 | printk(" P%d", map[i]); | |
1293 | if (i & 1) | |
cca3974e | 1294 | pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; |
d33f58b8 TH |
1295 | break; |
1296 | } | |
1297 | } | |
1298 | printk(" ]\n"); | |
1299 | ||
1300 | if (invalid_map) | |
1301 | dev_printk(KERN_ERR, &pdev->dev, | |
1302 | "invalid MAP value %u\n", map_value); | |
1303 | ||
8b09f0da | 1304 | return map; |
d33f58b8 TH |
1305 | } |
1306 | ||
43a98f05 TH |
1307 | static void piix_iocfg_bit18_quirk(struct pci_dev *pdev) |
1308 | { | |
1855256c | 1309 | static const struct dmi_system_id sysids[] = { |
43a98f05 TH |
1310 | { |
1311 | /* Clevo M570U sets IOCFG bit 18 if the cdrom | |
1312 | * isn't used to boot the system which | |
1313 | * disables the channel. | |
1314 | */ | |
1315 | .ident = "M570U", | |
1316 | .matches = { | |
1317 | DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), | |
1318 | DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), | |
1319 | }, | |
1320 | }, | |
7d051548 JG |
1321 | |
1322 | { } /* terminate list */ | |
43a98f05 TH |
1323 | }; |
1324 | u32 iocfg; | |
1325 | ||
1326 | if (!dmi_check_system(sysids)) | |
1327 | return; | |
1328 | ||
1329 | /* The datasheet says that bit 18 is NOOP but certain systems | |
1330 | * seem to use it to disable a channel. Clear the bit on the | |
1331 | * affected systems. | |
1332 | */ | |
1333 | pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg); | |
1334 | if (iocfg & (1 << 18)) { | |
1335 | dev_printk(KERN_INFO, &pdev->dev, | |
1336 | "applying IOCFG bit18 quirk\n"); | |
1337 | iocfg &= ~(1 << 18); | |
1338 | pci_write_config_dword(pdev, PIIX_IOCFG, iocfg); | |
1339 | } | |
1340 | } | |
1341 | ||
1da177e4 LT |
1342 | /** |
1343 | * piix_init_one - Register PIIX ATA PCI device with kernel services | |
1344 | * @pdev: PCI device to register | |
1345 | * @ent: Entry in piix_pci_tbl matching with @pdev | |
1346 | * | |
1347 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
1348 | * and then hand over control to libata, for it to do the rest. | |
1349 | * | |
1350 | * LOCKING: | |
1351 | * Inherited from PCI layer (may sleep). | |
1352 | * | |
1353 | * RETURNS: | |
1354 | * Zero on success, or -ERRNO value. | |
1355 | */ | |
1356 | ||
2dcb407e | 1357 | static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
1358 | { |
1359 | static int printed_version; | |
24dc5f33 | 1360 | struct device *dev = &pdev->dev; |
d33f58b8 | 1361 | struct ata_port_info port_info[2]; |
1626aeb8 | 1362 | const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; |
cca3974e | 1363 | unsigned long port_flags; |
8b09f0da TH |
1364 | struct ata_host *host; |
1365 | struct piix_host_priv *hpriv; | |
1366 | int rc; | |
1da177e4 LT |
1367 | |
1368 | if (!printed_version++) | |
6248e647 JG |
1369 | dev_printk(KERN_DEBUG, &pdev->dev, |
1370 | "version " DRV_VERSION "\n"); | |
1da177e4 LT |
1371 | |
1372 | /* no hotplugging support (FIXME) */ | |
1373 | if (!in_module_init) | |
1374 | return -ENODEV; | |
1375 | ||
8b09f0da TH |
1376 | port_info[0] = piix_port_info[ent->driver_data]; |
1377 | port_info[1] = piix_port_info[ent->driver_data]; | |
1378 | ||
1379 | port_flags = port_info[0].flags; | |
1380 | ||
1381 | /* enable device and prepare host */ | |
1382 | rc = pcim_enable_device(pdev); | |
1383 | if (rc) | |
1384 | return rc; | |
1385 | ||
1386 | /* SATA map init can change port_info, do it before prepping host */ | |
24dc5f33 | 1387 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
d96715c1 TH |
1388 | if (!hpriv) |
1389 | return -ENOMEM; | |
1390 | ||
8b09f0da TH |
1391 | if (port_flags & ATA_FLAG_SATA) |
1392 | hpriv->map = piix_init_sata_map(pdev, port_info, | |
1393 | piix_map_db_table[ent->driver_data]); | |
1da177e4 | 1394 | |
8b09f0da TH |
1395 | rc = ata_pci_prepare_sff_host(pdev, ppi, &host); |
1396 | if (rc) | |
1397 | return rc; | |
1398 | host->private_data = hpriv; | |
ff0fc146 | 1399 | |
8b09f0da | 1400 | /* initialize controller */ |
cca3974e | 1401 | if (port_flags & PIIX_FLAG_AHCI) { |
8a60a071 JG |
1402 | u8 tmp; |
1403 | pci_read_config_byte(pdev, PIIX_SCC, &tmp); | |
1404 | if (tmp == PIIX_AHCI_DEVICE) { | |
1405 | int rc = piix_disable_ahci(pdev); | |
1406 | if (rc) | |
1407 | return rc; | |
1408 | } | |
1da177e4 LT |
1409 | } |
1410 | ||
8b09f0da TH |
1411 | if (port_flags & ATA_FLAG_SATA) |
1412 | piix_init_pcs(host, piix_map_db_table[ent->driver_data]); | |
1da177e4 | 1413 | |
43a98f05 TH |
1414 | /* apply IOCFG bit18 quirk */ |
1415 | piix_iocfg_bit18_quirk(pdev); | |
1416 | ||
1da177e4 LT |
1417 | /* On ICH5, some BIOSen disable the interrupt using the |
1418 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. | |
1419 | * On ICH6, this bit has the same effect, but only when | |
1420 | * MSI is disabled (and it is disabled, as we don't use | |
1421 | * message-signalled interrupts currently). | |
1422 | */ | |
cca3974e | 1423 | if (port_flags & PIIX_FLAG_CHECKINTR) |
a04ce0ff | 1424 | pci_intx(pdev, 1); |
1da177e4 | 1425 | |
c621b140 AC |
1426 | if (piix_check_450nx_errata(pdev)) { |
1427 | /* This writes into the master table but it does not | |
1428 | really matter for this errata as we will apply it to | |
1429 | all the PIIX devices on the board */ | |
8b09f0da TH |
1430 | host->ports[0]->mwdma_mask = 0; |
1431 | host->ports[0]->udma_mask = 0; | |
1432 | host->ports[1]->mwdma_mask = 0; | |
1433 | host->ports[1]->udma_mask = 0; | |
c621b140 | 1434 | } |
8b09f0da TH |
1435 | |
1436 | pci_set_master(pdev); | |
1437 | return ata_pci_activate_sff_host(host, ata_interrupt, &piix_sht); | |
1da177e4 LT |
1438 | } |
1439 | ||
1da177e4 LT |
1440 | static int __init piix_init(void) |
1441 | { | |
1442 | int rc; | |
1443 | ||
b7887196 PR |
1444 | DPRINTK("pci_register_driver\n"); |
1445 | rc = pci_register_driver(&piix_pci_driver); | |
1da177e4 LT |
1446 | if (rc) |
1447 | return rc; | |
1448 | ||
1449 | in_module_init = 0; | |
1450 | ||
1451 | DPRINTK("done\n"); | |
1452 | return 0; | |
1453 | } | |
1454 | ||
1da177e4 LT |
1455 | static void __exit piix_exit(void) |
1456 | { | |
1457 | pci_unregister_driver(&piix_pci_driver); | |
1458 | } | |
1459 | ||
1460 | module_init(piix_init); | |
1461 | module_exit(piix_exit); |