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1da177e4 | 1 | /* |
af36d7f0 JG |
2 | * ata_piix.c - Intel PATA/SATA controllers |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * | |
9 | * Copyright 2003-2005 Red Hat Inc | |
10 | * Copyright 2003-2005 Jeff Garzik | |
11 | * | |
12 | * | |
13 | * Copyright header from piix.c: | |
14 | * | |
15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
17 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
18 | * | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2, or (at your option) | |
23 | * any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; see the file COPYING. If not, write to | |
32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
33 | * | |
34 | * | |
35 | * libata documentation is available via 'make {ps|pdf}docs', | |
36 | * as Documentation/DocBook/libata.* | |
37 | * | |
38 | * Hardware documentation available at http://developer.intel.com/ | |
39 | * | |
d96212ed AC |
40 | * Documentation |
41 | * Publically available from Intel web site. Errata documentation | |
42 | * is also publically available. As an aide to anyone hacking on this | |
2c5ff671 | 43 | * driver the list of errata that are relevant is below, going back to |
d96212ed AC |
44 | * PIIX4. Older device documentation is now a bit tricky to find. |
45 | * | |
46 | * The chipsets all follow very much the same design. The orginal Triton | |
47 | * series chipsets do _not_ support independant device timings, but this | |
48 | * is fixed in Triton II. With the odd mobile exception the chips then | |
49 | * change little except in gaining more modes until SATA arrives. This | |
50 | * driver supports only the chips with independant timing (that is those | |
51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix | |
52 | * for the early chip drivers. | |
53 | * | |
54 | * Errata of note: | |
55 | * | |
56 | * Unfixable | |
57 | * PIIX4 errata #9 - Only on ultra obscure hw | |
58 | * ICH3 errata #13 - Not observed to affect real hw | |
59 | * by Intel | |
60 | * | |
61 | * Things we must deal with | |
62 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
63 | * (must stop/start dma to recover) | |
64 | * 440MX errata #15 - As PIIX4 errata #10 | |
65 | * PIIX4 errata #15 - Must not read control registers | |
66 | * during a PIO transfer | |
67 | * 440MX errata #13 - As PIIX4 errata #15 | |
68 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
69 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
70 | * ICH2 spec c #9 - Extra operations needed to handle | |
71 | * drive hotswap [NOT YET SUPPORTED] | |
72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
73 | * and must be dword aligned | |
74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
75 | * | |
76 | * Should have been BIOS fixed: | |
77 | * 450NX: errata #19 - DMA hangs on old 450NX | |
78 | * 450NX: errata #20 - DMA hangs on old 450NX | |
79 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
80 | * ICH3 errata #15 - IDE deadlock under high load | |
81 | * (BIOS must set dev 31 fn 0 bit 23) | |
82 | * ICH3 errata #18 - Don't use native mode | |
1da177e4 LT |
83 | */ |
84 | ||
85 | #include <linux/kernel.h> | |
86 | #include <linux/module.h> | |
87 | #include <linux/pci.h> | |
88 | #include <linux/init.h> | |
89 | #include <linux/blkdev.h> | |
90 | #include <linux/delay.h> | |
6248e647 | 91 | #include <linux/device.h> |
1da177e4 LT |
92 | #include <scsi/scsi_host.h> |
93 | #include <linux/libata.h> | |
b8b275ef | 94 | #include <linux/dmi.h> |
1da177e4 LT |
95 | |
96 | #define DRV_NAME "ata_piix" | |
2a3103ce | 97 | #define DRV_VERSION "2.12" |
1da177e4 LT |
98 | |
99 | enum { | |
100 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ | |
101 | ICH5_PMR = 0x90, /* port mapping register */ | |
102 | ICH5_PCS = 0x92, /* port control and status */ | |
c7290724 TH |
103 | PIIX_SIDPR_BAR = 5, |
104 | PIIX_SIDPR_LEN = 16, | |
105 | PIIX_SIDPR_IDX = 0, | |
106 | PIIX_SIDPR_DATA = 4, | |
1da177e4 | 107 | |
ff0fc146 | 108 | PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ |
c7290724 | 109 | PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ |
1da177e4 | 110 | |
800b3996 TH |
111 | PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, |
112 | PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, | |
b3362f88 | 113 | |
1da177e4 LT |
114 | PIIX_80C_PRI = (1 << 5) | (1 << 4), |
115 | PIIX_80C_SEC = (1 << 7) | (1 << 6), | |
116 | ||
d33f58b8 TH |
117 | /* constants for mapping table */ |
118 | P0 = 0, /* port 0 */ | |
119 | P1 = 1, /* port 1 */ | |
120 | P2 = 2, /* port 2 */ | |
121 | P3 = 3, /* port 3 */ | |
122 | IDE = -1, /* IDE */ | |
123 | NA = -2, /* not avaliable */ | |
124 | RV = -3, /* reserved */ | |
125 | ||
7b6dbd68 | 126 | PIIX_AHCI_DEVICE = 6, |
b8b275ef TH |
127 | |
128 | /* host->flags bits */ | |
129 | PIIX_HOST_BROKEN_SUSPEND = (1 << 24), | |
1da177e4 LT |
130 | }; |
131 | ||
9cde9ed1 TH |
132 | enum piix_controller_ids { |
133 | /* controller IDs */ | |
134 | piix_pata_mwdma, /* PIIX3 MWDMA only */ | |
135 | piix_pata_33, /* PIIX4 at 33Mhz */ | |
136 | ich_pata_33, /* ICH up to UDMA 33 only */ | |
137 | ich_pata_66, /* ICH up to 66 Mhz */ | |
138 | ich_pata_100, /* ICH up to UDMA 100 */ | |
139 | ich5_sata, | |
140 | ich6_sata, | |
9c0bf675 TH |
141 | ich6m_sata, |
142 | ich8_sata, | |
9cde9ed1 | 143 | ich8_2port_sata, |
9c0bf675 TH |
144 | ich8m_apple_sata, /* locks up on second port enable */ |
145 | tolapai_sata, | |
9cde9ed1 TH |
146 | piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ |
147 | }; | |
148 | ||
d33f58b8 TH |
149 | struct piix_map_db { |
150 | const u32 mask; | |
73291a1c | 151 | const u16 port_enable; |
d33f58b8 TH |
152 | const int map[][4]; |
153 | }; | |
154 | ||
d96715c1 TH |
155 | struct piix_host_priv { |
156 | const int *map; | |
c7290724 | 157 | void __iomem *sidpr; |
d96715c1 TH |
158 | }; |
159 | ||
2dcb407e JG |
160 | static int piix_init_one(struct pci_dev *pdev, |
161 | const struct pci_device_id *ent); | |
a1efdaba | 162 | static int piix_pata_prereset(struct ata_link *link, unsigned long deadline); |
2dcb407e JG |
163 | static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); |
164 | static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); | |
165 | static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); | |
eb4a2c7f | 166 | static int ich_pata_cable_detect(struct ata_port *ap); |
25f98131 | 167 | static u8 piix_vmw_bmdma_status(struct ata_port *ap); |
a1efdaba TH |
168 | static int piix_sidpr_hardreset(struct ata_link *link, unsigned int *class, |
169 | unsigned long deadline); | |
c7290724 TH |
170 | static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val); |
171 | static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val); | |
b8b275ef TH |
172 | #ifdef CONFIG_PM |
173 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); | |
174 | static int piix_pci_device_resume(struct pci_dev *pdev); | |
175 | #endif | |
1da177e4 LT |
176 | |
177 | static unsigned int in_module_init = 1; | |
178 | ||
3b7d697d | 179 | static const struct pci_device_id piix_pci_tbl[] = { |
d2cdfc0d AC |
180 | /* Intel PIIX3 for the 430HX etc */ |
181 | { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, | |
25f98131 TH |
182 | /* VMware ICH4 */ |
183 | { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw }, | |
669a5db4 JG |
184 | /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ |
185 | /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ | |
186 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
669a5db4 JG |
187 | /* Intel PIIX4 */ |
188 | { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
189 | /* Intel PIIX4 */ | |
190 | { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
191 | /* Intel PIIX */ | |
192 | { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
193 | /* Intel ICH (i810, i815, i840) UDMA 66*/ | |
194 | { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, | |
195 | /* Intel ICH0 : UDMA 33*/ | |
196 | { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, | |
197 | /* Intel ICH2M */ | |
198 | { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
199 | /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ | |
200 | { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
201 | /* Intel ICH3M */ | |
202 | { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
203 | /* Intel ICH3 (E7500/1) UDMA 100 */ | |
204 | { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
205 | /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ | |
206 | { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
207 | { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
208 | /* Intel ICH5 */ | |
2eb829e9 | 209 | { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
669a5db4 JG |
210 | /* C-ICH (i810E2) */ |
211 | { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
85cd7251 | 212 | /* ESB (855GME/875P + 6300ESB) UDMA 100 */ |
669a5db4 JG |
213 | { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
214 | /* ICH6 (and 6) (i915) UDMA 100 */ | |
215 | { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
216 | /* ICH7/7-R (i945, i975) UDMA 100*/ | |
2eb829e9 | 217 | { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
669a5db4 | 218 | { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
c1e6f28c CL |
219 | /* ICH8 Mobile PATA Controller */ |
220 | { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
1da177e4 LT |
221 | |
222 | /* NOTE: The following PCI ids must be kept in sync with the | |
223 | * list in drivers/pci/quirks.c. | |
224 | */ | |
225 | ||
1d076e5b | 226 | /* 82801EB (ICH5) */ |
1da177e4 | 227 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 228 | /* 82801EB (ICH5) */ |
1da177e4 | 229 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 230 | /* 6300ESB (ICH5 variant with broken PCS present bits) */ |
5e56a37c | 231 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 232 | /* 6300ESB pretending RAID */ |
5e56a37c | 233 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 234 | /* 82801FB/FW (ICH6/ICH6W) */ |
1da177e4 | 235 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
1d076e5b | 236 | /* 82801FR/FRW (ICH6R/ICH6RW) */ |
9c0bf675 | 237 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
5016d7d2 TH |
238 | /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented). |
239 | * Attach iff the controller is in IDE mode. */ | |
240 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, | |
9c0bf675 | 241 | PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata }, |
1d076e5b | 242 | /* 82801GB/GR/GH (ICH7, identical to ICH6) */ |
9c0bf675 | 243 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
1d076e5b | 244 | /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
9c0bf675 | 245 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata }, |
f98b6573 | 246 | /* Enterprise Southbridge 2 (631xESB/632xESB) */ |
9c0bf675 | 247 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
f98b6573 | 248 | /* SATA Controller 1 IDE (ICH8) */ |
9c0bf675 | 249 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
f98b6573 | 250 | /* SATA Controller 2 IDE (ICH8) */ |
00242ec8 | 251 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 252 | /* Mobile SATA Controller IDE (ICH8M) */ |
9c0bf675 | 253 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
8d8ef2fb | 254 | /* Mobile SATA Controller IDE (ICH8M), Apple */ |
9c0bf675 | 255 | { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, |
f98b6573 | 256 | /* SATA Controller IDE (ICH9) */ |
9c0bf675 | 257 | { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
f98b6573 | 258 | /* SATA Controller IDE (ICH9) */ |
00242ec8 | 259 | { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 260 | /* SATA Controller IDE (ICH9) */ |
00242ec8 | 261 | { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 262 | /* SATA Controller IDE (ICH9M) */ |
00242ec8 | 263 | { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 264 | /* SATA Controller IDE (ICH9M) */ |
00242ec8 | 265 | { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 266 | /* SATA Controller IDE (ICH9M) */ |
9c0bf675 | 267 | { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
c5cf0ffa | 268 | /* SATA Controller IDE (Tolapai) */ |
9c0bf675 | 269 | { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata }, |
bf7f22b9 | 270 | /* SATA Controller IDE (ICH10) */ |
9c0bf675 | 271 | { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
bf7f22b9 JG |
272 | /* SATA Controller IDE (ICH10) */ |
273 | { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
274 | /* SATA Controller IDE (ICH10) */ | |
9c0bf675 | 275 | { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
bf7f22b9 JG |
276 | /* SATA Controller IDE (ICH10) */ |
277 | { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
1da177e4 LT |
278 | |
279 | { } /* terminate list */ | |
280 | }; | |
281 | ||
282 | static struct pci_driver piix_pci_driver = { | |
283 | .name = DRV_NAME, | |
284 | .id_table = piix_pci_tbl, | |
285 | .probe = piix_init_one, | |
286 | .remove = ata_pci_remove_one, | |
438ac6d5 | 287 | #ifdef CONFIG_PM |
b8b275ef TH |
288 | .suspend = piix_pci_device_suspend, |
289 | .resume = piix_pci_device_resume, | |
438ac6d5 | 290 | #endif |
1da177e4 LT |
291 | }; |
292 | ||
193515d5 | 293 | static struct scsi_host_template piix_sht = { |
68d1d07b | 294 | ATA_BMDMA_SHT(DRV_NAME), |
1da177e4 LT |
295 | }; |
296 | ||
029cfd6b TH |
297 | static struct ata_port_operations piix_pata_ops = { |
298 | .inherits = &ata_bmdma_port_ops, | |
299 | .cable_detect = ata_cable_40wire, | |
1da177e4 LT |
300 | .set_piomode = piix_set_piomode, |
301 | .set_dmamode = piix_set_dmamode, | |
a1efdaba | 302 | .prereset = piix_pata_prereset, |
1da177e4 LT |
303 | }; |
304 | ||
029cfd6b TH |
305 | static struct ata_port_operations piix_vmw_ops = { |
306 | .inherits = &piix_pata_ops, | |
307 | .bmdma_status = piix_vmw_bmdma_status, | |
669a5db4 JG |
308 | }; |
309 | ||
029cfd6b TH |
310 | static struct ata_port_operations ich_pata_ops = { |
311 | .inherits = &piix_pata_ops, | |
312 | .cable_detect = ich_pata_cable_detect, | |
313 | .set_dmamode = ich_set_dmamode, | |
1da177e4 LT |
314 | }; |
315 | ||
029cfd6b TH |
316 | static struct ata_port_operations piix_sata_ops = { |
317 | .inherits = &ata_bmdma_port_ops, | |
25f98131 TH |
318 | }; |
319 | ||
029cfd6b TH |
320 | static struct ata_port_operations piix_sidpr_sata_ops = { |
321 | .inherits = &piix_sata_ops, | |
a1efdaba | 322 | .hardreset = piix_sidpr_hardreset, |
c7290724 TH |
323 | .scr_read = piix_sidpr_scr_read, |
324 | .scr_write = piix_sidpr_scr_write, | |
c7290724 TH |
325 | }; |
326 | ||
d96715c1 | 327 | static const struct piix_map_db ich5_map_db = { |
d33f58b8 | 328 | .mask = 0x7, |
ea35d29e | 329 | .port_enable = 0x3, |
d33f58b8 TH |
330 | .map = { |
331 | /* PM PS SM SS MAP */ | |
332 | { P0, NA, P1, NA }, /* 000b */ | |
333 | { P1, NA, P0, NA }, /* 001b */ | |
334 | { RV, RV, RV, RV }, | |
335 | { RV, RV, RV, RV }, | |
336 | { P0, P1, IDE, IDE }, /* 100b */ | |
337 | { P1, P0, IDE, IDE }, /* 101b */ | |
338 | { IDE, IDE, P0, P1 }, /* 110b */ | |
339 | { IDE, IDE, P1, P0 }, /* 111b */ | |
340 | }, | |
341 | }; | |
342 | ||
d96715c1 | 343 | static const struct piix_map_db ich6_map_db = { |
d33f58b8 | 344 | .mask = 0x3, |
ea35d29e | 345 | .port_enable = 0xf, |
d33f58b8 TH |
346 | .map = { |
347 | /* PM PS SM SS MAP */ | |
79ea24e7 | 348 | { P0, P2, P1, P3 }, /* 00b */ |
d33f58b8 TH |
349 | { IDE, IDE, P1, P3 }, /* 01b */ |
350 | { P0, P2, IDE, IDE }, /* 10b */ | |
351 | { RV, RV, RV, RV }, | |
352 | }, | |
353 | }; | |
354 | ||
d96715c1 | 355 | static const struct piix_map_db ich6m_map_db = { |
d33f58b8 | 356 | .mask = 0x3, |
ea35d29e | 357 | .port_enable = 0x5, |
67083741 TH |
358 | |
359 | /* Map 01b isn't specified in the doc but some notebooks use | |
c6446a4c TH |
360 | * it anyway. MAP 01b have been spotted on both ICH6M and |
361 | * ICH7M. | |
67083741 TH |
362 | */ |
363 | .map = { | |
364 | /* PM PS SM SS MAP */ | |
e04b3b9d | 365 | { P0, P2, NA, NA }, /* 00b */ |
67083741 TH |
366 | { IDE, IDE, P1, P3 }, /* 01b */ |
367 | { P0, P2, IDE, IDE }, /* 10b */ | |
368 | { RV, RV, RV, RV }, | |
369 | }, | |
370 | }; | |
371 | ||
08f12edc JG |
372 | static const struct piix_map_db ich8_map_db = { |
373 | .mask = 0x3, | |
a0ce9aca | 374 | .port_enable = 0xf, |
08f12edc JG |
375 | .map = { |
376 | /* PM PS SM SS MAP */ | |
158f30c8 | 377 | { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ |
08f12edc | 378 | { RV, RV, RV, RV }, |
ac2b0437 | 379 | { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ |
08f12edc JG |
380 | { RV, RV, RV, RV }, |
381 | }, | |
382 | }; | |
383 | ||
00242ec8 | 384 | static const struct piix_map_db ich8_2port_map_db = { |
e2d352af JG |
385 | .mask = 0x3, |
386 | .port_enable = 0x3, | |
387 | .map = { | |
388 | /* PM PS SM SS MAP */ | |
389 | { P0, NA, P1, NA }, /* 00b */ | |
390 | { RV, RV, RV, RV }, /* 01b */ | |
391 | { RV, RV, RV, RV }, /* 10b */ | |
392 | { RV, RV, RV, RV }, | |
393 | }, | |
c5cf0ffa JG |
394 | }; |
395 | ||
8d8ef2fb TR |
396 | static const struct piix_map_db ich8m_apple_map_db = { |
397 | .mask = 0x3, | |
398 | .port_enable = 0x1, | |
399 | .map = { | |
400 | /* PM PS SM SS MAP */ | |
401 | { P0, NA, NA, NA }, /* 00b */ | |
402 | { RV, RV, RV, RV }, | |
403 | { P0, P2, IDE, IDE }, /* 10b */ | |
404 | { RV, RV, RV, RV }, | |
405 | }, | |
406 | }; | |
407 | ||
00242ec8 | 408 | static const struct piix_map_db tolapai_map_db = { |
8f73a688 JG |
409 | .mask = 0x3, |
410 | .port_enable = 0x3, | |
411 | .map = { | |
412 | /* PM PS SM SS MAP */ | |
413 | { P0, NA, P1, NA }, /* 00b */ | |
414 | { RV, RV, RV, RV }, /* 01b */ | |
415 | { RV, RV, RV, RV }, /* 10b */ | |
416 | { RV, RV, RV, RV }, | |
417 | }, | |
418 | }; | |
419 | ||
d96715c1 TH |
420 | static const struct piix_map_db *piix_map_db_table[] = { |
421 | [ich5_sata] = &ich5_map_db, | |
d96715c1 | 422 | [ich6_sata] = &ich6_map_db, |
9c0bf675 TH |
423 | [ich6m_sata] = &ich6m_map_db, |
424 | [ich8_sata] = &ich8_map_db, | |
00242ec8 | 425 | [ich8_2port_sata] = &ich8_2port_map_db, |
9c0bf675 TH |
426 | [ich8m_apple_sata] = &ich8m_apple_map_db, |
427 | [tolapai_sata] = &tolapai_map_db, | |
d96715c1 TH |
428 | }; |
429 | ||
1da177e4 | 430 | static struct ata_port_info piix_port_info[] = { |
00242ec8 TH |
431 | [piix_pata_mwdma] = /* PIIX3 MWDMA only */ |
432 | { | |
00242ec8 TH |
433 | .flags = PIIX_PATA_FLAGS, |
434 | .pio_mask = 0x1f, /* pio0-4 */ | |
435 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | |
436 | .port_ops = &piix_pata_ops, | |
437 | }, | |
438 | ||
ec300d99 | 439 | [piix_pata_33] = /* PIIX4 at 33MHz */ |
1d076e5b | 440 | { |
b3362f88 | 441 | .flags = PIIX_PATA_FLAGS, |
1d076e5b | 442 | .pio_mask = 0x1f, /* pio0-4 */ |
669a5db4 | 443 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ |
1d076e5b TH |
444 | .udma_mask = ATA_UDMA_MASK_40C, |
445 | .port_ops = &piix_pata_ops, | |
446 | }, | |
447 | ||
ec300d99 | 448 | [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ |
669a5db4 | 449 | { |
b3362f88 | 450 | .flags = PIIX_PATA_FLAGS, |
669a5db4 JG |
451 | .pio_mask = 0x1f, /* pio 0-4 */ |
452 | .mwdma_mask = 0x06, /* Check: maybe 0x07 */ | |
453 | .udma_mask = ATA_UDMA2, /* UDMA33 */ | |
454 | .port_ops = &ich_pata_ops, | |
455 | }, | |
ec300d99 JG |
456 | |
457 | [ich_pata_66] = /* ICH controllers up to 66MHz */ | |
1da177e4 | 458 | { |
b3362f88 | 459 | .flags = PIIX_PATA_FLAGS, |
669a5db4 JG |
460 | .pio_mask = 0x1f, /* pio 0-4 */ |
461 | .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ | |
462 | .udma_mask = ATA_UDMA4, | |
463 | .port_ops = &ich_pata_ops, | |
464 | }, | |
85cd7251 | 465 | |
ec300d99 | 466 | [ich_pata_100] = |
669a5db4 | 467 | { |
b3362f88 | 468 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, |
1da177e4 | 469 | .pio_mask = 0x1f, /* pio0-4 */ |
1da177e4 | 470 | .mwdma_mask = 0x06, /* mwdma1-2 */ |
669a5db4 JG |
471 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
472 | .port_ops = &ich_pata_ops, | |
1da177e4 LT |
473 | }, |
474 | ||
ec300d99 | 475 | [ich5_sata] = |
1da177e4 | 476 | { |
228c1590 | 477 | .flags = PIIX_SATA_FLAGS, |
1da177e4 LT |
478 | .pio_mask = 0x1f, /* pio0-4 */ |
479 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 480 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
481 | .port_ops = &piix_sata_ops, |
482 | }, | |
483 | ||
ec300d99 | 484 | [ich6_sata] = |
1da177e4 | 485 | { |
723159c5 | 486 | .flags = PIIX_SATA_FLAGS, |
1da177e4 LT |
487 | .pio_mask = 0x1f, /* pio0-4 */ |
488 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 489 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
490 | .port_ops = &piix_sata_ops, |
491 | }, | |
492 | ||
9c0bf675 | 493 | [ich6m_sata] = |
c368ca4e | 494 | { |
5016d7d2 | 495 | .flags = PIIX_SATA_FLAGS, |
c368ca4e JG |
496 | .pio_mask = 0x1f, /* pio0-4 */ |
497 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 498 | .udma_mask = ATA_UDMA6, |
c368ca4e JG |
499 | .port_ops = &piix_sata_ops, |
500 | }, | |
1d076e5b | 501 | |
9c0bf675 | 502 | [ich8_sata] = |
08f12edc | 503 | { |
5016d7d2 | 504 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, |
08f12edc JG |
505 | .pio_mask = 0x1f, /* pio0-4 */ |
506 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 507 | .udma_mask = ATA_UDMA6, |
08f12edc JG |
508 | .port_ops = &piix_sata_ops, |
509 | }, | |
669a5db4 | 510 | |
00242ec8 | 511 | [ich8_2port_sata] = |
c5cf0ffa | 512 | { |
5016d7d2 | 513 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, |
c5cf0ffa JG |
514 | .pio_mask = 0x1f, /* pio0-4 */ |
515 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
516 | .udma_mask = ATA_UDMA6, | |
517 | .port_ops = &piix_sata_ops, | |
518 | }, | |
8f73a688 | 519 | |
9c0bf675 | 520 | [tolapai_sata] = |
8f73a688 | 521 | { |
5016d7d2 | 522 | .flags = PIIX_SATA_FLAGS, |
8f73a688 JG |
523 | .pio_mask = 0x1f, /* pio0-4 */ |
524 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
525 | .udma_mask = ATA_UDMA6, | |
526 | .port_ops = &piix_sata_ops, | |
527 | }, | |
8d8ef2fb | 528 | |
9c0bf675 | 529 | [ich8m_apple_sata] = |
8d8ef2fb | 530 | { |
5016d7d2 | 531 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, |
8d8ef2fb TR |
532 | .pio_mask = 0x1f, /* pio0-4 */ |
533 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
534 | .udma_mask = ATA_UDMA6, | |
535 | .port_ops = &piix_sata_ops, | |
536 | }, | |
537 | ||
25f98131 TH |
538 | [piix_pata_vmw] = |
539 | { | |
25f98131 TH |
540 | .flags = PIIX_PATA_FLAGS, |
541 | .pio_mask = 0x1f, /* pio0-4 */ | |
542 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | |
543 | .udma_mask = ATA_UDMA_MASK_40C, | |
544 | .port_ops = &piix_vmw_ops, | |
545 | }, | |
546 | ||
1da177e4 LT |
547 | }; |
548 | ||
549 | static struct pci_bits piix_enable_bits[] = { | |
550 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ | |
551 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ | |
552 | }; | |
553 | ||
554 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); | |
555 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); | |
556 | MODULE_LICENSE("GPL"); | |
557 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
558 | MODULE_VERSION(DRV_VERSION); | |
559 | ||
fc085150 AC |
560 | struct ich_laptop { |
561 | u16 device; | |
562 | u16 subvendor; | |
563 | u16 subdevice; | |
564 | }; | |
565 | ||
566 | /* | |
567 | * List of laptops that use short cables rather than 80 wire | |
568 | */ | |
569 | ||
570 | static const struct ich_laptop ich_laptop[] = { | |
571 | /* devid, subvendor, subdev */ | |
572 | { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ | |
2655e2ce | 573 | { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ |
babfb682 | 574 | { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ |
12340106 | 575 | { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ |
54174db3 | 576 | { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ |
b33620f9 | 577 | { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ |
fc085150 AC |
578 | /* end marker */ |
579 | { 0, } | |
580 | }; | |
581 | ||
1da177e4 | 582 | /** |
eb4a2c7f | 583 | * ich_pata_cable_detect - Probe host controller cable detect info |
1da177e4 LT |
584 | * @ap: Port for which cable detect info is desired |
585 | * | |
586 | * Read 80c cable indicator from ATA PCI device's PCI config | |
587 | * register. This register is normally set by firmware (BIOS). | |
588 | * | |
589 | * LOCKING: | |
590 | * None (inherited from caller). | |
591 | */ | |
669a5db4 | 592 | |
eb4a2c7f | 593 | static int ich_pata_cable_detect(struct ata_port *ap) |
1da177e4 | 594 | { |
cca3974e | 595 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
fc085150 | 596 | const struct ich_laptop *lap = &ich_laptop[0]; |
1da177e4 LT |
597 | u8 tmp, mask; |
598 | ||
fc085150 AC |
599 | /* Check for specials - Acer Aspire 5602WLMi */ |
600 | while (lap->device) { | |
601 | if (lap->device == pdev->device && | |
602 | lap->subvendor == pdev->subsystem_vendor && | |
2dcb407e | 603 | lap->subdevice == pdev->subsystem_device) |
eb4a2c7f | 604 | return ATA_CBL_PATA40_SHORT; |
2dcb407e | 605 | |
fc085150 AC |
606 | lap++; |
607 | } | |
608 | ||
1da177e4 | 609 | /* check BIOS cable detect results */ |
2a88d1ac | 610 | mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; |
1da177e4 LT |
611 | pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); |
612 | if ((tmp & mask) == 0) | |
eb4a2c7f AC |
613 | return ATA_CBL_PATA40; |
614 | return ATA_CBL_PATA80; | |
1da177e4 LT |
615 | } |
616 | ||
617 | /** | |
ccc4672a | 618 | * piix_pata_prereset - prereset for PATA host controller |
cc0680a5 | 619 | * @link: Target link |
d4b2bab4 | 620 | * @deadline: deadline jiffies for the operation |
1da177e4 | 621 | * |
573db6b8 TH |
622 | * LOCKING: |
623 | * None (inherited from caller). | |
624 | */ | |
cc0680a5 | 625 | static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) |
1da177e4 | 626 | { |
cc0680a5 | 627 | struct ata_port *ap = link->ap; |
cca3974e | 628 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
1da177e4 | 629 | |
c961922b AC |
630 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) |
631 | return -ENOENT; | |
cc0680a5 | 632 | return ata_std_prereset(link, deadline); |
ccc4672a TH |
633 | } |
634 | ||
1da177e4 LT |
635 | /** |
636 | * piix_set_piomode - Initialize host controller PATA PIO timings | |
637 | * @ap: Port whose timings we are configuring | |
638 | * @adev: um | |
1da177e4 LT |
639 | * |
640 | * Set PIO mode for device, in host controller PCI config space. | |
641 | * | |
642 | * LOCKING: | |
643 | * None (inherited from caller). | |
644 | */ | |
645 | ||
2dcb407e | 646 | static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) |
1da177e4 LT |
647 | { |
648 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
cca3974e | 649 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
1da177e4 | 650 | unsigned int is_slave = (adev->devno != 0); |
2a88d1ac | 651 | unsigned int master_port= ap->port_no ? 0x42 : 0x40; |
1da177e4 LT |
652 | unsigned int slave_port = 0x44; |
653 | u16 master_data; | |
654 | u8 slave_data; | |
669a5db4 JG |
655 | u8 udma_enable; |
656 | int control = 0; | |
85cd7251 | 657 | |
669a5db4 JG |
658 | /* |
659 | * See Intel Document 298600-004 for the timing programing rules | |
660 | * for ICH controllers. | |
661 | */ | |
1da177e4 LT |
662 | |
663 | static const /* ISP RTC */ | |
664 | u8 timings[][2] = { { 0, 0 }, | |
665 | { 0, 0 }, | |
666 | { 1, 0 }, | |
667 | { 2, 1 }, | |
668 | { 2, 3 }, }; | |
669 | ||
669a5db4 JG |
670 | if (pio >= 2) |
671 | control |= 1; /* TIME1 enable */ | |
672 | if (ata_pio_need_iordy(adev)) | |
673 | control |= 2; /* IE enable */ | |
674 | ||
85cd7251 | 675 | /* Intel specifies that the PPE functionality is for disk only */ |
669a5db4 JG |
676 | if (adev->class == ATA_DEV_ATA) |
677 | control |= 4; /* PPE enable */ | |
678 | ||
a5bf5f5a TH |
679 | /* PIO configuration clears DTE unconditionally. It will be |
680 | * programmed in set_dmamode which is guaranteed to be called | |
681 | * after set_piomode if any DMA mode is available. | |
682 | */ | |
1da177e4 LT |
683 | pci_read_config_word(dev, master_port, &master_data); |
684 | if (is_slave) { | |
a5bf5f5a TH |
685 | /* clear TIME1|IE1|PPE1|DTE1 */ |
686 | master_data &= 0xff0f; | |
1967b7ff | 687 | /* Enable SITRE (separate slave timing register) */ |
1da177e4 | 688 | master_data |= 0x4000; |
669a5db4 JG |
689 | /* enable PPE1, IE1 and TIME1 as needed */ |
690 | master_data |= (control << 4); | |
1da177e4 | 691 | pci_read_config_byte(dev, slave_port, &slave_data); |
2a88d1ac | 692 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db4 | 693 | /* Load the timing nibble for this slave */ |
a5bf5f5a TH |
694 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) |
695 | << (ap->port_no ? 4 : 0); | |
1da177e4 | 696 | } else { |
a5bf5f5a TH |
697 | /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ |
698 | master_data &= 0xccf0; | |
669a5db4 JG |
699 | /* Enable PPE, IE and TIME as appropriate */ |
700 | master_data |= control; | |
a5bf5f5a | 701 | /* load ISP and RCT */ |
1da177e4 LT |
702 | master_data |= |
703 | (timings[pio][0] << 12) | | |
704 | (timings[pio][1] << 8); | |
705 | } | |
706 | pci_write_config_word(dev, master_port, master_data); | |
707 | if (is_slave) | |
708 | pci_write_config_byte(dev, slave_port, slave_data); | |
669a5db4 JG |
709 | |
710 | /* Ensure the UDMA bit is off - it will be turned back on if | |
711 | UDMA is selected */ | |
85cd7251 | 712 | |
669a5db4 JG |
713 | if (ap->udma_mask) { |
714 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
715 | udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); | |
716 | pci_write_config_byte(dev, 0x48, udma_enable); | |
717 | } | |
1da177e4 LT |
718 | } |
719 | ||
720 | /** | |
669a5db4 | 721 | * do_pata_set_dmamode - Initialize host controller PATA PIO timings |
1da177e4 | 722 | * @ap: Port whose timings we are configuring |
669a5db4 | 723 | * @adev: Drive in question |
1da177e4 | 724 | * @udma: udma mode, 0 - 6 |
c32a8fd7 | 725 | * @isich: set if the chip is an ICH device |
1da177e4 LT |
726 | * |
727 | * Set UDMA mode for device, in host controller PCI config space. | |
728 | * | |
729 | * LOCKING: | |
730 | * None (inherited from caller). | |
731 | */ | |
732 | ||
2dcb407e | 733 | static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) |
1da177e4 | 734 | { |
cca3974e | 735 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
669a5db4 JG |
736 | u8 master_port = ap->port_no ? 0x42 : 0x40; |
737 | u16 master_data; | |
738 | u8 speed = adev->dma_mode; | |
739 | int devid = adev->devno + 2 * ap->port_no; | |
dedf61db | 740 | u8 udma_enable = 0; |
85cd7251 | 741 | |
669a5db4 JG |
742 | static const /* ISP RTC */ |
743 | u8 timings[][2] = { { 0, 0 }, | |
744 | { 0, 0 }, | |
745 | { 1, 0 }, | |
746 | { 2, 1 }, | |
747 | { 2, 3 }, }; | |
748 | ||
749 | pci_read_config_word(dev, master_port, &master_data); | |
d2cdfc0d AC |
750 | if (ap->udma_mask) |
751 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
1da177e4 LT |
752 | |
753 | if (speed >= XFER_UDMA_0) { | |
669a5db4 JG |
754 | unsigned int udma = adev->dma_mode - XFER_UDMA_0; |
755 | u16 udma_timing; | |
756 | u16 ideconf; | |
757 | int u_clock, u_speed; | |
85cd7251 | 758 | |
669a5db4 | 759 | /* |
2dcb407e | 760 | * UDMA is handled by a combination of clock switching and |
85cd7251 JG |
761 | * selection of dividers |
762 | * | |
669a5db4 | 763 | * Handy rule: Odd modes are UDMATIMx 01, even are 02 |
85cd7251 | 764 | * except UDMA0 which is 00 |
669a5db4 JG |
765 | */ |
766 | u_speed = min(2 - (udma & 1), udma); | |
767 | if (udma == 5) | |
768 | u_clock = 0x1000; /* 100Mhz */ | |
769 | else if (udma > 2) | |
770 | u_clock = 1; /* 66Mhz */ | |
771 | else | |
772 | u_clock = 0; /* 33Mhz */ | |
85cd7251 | 773 | |
669a5db4 | 774 | udma_enable |= (1 << devid); |
85cd7251 | 775 | |
669a5db4 JG |
776 | /* Load the CT/RP selection */ |
777 | pci_read_config_word(dev, 0x4A, &udma_timing); | |
778 | udma_timing &= ~(3 << (4 * devid)); | |
779 | udma_timing |= u_speed << (4 * devid); | |
780 | pci_write_config_word(dev, 0x4A, udma_timing); | |
781 | ||
85cd7251 | 782 | if (isich) { |
669a5db4 JG |
783 | /* Select a 33/66/100Mhz clock */ |
784 | pci_read_config_word(dev, 0x54, &ideconf); | |
785 | ideconf &= ~(0x1001 << devid); | |
786 | ideconf |= u_clock << devid; | |
787 | /* For ICH or later we should set bit 10 for better | |
788 | performance (WR_PingPong_En) */ | |
789 | pci_write_config_word(dev, 0x54, ideconf); | |
1da177e4 | 790 | } |
1da177e4 | 791 | } else { |
669a5db4 JG |
792 | /* |
793 | * MWDMA is driven by the PIO timings. We must also enable | |
794 | * IORDY unconditionally along with TIME1. PPE has already | |
795 | * been set when the PIO timing was set. | |
796 | */ | |
797 | unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; | |
798 | unsigned int control; | |
799 | u8 slave_data; | |
800 | const unsigned int needed_pio[3] = { | |
801 | XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 | |
802 | }; | |
803 | int pio = needed_pio[mwdma] - XFER_PIO_0; | |
85cd7251 | 804 | |
669a5db4 | 805 | control = 3; /* IORDY|TIME1 */ |
85cd7251 | 806 | |
669a5db4 JG |
807 | /* If the drive MWDMA is faster than it can do PIO then |
808 | we must force PIO into PIO0 */ | |
85cd7251 | 809 | |
669a5db4 JG |
810 | if (adev->pio_mode < needed_pio[mwdma]) |
811 | /* Enable DMA timing only */ | |
812 | control |= 8; /* PIO cycles in PIO0 */ | |
813 | ||
814 | if (adev->devno) { /* Slave */ | |
815 | master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ | |
816 | master_data |= control << 4; | |
817 | pci_read_config_byte(dev, 0x44, &slave_data); | |
a5bf5f5a | 818 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db4 JG |
819 | /* Load the matching timing */ |
820 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); | |
821 | pci_write_config_byte(dev, 0x44, slave_data); | |
822 | } else { /* Master */ | |
85cd7251 | 823 | master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY |
669a5db4 JG |
824 | and master timing bits */ |
825 | master_data |= control; | |
826 | master_data |= | |
827 | (timings[pio][0] << 12) | | |
828 | (timings[pio][1] << 8); | |
829 | } | |
a5bf5f5a TH |
830 | |
831 | if (ap->udma_mask) { | |
832 | udma_enable &= ~(1 << devid); | |
833 | pci_write_config_word(dev, master_port, master_data); | |
834 | } | |
1da177e4 | 835 | } |
669a5db4 JG |
836 | /* Don't scribble on 0x48 if the controller does not support UDMA */ |
837 | if (ap->udma_mask) | |
838 | pci_write_config_byte(dev, 0x48, udma_enable); | |
839 | } | |
840 | ||
841 | /** | |
842 | * piix_set_dmamode - Initialize host controller PATA DMA timings | |
843 | * @ap: Port whose timings we are configuring | |
844 | * @adev: um | |
845 | * | |
846 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
847 | * | |
848 | * LOCKING: | |
849 | * None (inherited from caller). | |
850 | */ | |
851 | ||
2dcb407e | 852 | static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 JG |
853 | { |
854 | do_pata_set_dmamode(ap, adev, 0); | |
855 | } | |
856 | ||
857 | /** | |
858 | * ich_set_dmamode - Initialize host controller PATA DMA timings | |
859 | * @ap: Port whose timings we are configuring | |
860 | * @adev: um | |
861 | * | |
862 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
863 | * | |
864 | * LOCKING: | |
865 | * None (inherited from caller). | |
866 | */ | |
867 | ||
2dcb407e | 868 | static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 JG |
869 | { |
870 | do_pata_set_dmamode(ap, adev, 1); | |
1da177e4 LT |
871 | } |
872 | ||
c7290724 TH |
873 | /* |
874 | * Serial ATA Index/Data Pair Superset Registers access | |
875 | * | |
876 | * Beginning from ICH8, there's a sane way to access SCRs using index | |
877 | * and data register pair located at BAR5. This creates an | |
878 | * interesting problem of mapping two SCRs to one port. | |
879 | * | |
880 | * Although they have separate SCRs, the master and slave aren't | |
881 | * independent enough to be treated as separate links - e.g. softreset | |
882 | * resets both. Also, there's no protocol defined for hard resetting | |
883 | * singled device sharing the virtual port (no defined way to acquire | |
884 | * device signature). This is worked around by merging the SCR values | |
885 | * into one sensible value and requesting follow-up SRST after | |
886 | * hardreset. | |
887 | * | |
888 | * SCR merging is perfomed in nibbles which is the unit contents in | |
889 | * SCRs are organized. If two values are equal, the value is used. | |
890 | * When they differ, merge table which lists precedence of possible | |
891 | * values is consulted and the first match or the last entry when | |
892 | * nothing matches is used. When there's no merge table for the | |
893 | * specific nibble, value from the first port is used. | |
894 | */ | |
895 | static const int piix_sidx_map[] = { | |
896 | [SCR_STATUS] = 0, | |
897 | [SCR_ERROR] = 2, | |
898 | [SCR_CONTROL] = 1, | |
899 | }; | |
900 | ||
901 | static void piix_sidpr_sel(struct ata_device *dev, unsigned int reg) | |
902 | { | |
903 | struct ata_port *ap = dev->link->ap; | |
904 | struct piix_host_priv *hpriv = ap->host->private_data; | |
905 | ||
906 | iowrite32(((ap->port_no * 2 + dev->devno) << 8) | piix_sidx_map[reg], | |
907 | hpriv->sidpr + PIIX_SIDPR_IDX); | |
908 | } | |
909 | ||
910 | static int piix_sidpr_read(struct ata_device *dev, unsigned int reg) | |
911 | { | |
912 | struct piix_host_priv *hpriv = dev->link->ap->host->private_data; | |
913 | ||
914 | piix_sidpr_sel(dev, reg); | |
915 | return ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); | |
916 | } | |
917 | ||
918 | static void piix_sidpr_write(struct ata_device *dev, unsigned int reg, u32 val) | |
919 | { | |
920 | struct piix_host_priv *hpriv = dev->link->ap->host->private_data; | |
921 | ||
922 | piix_sidpr_sel(dev, reg); | |
923 | iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); | |
924 | } | |
925 | ||
4a537a55 | 926 | static u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl) |
c7290724 TH |
927 | { |
928 | u32 val = 0; | |
929 | int i, mi; | |
930 | ||
931 | for (i = 0, mi = 0; i < 32 / 4; i++) { | |
932 | u8 c0 = (val0 >> (i * 4)) & 0xf; | |
933 | u8 c1 = (val1 >> (i * 4)) & 0xf; | |
934 | u8 merged = c0; | |
935 | const int *cur; | |
936 | ||
937 | /* if no merge preference, assume the first value */ | |
938 | cur = merge_tbl[mi]; | |
939 | if (!cur) | |
940 | goto done; | |
941 | mi++; | |
942 | ||
943 | /* if two values equal, use it */ | |
944 | if (c0 == c1) | |
945 | goto done; | |
946 | ||
947 | /* choose the first match or the last from the merge table */ | |
948 | while (*cur != -1) { | |
949 | if (c0 == *cur || c1 == *cur) | |
950 | break; | |
951 | cur++; | |
952 | } | |
953 | if (*cur == -1) | |
954 | cur--; | |
955 | merged = *cur; | |
956 | done: | |
957 | val |= merged << (i * 4); | |
958 | } | |
959 | ||
960 | return val; | |
961 | } | |
962 | ||
963 | static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val) | |
964 | { | |
965 | const int * const sstatus_merge_tbl[] = { | |
966 | /* DET */ (const int []){ 1, 3, 0, 4, 3, -1 }, | |
967 | /* SPD */ (const int []){ 2, 1, 0, -1 }, | |
968 | /* IPM */ (const int []){ 6, 2, 1, 0, -1 }, | |
969 | NULL, | |
970 | }; | |
971 | const int * const scontrol_merge_tbl[] = { | |
972 | /* DET */ (const int []){ 1, 0, 4, 0, -1 }, | |
973 | /* SPD */ (const int []){ 0, 2, 1, 0, -1 }, | |
974 | /* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 }, | |
975 | NULL, | |
976 | }; | |
977 | u32 v0, v1; | |
978 | ||
979 | if (reg >= ARRAY_SIZE(piix_sidx_map)) | |
980 | return -EINVAL; | |
981 | ||
982 | if (!(ap->flags & ATA_FLAG_SLAVE_POSS)) { | |
983 | *val = piix_sidpr_read(&ap->link.device[0], reg); | |
984 | return 0; | |
985 | } | |
986 | ||
987 | v0 = piix_sidpr_read(&ap->link.device[0], reg); | |
988 | v1 = piix_sidpr_read(&ap->link.device[1], reg); | |
989 | ||
990 | switch (reg) { | |
991 | case SCR_STATUS: | |
992 | *val = piix_merge_scr(v0, v1, sstatus_merge_tbl); | |
993 | break; | |
994 | case SCR_ERROR: | |
995 | *val = v0 | v1; | |
996 | break; | |
997 | case SCR_CONTROL: | |
998 | *val = piix_merge_scr(v0, v1, scontrol_merge_tbl); | |
999 | break; | |
1000 | } | |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | ||
1005 | static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val) | |
1006 | { | |
1007 | if (reg >= ARRAY_SIZE(piix_sidx_map)) | |
1008 | return -EINVAL; | |
1009 | ||
1010 | piix_sidpr_write(&ap->link.device[0], reg, val); | |
1011 | ||
1012 | if (ap->flags & ATA_FLAG_SLAVE_POSS) | |
1013 | piix_sidpr_write(&ap->link.device[1], reg, val); | |
1014 | ||
1015 | return 0; | |
1016 | } | |
1017 | ||
1018 | static int piix_sidpr_hardreset(struct ata_link *link, unsigned int *class, | |
1019 | unsigned long deadline) | |
1020 | { | |
1021 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); | |
1022 | int rc; | |
1023 | ||
1024 | /* do hardreset */ | |
1025 | rc = sata_link_hardreset(link, timing, deadline); | |
1026 | if (rc) { | |
1027 | ata_link_printk(link, KERN_ERR, | |
1028 | "COMRESET failed (errno=%d)\n", rc); | |
1029 | return rc; | |
1030 | } | |
1031 | ||
1032 | /* TODO: phy layer with polling, timeouts, etc. */ | |
1033 | if (ata_link_offline(link)) { | |
1034 | *class = ATA_DEV_NONE; | |
1035 | return 0; | |
1036 | } | |
1037 | ||
1038 | return -EAGAIN; | |
1039 | } | |
1040 | ||
b8b275ef | 1041 | #ifdef CONFIG_PM |
8c3832eb TH |
1042 | static int piix_broken_suspend(void) |
1043 | { | |
1855256c | 1044 | static const struct dmi_system_id sysids[] = { |
4c74d4ec TH |
1045 | { |
1046 | .ident = "TECRA M3", | |
1047 | .matches = { | |
1048 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1049 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), | |
1050 | }, | |
1051 | }, | |
04d86d6f PS |
1052 | { |
1053 | .ident = "TECRA M3", | |
1054 | .matches = { | |
1055 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1056 | DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), | |
1057 | }, | |
1058 | }, | |
d1aa690a PS |
1059 | { |
1060 | .ident = "TECRA M4", | |
1061 | .matches = { | |
1062 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1063 | DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), | |
1064 | }, | |
1065 | }, | |
8c3832eb TH |
1066 | { |
1067 | .ident = "TECRA M5", | |
1068 | .matches = { | |
1069 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1070 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), | |
1071 | }, | |
b8b275ef | 1072 | }, |
ffe188dd PS |
1073 | { |
1074 | .ident = "TECRA M6", | |
1075 | .matches = { | |
1076 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1077 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), | |
1078 | }, | |
1079 | }, | |
5c08ea01 TH |
1080 | { |
1081 | .ident = "TECRA M7", | |
1082 | .matches = { | |
1083 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1084 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), | |
1085 | }, | |
1086 | }, | |
04d86d6f PS |
1087 | { |
1088 | .ident = "TECRA A8", | |
1089 | .matches = { | |
1090 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1091 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), | |
1092 | }, | |
1093 | }, | |
ffe188dd PS |
1094 | { |
1095 | .ident = "Satellite R20", | |
1096 | .matches = { | |
1097 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1098 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), | |
1099 | }, | |
1100 | }, | |
04d86d6f PS |
1101 | { |
1102 | .ident = "Satellite R25", | |
1103 | .matches = { | |
1104 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1105 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), | |
1106 | }, | |
1107 | }, | |
3cc0b9d3 TH |
1108 | { |
1109 | .ident = "Satellite U200", | |
1110 | .matches = { | |
1111 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1112 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), | |
1113 | }, | |
1114 | }, | |
04d86d6f PS |
1115 | { |
1116 | .ident = "Satellite U200", | |
1117 | .matches = { | |
1118 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1119 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), | |
1120 | }, | |
1121 | }, | |
62320e23 YC |
1122 | { |
1123 | .ident = "Satellite Pro U200", | |
1124 | .matches = { | |
1125 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1126 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), | |
1127 | }, | |
1128 | }, | |
8c3832eb TH |
1129 | { |
1130 | .ident = "Satellite U205", | |
1131 | .matches = { | |
1132 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1133 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), | |
1134 | }, | |
b8b275ef | 1135 | }, |
de753e5e TH |
1136 | { |
1137 | .ident = "SATELLITE U205", | |
1138 | .matches = { | |
1139 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1140 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), | |
1141 | }, | |
1142 | }, | |
8c3832eb TH |
1143 | { |
1144 | .ident = "Portege M500", | |
1145 | .matches = { | |
1146 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1147 | DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), | |
1148 | }, | |
b8b275ef | 1149 | }, |
7d051548 JG |
1150 | |
1151 | { } /* terminate list */ | |
8c3832eb | 1152 | }; |
7abe79c3 TH |
1153 | static const char *oemstrs[] = { |
1154 | "Tecra M3,", | |
1155 | }; | |
1156 | int i; | |
8c3832eb TH |
1157 | |
1158 | if (dmi_check_system(sysids)) | |
1159 | return 1; | |
1160 | ||
7abe79c3 TH |
1161 | for (i = 0; i < ARRAY_SIZE(oemstrs); i++) |
1162 | if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) | |
1163 | return 1; | |
1164 | ||
8c3832eb TH |
1165 | return 0; |
1166 | } | |
b8b275ef TH |
1167 | |
1168 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | |
1169 | { | |
1170 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1171 | unsigned long flags; | |
1172 | int rc = 0; | |
1173 | ||
1174 | rc = ata_host_suspend(host, mesg); | |
1175 | if (rc) | |
1176 | return rc; | |
1177 | ||
1178 | /* Some braindamaged ACPI suspend implementations expect the | |
1179 | * controller to be awake on entry; otherwise, it burns cpu | |
1180 | * cycles and power trying to do something to the sleeping | |
1181 | * beauty. | |
1182 | */ | |
3a2d5b70 | 1183 | if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) { |
b8b275ef TH |
1184 | pci_save_state(pdev); |
1185 | ||
1186 | /* mark its power state as "unknown", since we don't | |
1187 | * know if e.g. the BIOS will change its device state | |
1188 | * when we suspend. | |
1189 | */ | |
1190 | if (pdev->current_state == PCI_D0) | |
1191 | pdev->current_state = PCI_UNKNOWN; | |
1192 | ||
1193 | /* tell resume that it's waking up from broken suspend */ | |
1194 | spin_lock_irqsave(&host->lock, flags); | |
1195 | host->flags |= PIIX_HOST_BROKEN_SUSPEND; | |
1196 | spin_unlock_irqrestore(&host->lock, flags); | |
1197 | } else | |
1198 | ata_pci_device_do_suspend(pdev, mesg); | |
1199 | ||
1200 | return 0; | |
1201 | } | |
1202 | ||
1203 | static int piix_pci_device_resume(struct pci_dev *pdev) | |
1204 | { | |
1205 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1206 | unsigned long flags; | |
1207 | int rc; | |
1208 | ||
1209 | if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { | |
1210 | spin_lock_irqsave(&host->lock, flags); | |
1211 | host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; | |
1212 | spin_unlock_irqrestore(&host->lock, flags); | |
1213 | ||
1214 | pci_set_power_state(pdev, PCI_D0); | |
1215 | pci_restore_state(pdev); | |
1216 | ||
1217 | /* PCI device wasn't disabled during suspend. Use | |
0b62e13b TH |
1218 | * pci_reenable_device() to avoid affecting the enable |
1219 | * count. | |
b8b275ef | 1220 | */ |
0b62e13b | 1221 | rc = pci_reenable_device(pdev); |
b8b275ef TH |
1222 | if (rc) |
1223 | dev_printk(KERN_ERR, &pdev->dev, "failed to enable " | |
1224 | "device after resume (%d)\n", rc); | |
1225 | } else | |
1226 | rc = ata_pci_device_do_resume(pdev); | |
1227 | ||
1228 | if (rc == 0) | |
1229 | ata_host_resume(host); | |
1230 | ||
1231 | return rc; | |
1232 | } | |
1233 | #endif | |
1234 | ||
25f98131 TH |
1235 | static u8 piix_vmw_bmdma_status(struct ata_port *ap) |
1236 | { | |
1237 | return ata_bmdma_status(ap) & ~ATA_DMA_ERR; | |
1238 | } | |
1239 | ||
1da177e4 LT |
1240 | #define AHCI_PCI_BAR 5 |
1241 | #define AHCI_GLOBAL_CTL 0x04 | |
1242 | #define AHCI_ENABLE (1 << 31) | |
1243 | static int piix_disable_ahci(struct pci_dev *pdev) | |
1244 | { | |
ea6ba10b | 1245 | void __iomem *mmio; |
1da177e4 LT |
1246 | u32 tmp; |
1247 | int rc = 0; | |
1248 | ||
1249 | /* BUG: pci_enable_device has not yet been called. This | |
1250 | * works because this device is usually set up by BIOS. | |
1251 | */ | |
1252 | ||
374b1873 JG |
1253 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
1254 | !pci_resource_len(pdev, AHCI_PCI_BAR)) | |
1da177e4 | 1255 | return 0; |
7b6dbd68 | 1256 | |
374b1873 | 1257 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
1da177e4 LT |
1258 | if (!mmio) |
1259 | return -ENOMEM; | |
7b6dbd68 | 1260 | |
c47a631f | 1261 | tmp = ioread32(mmio + AHCI_GLOBAL_CTL); |
1da177e4 LT |
1262 | if (tmp & AHCI_ENABLE) { |
1263 | tmp &= ~AHCI_ENABLE; | |
c47a631f | 1264 | iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); |
1da177e4 | 1265 | |
c47a631f | 1266 | tmp = ioread32(mmio + AHCI_GLOBAL_CTL); |
1da177e4 LT |
1267 | if (tmp & AHCI_ENABLE) |
1268 | rc = -EIO; | |
1269 | } | |
7b6dbd68 | 1270 | |
374b1873 | 1271 | pci_iounmap(pdev, mmio); |
1da177e4 LT |
1272 | return rc; |
1273 | } | |
1274 | ||
c621b140 AC |
1275 | /** |
1276 | * piix_check_450nx_errata - Check for problem 450NX setup | |
c893a3ae | 1277 | * @ata_dev: the PCI device to check |
2e9edbf8 | 1278 | * |
c621b140 AC |
1279 | * Check for the present of 450NX errata #19 and errata #25. If |
1280 | * they are found return an error code so we can turn off DMA | |
1281 | */ | |
1282 | ||
1283 | static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) | |
1284 | { | |
1285 | struct pci_dev *pdev = NULL; | |
1286 | u16 cfg; | |
c621b140 | 1287 | int no_piix_dma = 0; |
2e9edbf8 | 1288 | |
2dcb407e | 1289 | while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { |
c621b140 AC |
1290 | /* Look for 450NX PXB. Check for problem configurations |
1291 | A PCI quirk checks bit 6 already */ | |
c621b140 AC |
1292 | pci_read_config_word(pdev, 0x41, &cfg); |
1293 | /* Only on the original revision: IDE DMA can hang */ | |
44c10138 | 1294 | if (pdev->revision == 0x00) |
c621b140 AC |
1295 | no_piix_dma = 1; |
1296 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
44c10138 | 1297 | else if (cfg & (1<<14) && pdev->revision < 5) |
c621b140 AC |
1298 | no_piix_dma = 2; |
1299 | } | |
31a34fe7 | 1300 | if (no_piix_dma) |
c621b140 | 1301 | dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); |
31a34fe7 | 1302 | if (no_piix_dma == 2) |
c621b140 AC |
1303 | dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); |
1304 | return no_piix_dma; | |
2e9edbf8 | 1305 | } |
c621b140 | 1306 | |
8b09f0da | 1307 | static void __devinit piix_init_pcs(struct ata_host *host, |
ea35d29e JG |
1308 | const struct piix_map_db *map_db) |
1309 | { | |
8b09f0da | 1310 | struct pci_dev *pdev = to_pci_dev(host->dev); |
ea35d29e JG |
1311 | u16 pcs, new_pcs; |
1312 | ||
1313 | pci_read_config_word(pdev, ICH5_PCS, &pcs); | |
1314 | ||
1315 | new_pcs = pcs | map_db->port_enable; | |
1316 | ||
1317 | if (new_pcs != pcs) { | |
1318 | DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); | |
1319 | pci_write_config_word(pdev, ICH5_PCS, new_pcs); | |
1320 | msleep(150); | |
1321 | } | |
1322 | } | |
1323 | ||
8b09f0da TH |
1324 | static const int *__devinit piix_init_sata_map(struct pci_dev *pdev, |
1325 | struct ata_port_info *pinfo, | |
1326 | const struct piix_map_db *map_db) | |
d33f58b8 | 1327 | { |
b4482a4b | 1328 | const int *map; |
d33f58b8 TH |
1329 | int i, invalid_map = 0; |
1330 | u8 map_value; | |
1331 | ||
1332 | pci_read_config_byte(pdev, ICH5_PMR, &map_value); | |
1333 | ||
1334 | map = map_db->map[map_value & map_db->mask]; | |
1335 | ||
1336 | dev_printk(KERN_INFO, &pdev->dev, "MAP ["); | |
1337 | for (i = 0; i < 4; i++) { | |
1338 | switch (map[i]) { | |
1339 | case RV: | |
1340 | invalid_map = 1; | |
1341 | printk(" XX"); | |
1342 | break; | |
1343 | ||
1344 | case NA: | |
1345 | printk(" --"); | |
1346 | break; | |
1347 | ||
1348 | case IDE: | |
1349 | WARN_ON((i & 1) || map[i + 1] != IDE); | |
669a5db4 | 1350 | pinfo[i / 2] = piix_port_info[ich_pata_100]; |
d33f58b8 TH |
1351 | i++; |
1352 | printk(" IDE IDE"); | |
1353 | break; | |
1354 | ||
1355 | default: | |
1356 | printk(" P%d", map[i]); | |
1357 | if (i & 1) | |
cca3974e | 1358 | pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; |
d33f58b8 TH |
1359 | break; |
1360 | } | |
1361 | } | |
1362 | printk(" ]\n"); | |
1363 | ||
1364 | if (invalid_map) | |
1365 | dev_printk(KERN_ERR, &pdev->dev, | |
1366 | "invalid MAP value %u\n", map_value); | |
1367 | ||
8b09f0da | 1368 | return map; |
d33f58b8 TH |
1369 | } |
1370 | ||
c7290724 TH |
1371 | static void __devinit piix_init_sidpr(struct ata_host *host) |
1372 | { | |
1373 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
1374 | struct piix_host_priv *hpriv = host->private_data; | |
1375 | int i; | |
1376 | ||
1377 | /* check for availability */ | |
1378 | for (i = 0; i < 4; i++) | |
1379 | if (hpriv->map[i] == IDE) | |
1380 | return; | |
1381 | ||
1382 | if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) | |
1383 | return; | |
1384 | ||
1385 | if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || | |
1386 | pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN) | |
1387 | return; | |
1388 | ||
1389 | if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME)) | |
1390 | return; | |
1391 | ||
1392 | hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; | |
1393 | host->ports[0]->ops = &piix_sidpr_sata_ops; | |
1394 | host->ports[1]->ops = &piix_sidpr_sata_ops; | |
1395 | } | |
1396 | ||
43a98f05 TH |
1397 | static void piix_iocfg_bit18_quirk(struct pci_dev *pdev) |
1398 | { | |
1855256c | 1399 | static const struct dmi_system_id sysids[] = { |
43a98f05 TH |
1400 | { |
1401 | /* Clevo M570U sets IOCFG bit 18 if the cdrom | |
1402 | * isn't used to boot the system which | |
1403 | * disables the channel. | |
1404 | */ | |
1405 | .ident = "M570U", | |
1406 | .matches = { | |
1407 | DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), | |
1408 | DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), | |
1409 | }, | |
1410 | }, | |
7d051548 JG |
1411 | |
1412 | { } /* terminate list */ | |
43a98f05 TH |
1413 | }; |
1414 | u32 iocfg; | |
1415 | ||
1416 | if (!dmi_check_system(sysids)) | |
1417 | return; | |
1418 | ||
1419 | /* The datasheet says that bit 18 is NOOP but certain systems | |
1420 | * seem to use it to disable a channel. Clear the bit on the | |
1421 | * affected systems. | |
1422 | */ | |
1423 | pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg); | |
1424 | if (iocfg & (1 << 18)) { | |
1425 | dev_printk(KERN_INFO, &pdev->dev, | |
1426 | "applying IOCFG bit18 quirk\n"); | |
1427 | iocfg &= ~(1 << 18); | |
1428 | pci_write_config_dword(pdev, PIIX_IOCFG, iocfg); | |
1429 | } | |
1430 | } | |
1431 | ||
1da177e4 LT |
1432 | /** |
1433 | * piix_init_one - Register PIIX ATA PCI device with kernel services | |
1434 | * @pdev: PCI device to register | |
1435 | * @ent: Entry in piix_pci_tbl matching with @pdev | |
1436 | * | |
1437 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
1438 | * and then hand over control to libata, for it to do the rest. | |
1439 | * | |
1440 | * LOCKING: | |
1441 | * Inherited from PCI layer (may sleep). | |
1442 | * | |
1443 | * RETURNS: | |
1444 | * Zero on success, or -ERRNO value. | |
1445 | */ | |
1446 | ||
bc5468f5 AB |
1447 | static int __devinit piix_init_one(struct pci_dev *pdev, |
1448 | const struct pci_device_id *ent) | |
1da177e4 LT |
1449 | { |
1450 | static int printed_version; | |
24dc5f33 | 1451 | struct device *dev = &pdev->dev; |
d33f58b8 | 1452 | struct ata_port_info port_info[2]; |
1626aeb8 | 1453 | const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; |
cca3974e | 1454 | unsigned long port_flags; |
8b09f0da TH |
1455 | struct ata_host *host; |
1456 | struct piix_host_priv *hpriv; | |
1457 | int rc; | |
1da177e4 LT |
1458 | |
1459 | if (!printed_version++) | |
6248e647 JG |
1460 | dev_printk(KERN_DEBUG, &pdev->dev, |
1461 | "version " DRV_VERSION "\n"); | |
1da177e4 LT |
1462 | |
1463 | /* no hotplugging support (FIXME) */ | |
1464 | if (!in_module_init) | |
1465 | return -ENODEV; | |
1466 | ||
8b09f0da TH |
1467 | port_info[0] = piix_port_info[ent->driver_data]; |
1468 | port_info[1] = piix_port_info[ent->driver_data]; | |
1469 | ||
1470 | port_flags = port_info[0].flags; | |
1471 | ||
1472 | /* enable device and prepare host */ | |
1473 | rc = pcim_enable_device(pdev); | |
1474 | if (rc) | |
1475 | return rc; | |
1476 | ||
5016d7d2 TH |
1477 | /* ICH6R may be driven by either ata_piix or ahci driver |
1478 | * regardless of BIOS configuration. Make sure AHCI mode is | |
1479 | * off. | |
1480 | */ | |
1481 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { | |
1482 | int rc = piix_disable_ahci(pdev); | |
1483 | if (rc) | |
1484 | return rc; | |
1485 | } | |
1486 | ||
8b09f0da | 1487 | /* SATA map init can change port_info, do it before prepping host */ |
24dc5f33 | 1488 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
d96715c1 TH |
1489 | if (!hpriv) |
1490 | return -ENOMEM; | |
1491 | ||
8b09f0da TH |
1492 | if (port_flags & ATA_FLAG_SATA) |
1493 | hpriv->map = piix_init_sata_map(pdev, port_info, | |
1494 | piix_map_db_table[ent->driver_data]); | |
1da177e4 | 1495 | |
8b09f0da TH |
1496 | rc = ata_pci_prepare_sff_host(pdev, ppi, &host); |
1497 | if (rc) | |
1498 | return rc; | |
1499 | host->private_data = hpriv; | |
ff0fc146 | 1500 | |
8b09f0da | 1501 | /* initialize controller */ |
c7290724 | 1502 | if (port_flags & ATA_FLAG_SATA) { |
8b09f0da | 1503 | piix_init_pcs(host, piix_map_db_table[ent->driver_data]); |
c7290724 TH |
1504 | piix_init_sidpr(host); |
1505 | } | |
1da177e4 | 1506 | |
43a98f05 TH |
1507 | /* apply IOCFG bit18 quirk */ |
1508 | piix_iocfg_bit18_quirk(pdev); | |
1509 | ||
1da177e4 LT |
1510 | /* On ICH5, some BIOSen disable the interrupt using the |
1511 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. | |
1512 | * On ICH6, this bit has the same effect, but only when | |
1513 | * MSI is disabled (and it is disabled, as we don't use | |
1514 | * message-signalled interrupts currently). | |
1515 | */ | |
cca3974e | 1516 | if (port_flags & PIIX_FLAG_CHECKINTR) |
a04ce0ff | 1517 | pci_intx(pdev, 1); |
1da177e4 | 1518 | |
c621b140 AC |
1519 | if (piix_check_450nx_errata(pdev)) { |
1520 | /* This writes into the master table but it does not | |
1521 | really matter for this errata as we will apply it to | |
1522 | all the PIIX devices on the board */ | |
8b09f0da TH |
1523 | host->ports[0]->mwdma_mask = 0; |
1524 | host->ports[0]->udma_mask = 0; | |
1525 | host->ports[1]->mwdma_mask = 0; | |
1526 | host->ports[1]->udma_mask = 0; | |
c621b140 | 1527 | } |
8b09f0da TH |
1528 | |
1529 | pci_set_master(pdev); | |
1530 | return ata_pci_activate_sff_host(host, ata_interrupt, &piix_sht); | |
1da177e4 LT |
1531 | } |
1532 | ||
1da177e4 LT |
1533 | static int __init piix_init(void) |
1534 | { | |
1535 | int rc; | |
1536 | ||
b7887196 PR |
1537 | DPRINTK("pci_register_driver\n"); |
1538 | rc = pci_register_driver(&piix_pci_driver); | |
1da177e4 LT |
1539 | if (rc) |
1540 | return rc; | |
1541 | ||
1542 | in_module_init = 0; | |
1543 | ||
1544 | DPRINTK("done\n"); | |
1545 | return 0; | |
1546 | } | |
1547 | ||
1da177e4 LT |
1548 | static void __exit piix_exit(void) |
1549 | { | |
1550 | pci_unregister_driver(&piix_pci_driver); | |
1551 | } | |
1552 | ||
1553 | module_init(piix_init); | |
1554 | module_exit(piix_exit); |