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669a5db4 JG |
1 | /* |
2 | * pata-legacy.c - Legacy port PATA/SATA controller driver. | |
ab771630 | 3 | * Copyright 2005/2006 Red Hat, all rights reserved. |
669a5db4 JG |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2, or (at your option) | |
8 | * any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; see the file COPYING. If not, write to | |
17 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | * | |
19 | * An ATA driver for the legacy ATA ports. | |
20 | * | |
21 | * Data Sources: | |
22 | * Opti 82C465/82C611 support: Data sheets at opti-inc.com | |
23 | * HT6560 series: | |
24 | * Promise 20230/20620: | |
25 | * http://www.ryston.cz/petr/vlb/pdc20230b.html | |
26 | * http://www.ryston.cz/petr/vlb/pdc20230c.html | |
27 | * http://www.ryston.cz/petr/vlb/pdc20630.html | |
28 | * | |
29 | * Unsupported but docs exist: | |
30 | * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 | |
669a5db4 JG |
31 | * |
32 | * This driver handles legacy (that is "ISA/VLB side") IDE ports found | |
33 | * on PC class systems. There are three hybrid devices that are exceptions | |
34 | * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and | |
35 | * the MPIIX where the tuning is PCI side but the IDE is "ISA side". | |
36 | * | |
37 | * Specific support is included for the ht6560a/ht6560b/opti82c611a/ | |
b8325487 | 38 | * opti82c465mv/promise 20230c/20630/winbond83759A |
669a5db4 JG |
39 | * |
40 | * Use the autospeed and pio_mask options with: | |
41 | * Appian ADI/2 aka CLPD7220 or AIC25VL01. | |
42 | * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with | |
43 | * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, | |
44 | * Winbond W83759A, Promise PDC20230-B | |
45 | * | |
46 | * For now use autospeed and pio_mask as above with the W83759A. This may | |
47 | * change. | |
48 | * | |
669a5db4 JG |
49 | */ |
50 | ||
51 | #include <linux/kernel.h> | |
52 | #include <linux/module.h> | |
53 | #include <linux/pci.h> | |
54 | #include <linux/init.h> | |
55 | #include <linux/blkdev.h> | |
56 | #include <linux/delay.h> | |
57 | #include <scsi/scsi_host.h> | |
58 | #include <linux/ata.h> | |
59 | #include <linux/libata.h> | |
60 | #include <linux/platform_device.h> | |
61 | ||
62 | #define DRV_NAME "pata_legacy" | |
b8325487 | 63 | #define DRV_VERSION "0.6.5" |
669a5db4 JG |
64 | |
65 | #define NR_HOST 6 | |
66 | ||
defc9cd8 AC |
67 | static int all; |
68 | module_param(all, int, 0444); | |
69 | MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)"); | |
669a5db4 JG |
70 | |
71 | struct legacy_data { | |
72 | unsigned long timing; | |
73 | u8 clock[2]; | |
74 | u8 last; | |
75 | int fast; | |
76 | struct platform_device *platform_dev; | |
77 | ||
78 | }; | |
79 | ||
defc9cd8 AC |
80 | enum controller { |
81 | BIOS = 0, | |
82 | SNOOP = 1, | |
83 | PDC20230 = 2, | |
84 | HT6560A = 3, | |
85 | HT6560B = 4, | |
86 | OPTI611A = 5, | |
87 | OPTI46X = 6, | |
88 | QDI6500 = 7, | |
89 | QDI6580 = 8, | |
90 | QDI6580DP = 9, /* Dual channel mode is different */ | |
b8325487 | 91 | W83759A = 10, |
defc9cd8 AC |
92 | |
93 | UNKNOWN = -1 | |
94 | }; | |
95 | ||
96 | ||
97 | struct legacy_probe { | |
98 | unsigned char *name; | |
99 | unsigned long port; | |
100 | unsigned int irq; | |
101 | unsigned int slot; | |
102 | enum controller type; | |
103 | unsigned long private; | |
104 | }; | |
105 | ||
106 | struct legacy_controller { | |
107 | const char *name; | |
108 | struct ata_port_operations *ops; | |
109 | unsigned int pio_mask; | |
110 | unsigned int flags; | |
e3cf95dd | 111 | unsigned int pflags; |
b8325487 AC |
112 | int (*setup)(struct platform_device *, struct legacy_probe *probe, |
113 | struct legacy_data *data); | |
defc9cd8 AC |
114 | }; |
115 | ||
116 | static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; | |
117 | ||
118 | static struct legacy_probe probe_list[NR_HOST]; | |
669a5db4 JG |
119 | static struct legacy_data legacy_data[NR_HOST]; |
120 | static struct ata_host *legacy_host[NR_HOST]; | |
121 | static int nr_legacy_host; | |
122 | ||
123 | ||
defc9cd8 AC |
124 | static int probe_all; /* Set to check all ISA port ranges */ |
125 | static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */ | |
126 | static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */ | |
127 | static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */ | |
128 | static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */ | |
129 | static int qdi; /* Set to probe QDI controllers */ | |
b8325487 | 130 | static int winbond; /* Set to probe Winbond controllers, |
8397248d | 131 | give I/O port if non standard */ |
defc9cd8 | 132 | static int autospeed; /* Chip present which snoops speed changes */ |
14bdef98 | 133 | static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */ |
f834e49f | 134 | static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */ |
669a5db4 | 135 | |
defc9cd8 AC |
136 | /** |
137 | * legacy_probe_add - Add interface to probe list | |
138 | * @port: Controller port | |
139 | * @irq: IRQ number | |
140 | * @type: Controller type | |
141 | * @private: Controller specific info | |
142 | * | |
143 | * Add an entry into the probe list for ATA controllers. This is used | |
144 | * to add the default ISA slots and then to build up the table | |
145 | * further according to other ISA/VLB/Weird device scans | |
146 | * | |
147 | * An I/O port list is used to keep ordering stable and sane, as we | |
148 | * don't have any good way to talk about ordering otherwise | |
149 | */ | |
150 | ||
151 | static int legacy_probe_add(unsigned long port, unsigned int irq, | |
152 | enum controller type, unsigned long private) | |
153 | { | |
154 | struct legacy_probe *lp = &probe_list[0]; | |
155 | int i; | |
156 | struct legacy_probe *free = NULL; | |
157 | ||
158 | for (i = 0; i < NR_HOST; i++) { | |
159 | if (lp->port == 0 && free == NULL) | |
160 | free = lp; | |
161 | /* Matching port, or the correct slot for ordering */ | |
162 | if (lp->port == port || legacy_port[i] == port) { | |
163 | free = lp; | |
164 | break; | |
165 | } | |
166 | lp++; | |
167 | } | |
168 | if (free == NULL) { | |
169 | printk(KERN_ERR "pata_legacy: Too many interfaces.\n"); | |
170 | return -1; | |
171 | } | |
172 | /* Fill in the entry for later probing */ | |
173 | free->port = port; | |
174 | free->irq = irq; | |
175 | free->type = type; | |
176 | free->private = private; | |
177 | return 0; | |
178 | } | |
179 | ||
180 | ||
669a5db4 JG |
181 | /** |
182 | * legacy_set_mode - mode setting | |
0260731f | 183 | * @link: IDE link |
b229a7b0 | 184 | * @unused: Device that failed when error is returned |
669a5db4 JG |
185 | * |
186 | * Use a non standard set_mode function. We don't want to be tuned. | |
187 | * | |
188 | * The BIOS configured everything. Our job is not to fiddle. Just use | |
189 | * whatever PIO the hardware is using and leave it at that. When we | |
190 | * get some kind of nice user driven API for control then we can | |
191 | * expand on this as per hdparm in the base kernel. | |
192 | */ | |
193 | ||
0260731f | 194 | static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) |
669a5db4 | 195 | { |
f58229f8 | 196 | struct ata_device *dev; |
669a5db4 | 197 | |
1eca4365 TH |
198 | ata_for_each_dev(dev, link, ENABLED) { |
199 | ata_dev_printk(dev, KERN_INFO, "configured for PIO\n"); | |
200 | dev->pio_mode = XFER_PIO_0; | |
201 | dev->xfer_mode = XFER_PIO_0; | |
202 | dev->xfer_shift = ATA_SHIFT_PIO; | |
203 | dev->flags |= ATA_DFLAG_PIO; | |
669a5db4 | 204 | } |
b229a7b0 | 205 | return 0; |
669a5db4 JG |
206 | } |
207 | ||
208 | static struct scsi_host_template legacy_sht = { | |
68d1d07b | 209 | ATA_PIO_SHT(DRV_NAME), |
669a5db4 JG |
210 | }; |
211 | ||
029cfd6b TH |
212 | static const struct ata_port_operations legacy_base_port_ops = { |
213 | .inherits = &ata_sff_port_ops, | |
214 | .cable_detect = ata_cable_40wire, | |
215 | }; | |
216 | ||
669a5db4 JG |
217 | /* |
218 | * These ops are used if the user indicates the hardware | |
219 | * snoops the commands to decide on the mode and handles the | |
220 | * mode selection "magically" itself. Several legacy controllers | |
221 | * do this. The mode range can be set if it is not 0x1F by setting | |
222 | * pio_mask as well. | |
223 | */ | |
224 | ||
225 | static struct ata_port_operations simple_port_ops = { | |
029cfd6b | 226 | .inherits = &legacy_base_port_ops, |
5682ed33 | 227 | .sff_data_xfer = ata_sff_data_xfer_noirq, |
669a5db4 JG |
228 | }; |
229 | ||
230 | static struct ata_port_operations legacy_port_ops = { | |
029cfd6b | 231 | .inherits = &legacy_base_port_ops, |
5682ed33 | 232 | .sff_data_xfer = ata_sff_data_xfer_noirq, |
029cfd6b | 233 | .set_mode = legacy_set_mode, |
669a5db4 JG |
234 | }; |
235 | ||
236 | /* | |
237 | * Promise 20230C and 20620 support | |
238 | * | |
defc9cd8 AC |
239 | * This controller supports PIO0 to PIO2. We set PIO timings |
240 | * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA | |
241 | * support is weird being DMA to controller and PIO'd to the host | |
242 | * and not supported. | |
669a5db4 JG |
243 | */ |
244 | ||
245 | static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
246 | { | |
247 | int tries = 5; | |
248 | int pio = adev->pio_mode - XFER_PIO_0; | |
249 | u8 rt; | |
250 | unsigned long flags; | |
85cd7251 | 251 | |
669a5db4 | 252 | /* Safe as UP only. Force I/Os to occur together */ |
85cd7251 | 253 | |
669a5db4 | 254 | local_irq_save(flags); |
85cd7251 | 255 | |
669a5db4 | 256 | /* Unlock the control interface */ |
defc9cd8 | 257 | do { |
669a5db4 JG |
258 | inb(0x1F5); |
259 | outb(inb(0x1F2) | 0x80, 0x1F2); | |
260 | inb(0x1F2); | |
261 | inb(0x3F6); | |
262 | inb(0x3F6); | |
263 | inb(0x1F2); | |
264 | inb(0x1F2); | |
265 | } | |
defc9cd8 | 266 | while ((inb(0x1F2) & 0x80) && --tries); |
669a5db4 JG |
267 | |
268 | local_irq_restore(flags); | |
85cd7251 | 269 | |
669a5db4 JG |
270 | outb(inb(0x1F4) & 0x07, 0x1F4); |
271 | ||
272 | rt = inb(0x1F3); | |
273 | rt &= 0x07 << (3 * adev->devno); | |
274 | if (pio) | |
275 | rt |= (1 + 3 * pio) << (3 * adev->devno); | |
276 | ||
277 | udelay(100); | |
278 | outb(inb(0x1F2) | 0x01, 0x1F2); | |
279 | udelay(100); | |
280 | inb(0x1F5); | |
281 | ||
282 | } | |
283 | ||
55dba312 | 284 | static unsigned int pdc_data_xfer_vlb(struct ata_device *dev, |
defc9cd8 | 285 | unsigned char *buf, unsigned int buflen, int rw) |
669a5db4 | 286 | { |
c55af1f5 | 287 | int slop = buflen & 3; |
16e6aeca ZX |
288 | struct ata_port *ap = dev->link->ap; |
289 | ||
c55af1f5 | 290 | /* 32bit I/O capable *and* we need to write a whole number of dwords */ |
e3cf95dd AC |
291 | if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3) |
292 | && (ap->pflags & ATA_PFLAG_PIO32)) { | |
55dba312 TH |
293 | unsigned long flags; |
294 | ||
669a5db4 JG |
295 | local_irq_save(flags); |
296 | ||
297 | /* Perform the 32bit I/O synchronization sequence */ | |
0d5ff566 TH |
298 | ioread8(ap->ioaddr.nsect_addr); |
299 | ioread8(ap->ioaddr.nsect_addr); | |
300 | ioread8(ap->ioaddr.nsect_addr); | |
669a5db4 JG |
301 | |
302 | /* Now the data */ | |
55dba312 | 303 | if (rw == READ) |
0d5ff566 | 304 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
55dba312 TH |
305 | else |
306 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); | |
669a5db4 JG |
307 | |
308 | if (unlikely(slop)) { | |
6ad67403 | 309 | __le32 pad; |
55dba312 | 310 | if (rw == READ) { |
b50e56d8 | 311 | pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); |
669a5db4 | 312 | memcpy(buf + buflen - slop, &pad, slop); |
55dba312 TH |
313 | } else { |
314 | memcpy(&pad, buf + buflen - slop, slop); | |
315 | iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); | |
669a5db4 | 316 | } |
55dba312 | 317 | buflen += 4 - slop; |
669a5db4 JG |
318 | } |
319 | local_irq_restore(flags); | |
55dba312 | 320 | } else |
9363c382 | 321 | buflen = ata_sff_data_xfer_noirq(dev, buf, buflen, rw); |
55dba312 TH |
322 | |
323 | return buflen; | |
669a5db4 JG |
324 | } |
325 | ||
326 | static struct ata_port_operations pdc20230_port_ops = { | |
029cfd6b | 327 | .inherits = &legacy_base_port_ops, |
669a5db4 | 328 | .set_piomode = pdc20230_set_piomode, |
5682ed33 | 329 | .sff_data_xfer = pdc_data_xfer_vlb, |
669a5db4 JG |
330 | }; |
331 | ||
332 | /* | |
333 | * Holtek 6560A support | |
334 | * | |
defc9cd8 AC |
335 | * This controller supports PIO0 to PIO2 (no IORDY even though higher |
336 | * timings can be loaded). | |
669a5db4 JG |
337 | */ |
338 | ||
339 | static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
340 | { | |
341 | u8 active, recover; | |
342 | struct ata_timing t; | |
343 | ||
344 | /* Get the timing data in cycles. For now play safe at 50Mhz */ | |
345 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
346 | ||
07633b5d HH |
347 | active = clamp_val(t.active, 2, 15); |
348 | recover = clamp_val(t.recover, 4, 15); | |
669a5db4 JG |
349 | |
350 | inb(0x3E6); | |
351 | inb(0x3E6); | |
352 | inb(0x3E6); | |
353 | inb(0x3E6); | |
354 | ||
0d5ff566 TH |
355 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
356 | ioread8(ap->ioaddr.status_addr); | |
669a5db4 JG |
357 | } |
358 | ||
359 | static struct ata_port_operations ht6560a_port_ops = { | |
029cfd6b | 360 | .inherits = &legacy_base_port_ops, |
669a5db4 | 361 | .set_piomode = ht6560a_set_piomode, |
669a5db4 JG |
362 | }; |
363 | ||
364 | /* | |
365 | * Holtek 6560B support | |
366 | * | |
defc9cd8 AC |
367 | * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO |
368 | * setting unless we see an ATAPI device in which case we force it off. | |
669a5db4 JG |
369 | * |
370 | * FIXME: need to implement 2nd channel support. | |
371 | */ | |
372 | ||
373 | static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
374 | { | |
375 | u8 active, recover; | |
376 | struct ata_timing t; | |
377 | ||
378 | /* Get the timing data in cycles. For now play safe at 50Mhz */ | |
379 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
380 | ||
07633b5d HH |
381 | active = clamp_val(t.active, 2, 15); |
382 | recover = clamp_val(t.recover, 2, 16); | |
669a5db4 JG |
383 | recover &= 0x15; |
384 | ||
385 | inb(0x3E6); | |
386 | inb(0x3E6); | |
387 | inb(0x3E6); | |
388 | inb(0x3E6); | |
389 | ||
0d5ff566 | 390 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
669a5db4 JG |
391 | |
392 | if (adev->class != ATA_DEV_ATA) { | |
393 | u8 rconf = inb(0x3E6); | |
394 | if (rconf & 0x24) { | |
defc9cd8 | 395 | rconf &= ~0x24; |
669a5db4 JG |
396 | outb(rconf, 0x3E6); |
397 | } | |
398 | } | |
0d5ff566 | 399 | ioread8(ap->ioaddr.status_addr); |
669a5db4 JG |
400 | } |
401 | ||
402 | static struct ata_port_operations ht6560b_port_ops = { | |
029cfd6b | 403 | .inherits = &legacy_base_port_ops, |
669a5db4 | 404 | .set_piomode = ht6560b_set_piomode, |
669a5db4 JG |
405 | }; |
406 | ||
407 | /* | |
408 | * Opti core chipset helpers | |
409 | */ | |
85cd7251 | 410 | |
669a5db4 JG |
411 | /** |
412 | * opti_syscfg - read OPTI chipset configuration | |
413 | * @reg: Configuration register to read | |
414 | * | |
415 | * Returns the value of an OPTI system board configuration register. | |
416 | */ | |
417 | ||
418 | static u8 opti_syscfg(u8 reg) | |
419 | { | |
420 | unsigned long flags; | |
421 | u8 r; | |
85cd7251 | 422 | |
669a5db4 JG |
423 | /* Uniprocessor chipset and must force cycles adjancent */ |
424 | local_irq_save(flags); | |
425 | outb(reg, 0x22); | |
426 | r = inb(0x24); | |
427 | local_irq_restore(flags); | |
428 | return r; | |
429 | } | |
430 | ||
431 | /* | |
432 | * Opti 82C611A | |
433 | * | |
434 | * This controller supports PIO0 to PIO3. | |
435 | */ | |
436 | ||
defc9cd8 AC |
437 | static void opti82c611a_set_piomode(struct ata_port *ap, |
438 | struct ata_device *adev) | |
669a5db4 JG |
439 | { |
440 | u8 active, recover, setup; | |
441 | struct ata_timing t; | |
442 | struct ata_device *pair = ata_dev_pair(adev); | |
443 | int clock; | |
444 | int khz[4] = { 50000, 40000, 33000, 25000 }; | |
445 | u8 rc; | |
446 | ||
447 | /* Enter configuration mode */ | |
0d5ff566 TH |
448 | ioread16(ap->ioaddr.error_addr); |
449 | ioread16(ap->ioaddr.error_addr); | |
450 | iowrite8(3, ap->ioaddr.nsect_addr); | |
669a5db4 JG |
451 | |
452 | /* Read VLB clock strapping */ | |
0d5ff566 | 453 | clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; |
669a5db4 JG |
454 | |
455 | /* Get the timing data in cycles */ | |
456 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); | |
457 | ||
458 | /* Setup timing is shared */ | |
459 | if (pair) { | |
460 | struct ata_timing tp; | |
461 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); | |
462 | ||
463 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
464 | } | |
465 | ||
07633b5d HH |
466 | active = clamp_val(t.active, 2, 17) - 2; |
467 | recover = clamp_val(t.recover, 1, 16) - 1; | |
468 | setup = clamp_val(t.setup, 1, 4) - 1; | |
669a5db4 JG |
469 | |
470 | /* Select the right timing bank for write timing */ | |
0d5ff566 | 471 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
472 | rc &= 0x7F; |
473 | rc |= (adev->devno << 7); | |
0d5ff566 | 474 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
475 | |
476 | /* Write the timings */ | |
0d5ff566 | 477 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
669a5db4 JG |
478 | |
479 | /* Select the right bank for read timings, also | |
480 | load the shared timings for address */ | |
0d5ff566 | 481 | rc = ioread8(ap->ioaddr.device_addr); |
669a5db4 JG |
482 | rc &= 0xC0; |
483 | rc |= adev->devno; /* Index select */ | |
484 | rc |= (setup << 4) | 0x04; | |
0d5ff566 | 485 | iowrite8(rc, ap->ioaddr.device_addr); |
669a5db4 JG |
486 | |
487 | /* Load the read timings */ | |
0d5ff566 | 488 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db4 JG |
489 | |
490 | /* Ensure the timing register mode is right */ | |
0d5ff566 | 491 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
492 | rc &= 0x73; |
493 | rc |= 0x84; | |
0d5ff566 | 494 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
495 | |
496 | /* Exit command mode */ | |
0d5ff566 | 497 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db4 JG |
498 | } |
499 | ||
500 | ||
501 | static struct ata_port_operations opti82c611a_port_ops = { | |
029cfd6b | 502 | .inherits = &legacy_base_port_ops, |
669a5db4 | 503 | .set_piomode = opti82c611a_set_piomode, |
669a5db4 JG |
504 | }; |
505 | ||
506 | /* | |
507 | * Opti 82C465MV | |
508 | * | |
509 | * This controller supports PIO0 to PIO3. Unlike the 611A the MVB | |
510 | * version is dual channel but doesn't have a lot of unique registers. | |
511 | */ | |
512 | ||
513 | static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
514 | { | |
515 | u8 active, recover, setup; | |
516 | struct ata_timing t; | |
517 | struct ata_device *pair = ata_dev_pair(adev); | |
518 | int clock; | |
519 | int khz[4] = { 50000, 40000, 33000, 25000 }; | |
520 | u8 rc; | |
521 | u8 sysclk; | |
522 | ||
523 | /* Get the clock */ | |
524 | sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */ | |
525 | ||
526 | /* Enter configuration mode */ | |
0d5ff566 TH |
527 | ioread16(ap->ioaddr.error_addr); |
528 | ioread16(ap->ioaddr.error_addr); | |
529 | iowrite8(3, ap->ioaddr.nsect_addr); | |
669a5db4 JG |
530 | |
531 | /* Read VLB clock strapping */ | |
532 | clock = 1000000000 / khz[sysclk]; | |
533 | ||
534 | /* Get the timing data in cycles */ | |
535 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); | |
536 | ||
537 | /* Setup timing is shared */ | |
538 | if (pair) { | |
539 | struct ata_timing tp; | |
540 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); | |
541 | ||
542 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
543 | } | |
544 | ||
07633b5d HH |
545 | active = clamp_val(t.active, 2, 17) - 2; |
546 | recover = clamp_val(t.recover, 1, 16) - 1; | |
547 | setup = clamp_val(t.setup, 1, 4) - 1; | |
669a5db4 JG |
548 | |
549 | /* Select the right timing bank for write timing */ | |
0d5ff566 | 550 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
551 | rc &= 0x7F; |
552 | rc |= (adev->devno << 7); | |
0d5ff566 | 553 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
554 | |
555 | /* Write the timings */ | |
0d5ff566 | 556 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
669a5db4 JG |
557 | |
558 | /* Select the right bank for read timings, also | |
559 | load the shared timings for address */ | |
0d5ff566 | 560 | rc = ioread8(ap->ioaddr.device_addr); |
669a5db4 JG |
561 | rc &= 0xC0; |
562 | rc |= adev->devno; /* Index select */ | |
563 | rc |= (setup << 4) | 0x04; | |
0d5ff566 | 564 | iowrite8(rc, ap->ioaddr.device_addr); |
669a5db4 JG |
565 | |
566 | /* Load the read timings */ | |
0d5ff566 | 567 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db4 JG |
568 | |
569 | /* Ensure the timing register mode is right */ | |
0d5ff566 | 570 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
571 | rc &= 0x73; |
572 | rc |= 0x84; | |
0d5ff566 | 573 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
574 | |
575 | /* Exit command mode */ | |
0d5ff566 | 576 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db4 JG |
577 | |
578 | /* We need to know this for quad device on the MVB */ | |
579 | ap->host->private_data = ap; | |
580 | } | |
581 | ||
582 | /** | |
9363c382 | 583 | * opt82c465mv_qc_issue - command issue |
669a5db4 JG |
584 | * @qc: command pending |
585 | * | |
586 | * Called when the libata layer is about to issue a command. We wrap | |
587 | * this interface so that we can load the correct ATA timings. The | |
588 | * MVB has a single set of timing registers and these are shared | |
589 | * across channels. As there are two registers we really ought to | |
590 | * track the last two used values as a sort of register window. For | |
591 | * now we just reload on a channel switch. On the single channel | |
592 | * setup this condition never fires so we do nothing extra. | |
593 | * | |
594 | * FIXME: dual channel needs ->serialize support | |
595 | */ | |
596 | ||
9363c382 | 597 | static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc) |
669a5db4 JG |
598 | { |
599 | struct ata_port *ap = qc->ap; | |
600 | struct ata_device *adev = qc->dev; | |
601 | ||
602 | /* If timings are set and for the wrong channel (2nd test is | |
603 | due to a libata shortcoming and will eventually go I hope) */ | |
604 | if (ap->host->private_data != ap->host | |
605 | && ap->host->private_data != NULL) | |
606 | opti82c46x_set_piomode(ap, adev); | |
607 | ||
9363c382 | 608 | return ata_sff_qc_issue(qc); |
669a5db4 JG |
609 | } |
610 | ||
611 | static struct ata_port_operations opti82c46x_port_ops = { | |
029cfd6b | 612 | .inherits = &legacy_base_port_ops, |
669a5db4 | 613 | .set_piomode = opti82c46x_set_piomode, |
9363c382 | 614 | .qc_issue = opti82c46x_qc_issue, |
669a5db4 JG |
615 | }; |
616 | ||
defc9cd8 AC |
617 | static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev) |
618 | { | |
619 | struct ata_timing t; | |
cb616dd5 | 620 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 AC |
621 | int active, recovery; |
622 | u8 timing; | |
623 | ||
624 | /* Get the timing data in cycles */ | |
625 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
626 | ||
cb616dd5 | 627 | if (ld_qdi->fast) { |
07633b5d HH |
628 | active = 8 - clamp_val(t.active, 1, 8); |
629 | recovery = 18 - clamp_val(t.recover, 3, 18); | |
defc9cd8 | 630 | } else { |
07633b5d HH |
631 | active = 9 - clamp_val(t.active, 2, 9); |
632 | recovery = 15 - clamp_val(t.recover, 0, 15); | |
defc9cd8 AC |
633 | } |
634 | timing = (recovery << 4) | active | 0x08; | |
635 | ||
cb616dd5 | 636 | ld_qdi->clock[adev->devno] = timing; |
defc9cd8 | 637 | |
cb616dd5 | 638 | outb(timing, ld_qdi->timing); |
defc9cd8 | 639 | } |
669a5db4 JG |
640 | |
641 | /** | |
defc9cd8 AC |
642 | * qdi6580dp_set_piomode - PIO setup for dual channel |
643 | * @ap: Port | |
644 | * @adev: Device | |
669a5db4 | 645 | * |
defc9cd8 | 646 | * In dual channel mode the 6580 has one clock per channel and we have |
9363c382 | 647 | * to software clockswitch in qc_issue. |
669a5db4 JG |
648 | */ |
649 | ||
defc9cd8 | 650 | static void qdi6580dp_set_piomode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 | 651 | { |
defc9cd8 | 652 | struct ata_timing t; |
cb616dd5 | 653 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 AC |
654 | int active, recovery; |
655 | u8 timing; | |
669a5db4 | 656 | |
defc9cd8 AC |
657 | /* Get the timing data in cycles */ |
658 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
659 | ||
cb616dd5 | 660 | if (ld_qdi->fast) { |
07633b5d HH |
661 | active = 8 - clamp_val(t.active, 1, 8); |
662 | recovery = 18 - clamp_val(t.recover, 3, 18); | |
defc9cd8 | 663 | } else { |
07633b5d HH |
664 | active = 9 - clamp_val(t.active, 2, 9); |
665 | recovery = 15 - clamp_val(t.recover, 0, 15); | |
defc9cd8 AC |
666 | } |
667 | timing = (recovery << 4) | active | 0x08; | |
24dc5f33 | 668 | |
cb616dd5 | 669 | ld_qdi->clock[adev->devno] = timing; |
669a5db4 | 670 | |
cb616dd5 | 671 | outb(timing, ld_qdi->timing + 2 * ap->port_no); |
defc9cd8 AC |
672 | /* Clear the FIFO */ |
673 | if (adev->class != ATA_DEV_ATA) | |
cb616dd5 | 674 | outb(0x5F, ld_qdi->timing + 3); |
defc9cd8 | 675 | } |
0d5ff566 | 676 | |
defc9cd8 AC |
677 | /** |
678 | * qdi6580_set_piomode - PIO setup for single channel | |
679 | * @ap: Port | |
680 | * @adev: Device | |
681 | * | |
682 | * In single channel mode the 6580 has one clock per device and we can | |
683 | * avoid the requirement to clock switch. We also have to load the timing | |
684 | * into the right clock according to whether we are master or slave. | |
685 | */ | |
686 | ||
687 | static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
688 | { | |
689 | struct ata_timing t; | |
cb616dd5 | 690 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 AC |
691 | int active, recovery; |
692 | u8 timing; | |
693 | ||
694 | /* Get the timing data in cycles */ | |
695 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
696 | ||
cb616dd5 | 697 | if (ld_qdi->fast) { |
07633b5d HH |
698 | active = 8 - clamp_val(t.active, 1, 8); |
699 | recovery = 18 - clamp_val(t.recover, 3, 18); | |
defc9cd8 | 700 | } else { |
07633b5d HH |
701 | active = 9 - clamp_val(t.active, 2, 9); |
702 | recovery = 15 - clamp_val(t.recover, 0, 15); | |
669a5db4 | 703 | } |
defc9cd8 | 704 | timing = (recovery << 4) | active | 0x08; |
cb616dd5 HH |
705 | ld_qdi->clock[adev->devno] = timing; |
706 | outb(timing, ld_qdi->timing + 2 * adev->devno); | |
defc9cd8 AC |
707 | /* Clear the FIFO */ |
708 | if (adev->class != ATA_DEV_ATA) | |
cb616dd5 | 709 | outb(0x5F, ld_qdi->timing + 3); |
defc9cd8 AC |
710 | } |
711 | ||
712 | /** | |
9363c382 | 713 | * qdi_qc_issue - command issue |
defc9cd8 AC |
714 | * @qc: command pending |
715 | * | |
716 | * Called when the libata layer is about to issue a command. We wrap | |
717 | * this interface so that we can load the correct ATA timings. | |
718 | */ | |
719 | ||
9363c382 | 720 | static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc) |
defc9cd8 AC |
721 | { |
722 | struct ata_port *ap = qc->ap; | |
723 | struct ata_device *adev = qc->dev; | |
cb616dd5 | 724 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 | 725 | |
cb616dd5 | 726 | if (ld_qdi->clock[adev->devno] != ld_qdi->last) { |
defc9cd8 | 727 | if (adev->pio_mode) { |
cb616dd5 HH |
728 | ld_qdi->last = ld_qdi->clock[adev->devno]; |
729 | outb(ld_qdi->clock[adev->devno], ld_qdi->timing + | |
defc9cd8 AC |
730 | 2 * ap->port_no); |
731 | } | |
669a5db4 | 732 | } |
9363c382 | 733 | return ata_sff_qc_issue(qc); |
defc9cd8 | 734 | } |
669a5db4 | 735 | |
b8325487 | 736 | static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf, |
defc9cd8 AC |
737 | unsigned int buflen, int rw) |
738 | { | |
739 | struct ata_port *ap = adev->link->ap; | |
740 | int slop = buflen & 3; | |
669a5db4 | 741 | |
e3cf95dd AC |
742 | if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3) |
743 | && (ap->pflags & ATA_PFLAG_PIO32)) { | |
defc9cd8 AC |
744 | if (rw == WRITE) |
745 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); | |
746 | else | |
747 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); | |
669a5db4 | 748 | |
defc9cd8 | 749 | if (unlikely(slop)) { |
6ad67403 | 750 | __le32 pad; |
defc9cd8 AC |
751 | if (rw == WRITE) { |
752 | memcpy(&pad, buf + buflen - slop, slop); | |
6ad67403 | 753 | iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); |
defc9cd8 | 754 | } else { |
6ad67403 | 755 | pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); |
defc9cd8 AC |
756 | memcpy(buf + buflen - slop, &pad, slop); |
757 | } | |
758 | } | |
759 | return (buflen + 3) & ~3; | |
760 | } else | |
9363c382 | 761 | return ata_sff_data_xfer(adev, buf, buflen, rw); |
defc9cd8 AC |
762 | } |
763 | ||
b8325487 AC |
764 | static int qdi_port(struct platform_device *dev, |
765 | struct legacy_probe *lp, struct legacy_data *ld) | |
766 | { | |
767 | if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL) | |
768 | return -EBUSY; | |
769 | ld->timing = lp->private; | |
770 | return 0; | |
771 | } | |
772 | ||
defc9cd8 | 773 | static struct ata_port_operations qdi6500_port_ops = { |
029cfd6b | 774 | .inherits = &legacy_base_port_ops, |
defc9cd8 | 775 | .set_piomode = qdi6500_set_piomode, |
9363c382 | 776 | .qc_issue = qdi_qc_issue, |
5682ed33 | 777 | .sff_data_xfer = vlb32_data_xfer, |
defc9cd8 AC |
778 | }; |
779 | ||
780 | static struct ata_port_operations qdi6580_port_ops = { | |
029cfd6b | 781 | .inherits = &legacy_base_port_ops, |
defc9cd8 | 782 | .set_piomode = qdi6580_set_piomode, |
5682ed33 | 783 | .sff_data_xfer = vlb32_data_xfer, |
defc9cd8 AC |
784 | }; |
785 | ||
786 | static struct ata_port_operations qdi6580dp_port_ops = { | |
029cfd6b | 787 | .inherits = &legacy_base_port_ops, |
defc9cd8 | 788 | .set_piomode = qdi6580dp_set_piomode, |
5682ed33 | 789 | .sff_data_xfer = vlb32_data_xfer, |
defc9cd8 AC |
790 | }; |
791 | ||
b8325487 AC |
792 | static DEFINE_SPINLOCK(winbond_lock); |
793 | ||
794 | static void winbond_writecfg(unsigned long port, u8 reg, u8 val) | |
795 | { | |
796 | unsigned long flags; | |
797 | spin_lock_irqsave(&winbond_lock, flags); | |
798 | outb(reg, port + 0x01); | |
799 | outb(val, port + 0x02); | |
800 | spin_unlock_irqrestore(&winbond_lock, flags); | |
801 | } | |
802 | ||
803 | static u8 winbond_readcfg(unsigned long port, u8 reg) | |
804 | { | |
805 | u8 val; | |
806 | ||
807 | unsigned long flags; | |
808 | spin_lock_irqsave(&winbond_lock, flags); | |
809 | outb(reg, port + 0x01); | |
810 | val = inb(port + 0x02); | |
811 | spin_unlock_irqrestore(&winbond_lock, flags); | |
812 | ||
813 | return val; | |
814 | } | |
815 | ||
816 | static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
817 | { | |
818 | struct ata_timing t; | |
cb616dd5 | 819 | struct legacy_data *ld_winbond = ap->host->private_data; |
b8325487 AC |
820 | int active, recovery; |
821 | u8 reg; | |
822 | int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); | |
823 | ||
cb616dd5 | 824 | reg = winbond_readcfg(ld_winbond->timing, 0x81); |
b8325487 AC |
825 | |
826 | /* Get the timing data in cycles */ | |
827 | if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ | |
828 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
829 | else | |
830 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
831 | ||
07633b5d HH |
832 | active = (clamp_val(t.active, 3, 17) - 1) & 0x0F; |
833 | recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F; | |
b8325487 | 834 | timing = (active << 4) | recovery; |
cb616dd5 | 835 | winbond_writecfg(ld_winbond->timing, timing, reg); |
b8325487 AC |
836 | |
837 | /* Load the setup timing */ | |
838 | ||
839 | reg = 0x35; | |
840 | if (adev->class != ATA_DEV_ATA) | |
841 | reg |= 0x08; /* FIFO off */ | |
842 | if (!ata_pio_need_iordy(adev)) | |
843 | reg |= 0x02; /* IORDY off */ | |
07633b5d | 844 | reg |= (clamp_val(t.setup, 0, 3) << 6); |
cb616dd5 | 845 | winbond_writecfg(ld_winbond->timing, timing + 1, reg); |
b8325487 AC |
846 | } |
847 | ||
848 | static int winbond_port(struct platform_device *dev, | |
849 | struct legacy_probe *lp, struct legacy_data *ld) | |
850 | { | |
851 | if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL) | |
852 | return -EBUSY; | |
853 | ld->timing = lp->private; | |
854 | return 0; | |
855 | } | |
856 | ||
857 | static struct ata_port_operations winbond_port_ops = { | |
029cfd6b | 858 | .inherits = &legacy_base_port_ops, |
b8325487 | 859 | .set_piomode = winbond_set_piomode, |
5682ed33 | 860 | .sff_data_xfer = vlb32_data_xfer, |
b8325487 AC |
861 | }; |
862 | ||
defc9cd8 AC |
863 | static struct legacy_controller controllers[] = { |
864 | {"BIOS", &legacy_port_ops, 0x1F, | |
e3cf95dd | 865 | ATA_FLAG_NO_IORDY, 0, NULL }, |
defc9cd8 | 866 | {"Snooping", &simple_port_ops, 0x1F, |
e3cf95dd | 867 | 0, 0, NULL }, |
defc9cd8 | 868 | {"PDC20230", &pdc20230_port_ops, 0x7, |
e3cf95dd | 869 | ATA_FLAG_NO_IORDY, |
16e6aeca | 870 | ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL }, |
defc9cd8 | 871 | {"HT6560A", &ht6560a_port_ops, 0x07, |
e3cf95dd | 872 | ATA_FLAG_NO_IORDY, 0, NULL }, |
defc9cd8 | 873 | {"HT6560B", &ht6560b_port_ops, 0x1F, |
e3cf95dd | 874 | ATA_FLAG_NO_IORDY, 0, NULL }, |
defc9cd8 | 875 | {"OPTI82C611A", &opti82c611a_port_ops, 0x0F, |
e3cf95dd | 876 | 0, 0, NULL }, |
defc9cd8 | 877 | {"OPTI82C46X", &opti82c46x_port_ops, 0x0F, |
e3cf95dd | 878 | 0, 0, NULL }, |
defc9cd8 | 879 | {"QDI6500", &qdi6500_port_ops, 0x07, |
e3cf95dd | 880 | ATA_FLAG_NO_IORDY, |
16e6aeca | 881 | ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
defc9cd8 | 882 | {"QDI6580", &qdi6580_port_ops, 0x1F, |
16e6aeca | 883 | 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
defc9cd8 | 884 | {"QDI6580DP", &qdi6580dp_port_ops, 0x1F, |
16e6aeca | 885 | 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
b8325487 | 886 | {"W83759A", &winbond_port_ops, 0x1F, |
16e6aeca | 887 | 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, |
e3cf95dd | 888 | winbond_port } |
defc9cd8 AC |
889 | }; |
890 | ||
891 | /** | |
892 | * probe_chip_type - Discover controller | |
893 | * @probe: Probe entry to check | |
894 | * | |
895 | * Probe an ATA port and identify the type of controller. We don't | |
896 | * check if the controller appears to be driveless at this point. | |
897 | */ | |
898 | ||
b8325487 | 899 | static __init int probe_chip_type(struct legacy_probe *probe) |
defc9cd8 AC |
900 | { |
901 | int mask = 1 << probe->slot; | |
902 | ||
b8325487 AC |
903 | if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) { |
904 | u8 reg = winbond_readcfg(winbond, 0x81); | |
905 | reg |= 0x80; /* jumpered mode off */ | |
906 | winbond_writecfg(winbond, 0x81, reg); | |
907 | reg = winbond_readcfg(winbond, 0x83); | |
908 | reg |= 0xF0; /* local control */ | |
909 | winbond_writecfg(winbond, 0x83, reg); | |
910 | reg = winbond_readcfg(winbond, 0x85); | |
911 | reg |= 0xF0; /* programmable timing */ | |
912 | winbond_writecfg(winbond, 0x85, reg); | |
913 | ||
914 | reg = winbond_readcfg(winbond, 0x81); | |
915 | ||
916 | if (reg & mask) | |
917 | return W83759A; | |
918 | } | |
defc9cd8 AC |
919 | if (probe->port == 0x1F0) { |
920 | unsigned long flags; | |
921 | local_irq_save(flags); | |
669a5db4 | 922 | /* Probes */ |
669a5db4 | 923 | outb(inb(0x1F2) | 0x80, 0x1F2); |
defc9cd8 | 924 | inb(0x1F5); |
669a5db4 JG |
925 | inb(0x1F2); |
926 | inb(0x3F6); | |
927 | inb(0x3F6); | |
928 | inb(0x1F2); | |
929 | inb(0x1F2); | |
930 | ||
931 | if ((inb(0x1F2) & 0x80) == 0) { | |
932 | /* PDC20230c or 20630 ? */ | |
defc9cd8 AC |
933 | printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller" |
934 | " detected.\n"); | |
669a5db4 JG |
935 | udelay(100); |
936 | inb(0x1F5); | |
defc9cd8 AC |
937 | local_irq_restore(flags); |
938 | return PDC20230; | |
669a5db4 JG |
939 | } else { |
940 | outb(0x55, 0x1F2); | |
941 | inb(0x1F2); | |
942 | inb(0x1F2); | |
defc9cd8 AC |
943 | if (inb(0x1F2) == 0x00) |
944 | printk(KERN_INFO "PDC20230-B VLB ATA " | |
945 | "controller detected.\n"); | |
946 | local_irq_restore(flags); | |
947 | return BIOS; | |
669a5db4 JG |
948 | } |
949 | local_irq_restore(flags); | |
950 | } | |
951 | ||
defc9cd8 AC |
952 | if (ht6560a & mask) |
953 | return HT6560A; | |
954 | if (ht6560b & mask) | |
955 | return HT6560B; | |
956 | if (opti82c611a & mask) | |
957 | return OPTI611A; | |
958 | if (opti82c46x & mask) | |
959 | return OPTI46X; | |
960 | if (autospeed & mask) | |
961 | return SNOOP; | |
962 | return BIOS; | |
963 | } | |
964 | ||
965 | ||
966 | /** | |
967 | * legacy_init_one - attach a legacy interface | |
968 | * @pl: probe record | |
969 | * | |
970 | * Register an ISA bus IDE interface. Such interfaces are PIO and we | |
971 | * assume do not support IRQ sharing. | |
972 | */ | |
973 | ||
974 | static __init int legacy_init_one(struct legacy_probe *probe) | |
975 | { | |
976 | struct legacy_controller *controller = &controllers[probe->type]; | |
977 | int pio_modes = controller->pio_mask; | |
978 | unsigned long io = probe->port; | |
979 | u32 mask = (1 << probe->slot); | |
980 | struct ata_port_operations *ops = controller->ops; | |
981 | struct legacy_data *ld = &legacy_data[probe->slot]; | |
982 | struct ata_host *host = NULL; | |
983 | struct ata_port *ap; | |
984 | struct platform_device *pdev; | |
985 | struct ata_device *dev; | |
986 | void __iomem *io_addr, *ctrl_addr; | |
987 | u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; | |
988 | int ret; | |
989 | ||
990 | iordy |= controller->flags; | |
991 | ||
992 | pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0); | |
993 | if (IS_ERR(pdev)) | |
994 | return PTR_ERR(pdev); | |
669a5db4 | 995 | |
defc9cd8 AC |
996 | ret = -EBUSY; |
997 | if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || | |
998 | devm_request_region(&pdev->dev, io + 0x0206, 1, | |
999 | "pata_legacy") == NULL) | |
1000 | goto fail; | |
f834e49f | 1001 | |
5d728824 | 1002 | ret = -ENOMEM; |
defc9cd8 AC |
1003 | io_addr = devm_ioport_map(&pdev->dev, io, 8); |
1004 | ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1); | |
1005 | if (!io_addr || !ctrl_addr) | |
1006 | goto fail; | |
1007 | if (controller->setup) | |
b8325487 | 1008 | if (controller->setup(pdev, probe, ld) < 0) |
defc9cd8 | 1009 | goto fail; |
5d728824 TH |
1010 | host = ata_host_alloc(&pdev->dev, 1); |
1011 | if (!host) | |
1012 | goto fail; | |
1013 | ap = host->ports[0]; | |
1014 | ||
1015 | ap->ops = ops; | |
1016 | ap->pio_mask = pio_modes; | |
1017 | ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; | |
e3cf95dd | 1018 | ap->pflags |= controller->pflags; |
5d728824 TH |
1019 | ap->ioaddr.cmd_addr = io_addr; |
1020 | ap->ioaddr.altstatus_addr = ctrl_addr; | |
1021 | ap->ioaddr.ctl_addr = ctrl_addr; | |
9363c382 | 1022 | ata_sff_std_ports(&ap->ioaddr); |
b8325487 | 1023 | ap->host->private_data = ld; |
5d728824 | 1024 | |
defc9cd8 | 1025 | ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206); |
cbcdd875 | 1026 | |
9363c382 TH |
1027 | ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0, |
1028 | &legacy_sht); | |
5d728824 | 1029 | if (ret) |
669a5db4 | 1030 | goto fail; |
669a5db4 | 1031 | ld->platform_dev = pdev; |
669a5db4 | 1032 | |
defc9cd8 AC |
1033 | /* Nothing found means we drop the port as its probably not there */ |
1034 | ||
1035 | ret = -ENODEV; | |
1eca4365 | 1036 | ata_for_each_dev(dev, &ap->link, ALL) { |
defc9cd8 AC |
1037 | if (!ata_dev_absent(dev)) { |
1038 | legacy_host[probe->slot] = host; | |
1039 | ld->platform_dev = pdev; | |
1040 | return 0; | |
1041 | } | |
1042 | } | |
20cbf5f8 | 1043 | ata_host_detach(host); |
669a5db4 JG |
1044 | fail: |
1045 | platform_device_unregister(pdev); | |
669a5db4 JG |
1046 | return ret; |
1047 | } | |
1048 | ||
1049 | /** | |
1050 | * legacy_check_special_cases - ATA special cases | |
1051 | * @p: PCI device to check | |
1052 | * @master: set this if we find an ATA master | |
1053 | * @master: set this if we find an ATA secondary | |
1054 | * | |
defc9cd8 AC |
1055 | * A small number of vendors implemented early PCI ATA interfaces |
1056 | * on bridge logic without the ATA interface being PCI visible. | |
1057 | * Where we have a matching PCI driver we must skip the relevant | |
1058 | * device here. If we don't know about it then the legacy driver | |
1059 | * is the right driver anyway. | |
669a5db4 JG |
1060 | */ |
1061 | ||
b8325487 | 1062 | static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, |
defc9cd8 | 1063 | int *secondary) |
669a5db4 JG |
1064 | { |
1065 | /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ | |
1066 | if (p->vendor == 0x1078 && p->device == 0x0000) { | |
1067 | *primary = *secondary = 1; | |
1068 | return; | |
1069 | } | |
1070 | /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ | |
1071 | if (p->vendor == 0x1078 && p->device == 0x0002) { | |
1072 | *primary = *secondary = 1; | |
1073 | return; | |
1074 | } | |
1075 | /* Intel MPIIX - PIO ATA on non PCI side of bridge */ | |
1076 | if (p->vendor == 0x8086 && p->device == 0x1234) { | |
1077 | u16 r; | |
1078 | pci_read_config_word(p, 0x6C, &r); | |
defc9cd8 AC |
1079 | if (r & 0x8000) { |
1080 | /* ATA port enabled */ | |
669a5db4 JG |
1081 | if (r & 0x4000) |
1082 | *secondary = 1; | |
1083 | else | |
1084 | *primary = 1; | |
1085 | } | |
1086 | return; | |
1087 | } | |
1088 | } | |
1089 | ||
defc9cd8 AC |
1090 | static __init void probe_opti_vlb(void) |
1091 | { | |
1092 | /* If an OPTI 82C46X is present find out where the channels are */ | |
1093 | static const char *optis[4] = { | |
1094 | "3/463MV", "5MV", | |
1095 | "5MVA", "5MVB" | |
1096 | }; | |
1097 | u8 chans = 1; | |
1098 | u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; | |
1099 | ||
1100 | opti82c46x = 3; /* Assume master and slave first */ | |
1101 | printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", | |
1102 | optis[ctrl]); | |
1103 | if (ctrl == 3) | |
1104 | chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; | |
1105 | ctrl = opti_syscfg(0xAC); | |
1106 | /* Check enabled and this port is the 465MV port. On the | |
1107 | MVB we may have two channels */ | |
1108 | if (ctrl & 8) { | |
1109 | if (chans == 2) { | |
1110 | legacy_probe_add(0x1F0, 14, OPTI46X, 0); | |
1111 | legacy_probe_add(0x170, 15, OPTI46X, 0); | |
1112 | } | |
1113 | if (ctrl & 4) | |
1114 | legacy_probe_add(0x170, 15, OPTI46X, 0); | |
1115 | else | |
1116 | legacy_probe_add(0x1F0, 14, OPTI46X, 0); | |
1117 | } else | |
1118 | legacy_probe_add(0x1F0, 14, OPTI46X, 0); | |
1119 | } | |
1120 | ||
1121 | static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port) | |
1122 | { | |
1123 | static const unsigned long ide_port[2] = { 0x170, 0x1F0 }; | |
1124 | /* Check card type */ | |
1125 | if ((r & 0xF0) == 0xC0) { | |
1126 | /* QD6500: single channel */ | |
b8325487 | 1127 | if (r & 8) |
defc9cd8 | 1128 | /* Disabled ? */ |
defc9cd8 | 1129 | return; |
defc9cd8 AC |
1130 | legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), |
1131 | QDI6500, port); | |
1132 | } | |
1133 | if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) { | |
1134 | /* QD6580: dual channel */ | |
1135 | if (!request_region(port + 2 , 2, "pata_qdi")) { | |
1136 | release_region(port, 2); | |
1137 | return; | |
1138 | } | |
1139 | res = inb(port + 3); | |
1140 | /* Single channel mode ? */ | |
1141 | if (res & 1) | |
1142 | legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), | |
1143 | QDI6580, port); | |
1144 | else { /* Dual channel mode */ | |
1145 | legacy_probe_add(0x1F0, 14, QDI6580DP, port); | |
1146 | /* port + 0x02, r & 0x04 */ | |
1147 | legacy_probe_add(0x170, 15, QDI6580DP, port + 2); | |
1148 | } | |
b8325487 | 1149 | release_region(port + 2, 2); |
defc9cd8 AC |
1150 | } |
1151 | } | |
1152 | ||
1153 | static __init void probe_qdi_vlb(void) | |
1154 | { | |
1155 | unsigned long flags; | |
1156 | static const unsigned long qd_port[2] = { 0x30, 0xB0 }; | |
1157 | int i; | |
1158 | ||
1159 | /* | |
1160 | * Check each possible QD65xx base address | |
1161 | */ | |
1162 | ||
1163 | for (i = 0; i < 2; i++) { | |
1164 | unsigned long port = qd_port[i]; | |
1165 | u8 r, res; | |
1166 | ||
1167 | ||
1168 | if (request_region(port, 2, "pata_qdi")) { | |
1169 | /* Check for a card */ | |
1170 | local_irq_save(flags); | |
1171 | /* I have no h/w that needs this delay but it | |
1172 | is present in the historic code */ | |
1173 | r = inb(port); | |
1174 | udelay(1); | |
1175 | outb(0x19, port); | |
1176 | udelay(1); | |
1177 | res = inb(port); | |
1178 | udelay(1); | |
1179 | outb(r, port); | |
1180 | udelay(1); | |
1181 | local_irq_restore(flags); | |
1182 | ||
1183 | /* Fail */ | |
1184 | if (res == 0x19) { | |
1185 | release_region(port, 2); | |
1186 | continue; | |
1187 | } | |
1188 | /* Passes the presence test */ | |
1189 | r = inb(port + 1); | |
1190 | udelay(1); | |
1191 | /* Check port agrees with port set */ | |
b8325487 AC |
1192 | if ((r & 2) >> 1 == i) |
1193 | qdi65_identify_port(r, res, port); | |
1194 | release_region(port, 2); | |
defc9cd8 AC |
1195 | } |
1196 | } | |
1197 | } | |
669a5db4 JG |
1198 | |
1199 | /** | |
1200 | * legacy_init - attach legacy interfaces | |
1201 | * | |
1202 | * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. | |
1203 | * Right now we do not scan the ide0 and ide1 address but should do so | |
1204 | * for non PCI systems or systems with no PCI IDE legacy mode devices. | |
1205 | * If you fix that note there are special cases to consider like VLB | |
1206 | * drivers and CS5510/20. | |
1207 | */ | |
1208 | ||
1209 | static __init int legacy_init(void) | |
1210 | { | |
1211 | int i; | |
1212 | int ct = 0; | |
1213 | int primary = 0; | |
1214 | int secondary = 0; | |
defc9cd8 AC |
1215 | int pci_present = 0; |
1216 | struct legacy_probe *pl = &probe_list[0]; | |
1217 | int slot = 0; | |
669a5db4 JG |
1218 | |
1219 | struct pci_dev *p = NULL; | |
1220 | ||
1221 | for_each_pci_dev(p) { | |
1222 | int r; | |
defc9cd8 AC |
1223 | /* Check for any overlap of the system ATA mappings. Native |
1224 | mode controllers stuck on these addresses or some devices | |
1225 | in 'raid' mode won't be found by the storage class test */ | |
669a5db4 JG |
1226 | for (r = 0; r < 6; r++) { |
1227 | if (pci_resource_start(p, r) == 0x1f0) | |
1228 | primary = 1; | |
1229 | if (pci_resource_start(p, r) == 0x170) | |
1230 | secondary = 1; | |
1231 | } | |
1232 | /* Check for special cases */ | |
1233 | legacy_check_special_cases(p, &primary, &secondary); | |
1234 | ||
defc9cd8 AC |
1235 | /* If PCI bus is present then don't probe for tertiary |
1236 | legacy ports */ | |
1237 | pci_present = 1; | |
669a5db4 JG |
1238 | } |
1239 | ||
b8325487 AC |
1240 | if (winbond == 1) |
1241 | winbond = 0x130; /* Default port, alt is 1B0 */ | |
1242 | ||
defc9cd8 AC |
1243 | if (primary == 0 || all) |
1244 | legacy_probe_add(0x1F0, 14, UNKNOWN, 0); | |
1245 | if (secondary == 0 || all) | |
1246 | legacy_probe_add(0x170, 15, UNKNOWN, 0); | |
1247 | ||
1248 | if (probe_all || !pci_present) { | |
1249 | /* ISA/VLB extra ports */ | |
1250 | legacy_probe_add(0x1E8, 11, UNKNOWN, 0); | |
1251 | legacy_probe_add(0x168, 10, UNKNOWN, 0); | |
1252 | legacy_probe_add(0x1E0, 8, UNKNOWN, 0); | |
1253 | legacy_probe_add(0x160, 12, UNKNOWN, 0); | |
669a5db4 JG |
1254 | } |
1255 | ||
defc9cd8 AC |
1256 | if (opti82c46x) |
1257 | probe_opti_vlb(); | |
1258 | if (qdi) | |
1259 | probe_qdi_vlb(); | |
1260 | ||
defc9cd8 AC |
1261 | for (i = 0; i < NR_HOST; i++, pl++) { |
1262 | if (pl->port == 0) | |
669a5db4 | 1263 | continue; |
defc9cd8 AC |
1264 | if (pl->type == UNKNOWN) |
1265 | pl->type = probe_chip_type(pl); | |
1266 | pl->slot = slot++; | |
1267 | if (legacy_init_one(pl) == 0) | |
669a5db4 JG |
1268 | ct++; |
1269 | } | |
1270 | if (ct != 0) | |
1271 | return 0; | |
1272 | return -ENODEV; | |
1273 | } | |
1274 | ||
1275 | static __exit void legacy_exit(void) | |
1276 | { | |
1277 | int i; | |
1278 | ||
1279 | for (i = 0; i < nr_legacy_host; i++) { | |
1280 | struct legacy_data *ld = &legacy_data[i]; | |
24dc5f33 | 1281 | ata_host_detach(legacy_host[i]); |
669a5db4 | 1282 | platform_device_unregister(ld->platform_dev); |
669a5db4 JG |
1283 | } |
1284 | } | |
1285 | ||
1286 | MODULE_AUTHOR("Alan Cox"); | |
1287 | MODULE_DESCRIPTION("low-level driver for legacy ATA"); | |
1288 | MODULE_LICENSE("GPL"); | |
1289 | MODULE_VERSION(DRV_VERSION); | |
1290 | ||
1291 | module_param(probe_all, int, 0); | |
1292 | module_param(autospeed, int, 0); | |
1293 | module_param(ht6560a, int, 0); | |
1294 | module_param(ht6560b, int, 0); | |
1295 | module_param(opti82c611a, int, 0); | |
1296 | module_param(opti82c46x, int, 0); | |
defc9cd8 | 1297 | module_param(qdi, int, 0); |
669a5db4 | 1298 | module_param(pio_mask, int, 0); |
f834e49f | 1299 | module_param(iordy_mask, int, 0); |
669a5db4 JG |
1300 | |
1301 | module_init(legacy_init); | |
1302 | module_exit(legacy_exit); |