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669a5db4 JG |
1 | /* |
2 | * pata_mpiix.c - Intel MPIIX PATA for new ATA layer | |
3 | * (C) 2005-2006 Red Hat Inc | |
4 | * Alan Cox <alan@redhat.com> | |
5 | * | |
6 | * The MPIIX is different enough to the PIIX4 and friends that we give it | |
7 | * a separate driver. The old ide/pci code handles this by just not tuning | |
8 | * MPIIX at all. | |
9 | * | |
10 | * The MPIIX also differs in another important way from the majority of PIIX | |
11 | * devices. The chip is a bridge (pardon the pun) between the old world of | |
12 | * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual | |
13 | * IDE controller is not decoded in PCI space and the chip does not claim to | |
14 | * be IDE class PCI. This requires slightly non-standard probe logic compared | |
15 | * with PCI IDE and also that we do not disable the device when our driver is | |
16 | * unloaded (as it has many other functions). | |
17 | * | |
18 | * The driver conciously keeps this logic internally to avoid pushing quirky | |
19 | * PATA history into the clean libata layer. | |
20 | * | |
c961922b | 21 | * Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA |
669a5db4 JG |
22 | * hard disk present this driver will not detect it. This is not a bug. In this |
23 | * configuration the secondary port of the MPIIX is disabled and the addresses | |
24 | * are decoded by the PCMCIA bridge and therefore are for a generic IDE driver | |
25 | * to operate. | |
26 | */ | |
27 | ||
28 | #include <linux/kernel.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/blkdev.h> | |
33 | #include <linux/delay.h> | |
34 | #include <scsi/scsi_host.h> | |
35 | #include <linux/libata.h> | |
36 | ||
37 | #define DRV_NAME "pata_mpiix" | |
7b4f1a13 | 38 | #define DRV_VERSION "0.7.4" |
669a5db4 JG |
39 | |
40 | enum { | |
41 | IDETIM = 0x6C, /* IDE control register */ | |
42 | IORDY = (1 << 1), | |
43 | PPE = (1 << 2), | |
44 | FTIM = (1 << 0), | |
45 | ENABLED = (1 << 15), | |
46 | SECONDARY = (1 << 14) | |
47 | }; | |
48 | ||
49 | static int mpiix_pre_reset(struct ata_port *ap) | |
50 | { | |
51 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
52 | static const struct pci_bits mpiix_enable_bits[] = { | |
53 | { 0x6D, 1, 0x80, 0x80 }, | |
54 | { 0x6F, 1, 0x80, 0x80 } | |
55 | }; | |
56 | ||
c961922b AC |
57 | if (!pci_test_config_bits(pdev, &mpiix_enable_bits[ap->port_no])) |
58 | return -ENOENT; | |
669a5db4 JG |
59 | ap->cbl = ATA_CBL_PATA40; |
60 | return ata_std_prereset(ap); | |
61 | } | |
62 | ||
63 | /** | |
64 | * mpiix_error_handler - probe reset | |
65 | * @ap: ATA port | |
66 | * | |
67 | * Perform the ATA probe and bus reset sequence plus specific handling | |
68 | * for this hardware. The MPIIX has the enable bits in a different place | |
69 | * to PIIX4 and friends. As a pure PIO device it has no cable detect | |
70 | */ | |
71 | ||
72 | static void mpiix_error_handler(struct ata_port *ap) | |
73 | { | |
74 | ata_bmdma_drive_eh(ap, mpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
75 | } | |
76 | ||
77 | /** | |
78 | * mpiix_set_piomode - set initial PIO mode data | |
79 | * @ap: ATA interface | |
80 | * @adev: ATA device | |
81 | * | |
82 | * Called to do the PIO mode setup. The MPIIX allows us to program the | |
7b4f1a13 SS |
83 | * IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether |
84 | * prefetching or IORDY are used. | |
669a5db4 JG |
85 | * |
86 | * This would get very ugly because we can only program timing for one | |
87 | * device at a time, the other gets PIO0. Fortunately libata calls | |
88 | * our qc_issue_prot command before a command is issued so we can | |
89 | * flip the timings back and forth to reduce the pain. | |
90 | */ | |
91 | ||
92 | static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
93 | { | |
94 | int control = 0; | |
95 | int pio = adev->pio_mode - XFER_PIO_0; | |
96 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
97 | u16 idetim; | |
98 | static const /* ISP RTC */ | |
99 | u8 timings[][2] = { { 0, 0 }, | |
100 | { 0, 0 }, | |
101 | { 1, 0 }, | |
102 | { 2, 1 }, | |
103 | { 2, 3 }, }; | |
104 | ||
105 | pci_read_config_word(pdev, IDETIM, &idetim); | |
7b4f1a13 SS |
106 | |
107 | /* Mask the IORDY/TIME/PPE for this device */ | |
669a5db4 | 108 | if (adev->class == ATA_DEV_ATA) |
7b4f1a13 | 109 | control |= PPE; /* Enable prefetch/posting for disk */ |
669a5db4 | 110 | if (ata_pio_need_iordy(adev)) |
7b4f1a13 SS |
111 | control |= IORDY; |
112 | if (pio > 1) | |
669a5db4 JG |
113 | control |= FTIM; /* This drive is on the fast timing bank */ |
114 | ||
115 | /* Mask out timing and clear both TIME bank selects */ | |
116 | idetim &= 0xCCEE; | |
7b4f1a13 SS |
117 | idetim &= ~(0x07 << (4 * adev->devno)); |
118 | idetim |= control << (4 * adev->devno); | |
669a5db4 JG |
119 | |
120 | idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8); | |
121 | pci_write_config_word(pdev, IDETIM, idetim); | |
122 | ||
123 | /* We use ap->private_data as a pointer to the device currently | |
124 | loaded for timing */ | |
125 | ap->private_data = adev; | |
126 | } | |
127 | ||
128 | /** | |
129 | * mpiix_qc_issue_prot - command issue | |
130 | * @qc: command pending | |
131 | * | |
132 | * Called when the libata layer is about to issue a command. We wrap | |
133 | * this interface so that we can load the correct ATA timings if | |
134 | * neccessary. Our logic also clears TIME0/TIME1 for the other device so | |
135 | * that, even if we get this wrong, cycles to the other device will | |
136 | * be made PIO0. | |
137 | */ | |
138 | ||
139 | static unsigned int mpiix_qc_issue_prot(struct ata_queued_cmd *qc) | |
140 | { | |
141 | struct ata_port *ap = qc->ap; | |
142 | struct ata_device *adev = qc->dev; | |
143 | ||
144 | /* If modes have been configured and the channel data is not loaded | |
145 | then load it. We have to check if pio_mode is set as the core code | |
146 | does not set adev->pio_mode to XFER_PIO_0 while probing as would be | |
147 | logical */ | |
148 | ||
149 | if (adev->pio_mode && adev != ap->private_data) | |
150 | mpiix_set_piomode(ap, adev); | |
151 | ||
152 | return ata_qc_issue_prot(qc); | |
153 | } | |
154 | ||
155 | static struct scsi_host_template mpiix_sht = { | |
156 | .module = THIS_MODULE, | |
157 | .name = DRV_NAME, | |
158 | .ioctl = ata_scsi_ioctl, | |
159 | .queuecommand = ata_scsi_queuecmd, | |
160 | .can_queue = ATA_DEF_QUEUE, | |
161 | .this_id = ATA_SHT_THIS_ID, | |
162 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
163 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
164 | .emulated = ATA_SHT_EMULATED, | |
165 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
166 | .proc_name = DRV_NAME, | |
167 | .dma_boundary = ATA_DMA_BOUNDARY, | |
168 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 169 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 | 170 | .bios_param = ata_std_bios_param, |
30ced0f0 AC |
171 | .resume = ata_scsi_device_resume, |
172 | .suspend = ata_scsi_device_suspend, | |
669a5db4 JG |
173 | }; |
174 | ||
175 | static struct ata_port_operations mpiix_port_ops = { | |
176 | .port_disable = ata_port_disable, | |
177 | .set_piomode = mpiix_set_piomode, | |
178 | ||
179 | .tf_load = ata_tf_load, | |
180 | .tf_read = ata_tf_read, | |
181 | .check_status = ata_check_status, | |
182 | .exec_command = ata_exec_command, | |
183 | .dev_select = ata_std_dev_select, | |
184 | ||
185 | .freeze = ata_bmdma_freeze, | |
186 | .thaw = ata_bmdma_thaw, | |
187 | .error_handler = mpiix_error_handler, | |
188 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
189 | ||
190 | .qc_prep = ata_qc_prep, | |
191 | .qc_issue = mpiix_qc_issue_prot, | |
0d5ff566 | 192 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
193 | |
194 | .irq_handler = ata_interrupt, | |
195 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
196 | .irq_on = ata_irq_on, |
197 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
198 | |
199 | .port_start = ata_port_start, | |
669a5db4 JG |
200 | }; |
201 | ||
202 | static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
203 | { | |
204 | /* Single threaded by the PCI probe logic */ | |
0d5ff566 | 205 | static struct ata_probe_ent probe; |
669a5db4 | 206 | static int printed_version; |
0d5ff566 | 207 | void __iomem *cmd_addr, *ctl_addr; |
669a5db4 | 208 | u16 idetim; |
0d5ff566 | 209 | int irq; |
669a5db4 JG |
210 | |
211 | if (!printed_version++) | |
212 | dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n"); | |
213 | ||
214 | /* MPIIX has many functions which can be turned on or off according | |
215 | to other devices present. Make sure IDE is enabled before we try | |
216 | and use it */ | |
217 | ||
218 | pci_read_config_word(dev, IDETIM, &idetim); | |
219 | if (!(idetim & ENABLED)) | |
220 | return -ENODEV; | |
221 | ||
0d5ff566 TH |
222 | if (!(idetim & SECONDARY)) { |
223 | irq = 14; | |
224 | cmd_addr = devm_ioport_map(&dev->dev, 0x1F0, 8); | |
225 | ctl_addr = devm_ioport_map(&dev->dev, 0x3F6, 1); | |
226 | } else { | |
227 | irq = 15; | |
228 | cmd_addr = devm_ioport_map(&dev->dev, 0x170, 8); | |
229 | ctl_addr = devm_ioport_map(&dev->dev, 0x376, 1); | |
230 | } | |
231 | ||
232 | if (!cmd_addr || !ctl_addr) | |
233 | return -ENOMEM; | |
234 | ||
669a5db4 JG |
235 | /* We do our own plumbing to avoid leaking special cases for whacko |
236 | ancient hardware into the core code. There are two issues to | |
237 | worry about. #1 The chip is a bridge so if in legacy mode and | |
238 | without BARs set fools the setup. #2 If you pci_disable_device | |
239 | the MPIIX your box goes castors up */ | |
240 | ||
0d5ff566 TH |
241 | INIT_LIST_HEAD(&probe.node); |
242 | probe.dev = pci_dev_to_dev(dev); | |
243 | probe.port_ops = &mpiix_port_ops; | |
244 | probe.sht = &mpiix_sht; | |
245 | probe.pio_mask = 0x1F; | |
246 | probe.irq = irq; | |
247 | probe.irq_flags = SA_SHIRQ; | |
248 | probe.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST; | |
249 | probe.n_ports = 1; | |
250 | probe.port[0].cmd_addr = cmd_addr; | |
251 | probe.port[0].ctl_addr = ctl_addr; | |
252 | probe.port[0].altstatus_addr = ctl_addr; | |
669a5db4 JG |
253 | |
254 | /* Let libata fill in the port details */ | |
0d5ff566 | 255 | ata_std_ports(&probe.port[0]); |
669a5db4 JG |
256 | |
257 | /* Now add the port that is active */ | |
0d5ff566 | 258 | if (ata_device_add(&probe)) |
669a5db4 JG |
259 | return 0; |
260 | return -ENODEV; | |
261 | } | |
262 | ||
669a5db4 | 263 | static const struct pci_device_id mpiix[] = { |
2d2744fc JG |
264 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), }, |
265 | ||
266 | { }, | |
669a5db4 JG |
267 | }; |
268 | ||
269 | static struct pci_driver mpiix_pci_driver = { | |
270 | .name = DRV_NAME, | |
271 | .id_table = mpiix, | |
272 | .probe = mpiix_init_one, | |
24dc5f33 | 273 | .remove = ata_pci_remove_one, |
30ced0f0 AC |
274 | .suspend = ata_pci_device_suspend, |
275 | .resume = ata_pci_device_resume, | |
669a5db4 JG |
276 | }; |
277 | ||
278 | static int __init mpiix_init(void) | |
279 | { | |
280 | return pci_register_driver(&mpiix_pci_driver); | |
281 | } | |
282 | ||
669a5db4 JG |
283 | static void __exit mpiix_exit(void) |
284 | { | |
285 | pci_unregister_driver(&mpiix_pci_driver); | |
286 | } | |
287 | ||
669a5db4 JG |
288 | MODULE_AUTHOR("Alan Cox"); |
289 | MODULE_DESCRIPTION("low-level driver for Intel MPIIX"); | |
290 | MODULE_LICENSE("GPL"); | |
291 | MODULE_DEVICE_TABLE(pci, mpiix); | |
292 | MODULE_VERSION(DRV_VERSION); | |
293 | ||
294 | module_init(mpiix_init); | |
295 | module_exit(mpiix_exit); |