[mirror_ubuntu-artful-kernel.git] / drivers / ata / pata_sil680.c

/*
 * pata_sil680.c 	- SIL680 PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * based upon
 *
 * linux/drivers/ide/pci/siimage.c		Version 1.07	Nov 30, 2003
 *
 * Copyright (C) 2001-2002	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2003		Red Hat <alan@redhat.com>
 *
 *  May be copied or modified under the terms of the GNU General Public License
 *
 *  Documentation publically available.
 *
 *	If you have strange problems with nVidia chipset systems please
 *	see the SI support documentation and update your system BIOS
 *	if necessary
 *
 * TODO
 *	If we know all our devices are LBA28 (or LBA28 sized)  we could use
 *	the command fifo mode.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_sil680"
#define DRV_VERSION "0.4.8"

#define SIL680_MMIO_BAR		5

/**
 *	sil680_selreg		-	return register base
 *	@hwif: interface
 *	@r: config offset
 *
 *	Turn a config register offset into the right address in either
 *	PCI space or MMIO space to access the control register in question
 *	Thankfully this is a configuration operation so isnt performance
 *	criticial.
 */

static unsigned long sil680_selreg(struct ata_port *ap, int r)
{
	unsigned long base = 0xA0 + r;
	base += (ap->port_no << 4);
	return base;
}

/**
 *	sil680_seldev		-	return register base
 *	@hwif: interface
 *	@r: config offset
 *
 *	Turn a config register offset into the right address in either
 *	PCI space or MMIO space to access the control register in question
 *	including accounting for the unit shift.
 */

static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
{
	unsigned long base = 0xA0 + r;
	base += (ap->port_no << 4);
	base |= adev->devno ? 2 : 0;
	return base;
}


/**
 *	sil680_cable_detect	-	cable detection
 *	@ap: ATA port
 *
 *	Perform cable detection. The SIL680 stores this in PCI config
 *	space for us.
 */

static int sil680_cable_detect(struct ata_port *ap) {
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned long addr = sil680_selreg(ap, 0);
	u8 ata66;
	pci_read_config_byte(pdev, addr, &ata66);
	if (ata66 & 1)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

/**
 *	sil680_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the SIL680 registers for PIO mode. Note that the task speed
 *	registers are shared between the devices so we must pick the lowest
 *	mode for command work.
 */

static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 };
	static u16 speed_t[5] = { 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 };

	unsigned long tfaddr = sil680_selreg(ap, 0x02);
	unsigned long addr = sil680_seldev(ap, adev, 0x04);
	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int pio = adev->pio_mode - XFER_PIO_0;
	int lowest_pio = pio;
	int port_shift = 4 * adev->devno;
	u16 reg;
	u8 mode;

	struct ata_device *pair = ata_dev_pair(adev);

	if (pair != NULL && adev->pio_mode > pair->pio_mode)
		lowest_pio = pair->pio_mode - XFER_PIO_0;

	pci_write_config_word(pdev, addr, speed_p[pio]);
	pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);

	pci_read_config_word(pdev, tfaddr-2, &reg);
	pci_read_config_byte(pdev, addr_mask, &mode);

	reg &= ~0x0200;			/* Clear IORDY */
	mode &= ~(3 << port_shift);	/* Clear IORDY and DMA bits */

	if (ata_pio_need_iordy(adev)) {
		reg |= 0x0200;		/* Enable IORDY */
		mode |= 1 << port_shift;
	}
	pci_write_config_word(pdev, tfaddr-2, reg);
	pci_write_config_byte(pdev, addr_mask, mode);
}

/**
 *	sil680_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the MWDMA/UDMA modes for the sil680 k
 *	chipset. The MWDMA mode values are pulled from a lookup table
 *	while the chipset uses mode number for UDMA.
 */

static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static u8 ultra_table[2][7] = {
		{ 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF },	/* 100MHz */
		{ 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 },	/* 133Mhz */
	};
	static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned long ma = sil680_seldev(ap, adev, 0x08);
	unsigned long ua = sil680_seldev(ap, adev, 0x0C);
	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
	int port_shift = adev->devno * 4;
	u8 scsc, mode;
	u16 multi, ultra;

	pci_read_config_byte(pdev, 0x8A, &scsc);
	pci_read_config_byte(pdev, addr_mask, &mode);
	pci_read_config_word(pdev, ma, &multi);
	pci_read_config_word(pdev, ua, &ultra);

	/* Mask timing bits */
	ultra &= ~0x3F;
	mode &= ~(0x03 << port_shift);

	/* Extract scsc */
	scsc = (scsc & 0x30) ? 1: 0;

	if (adev->dma_mode >= XFER_UDMA_0) {
		multi = 0x10C1;
		ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
		mode |= (0x03 << port_shift);
	} else {
		multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
		mode |= (0x02 << port_shift);
	}
	pci_write_config_byte(pdev, addr_mask, mode);
	pci_write_config_word(pdev, ma, multi);
	pci_write_config_word(pdev, ua, ultra);
}

static struct scsi_host_template sil680_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations sil680_port_ops = {
	.set_piomode	= sil680_set_piomode,
	.set_dmamode	= sil680_set_dmamode,
	.mode_filter	= ata_pci_default_filter,
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= ata_bmdma_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= sil680_cable_detect,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,

	.port_start	= ata_sff_port_start,
};

/**
 *	sil680_init_chip		-	chip setup
 *	@pdev: PCI device
 *
 *	Perform all the chip setup which must be done both when the device
 *	is powered up on boot and when we resume in case we resumed from RAM.
 *	Returns the final clock settings.
 */

static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio)
{
	u32 class_rev	= 0;
	u8 tmpbyte	= 0;

        pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
        class_rev &= 0xff;
        /* FIXME: double check */
	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);

	pci_write_config_byte(pdev, 0x80, 0x00);
	pci_write_config_byte(pdev, 0x84, 0x00);

	pci_read_config_byte(pdev, 0x8A, &tmpbyte);

	dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
		tmpbyte & 1, tmpbyte & 0x30);

	*try_mmio = 0;
#ifdef CONFIG_PPC_MERGE
	if (machine_is(cell))
		*try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5);
#endif

	switch(tmpbyte & 0x30) {
		case 0x00:
			/* 133 clock attempt to force it on */
			pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);
			break;
		case 0x30:
			/* if clocking is disabled */
			/* 133 clock attempt to force it on */
			pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
			break;
		case 0x10:
			/* 133 already */
			break;
		case 0x20:
			/* BIOS set PCI x2 clocking */
			break;
	}

	pci_read_config_byte(pdev,   0x8A, &tmpbyte);
	dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
		tmpbyte & 1, tmpbyte & 0x30);

	pci_write_config_byte(pdev,  0xA1, 0x72);
	pci_write_config_word(pdev,  0xA2, 0x328A);
	pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
	pci_write_config_dword(pdev, 0xA8, 0x43924392);
	pci_write_config_dword(pdev, 0xAC, 0x40094009);
	pci_write_config_byte(pdev,  0xB1, 0x72);
	pci_write_config_word(pdev,  0xB2, 0x328A);
	pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
	pci_write_config_dword(pdev, 0xB8, 0x43924392);
	pci_write_config_dword(pdev, 0xBC, 0x40094009);

	switch(tmpbyte & 0x30) {
		case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break;
		case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break;
		case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break;
		/* This last case is _NOT_ ok */
		case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n");
	}
	return tmpbyte & 0x30;
}

static int __devinit sil680_init_one(struct pci_dev *pdev,
				     const struct pci_device_id *id)
{
	static const struct ata_port_info info = {
		.sht = &sil680_sht,
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = ATA_UDMA6,
		.port_ops = &sil680_port_ops
	};
	static const struct ata_port_info info_slow = {
		.sht = &sil680_sht,
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = ATA_UDMA5,
		.port_ops = &sil680_port_ops
	};
	const struct ata_port_info *ppi[] = { &info, NULL };
	static int printed_version;
	struct ata_host *host;
	void __iomem *mmio_base;
	int rc, try_mmio;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	switch (sil680_init_chip(pdev, &try_mmio)) {
		case 0:
			ppi[0] = &info_slow;
			break;
		case 0x30:
			return -ENODEV;
	}

	if (!try_mmio)
		goto use_ioports;

	/* Try to acquire MMIO resources and fallback to PIO if
	 * that fails
	 */
	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;
	rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME);
	if (rc)
		goto use_ioports;

	/* Allocate host and set it up */
	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	if (!host)
		return -ENOMEM;
	host->iomap = pcim_iomap_table(pdev);

	/* Setup DMA masks */
	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;
	pci_set_master(pdev);

	/* Get MMIO base and initialize port addresses */
	mmio_base = host->iomap[SIL680_MMIO_BAR];
	host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;
	host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;
	host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;
	host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;
	ata_std_ports(&host->ports[0]->ioaddr);
	host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;
	host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;
	host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;
	host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;
	ata_std_ports(&host->ports[1]->ioaddr);

	/* Register & activate */
	return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
				 &sil680_sht);

use_ioports:
	return ata_pci_init_one(pdev, ppi);
}

#ifdef CONFIG_PM
static int sil680_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	int try_mmio, rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;
	sil680_init_chip(pdev, &try_mmio);
	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id sil680[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },

	{ },
};

static struct pci_driver sil680_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= sil680,
	.probe 		= sil680_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= sil680_reinit_one,
#endif
};

static int __init sil680_init(void)
{
	return pci_register_driver(&sil680_pci_driver);
}

static void __exit sil680_exit(void)
{
	pci_unregister_driver(&sil680_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for SI680 PATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sil680);
MODULE_VERSION(DRV_VERSION);

module_init(sil680_init);
module_exit(sil680_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_sil680.c - SIL680 PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* based upon
	7	*
	8	* linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
	9	*
	10	* Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
	11	* Copyright (C) 2003 Red Hat <alan@redhat.com>
	12	*
	13	* May be copied or modified under the terms of the GNU General Public License
	14	*
	15	* Documentation publically available.
	16	*
	17	* If you have strange problems with nVidia chipset systems please
	18	* see the SI support documentation and update your system BIOS
3a4fa0a2	19	* if necessary
669a5db4 JG	20	*
	21	* TODO
	22	* If we know all our devices are LBA28 (or LBA28 sized) we could use
	23	* the command fifo mode.
	24	*/
	25
	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
	28	#include <linux/pci.h>
	29	#include <linux/init.h>
	30	#include <linux/blkdev.h>
	31	#include <linux/delay.h>
	32	#include <scsi/scsi_host.h>
	33	#include <linux/libata.h>
	34
	35	#define DRV_NAME "pata_sil680"
dd05c199	36	#define DRV_VERSION "0.4.8"
669a5db4	37
79b0bde1 JG	38	#define SIL680_MMIO_BAR 5
79b0bde1 JG	39
669a5db4 JG	40	/**
	41	* sil680_selreg - return register base
	42	* @hwif: interface
	43	* @r: config offset
	44	*
	45	* Turn a config register offset into the right address in either
	46	* PCI space or MMIO space to access the control register in question
	47	* Thankfully this is a configuration operation so isnt performance
	48	* criticial.
	49	*/
	50
	51	static unsigned long sil680_selreg(struct ata_port *ap, int r)
	52	{
	53	unsigned long base = 0xA0 + r;
	54	base += (ap->port_no << 4);
	55	return base;
	56	}
	57
	58	/**
	59	* sil680_seldev - return register base
	60	* @hwif: interface
	61	* @r: config offset
	62	*
	63	* Turn a config register offset into the right address in either
	64	* PCI space or MMIO space to access the control register in question
	65	* including accounting for the unit shift.
	66	*/
	67
	68	static unsigned long sil680_seldev(struct ata_port ap, struct ata_device adev, int r)
	69	{
	70	unsigned long base = 0xA0 + r;
	71	base += (ap->port_no << 4);
	72	base \|= adev->devno ? 2 : 0;
	73	return base;
	74	}
	75
	76
	77	/**
	78	* sil680_cable_detect - cable detection
	79	* @ap: ATA port
	80	*
	81	* Perform cable detection. The SIL680 stores this in PCI config
	82	* space for us.
	83	*/
	84
	85	static int sil680_cable_detect(struct ata_port *ap) {
	86	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	87	unsigned long addr = sil680_selreg(ap, 0);
	88	u8 ata66;
	89	pci_read_config_byte(pdev, addr, &ata66);
	90	if (ata66 & 1)
	91	return ATA_CBL_PATA80;
	92	else
	93	return ATA_CBL_PATA40;
	94	}
	95
669a5db4 JG	96	/**
	97	* sil680_set_piomode - set initial PIO mode data
	98	* @ap: ATA interface
	99	* @adev: ATA device
	100	*
	101	* Program the SIL680 registers for PIO mode. Note that the task speed
	102	* registers are shared between the devices so we must pick the lowest
	103	* mode for command work.
	104	*/
	105
	106	static void sil680_set_piomode(struct ata_port ap, struct ata_device adev)
	107	{
	108	static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 };
5dcade90	109	static u16 speed_t[5] = { 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 };
669a5db4 JG	110
	111	unsigned long tfaddr = sil680_selreg(ap, 0x02);
	112	unsigned long addr = sil680_seldev(ap, adev, 0x04);
cb0e34ba	113	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
669a5db4 JG	114	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	115	int pio = adev->pio_mode - XFER_PIO_0;
	116	int lowest_pio = pio;
cb0e34ba	117	int port_shift = 4 * adev->devno;
669a5db4	118	u16 reg;
cb0e34ba	119	u8 mode;
669a5db4 JG	120
	121	struct ata_device *pair = ata_dev_pair(adev);
	122
	123	if (pair != NULL && adev->pio_mode > pair->pio_mode)
	124	lowest_pio = pair->pio_mode - XFER_PIO_0;
	125
	126	pci_write_config_word(pdev, addr, speed_p[pio]);
	127	pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);
	128
	129	pci_read_config_word(pdev, tfaddr-2, &reg);
cb0e34ba	130	pci_read_config_byte(pdev, addr_mask, &mode);
a84471fe	131
669a5db4	132	reg &= ~0x0200; /* Clear IORDY */
cb0e34ba	133	mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */
a84471fe	134
cb0e34ba	135	if (ata_pio_need_iordy(adev)) {
669a5db4	136	reg \|= 0x0200; /* Enable IORDY */
cb0e34ba AC	137	mode \|= 1 << port_shift;
cb0e34ba AC	138	}
669a5db4	139	pci_write_config_word(pdev, tfaddr-2, reg);
cb0e34ba	140	pci_write_config_byte(pdev, addr_mask, mode);
669a5db4 JG	141	}
	142
	143	/**
	144	* sil680_set_dmamode - set initial DMA mode data
	145	* @ap: ATA interface
	146	* @adev: ATA device
	147	*
	148	* Program the MWDMA/UDMA modes for the sil680 k
	149	* chipset. The MWDMA mode values are pulled from a lookup table
	150	* while the chipset uses mode number for UDMA.
	151	*/
	152
	153	static void sil680_set_dmamode(struct ata_port ap, struct ata_device adev)
	154	{
	155	static u8 ultra_table[2][7] = {
	156	{ 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */
	157	{ 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */
	158	};
	159	static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
	160
	161	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	162	unsigned long ma = sil680_seldev(ap, adev, 0x08);
	163	unsigned long ua = sil680_seldev(ap, adev, 0x0C);
	164	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
	165	int port_shift = adev->devno * 4;
	166	u8 scsc, mode;
	167	u16 multi, ultra;
	168
	169	pci_read_config_byte(pdev, 0x8A, &scsc);
	170	pci_read_config_byte(pdev, addr_mask, &mode);
	171	pci_read_config_word(pdev, ma, &multi);
	172	pci_read_config_word(pdev, ua, &ultra);
	173
	174	/* Mask timing bits */
	175	ultra &= ~0x3F;
	176	mode &= ~(0x03 << port_shift);
	177
	178	/* Extract scsc */
	179	scsc = (scsc & 0x30) ? 1: 0;
	180
	181	if (adev->dma_mode >= XFER_UDMA_0) {
	182	multi = 0x10C1;
	183	ultra \|= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
	184	mode \|= (0x03 << port_shift);
	185	} else {
	186	multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
	187	mode \|= (0x02 << port_shift);
	188	}
	189	pci_write_config_byte(pdev, addr_mask, mode);
	190	pci_write_config_word(pdev, ma, multi);
	191	pci_write_config_word(pdev, ua, ultra);
	192	}
	193
	194	static struct scsi_host_template sil680_sht = {
68d1d07b	195	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	196	};
	197
	198	static struct ata_port_operations sil680_port_ops = {
669a5db4 JG	199	.set_piomode = sil680_set_piomode,
	200	.set_dmamode = sil680_set_dmamode,
	201	.mode_filter = ata_pci_default_filter,
	202	.tf_load = ata_tf_load,
	203	.tf_read = ata_tf_read,
	204	.check_status = ata_check_status,
	205	.exec_command = ata_exec_command,
	206	.dev_select = ata_std_dev_select,
	207
	208	.freeze = ata_bmdma_freeze,
	209	.thaw = ata_bmdma_thaw,
dd05c199	210	.error_handler = ata_bmdma_error_handler,
669a5db4	211	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a0fcdc02	212	.cable_detect = sil680_cable_detect,
669a5db4 JG	213
	214	.bmdma_setup = ata_bmdma_setup,
	215	.bmdma_start = ata_bmdma_start,
	216	.bmdma_stop = ata_bmdma_stop,
	217	.bmdma_status = ata_bmdma_status,
	218
	219	.qc_prep = ata_qc_prep,
	220	.qc_issue = ata_qc_issue_prot,
bda30288	221
0d5ff566	222	.data_xfer = ata_data_xfer,
669a5db4 JG	223
	224	.irq_handler = ata_interrupt,
	225	.irq_clear = ata_bmdma_irq_clear,
246ce3b6	226	.irq_on = ata_irq_on,
669a5db4	227
81ad1837	228	.port_start = ata_sff_port_start,
669a5db4 JG	229	};
669a5db4 JG	230
8550c163 AC	231	/**
	232	* sil680_init_chip - chip setup
	233	* @pdev: PCI device
	234	*
	235	* Perform all the chip setup which must be done both when the device
	236	* is powered up on boot and when we resume in case we resumed from RAM.
	237	* Returns the final clock settings.
	238	*/
f20b16ff	239
2b9e68f7	240	static u8 sil680_init_chip(struct pci_dev pdev, int try_mmio)
669a5db4	241	{
669a5db4 JG	242	u32 class_rev = 0;
	243	u8 tmpbyte = 0;
	244
669a5db4 JG	245	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
	246	class_rev &= 0xff;
	247	/* FIXME: double check */
	248	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
	249
	250	pci_write_config_byte(pdev, 0x80, 0x00);
	251	pci_write_config_byte(pdev, 0x84, 0x00);
	252
	253	pci_read_config_byte(pdev, 0x8A, &tmpbyte);
	254
79b0bde1 JG	255	dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
79b0bde1 JG	256	tmpbyte & 1, tmpbyte & 0x30);
669a5db4	257
0f436eff	258	*try_mmio = 0;
119b3aa6	259	#ifdef CONFIG_PPC_MERGE
0f436eff BH	260	if (machine_is(cell))
	261	*try_mmio = (tmpbyte & 1) \|\| pci_resource_start(pdev, 5);
	262	#endif
2b9e68f7	263
669a5db4 JG	264	switch(tmpbyte & 0x30) {
	265	case 0x00:
	266	/* 133 clock attempt to force it on */
	267	pci_write_config_byte(pdev, 0x8A, tmpbyte\|0x10);
	268	break;
	269	case 0x30:
	270	/* if clocking is disabled */
	271	/* 133 clock attempt to force it on */
	272	pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
	273	break;
	274	case 0x10:
	275	/* 133 already */
	276	break;
	277	case 0x20:
	278	/* BIOS set PCI x2 clocking */
	279	break;
	280	}
	281
	282	pci_read_config_byte(pdev, 0x8A, &tmpbyte);
79b0bde1 JG	283	dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
79b0bde1 JG	284	tmpbyte & 1, tmpbyte & 0x30);
669a5db4 JG	285
	286	pci_write_config_byte(pdev, 0xA1, 0x72);
	287	pci_write_config_word(pdev, 0xA2, 0x328A);
	288	pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
	289	pci_write_config_dword(pdev, 0xA8, 0x43924392);
	290	pci_write_config_dword(pdev, 0xAC, 0x40094009);
	291	pci_write_config_byte(pdev, 0xB1, 0x72);
	292	pci_write_config_word(pdev, 0xB2, 0x328A);
	293	pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
	294	pci_write_config_dword(pdev, 0xB8, 0x43924392);
	295	pci_write_config_dword(pdev, 0xBC, 0x40094009);
	296
	297	switch(tmpbyte & 0x30) {
	298	case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break;
	299	case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break;
	300	case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break;
	301	/* This last case is _NOT_ ok */
	302	case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n");
8550c163 AC	303	}
	304	return tmpbyte & 0x30;
	305	}
	306
79b0bde1 JG	307	static int __devinit sil680_init_one(struct pci_dev *pdev,
79b0bde1 JG	308	const struct pci_device_id *id)
8550c163	309	{
1626aeb8	310	static const struct ata_port_info info = {
8550c163	311	.sht = &sil680_sht,
1d2808fd	312	.flags = ATA_FLAG_SLAVE_POSS,
8550c163 AC	313	.pio_mask = 0x1f,
8550c163 AC	314	.mwdma_mask = 0x07,
bf6263a8	315	.udma_mask = ATA_UDMA6,
8550c163 AC	316	.port_ops = &sil680_port_ops
8550c163 AC	317	};
1626aeb8	318	static const struct ata_port_info info_slow = {
8550c163	319	.sht = &sil680_sht,
1d2808fd	320	.flags = ATA_FLAG_SLAVE_POSS,
8550c163 AC	321	.pio_mask = 0x1f,
8550c163 AC	322	.mwdma_mask = 0x07,
bf6263a8	323	.udma_mask = ATA_UDMA5,
8550c163 AC	324	.port_ops = &sil680_port_ops
8550c163 AC	325	};
1626aeb8	326	const struct ata_port_info *ppi[] = { &info, NULL };
8550c163	327	static int printed_version;
2b9e68f7 BH	328	struct ata_host *host;
	329	void __iomem *mmio_base;
	330	int rc, try_mmio;
8550c163 AC	331
	332	if (!printed_version++)
	333	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
	334
f08048e9 TH	335	rc = pcim_enable_device(pdev);
	336	if (rc)
	337	return rc;
	338
2b9e68f7	339	switch (sil680_init_chip(pdev, &try_mmio)) {
8550c163	340	case 0:
1626aeb8	341	ppi[0] = &info_slow;
8550c163 AC	342	break;
	343	case 0x30:
	344	return -ENODEV;
669a5db4	345	}
2b9e68f7 BH	346
	347	if (!try_mmio)
	348	goto use_ioports;
	349
	350	/* Try to acquire MMIO resources and fallback to PIO if
	351	* that fails
	352	*/
	353	rc = pcim_enable_device(pdev);
	354	if (rc)
	355	return rc;
	356	rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME);
	357	if (rc)
	358	goto use_ioports;
	359
	360	/* Allocate host and set it up */
	361	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	362	if (!host)
	363	return -ENOMEM;
	364	host->iomap = pcim_iomap_table(pdev);
	365
	366	/* Setup DMA masks */
	367	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	368	if (rc)
	369	return rc;
	370	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	371	if (rc)
	372	return rc;
	373	pci_set_master(pdev);
	374
	375	/* Get MMIO base and initialize port addresses */
	376	mmio_base = host->iomap[SIL680_MMIO_BAR];
	377	host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;
	378	host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;
	379	host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;
	380	host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;
	381	ata_std_ports(&host->ports[0]->ioaddr);
	382	host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;
	383	host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;
	384	host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;
	385	host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;
	386	ata_std_ports(&host->ports[1]->ioaddr);
	387
	388	/* Register & activate */
	389	return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
	390	&sil680_sht);
	391
	392	use_ioports:
1626aeb8	393	return ata_pci_init_one(pdev, ppi);
669a5db4 JG	394	}
669a5db4 JG	395
438ac6d5	396	#ifdef CONFIG_PM
8550c163 AC	397	static int sil680_reinit_one(struct pci_dev *pdev)
8550c163 AC	398	{
f08048e9 TH	399	struct ata_host *host = dev_get_drvdata(&pdev->dev);
f08048e9 TH	400	int try_mmio, rc;
2b9e68f7	401
f08048e9 TH	402	rc = ata_pci_device_do_resume(pdev);
	403	if (rc)
	404	return rc;
2b9e68f7	405	sil680_init_chip(pdev, &try_mmio);
f08048e9 TH	406	ata_host_resume(host);
f08048e9 TH	407	return 0;
8550c163	408	}
438ac6d5	409	#endif
8550c163	410
669a5db4	411	static const struct pci_device_id sil680[] = {
2d2744fc JG	412	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },
	413
	414	{ },
669a5db4 JG	415	};
	416
	417	static struct pci_driver sil680_pci_driver = {
2d2744fc	418	.name = DRV_NAME,
669a5db4 JG	419	.id_table = sil680,
669a5db4 JG	420	.probe = sil680_init_one,
8550c163	421	.remove = ata_pci_remove_one,
438ac6d5	422	#ifdef CONFIG_PM
8550c163 AC	423	.suspend = ata_pci_device_suspend,
8550c163 AC	424	.resume = sil680_reinit_one,
438ac6d5	425	#endif
669a5db4 JG	426	};
	427
	428	static int __init sil680_init(void)
	429	{
	430	return pci_register_driver(&sil680_pci_driver);
	431	}
	432
669a5db4 JG	433	static void __exit sil680_exit(void)
	434	{
	435	pci_unregister_driver(&sil680_pci_driver);
	436	}
	437
669a5db4 JG	438	MODULE_AUTHOR("Alan Cox");
	439	MODULE_DESCRIPTION("low-level driver for SI680 PATA");
	440	MODULE_LICENSE("GPL");
	441	MODULE_DEVICE_TABLE(pci, sil680);
	442	MODULE_VERSION(DRV_VERSION);
	443
	444	module_init(sil680_init);
	445	module_exit(sil680_exit);