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Commit | Line | Data |
---|---|---|
9352f69c RM |
1 | /* |
2 | * Broadcom specific AMBA | |
3 | * PCI Core in hostmode | |
4 | * | |
49dc9577 HM |
5 | * Copyright 2005 - 2011, Broadcom Corporation |
6 | * Copyright 2006, 2007, Michael Buesch <m@bues.ch> | |
7 | * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> | |
8 | * | |
9352f69c RM |
9 | * Licensed under the GNU/GPL. See COPYING for details. |
10 | */ | |
11 | ||
12 | #include "bcma_private.h" | |
58f743ee | 13 | #include <linux/pci.h> |
49dc9577 | 14 | #include <linux/export.h> |
9352f69c | 15 | #include <linux/bcma/bcma.h> |
49dc9577 HM |
16 | #include <asm/paccess.h> |
17 | ||
18 | /* Probe a 32bit value on the bus and catch bus exceptions. | |
19 | * Returns nonzero on a bus exception. | |
20 | * This is MIPS specific */ | |
21 | #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr))) | |
22 | ||
23 | /* Assume one-hot slot wiring */ | |
24 | #define BCMA_PCI_SLOT_MAX 16 | |
25 | #define PCI_CONFIG_SPACE_SIZE 256 | |
26 | ||
27 | bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) | |
28 | { | |
29 | struct bcma_bus *bus = pc->core->bus; | |
30 | u16 chipid_top; | |
31 | u32 tmp; | |
32 | ||
33 | chipid_top = (bus->chipinfo.id & 0xFF00); | |
34 | if (chipid_top != 0x4700 && | |
35 | chipid_top != 0x5300) | |
36 | return false; | |
37 | ||
49dc9577 HM |
38 | bcma_core_enable(pc->core, 0); |
39 | ||
40 | return !mips_busprobe32(tmp, pc->core->io_addr); | |
41 | } | |
42 | ||
43 | static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address) | |
44 | { | |
45 | pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address); | |
46 | pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR); | |
47 | return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA); | |
48 | } | |
49 | ||
50 | static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address, | |
51 | u32 data) | |
52 | { | |
53 | pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address); | |
54 | pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR); | |
55 | pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data); | |
56 | } | |
57 | ||
58 | static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev, | |
59 | unsigned int func, unsigned int off) | |
60 | { | |
61 | u32 addr = 0; | |
62 | ||
63 | /* Issue config commands only when the data link is up (atleast | |
64 | * one external pcie device is present). | |
65 | */ | |
66 | if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG) | |
67 | & BCMA_CORE_PCI_DLLP_LSREG_LINKUP)) | |
68 | goto out; | |
69 | ||
70 | /* Type 0 transaction */ | |
71 | /* Slide the PCI window to the appropriate slot */ | |
72 | pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0); | |
73 | /* Calculate the address */ | |
74 | addr = pc->host_controller->host_cfg_addr; | |
75 | addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT); | |
76 | addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT); | |
77 | addr |= (off & ~3); | |
78 | ||
79 | out: | |
80 | return addr; | |
81 | } | |
82 | ||
83 | static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev, | |
84 | unsigned int func, unsigned int off, | |
85 | void *buf, int len) | |
86 | { | |
87 | int err = -EINVAL; | |
88 | u32 addr, val; | |
89 | void __iomem *mmio = 0; | |
90 | ||
91 | WARN_ON(!pc->hostmode); | |
92 | if (unlikely(len != 1 && len != 2 && len != 4)) | |
93 | goto out; | |
94 | if (dev == 0) { | |
95 | /* we support only two functions on device 0 */ | |
96 | if (func > 1) | |
a35ab937 | 97 | goto out; |
49dc9577 HM |
98 | |
99 | /* accesses to config registers with offsets >= 256 | |
100 | * requires indirect access. | |
101 | */ | |
102 | if (off >= PCI_CONFIG_SPACE_SIZE) { | |
103 | addr = (func << 12); | |
b09e9abd | 104 | addr |= (off & 0x0FFC); |
49dc9577 HM |
105 | val = bcma_pcie_read_config(pc, addr); |
106 | } else { | |
107 | addr = BCMA_CORE_PCI_PCICFG0; | |
108 | addr |= (func << 8); | |
660b9caa | 109 | addr |= (off & 0xFC); |
49dc9577 HM |
110 | val = pcicore_read32(pc, addr); |
111 | } | |
112 | } else { | |
113 | addr = bcma_get_cfgspace_addr(pc, dev, func, off); | |
114 | if (unlikely(!addr)) | |
115 | goto out; | |
116 | err = -ENOMEM; | |
c61cab3a | 117 | mmio = ioremap_nocache(addr, sizeof(val)); |
49dc9577 HM |
118 | if (!mmio) |
119 | goto out; | |
120 | ||
121 | if (mips_busprobe32(val, mmio)) { | |
660b9caa | 122 | val = 0xFFFFFFFF; |
49dc9577 HM |
123 | goto unmap; |
124 | } | |
49dc9577 HM |
125 | } |
126 | val >>= (8 * (off & 3)); | |
127 | ||
128 | switch (len) { | |
129 | case 1: | |
130 | *((u8 *)buf) = (u8)val; | |
131 | break; | |
132 | case 2: | |
133 | *((u16 *)buf) = (u16)val; | |
134 | break; | |
135 | case 4: | |
136 | *((u32 *)buf) = (u32)val; | |
137 | break; | |
138 | } | |
139 | err = 0; | |
140 | unmap: | |
141 | if (mmio) | |
142 | iounmap(mmio); | |
143 | out: | |
144 | return err; | |
145 | } | |
146 | ||
147 | static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev, | |
148 | unsigned int func, unsigned int off, | |
149 | const void *buf, int len) | |
150 | { | |
151 | int err = -EINVAL; | |
447d7e25 | 152 | u32 addr, val; |
49dc9577 HM |
153 | void __iomem *mmio = 0; |
154 | u16 chipid = pc->core->bus->chipinfo.id; | |
155 | ||
156 | WARN_ON(!pc->hostmode); | |
157 | if (unlikely(len != 1 && len != 2 && len != 4)) | |
158 | goto out; | |
159 | if (dev == 0) { | |
a35ab937 NH |
160 | /* we support only two functions on device 0 */ |
161 | if (func > 1) | |
162 | goto out; | |
163 | ||
49dc9577 HM |
164 | /* accesses to config registers with offsets >= 256 |
165 | * requires indirect access. | |
166 | */ | |
b09e9abd NH |
167 | if (off >= PCI_CONFIG_SPACE_SIZE) { |
168 | addr = (func << 12); | |
169 | addr |= (off & 0x0FFC); | |
170 | val = bcma_pcie_read_config(pc, addr); | |
171 | } else { | |
447d7e25 | 172 | addr = BCMA_CORE_PCI_PCICFG0; |
49dc9577 | 173 | addr |= (func << 8); |
660b9caa | 174 | addr |= (off & 0xFC); |
447d7e25 | 175 | val = pcicore_read32(pc, addr); |
49dc9577 HM |
176 | } |
177 | } else { | |
178 | addr = bcma_get_cfgspace_addr(pc, dev, func, off); | |
179 | if (unlikely(!addr)) | |
180 | goto out; | |
181 | err = -ENOMEM; | |
c61cab3a | 182 | mmio = ioremap_nocache(addr, sizeof(val)); |
49dc9577 HM |
183 | if (!mmio) |
184 | goto out; | |
185 | ||
186 | if (mips_busprobe32(val, mmio)) { | |
660b9caa | 187 | val = 0xFFFFFFFF; |
49dc9577 HM |
188 | goto unmap; |
189 | } | |
190 | } | |
191 | ||
192 | switch (len) { | |
193 | case 1: | |
49dc9577 HM |
194 | val &= ~(0xFF << (8 * (off & 3))); |
195 | val |= *((const u8 *)buf) << (8 * (off & 3)); | |
196 | break; | |
197 | case 2: | |
49dc9577 HM |
198 | val &= ~(0xFFFF << (8 * (off & 3))); |
199 | val |= *((const u16 *)buf) << (8 * (off & 3)); | |
200 | break; | |
201 | case 4: | |
202 | val = *((const u32 *)buf); | |
203 | break; | |
204 | } | |
447d7e25 | 205 | if (dev == 0) { |
49dc9577 HM |
206 | /* accesses to config registers with offsets >= 256 |
207 | * requires indirect access. | |
208 | */ | |
b09e9abd | 209 | if (off >= PCI_CONFIG_SPACE_SIZE) |
447d7e25 | 210 | bcma_pcie_write_config(pc, addr, val); |
b09e9abd | 211 | else |
447d7e25 | 212 | pcicore_write32(pc, addr, val); |
49dc9577 HM |
213 | } else { |
214 | writel(val, mmio); | |
215 | ||
4b4f5be2 HM |
216 | if (chipid == BCMA_CHIP_ID_BCM4716 || |
217 | chipid == BCMA_CHIP_ID_BCM4748) | |
49dc9577 HM |
218 | readl(mmio); |
219 | } | |
220 | ||
221 | err = 0; | |
222 | unmap: | |
223 | if (mmio) | |
224 | iounmap(mmio); | |
225 | out: | |
226 | return err; | |
227 | } | |
228 | ||
229 | static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus, | |
230 | unsigned int devfn, | |
231 | int reg, int size, u32 *val) | |
232 | { | |
233 | unsigned long flags; | |
234 | int err; | |
235 | struct bcma_drv_pci *pc; | |
236 | struct bcma_drv_pci_host *pc_host; | |
237 | ||
238 | pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops); | |
239 | pc = pc_host->pdev; | |
240 | ||
241 | spin_lock_irqsave(&pc_host->cfgspace_lock, flags); | |
242 | err = bcma_extpci_read_config(pc, PCI_SLOT(devfn), | |
243 | PCI_FUNC(devfn), reg, val, size); | |
244 | spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags); | |
245 | ||
246 | return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; | |
247 | } | |
248 | ||
249 | static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus, | |
250 | unsigned int devfn, | |
251 | int reg, int size, u32 val) | |
252 | { | |
253 | unsigned long flags; | |
254 | int err; | |
255 | struct bcma_drv_pci *pc; | |
256 | struct bcma_drv_pci_host *pc_host; | |
257 | ||
258 | pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops); | |
259 | pc = pc_host->pdev; | |
260 | ||
261 | spin_lock_irqsave(&pc_host->cfgspace_lock, flags); | |
262 | err = bcma_extpci_write_config(pc, PCI_SLOT(devfn), | |
263 | PCI_FUNC(devfn), reg, &val, size); | |
264 | spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags); | |
265 | ||
266 | return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; | |
267 | } | |
268 | ||
269 | /* return cap_offset if requested capability exists in the PCI config space */ | |
270 | static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc, | |
271 | unsigned int dev, | |
272 | unsigned int func, u8 req_cap_id, | |
273 | unsigned char *buf, u32 *buflen) | |
274 | { | |
275 | u8 cap_id; | |
276 | u8 cap_ptr = 0; | |
277 | u32 bufsize; | |
278 | u8 byte_val; | |
279 | ||
280 | /* check for Header type 0 */ | |
281 | bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val, | |
282 | sizeof(u8)); | |
660b9caa | 283 | if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL) |
49dc9577 HM |
284 | return cap_ptr; |
285 | ||
286 | /* check if the capability pointer field exists */ | |
287 | bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val, | |
288 | sizeof(u8)); | |
289 | if (!(byte_val & PCI_STATUS_CAP_LIST)) | |
290 | return cap_ptr; | |
291 | ||
292 | /* check if the capability pointer is 0x00 */ | |
293 | bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr, | |
294 | sizeof(u8)); | |
295 | if (cap_ptr == 0x00) | |
296 | return cap_ptr; | |
297 | ||
298 | /* loop thr'u the capability list and see if the requested capabilty | |
299 | * exists */ | |
300 | bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8)); | |
301 | while (cap_id != req_cap_id) { | |
302 | bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr, | |
303 | sizeof(u8)); | |
304 | if (cap_ptr == 0x00) | |
305 | return cap_ptr; | |
306 | bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, | |
307 | sizeof(u8)); | |
308 | } | |
309 | ||
310 | /* found the caller requested capability */ | |
311 | if ((buf != NULL) && (buflen != NULL)) { | |
312 | u8 cap_data; | |
313 | ||
314 | bufsize = *buflen; | |
315 | if (!bufsize) | |
316 | return cap_ptr; | |
317 | ||
318 | *buflen = 0; | |
319 | ||
320 | /* copy the cpability data excluding cap ID and next ptr */ | |
321 | cap_data = cap_ptr + 2; | |
322 | if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE) | |
323 | bufsize = PCI_CONFIG_SPACE_SIZE - cap_data; | |
324 | *buflen = bufsize; | |
325 | while (bufsize--) { | |
326 | bcma_extpci_read_config(pc, dev, func, cap_data, buf, | |
327 | sizeof(u8)); | |
328 | cap_data++; | |
329 | buf++; | |
330 | } | |
331 | } | |
332 | ||
333 | return cap_ptr; | |
334 | } | |
335 | ||
336 | /* If the root port is capable of returning Config Request | |
337 | * Retry Status (CRS) Completion Status to software then | |
338 | * enable the feature. | |
339 | */ | |
340 | static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc) | |
341 | { | |
3d9d8af3 | 342 | struct bcma_bus *bus = pc->core->bus; |
49dc9577 HM |
343 | u8 cap_ptr, root_ctrl, root_cap, dev; |
344 | u16 val16; | |
345 | int i; | |
346 | ||
347 | cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL, | |
348 | NULL); | |
349 | root_cap = cap_ptr + PCI_EXP_RTCAP; | |
350 | bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16)); | |
351 | if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) { | |
352 | /* Enable CRS software visibility */ | |
353 | root_ctrl = cap_ptr + PCI_EXP_RTCTL; | |
354 | val16 = PCI_EXP_RTCTL_CRSSVE; | |
355 | bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16, | |
356 | sizeof(u16)); | |
357 | ||
358 | /* Initiate a configuration request to read the vendor id | |
359 | * field of the device function's config space header after | |
360 | * 100 ms wait time from the end of Reset. If the device is | |
361 | * not done with its internal initialization, it must at | |
362 | * least return a completion TLP, with a completion status | |
363 | * of "Configuration Request Retry Status (CRS)". The root | |
364 | * complex must complete the request to the host by returning | |
365 | * a read-data value of 0001h for the Vendor ID field and | |
366 | * all 1s for any additional bytes included in the request. | |
367 | * Poll using the config reads for max wait time of 1 sec or | |
368 | * until we receive the successful completion status. Repeat | |
369 | * the procedure for all the devices. | |
370 | */ | |
371 | for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) { | |
372 | for (i = 0; i < 100000; i++) { | |
373 | bcma_extpci_read_config(pc, dev, 0, | |
374 | PCI_VENDOR_ID, &val16, | |
375 | sizeof(val16)); | |
376 | if (val16 != 0x1) | |
377 | break; | |
378 | udelay(10); | |
379 | } | |
380 | if (val16 == 0x1) | |
3d9d8af3 RM |
381 | bcma_err(bus, "PCI: Broken device in slot %d\n", |
382 | dev); | |
49dc9577 HM |
383 | } |
384 | } | |
385 | } | |
9352f69c | 386 | |
d1a7a8e1 | 387 | void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) |
9352f69c | 388 | { |
49dc9577 HM |
389 | struct bcma_bus *bus = pc->core->bus; |
390 | struct bcma_drv_pci_host *pc_host; | |
391 | u32 tmp; | |
392 | u32 pci_membase_1G; | |
393 | unsigned long io_map_base; | |
394 | ||
3d9d8af3 | 395 | bcma_info(bus, "PCIEcore in host mode found\n"); |
49dc9577 | 396 | |
2b4766c3 HM |
397 | if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) { |
398 | bcma_info(bus, "This PCIE core is disabled and not working\n"); | |
399 | return; | |
400 | } | |
401 | ||
49dc9577 HM |
402 | pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL); |
403 | if (!pc_host) { | |
3d9d8af3 | 404 | bcma_err(bus, "can not allocate memory"); |
49dc9577 HM |
405 | return; |
406 | } | |
407 | ||
408 | pc->host_controller = pc_host; | |
409 | pc_host->pci_controller.io_resource = &pc_host->io_resource; | |
410 | pc_host->pci_controller.mem_resource = &pc_host->mem_resource; | |
411 | pc_host->pci_controller.pci_ops = &pc_host->pci_ops; | |
412 | pc_host->pdev = pc; | |
413 | ||
414 | pci_membase_1G = BCMA_SOC_PCI_DMA; | |
415 | pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG; | |
416 | ||
417 | pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config; | |
418 | pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config; | |
419 | ||
420 | pc_host->mem_resource.name = "BCMA PCIcore external memory", | |
421 | pc_host->mem_resource.start = BCMA_SOC_PCI_DMA; | |
422 | pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1; | |
423 | pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED; | |
424 | ||
425 | pc_host->io_resource.name = "BCMA PCIcore external I/O", | |
426 | pc_host->io_resource.start = 0x100; | |
427 | pc_host->io_resource.end = 0x7FF; | |
428 | pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED; | |
429 | ||
430 | /* Reset RC */ | |
1fd41a65 | 431 | usleep_range(3000, 5000); |
49dc9577 | 432 | pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE); |
990debe2 | 433 | msleep(50); |
49dc9577 HM |
434 | pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST | |
435 | BCMA_CORE_PCI_CTL_RST_OE); | |
436 | ||
437 | /* 64 MB I/O access window. On 4716, use | |
438 | * sbtopcie0 to access the device registers. We | |
439 | * can't use address match 2 (1 GB window) region | |
440 | * as mips can't generate 64-bit address on the | |
441 | * backplane. | |
442 | */ | |
4b4f5be2 HM |
443 | if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 || |
444 | bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) { | |
49dc9577 HM |
445 | pc_host->mem_resource.start = BCMA_SOC_PCI_MEM; |
446 | pc_host->mem_resource.end = BCMA_SOC_PCI_MEM + | |
447 | BCMA_SOC_PCI_MEM_SZ - 1; | |
448 | pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, | |
449 | BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM); | |
4b4f5be2 | 450 | } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) { |
49dc9577 HM |
451 | tmp = BCMA_CORE_PCI_SBTOPCI_MEM; |
452 | tmp |= BCMA_CORE_PCI_SBTOPCI_PREF; | |
453 | tmp |= BCMA_CORE_PCI_SBTOPCI_BURST; | |
454 | if (pc->core->core_unit == 0) { | |
455 | pc_host->mem_resource.start = BCMA_SOC_PCI_MEM; | |
456 | pc_host->mem_resource.end = BCMA_SOC_PCI_MEM + | |
457 | BCMA_SOC_PCI_MEM_SZ - 1; | |
dfae7143 HM |
458 | pc_host->io_resource.start = 0x100; |
459 | pc_host->io_resource.end = 0x47F; | |
49dc9577 HM |
460 | pci_membase_1G = BCMA_SOC_PCIE_DMA_H32; |
461 | pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, | |
462 | tmp | BCMA_SOC_PCI_MEM); | |
463 | } else if (pc->core->core_unit == 1) { | |
464 | pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM; | |
465 | pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM + | |
466 | BCMA_SOC_PCI_MEM_SZ - 1; | |
dfae7143 HM |
467 | pc_host->io_resource.start = 0x480; |
468 | pc_host->io_resource.end = 0x7FF; | |
49dc9577 HM |
469 | pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32; |
470 | pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG; | |
471 | pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, | |
472 | tmp | BCMA_SOC_PCI1_MEM); | |
473 | } | |
474 | } else | |
475 | pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, | |
476 | BCMA_CORE_PCI_SBTOPCI_IO); | |
477 | ||
478 | /* 64 MB configuration access window */ | |
479 | pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0); | |
480 | ||
481 | /* 1 GB memory access window */ | |
482 | pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2, | |
483 | BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G); | |
484 | ||
485 | ||
486 | /* As per PCI Express Base Spec 1.1 we need to wait for | |
487 | * at least 100 ms from the end of a reset (cold/warm/hot) | |
488 | * before issuing configuration requests to PCI Express | |
489 | * devices. | |
490 | */ | |
1fd41a65 | 491 | msleep(100); |
49dc9577 HM |
492 | |
493 | bcma_core_pci_enable_crs(pc); | |
494 | ||
990debe2 NH |
495 | if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 || |
496 | bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) { | |
497 | u16 val16; | |
498 | bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL, | |
499 | &val16, sizeof(val16)); | |
500 | val16 |= (2 << 5); /* Max payload size of 512 */ | |
501 | val16 |= (2 << 12); /* MRRS 512 */ | |
502 | bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL, | |
503 | &val16, sizeof(val16)); | |
504 | } | |
505 | ||
49dc9577 HM |
506 | /* Enable PCI bridge BAR0 memory & master access */ |
507 | tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; | |
508 | bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp)); | |
509 | ||
510 | /* Enable PCI interrupts */ | |
511 | pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA); | |
512 | ||
513 | /* Ok, ready to run, register it to the system. | |
514 | * The following needs change, if we want to port hostmode | |
515 | * to non-MIPS platform. */ | |
4acabf45 NH |
516 | io_map_base = (unsigned long)ioremap_nocache(pc_host->mem_resource.start, |
517 | resource_size(&pc_host->mem_resource)); | |
49dc9577 HM |
518 | pc_host->pci_controller.io_map_base = io_map_base; |
519 | set_io_port_base(pc_host->pci_controller.io_map_base); | |
520 | /* Give some time to the PCI controller to configure itself with the new | |
521 | * values. Not waiting at this point causes crashes of the machine. */ | |
1fd41a65 | 522 | usleep_range(10000, 15000); |
49dc9577 HM |
523 | register_pci_controller(&pc_host->pci_controller); |
524 | return; | |
525 | } | |
526 | ||
527 | /* Early PCI fixup for a device on the PCI-core bridge. */ | |
528 | static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev) | |
529 | { | |
530 | if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { | |
531 | /* This is not a device on the PCI-core bridge. */ | |
532 | return; | |
533 | } | |
534 | if (PCI_SLOT(dev->devfn) != 0) | |
535 | return; | |
536 | ||
537 | pr_info("PCI: Fixing up bridge %s\n", pci_name(dev)); | |
538 | ||
539 | /* Enable PCI bridge bus mastering and memory space */ | |
540 | pci_set_master(dev); | |
541 | if (pcibios_enable_device(dev, ~0) < 0) { | |
542 | pr_err("PCI: BCMA bridge enable failed\n"); | |
543 | return; | |
544 | } | |
545 | ||
546 | /* Enable PCI bridge BAR1 prefetch and burst */ | |
547 | pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3); | |
548 | } | |
549 | DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge); | |
550 | ||
551 | /* Early PCI fixup for all PCI-cores to set the correct memory address. */ | |
552 | static void bcma_core_pci_fixup_addresses(struct pci_dev *dev) | |
553 | { | |
554 | struct resource *res; | |
4a7267c9 | 555 | int pos, err; |
49dc9577 HM |
556 | |
557 | if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { | |
558 | /* This is not a device on the PCI-core bridge. */ | |
559 | return; | |
560 | } | |
561 | if (PCI_SLOT(dev->devfn) == 0) | |
562 | return; | |
563 | ||
564 | pr_info("PCI: Fixing up addresses %s\n", pci_name(dev)); | |
565 | ||
566 | for (pos = 0; pos < 6; pos++) { | |
567 | res = &dev->resource[pos]; | |
4a7267c9 HM |
568 | if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) { |
569 | err = pci_assign_resource(dev, pos); | |
570 | if (err) | |
571 | pr_err("PCI: Problem fixing up the addresses on %s\n", | |
572 | pci_name(dev)); | |
573 | } | |
49dc9577 HM |
574 | } |
575 | } | |
576 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses); | |
577 | ||
578 | /* This function is called when doing a pci_enable_device(). | |
579 | * We must first check if the device is a device on the PCI-core bridge. */ | |
580 | int bcma_core_pci_plat_dev_init(struct pci_dev *dev) | |
581 | { | |
582 | struct bcma_drv_pci_host *pc_host; | |
583 | ||
584 | if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { | |
585 | /* This is not a device on the PCI-core bridge. */ | |
586 | return -ENODEV; | |
587 | } | |
588 | pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, | |
589 | pci_ops); | |
590 | ||
591 | pr_info("PCI: Fixing up device %s\n", pci_name(dev)); | |
592 | ||
593 | /* Fix up interrupt lines */ | |
e2aa19fa | 594 | dev->irq = bcma_core_irq(pc_host->pdev->core); |
49dc9577 HM |
595 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); |
596 | ||
597 | return 0; | |
598 | } | |
599 | EXPORT_SYMBOL(bcma_core_pci_plat_dev_init); | |
600 | ||
601 | /* PCI device IRQ mapping. */ | |
602 | int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev) | |
603 | { | |
604 | struct bcma_drv_pci_host *pc_host; | |
605 | ||
606 | if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { | |
607 | /* This is not a device on the PCI-core bridge. */ | |
608 | return -ENODEV; | |
609 | } | |
610 | ||
611 | pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, | |
612 | pci_ops); | |
e2aa19fa | 613 | return bcma_core_irq(pc_host->pdev->core); |
9352f69c | 614 | } |
49dc9577 | 615 | EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq); |