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ed0e3520 | 1 | /* |
c10d5c9e | 2 | * OMAP L3 Interconnect error handling driver header |
ed0e3520 | 3 | * |
c5f2aea0 | 4 | * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/ |
ed0e3520 | 5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
6 | * sricharan <r.sricharan@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
c5f2aea0 NM |
9 | * it under the terms of the GNU General Public License version 2 as |
10 | * published by the Free Software Foundation. | |
ed0e3520 | 11 | * |
c5f2aea0 NM |
12 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
13 | * kind, whether express or implied; without even the implied warranty | |
14 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
ed0e3520 | 15 | * GNU General Public License for more details. |
ed0e3520 | 16 | */ |
c10d5c9e S |
17 | #ifndef __OMAP_L3_NOC_H |
18 | #define __OMAP_L3_NOC_H | |
2722e56d | 19 | |
0659452d | 20 | #define MAX_L3_MODULES 3 |
97708c08 | 21 | #define MAX_CLKDM_TARGETS 31 |
0659452d | 22 | |
2722e56d SS |
23 | #define CLEAR_STDERR_LOG (1 << 31) |
24 | #define CUSTOM_ERROR 0x2 | |
25 | #define STANDARD_ERROR 0x0 | |
26 | #define INBAND_ERROR 0x0 | |
2722e56d SS |
27 | #define L3_APPLICATION_ERROR 0x0 |
28 | #define L3_DEBUG_ERROR 0x1 | |
29 | ||
342fd144 | 30 | /* L3 TARG register offsets */ |
ed0e3520 | 31 | #define L3_TARG_STDERRLOG_MAIN 0x48 |
7f9de02d | 32 | #define L3_TARG_STDERRLOG_HDR 0x4c |
c98aa7aa | 33 | #define L3_TARG_STDERRLOG_MSTADDR 0x50 |
cf52b2ec | 34 | #define L3_TARG_STDERRLOG_INFO 0x58 |
ed0e3520 | 35 | #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c |
cf52b2ec | 36 | #define L3_TARG_STDERRLOG_CINFO_INFO 0x64 |
c98aa7aa | 37 | #define L3_TARG_STDERRLOG_CINFO_MSTADDR 0x68 |
7f9de02d | 38 | #define L3_TARG_STDERRLOG_CINFO_OPCODE 0x6c |
ed0e3520 | 39 | #define L3_FLAGMUX_REGERR0 0xc |
3340d739 RN |
40 | #define L3_FLAGMUX_MASK0 0x8 |
41 | ||
42 | #define L3_TARGET_NOT_SUPPORTED NULL | |
43 | ||
7f9de02d NM |
44 | static const char * const l3_transaction_type[] = { |
45 | /* 0 0 0 */ "Idle", | |
46 | /* 0 0 1 */ "Write", | |
47 | /* 0 1 0 */ "Read", | |
48 | /* 0 1 1 */ "ReadEx", | |
49 | /* 1 0 0 */ "Read Link", | |
50 | /* 1 0 1 */ "Write Non-Posted", | |
51 | /* 1 1 0 */ "Write Conditional", | |
52 | /* 1 1 1 */ "Write Broadcast", | |
53 | }; | |
54 | ||
f0a6e654 NM |
55 | /** |
56 | * struct l3_masters_data - L3 Master information | |
57 | * @id: ID of the L3 Master | |
58 | * @name: master name | |
59 | */ | |
60 | struct l3_masters_data { | |
61 | u32 id; | |
62 | char *name; | |
63 | }; | |
64 | ||
3ae9af7c NM |
65 | /** |
66 | * struct l3_target_data - L3 Target information | |
67 | * @offset: Offset from base for L3 Target | |
68 | * @name: Target name | |
69 | * | |
70 | * Target information is organized indexed by bit field definitions. | |
71 | */ | |
72 | struct l3_target_data { | |
73 | u32 offset; | |
74 | char *name; | |
75 | }; | |
76 | ||
97708c08 NM |
77 | /** |
78 | * struct l3_flagmux_data - Flag Mux information | |
79 | * @offset: offset from base for flagmux register | |
80 | * @l3_targ: array indexed by flagmux index (bit offset) pointing to the | |
81 | * target data. unsupported ones are marked with | |
82 | * L3_TARGET_NOT_SUPPORTED | |
83 | * @num_targ_data: number of entries in target data | |
2100b595 AM |
84 | * @mask_app_bits: ignore these from raw application irq status |
85 | * @mask_dbg_bits: ignore these from raw debug irq status | |
97708c08 NM |
86 | */ |
87 | struct l3_flagmux_data { | |
88 | u32 offset; | |
89 | struct l3_target_data *l3_targ; | |
90 | u8 num_targ_data; | |
2100b595 AM |
91 | u32 mask_app_bits; |
92 | u32 mask_dbg_bits; | |
97708c08 NM |
93 | }; |
94 | ||
0659452d S |
95 | |
96 | /** | |
97 | * struct omap_l3 - Description of data relevant for L3 bus. | |
98 | * @dev: device representing the bus (populated runtime) | |
99 | * @l3_base: base addresses of modules (populated runtime) | |
97708c08 | 100 | * @l3_flag_mux: array containing flag mux data per module |
0659452d S |
101 | * offset from corresponding module base indexed per |
102 | * module. | |
103 | * @num_modules: number of clock domains / modules. | |
104 | * @l3_masters: array pointing to master data containing name and register | |
105 | * offset for the master. | |
106 | * @num_master: number of masters | |
d4d8819e | 107 | * @mst_addr_mask: Mask representing MSTADDR information of NTTP packet |
0659452d S |
108 | * @debug_irq: irq number of the debug interrupt (populated runtime) |
109 | * @app_irq: irq number of the application interrupt (populated runtime) | |
110 | */ | |
111 | struct omap_l3 { | |
112 | struct device *dev; | |
113 | ||
114 | void __iomem *l3_base[MAX_L3_MODULES]; | |
97708c08 | 115 | struct l3_flagmux_data **l3_flagmux; |
0659452d S |
116 | int num_modules; |
117 | ||
118 | struct l3_masters_data *l3_masters; | |
119 | int num_masters; | |
d4d8819e | 120 | u32 mst_addr_mask; |
0659452d | 121 | |
0659452d S |
122 | int debug_irq; |
123 | int app_irq; | |
124 | }; | |
125 | ||
97708c08 | 126 | static struct l3_target_data omap_l3_target_data_clk1[] = { |
3ae9af7c NM |
127 | {0x100, "DMM1",}, |
128 | {0x200, "DMM2",}, | |
129 | {0x300, "ABE",}, | |
130 | {0x400, "L4CFG",}, | |
131 | {0x600, "CLK2PWRDISC",}, | |
132 | {0x0, "HOSTCLK1",}, | |
133 | {0x900, "L4WAKEUP",}, | |
2722e56d SS |
134 | }; |
135 | ||
97708c08 NM |
136 | static struct l3_flagmux_data omap_l3_flagmux_clk1 = { |
137 | .offset = 0x500, | |
138 | .l3_targ = omap_l3_target_data_clk1, | |
139 | .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk1), | |
140 | }; | |
141 | ||
142 | ||
143 | static struct l3_target_data omap_l3_target_data_clk2[] = { | |
3ae9af7c NM |
144 | {0x500, "CORTEXM3",}, |
145 | {0x300, "DSS",}, | |
146 | {0x100, "GPMC",}, | |
147 | {0x400, "ISS",}, | |
148 | {0x700, "IVAHD",}, | |
149 | {0xD00, "AES1",}, | |
150 | {0x900, "L4PER0",}, | |
151 | {0x200, "OCMRAM",}, | |
152 | {0x100, "GPMCsERROR",}, | |
153 | {0x600, "SGX",}, | |
154 | {0x800, "SL2",}, | |
155 | {0x1600, "C2C",}, | |
156 | {0x1100, "PWRDISCCLK1",}, | |
157 | {0xF00, "SHA1",}, | |
158 | {0xE00, "AES2",}, | |
159 | {0xC00, "L4PER3",}, | |
160 | {0xA00, "L4PER1",}, | |
161 | {0xB00, "L4PER2",}, | |
162 | {0x0, "HOSTCLK2",}, | |
163 | {0x1800, "CAL",}, | |
164 | {0x1700, "LLI",}, | |
2722e56d SS |
165 | }; |
166 | ||
97708c08 NM |
167 | static struct l3_flagmux_data omap_l3_flagmux_clk2 = { |
168 | .offset = 0x1000, | |
169 | .l3_targ = omap_l3_target_data_clk2, | |
170 | .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk2), | |
171 | }; | |
172 | ||
173 | ||
174 | static struct l3_target_data omap_l3_target_data_clk3[] = { | |
3ae9af7c NM |
175 | {0x0100, "EMUSS",}, |
176 | {0x0300, "DEBUG SOURCE",}, | |
177 | {0x0, "HOST CLK3",}, | |
2722e56d SS |
178 | }; |
179 | ||
97708c08 NM |
180 | static struct l3_flagmux_data omap_l3_flagmux_clk3 = { |
181 | .offset = 0x0200, | |
182 | .l3_targ = omap_l3_target_data_clk3, | |
183 | .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk3), | |
184 | }; | |
185 | ||
0659452d | 186 | static struct l3_masters_data omap_l3_masters[] = { |
551a9fa9 | 187 | { 0x0 , "MPU"}, |
188 | { 0x10, "CS_ADP"}, | |
189 | { 0x14, "xxx"}, | |
190 | { 0x20, "DSP"}, | |
191 | { 0x30, "IVAHD"}, | |
192 | { 0x40, "ISS"}, | |
193 | { 0x44, "DucatiM3"}, | |
194 | { 0x48, "FaceDetect"}, | |
195 | { 0x50, "SDMA_Rd"}, | |
196 | { 0x54, "SDMA_Wr"}, | |
197 | { 0x58, "xxx"}, | |
198 | { 0x5C, "xxx"}, | |
199 | { 0x60, "SGX"}, | |
200 | { 0x70, "DSS"}, | |
201 | { 0x80, "C2C"}, | |
202 | { 0x88, "xxx"}, | |
203 | { 0x8C, "xxx"}, | |
204 | { 0x90, "HSI"}, | |
205 | { 0xA0, "MMC1"}, | |
206 | { 0xA4, "MMC2"}, | |
207 | { 0xA8, "MMC6"}, | |
208 | { 0xB0, "UNIPRO1"}, | |
209 | { 0xC0, "USBHOSTHS"}, | |
210 | { 0xC4, "USBOTGHS"}, | |
211 | { 0xC8, "USBHOSTFS"} | |
212 | }; | |
213 | ||
97708c08 NM |
214 | static struct l3_flagmux_data *omap_l3_flagmux[] = { |
215 | &omap_l3_flagmux_clk1, | |
216 | &omap_l3_flagmux_clk2, | |
217 | &omap_l3_flagmux_clk3, | |
2722e56d SS |
218 | }; |
219 | ||
0659452d S |
220 | static const struct omap_l3 omap_l3_data = { |
221 | .l3_flagmux = omap_l3_flagmux, | |
97708c08 | 222 | .num_modules = ARRAY_SIZE(omap_l3_flagmux), |
0659452d S |
223 | .l3_masters = omap_l3_masters, |
224 | .num_masters = ARRAY_SIZE(omap_l3_masters), | |
d4d8819e NM |
225 | /* The 6 MSBs of register field used to distinguish initiator */ |
226 | .mst_addr_mask = 0xFC, | |
2722e56d | 227 | }; |
c10d5c9e S |
228 | |
229 | #endif /* __OMAP_L3_NOC_H */ |