[mirror_ubuntu-bionic-kernel.git] / drivers / clk / clk-divider.c

/*
 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Adjustable divider clock implementation
 */

#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/string.h>
#include <linux/log2.h>

/*
 * DOC: basic adjustable divider clock that cannot gate
 *
 * Traits of this clock:
 * prepare - clk_prepare only ensures that parents are prepared
 * enable - clk_enable only ensures that parents are enabled
 * rate - rate is adjustable.  clk->rate = DIV_ROUND_UP(parent->rate / divisor)
 * parent - fixed parent.  No clk_set_parent support
 */

#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)

#define div_mask(d)	((1 << ((d)->width)) - 1)

static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
{
	unsigned int maxdiv = 0;
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->div > maxdiv)
			maxdiv = clkt->div;
	return maxdiv;
}

static unsigned int _get_table_mindiv(const struct clk_div_table *table)
{
	unsigned int mindiv = UINT_MAX;
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->div < mindiv)
			mindiv = clkt->div;
	return mindiv;
}

static unsigned int _get_maxdiv(struct clk_divider *divider)
{
	if (divider->flags & CLK_DIVIDER_ONE_BASED)
		return div_mask(divider);
	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
		return 1 << div_mask(divider);
	if (divider->table)
		return _get_table_maxdiv(divider->table);
	return div_mask(divider) + 1;
}

static unsigned int _get_table_div(const struct clk_div_table *table,
							unsigned int val)
{
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->val == val)
			return clkt->div;
	return 0;
}

static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
{
	if (divider->flags & CLK_DIVIDER_ONE_BASED)
		return val;
	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
		return 1 << val;
	if (divider->table)
		return _get_table_div(divider->table, val);
	return val + 1;
}

static unsigned int _get_table_val(const struct clk_div_table *table,
							unsigned int div)
{
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->div == div)
			return clkt->val;
	return 0;
}

static unsigned int _get_val(struct clk_divider *divider, unsigned int div)
{
	if (divider->flags & CLK_DIVIDER_ONE_BASED)
		return div;
	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
		return __ffs(div);
	if (divider->table)
		return  _get_table_val(divider->table, div);
	return div - 1;
}

static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{
	struct clk_divider *divider = to_clk_divider(hw);
	unsigned int div, val;

	val = clk_readl(divider->reg) >> divider->shift;
	val &= div_mask(divider);

	div = _get_div(divider, val);
	if (!div) {
		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
			"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
			__clk_get_name(hw->clk));
		return parent_rate;
	}

	return DIV_ROUND_UP(parent_rate, div);
}

/*
 * The reverse of DIV_ROUND_UP: The maximum number which
 * divided by m is r
 */
#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)

static bool _is_valid_table_div(const struct clk_div_table *table,
							 unsigned int div)
{
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->div == div)
			return true;
	return false;
}

static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
{
	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
		return is_power_of_2(div);
	if (divider->table)
		return _is_valid_table_div(divider->table, div);
	return true;
}

static int _round_up_table(const struct clk_div_table *table, int div)
{
	const struct clk_div_table *clkt;
	int up = _get_table_maxdiv(table);

	for (clkt = table; clkt->div; clkt++) {
		if (clkt->div == div)
			return clkt->div;
		else if (clkt->div < div)
			continue;

		if ((clkt->div - div) < (up - div))
			up = clkt->div;
	}

	return up;
}

static int _round_down_table(const struct clk_div_table *table, int div)
{
	const struct clk_div_table *clkt;
	int down = _get_table_mindiv(table);

	for (clkt = table; clkt->div; clkt++) {
		if (clkt->div == div)
			return clkt->div;
		else if (clkt->div > div)
			continue;

		if ((div - clkt->div) < (div - down))
			down = clkt->div;
	}

	return down;
}

static int _div_round_up(struct clk_divider *divider,
		unsigned long parent_rate, unsigned long rate)
{
	int div = DIV_ROUND_UP(parent_rate, rate);

	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
		div = __roundup_pow_of_two(div);
	if (divider->table)
		div = _round_up_table(divider->table, div);

	return div;
}

static int _div_round_closest(struct clk_divider *divider,
		unsigned long parent_rate, unsigned long rate)
{
	int up, down, div;

	up = down = div = DIV_ROUND_CLOSEST(parent_rate, rate);

	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) {
		up = __roundup_pow_of_two(div);
		down = __rounddown_pow_of_two(div);
	} else if (divider->table) {
		up = _round_up_table(divider->table, div);
		down = _round_down_table(divider->table, div);
	}

	return (up - div) <= (div - down) ? up : down;
}

static int _div_round(struct clk_divider *divider, unsigned long parent_rate,
		unsigned long rate)
{
	if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST)
		return _div_round_closest(divider, parent_rate, rate);

	return _div_round_up(divider, parent_rate, rate);
}

static bool _is_best_div(struct clk_divider *divider,
		int rate, int now, int best)
{
	if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST)
		return abs(rate - now) < abs(rate - best);

	return now <= rate && now > best;
}

static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
		unsigned long *best_parent_rate)
{
	struct clk_divider *divider = to_clk_divider(hw);
	int i, bestdiv = 0;
	unsigned long parent_rate, best = 0, now, maxdiv;
	unsigned long parent_rate_saved = *best_parent_rate;

	if (!rate)
		rate = 1;

	maxdiv = _get_maxdiv(divider);

	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
		parent_rate = *best_parent_rate;
		bestdiv = _div_round(divider, parent_rate, rate);
		bestdiv = bestdiv == 0 ? 1 : bestdiv;
		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
		return bestdiv;
	}

	/*
	 * The maximum divider we can use without overflowing
	 * unsigned long in rate * i below
	 */
	maxdiv = min(ULONG_MAX / rate, maxdiv);

	for (i = 1; i <= maxdiv; i++) {
		if (!_is_valid_div(divider, i))
			continue;
		if (rate * i == parent_rate_saved) {
			/*
			 * It's the most ideal case if the requested rate can be
			 * divided from parent clock without needing to change
			 * parent rate, so return the divider immediately.
			 */
			*best_parent_rate = parent_rate_saved;
			return i;
		}
		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
				MULT_ROUND_UP(rate, i));
		now = DIV_ROUND_UP(parent_rate, i);
		if (_is_best_div(divider, rate, now, best)) {
			bestdiv = i;
			best = now;
			*best_parent_rate = parent_rate;
		}
	}

	if (!bestdiv) {
		bestdiv = _get_maxdiv(divider);
		*best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
	}

	return bestdiv;
}

static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long *prate)
{
	int div;
	div = clk_divider_bestdiv(hw, rate, prate);

	return DIV_ROUND_UP(*prate, div);
}

static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{
	struct clk_divider *divider = to_clk_divider(hw);
	unsigned int div, value;
	unsigned long flags = 0;
	u32 val;

	div = DIV_ROUND_UP(parent_rate, rate);

	if (!_is_valid_div(divider, div))
		return -EINVAL;

	value = _get_val(divider, div);

	if (value > div_mask(divider))
		value = div_mask(divider);

	if (divider->lock)
		spin_lock_irqsave(divider->lock, flags);

	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
		val = div_mask(divider) << (divider->shift + 16);
	} else {
		val = clk_readl(divider->reg);
		val &= ~(div_mask(divider) << divider->shift);
	}
	val |= value << divider->shift;
	clk_writel(val, divider->reg);

	if (divider->lock)
		spin_unlock_irqrestore(divider->lock, flags);

	return 0;
}

const struct clk_ops clk_divider_ops = {
	.recalc_rate = clk_divider_recalc_rate,
	.round_rate = clk_divider_round_rate,
	.set_rate = clk_divider_set_rate,
};
EXPORT_SYMBOL_GPL(clk_divider_ops);

static struct clk *_register_divider(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_divider_flags, const struct clk_div_table *table,
		spinlock_t *lock)
{
	struct clk_divider *div;
	struct clk *clk;
	struct clk_init_data init;

	if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
		if (width + shift > 16) {
			pr_warn("divider value exceeds LOWORD field\n");
			return ERR_PTR(-EINVAL);
		}
	}

	/* allocate the divider */
	div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
	if (!div) {
		pr_err("%s: could not allocate divider clk\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	init.name = name;
	init.ops = &clk_divider_ops;
	init.flags = flags | CLK_IS_BASIC;
	init.parent_names = (parent_name ? &parent_name: NULL);
	init.num_parents = (parent_name ? 1 : 0);

	/* struct clk_divider assignments */
	div->reg = reg;
	div->shift = shift;
	div->width = width;
	div->flags = clk_divider_flags;
	div->lock = lock;
	div->hw.init = &init;
	div->table = table;

	/* register the clock */
	clk = clk_register(dev, &div->hw);

	if (IS_ERR(clk))
		kfree(div);

	return clk;
}

/**
 * clk_register_divider - register a divider clock with the clock framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @lock: shared register lock for this clock
 */
struct clk *clk_register_divider(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_divider_flags, spinlock_t *lock)
{
	return _register_divider(dev, name, parent_name, flags, reg, shift,
			width, clk_divider_flags, NULL, lock);
}
EXPORT_SYMBOL_GPL(clk_register_divider);

/**
 * clk_register_divider_table - register a table based divider clock with
 * the clock framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @table: array of divider/value pairs ending with a div set to 0
 * @lock: shared register lock for this clock
 */
struct clk *clk_register_divider_table(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_divider_flags, const struct clk_div_table *table,
		spinlock_t *lock)
{
	return _register_divider(dev, name, parent_name, flags, reg, shift,
			width, clk_divider_flags, table, lock);
}
EXPORT_SYMBOL_GPL(clk_register_divider_table);
Commit	Line	Data
9d9f78ed MT	1	/*
	2	* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
	3	* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
	4	* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Adjustable divider clock implementation
	11	*/
	12
	13	#include <linux/clk-provider.h>
	14	#include <linux/module.h>
	15	#include <linux/slab.h>
	16	#include <linux/io.h>
	17	#include <linux/err.h>
	18	#include <linux/string.h>
1a3cd184	19	#include <linux/log2.h>
9d9f78ed MT	20
	21	/*
	22	* DOC: basic adjustable divider clock that cannot gate
	23	*
	24	* Traits of this clock:
	25	* prepare - clk_prepare only ensures that parents are prepared
	26	* enable - clk_enable only ensures that parents are enabled
b11d282d	27	* rate - rate is adjustable. clk->rate = DIV_ROUND_UP(parent->rate / divisor)
9d9f78ed MT	28	* parent - fixed parent. No clk_set_parent support
	29	*/
	30
	31	#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
	32
1a3cd184	33	#define div_mask(d) ((1 << ((d)->width)) - 1)
6d9252bd	34
357c3f0a RN	35	static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
	36	{
	37	unsigned int maxdiv = 0;
	38	const struct clk_div_table *clkt;
	39
	40	for (clkt = table; clkt->div; clkt++)
	41	if (clkt->div > maxdiv)
	42	maxdiv = clkt->div;
	43	return maxdiv;
	44	}
	45
774b5143 MC	46	static unsigned int _get_table_mindiv(const struct clk_div_table *table)
	47	{
	48	unsigned int mindiv = UINT_MAX;
	49	const struct clk_div_table *clkt;
	50
	51	for (clkt = table; clkt->div; clkt++)
	52	if (clkt->div < mindiv)
	53	mindiv = clkt->div;
	54	return mindiv;
	55	}
	56
6d9252bd RN	57	static unsigned int _get_maxdiv(struct clk_divider *divider)
	58	{
	59	if (divider->flags & CLK_DIVIDER_ONE_BASED)
	60	return div_mask(divider);
	61	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
	62	return 1 << div_mask(divider);
357c3f0a RN	63	if (divider->table)
357c3f0a RN	64	return _get_table_maxdiv(divider->table);
6d9252bd RN	65	return div_mask(divider) + 1;
	66	}
	67
357c3f0a RN	68	static unsigned int _get_table_div(const struct clk_div_table *table,
	69	unsigned int val)
	70	{
	71	const struct clk_div_table *clkt;
	72
	73	for (clkt = table; clkt->div; clkt++)
	74	if (clkt->val == val)
	75	return clkt->div;
	76	return 0;
	77	}
	78
6d9252bd RN	79	static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
	80	{
	81	if (divider->flags & CLK_DIVIDER_ONE_BASED)
	82	return val;
	83	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
	84	return 1 << val;
357c3f0a RN	85	if (divider->table)
357c3f0a RN	86	return _get_table_div(divider->table, val);
6d9252bd RN	87	return val + 1;
	88	}
	89
357c3f0a RN	90	static unsigned int _get_table_val(const struct clk_div_table *table,
	91	unsigned int div)
	92	{
	93	const struct clk_div_table *clkt;
	94
	95	for (clkt = table; clkt->div; clkt++)
	96	if (clkt->div == div)
	97	return clkt->val;
	98	return 0;
	99	}
	100
778037e1	101	static unsigned int _get_val(struct clk_divider *divider, unsigned int div)
6d9252bd RN	102	{
	103	if (divider->flags & CLK_DIVIDER_ONE_BASED)
	104	return div;
	105	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
	106	return __ffs(div);
357c3f0a RN	107	if (divider->table)
357c3f0a RN	108	return _get_table_val(divider->table, div);
6d9252bd RN	109	return div - 1;
6d9252bd RN	110	}
9d9f78ed MT	111
	112	static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
	113	unsigned long parent_rate)
	114	{
	115	struct clk_divider *divider = to_clk_divider(hw);
6d9252bd	116	unsigned int div, val;
9d9f78ed	117
aa514ce3	118	val = clk_readl(divider->reg) >> divider->shift;
6d9252bd	119	val &= div_mask(divider);
9d9f78ed	120
6d9252bd RN	121	div = _get_div(divider, val);
6d9252bd RN	122	if (!div) {
056b2053 SB	123	WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
	124	"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
	125	__clk_get_name(hw->clk));
6d9252bd RN	126	return parent_rate;
6d9252bd RN	127	}
9d9f78ed	128
b11d282d	129	return DIV_ROUND_UP(parent_rate, div);
9d9f78ed	130	}
9d9f78ed MT	131
	132	/*
	133	* The reverse of DIV_ROUND_UP: The maximum number which
	134	* divided by m is r
	135	*/
	136	#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
	137
357c3f0a RN	138	static bool _is_valid_table_div(const struct clk_div_table *table,
	139	unsigned int div)
	140	{
	141	const struct clk_div_table *clkt;
	142
	143	for (clkt = table; clkt->div; clkt++)
	144	if (clkt->div == div)
	145	return true;
	146	return false;
	147	}
	148
	149	static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
	150	{
	151	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
1a3cd184	152	return is_power_of_2(div);
357c3f0a RN	153	if (divider->table)
	154	return _is_valid_table_div(divider->table, div);
	155	return true;
	156	}
	157
dd23c2cd MC	158	static int _round_up_table(const struct clk_div_table *table, int div)
	159	{
	160	const struct clk_div_table *clkt;
	161	int up = _get_table_maxdiv(table);
	162
	163	for (clkt = table; clkt->div; clkt++) {
	164	if (clkt->div == div)
	165	return clkt->div;
	166	else if (clkt->div < div)
	167	continue;
	168
	169	if ((clkt->div - div) < (up - div))
	170	up = clkt->div;
	171	}
	172
	173	return up;
	174	}
	175
774b5143 MC	176	static int _round_down_table(const struct clk_div_table *table, int div)
	177	{
	178	const struct clk_div_table *clkt;
	179	int down = _get_table_mindiv(table);
	180
	181	for (clkt = table; clkt->div; clkt++) {
	182	if (clkt->div == div)
	183	return clkt->div;
	184	else if (clkt->div > div)
	185	continue;
	186
	187	if ((div - clkt->div) < (div - down))
	188	down = clkt->div;
	189	}
	190
	191	return down;
	192	}
	193
dd23c2cd MC	194	static int _div_round_up(struct clk_divider *divider,
	195	unsigned long parent_rate, unsigned long rate)
	196	{
	197	int div = DIV_ROUND_UP(parent_rate, rate);
	198
	199	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
	200	div = __roundup_pow_of_two(div);
	201	if (divider->table)
	202	div = _round_up_table(divider->table, div);
	203
	204	return div;
	205	}
	206
774b5143 MC	207	static int _div_round_closest(struct clk_divider *divider,
	208	unsigned long parent_rate, unsigned long rate)
	209	{
	210	int up, down, div;
	211
	212	up = down = div = DIV_ROUND_CLOSEST(parent_rate, rate);
	213
	214	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) {
	215	up = __roundup_pow_of_two(div);
	216	down = __rounddown_pow_of_two(div);
	217	} else if (divider->table) {
	218	up = _round_up_table(divider->table, div);
	219	down = _round_down_table(divider->table, div);
	220	}
	221
	222	return (up - div) <= (div - down) ? up : down;
	223	}
	224
	225	static int _div_round(struct clk_divider *divider, unsigned long parent_rate,
	226	unsigned long rate)
	227	{
	228	if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST)
	229	return _div_round_closest(divider, parent_rate, rate);
	230
	231	return _div_round_up(divider, parent_rate, rate);
	232	}
	233
	234	static bool _is_best_div(struct clk_divider *divider,
	235	int rate, int now, int best)
	236	{
	237	if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST)
	238	return abs(rate - now) < abs(rate - best);
	239
	240	return now <= rate && now > best;
	241	}
	242
9d9f78ed MT	243	static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
	244	unsigned long *best_parent_rate)
	245	{
	246	struct clk_divider *divider = to_clk_divider(hw);
	247	int i, bestdiv = 0;
	248	unsigned long parent_rate, best = 0, now, maxdiv;
081c9025	249	unsigned long parent_rate_saved = *best_parent_rate;
9d9f78ed MT	250
	251	if (!rate)
	252	rate = 1;
	253
6d9252bd	254	maxdiv = _get_maxdiv(divider);
9d9f78ed	255
81536e07 SG	256	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
81536e07 SG	257	parent_rate = *best_parent_rate;
774b5143	258	bestdiv = _div_round(divider, parent_rate, rate);
9d9f78ed MT	259	bestdiv = bestdiv == 0 ? 1 : bestdiv;
	260	bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
	261	return bestdiv;
	262	}
	263
	264	/*
	265	* The maximum divider we can use without overflowing
	266	* unsigned long in rate * i below
	267	*/
	268	maxdiv = min(ULONG_MAX / rate, maxdiv);
	269
	270	for (i = 1; i <= maxdiv; i++) {
357c3f0a	271	if (!_is_valid_div(divider, i))
6d9252bd	272	continue;
081c9025 SG	273	if (rate * i == parent_rate_saved) {
	274	/*
	275	* It's the most ideal case if the requested rate can be
	276	* divided from parent clock without needing to change
	277	* parent rate, so return the divider immediately.
	278	*/
	279	*best_parent_rate = parent_rate_saved;
	280	return i;
	281	}
9d9f78ed MT	282	parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
9d9f78ed MT	283	MULT_ROUND_UP(rate, i));
b11d282d	284	now = DIV_ROUND_UP(parent_rate, i);
774b5143	285	if (_is_best_div(divider, rate, now, best)) {
9d9f78ed MT	286	bestdiv = i;
	287	best = now;
	288	*best_parent_rate = parent_rate;
	289	}
	290	}
	291
	292	if (!bestdiv) {
6d9252bd	293	bestdiv = _get_maxdiv(divider);
9d9f78ed MT	294	*best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
	295	}
	296
	297	return bestdiv;
	298	}
	299
	300	static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
	301	unsigned long *prate)
	302	{
	303	int div;
	304	div = clk_divider_bestdiv(hw, rate, prate);
	305
b11d282d	306	return DIV_ROUND_UP(*prate, div);
9d9f78ed	307	}
9d9f78ed	308
1c0035d7 SG	309	static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
1c0035d7 SG	310	unsigned long parent_rate)
9d9f78ed MT	311	{
9d9f78ed MT	312	struct clk_divider *divider = to_clk_divider(hw);
6d9252bd	313	unsigned int div, value;
9d9f78ed MT	314	unsigned long flags = 0;
	315	u32 val;
	316
b11d282d	317	div = DIV_ROUND_UP(parent_rate, rate);
dd23c2cd MC	318
	319	if (!_is_valid_div(divider, div))
	320	return -EINVAL;
	321
6d9252bd	322	value = _get_val(divider, div);
9d9f78ed	323
6d9252bd RN	324	if (value > div_mask(divider))
6d9252bd RN	325	value = div_mask(divider);
9d9f78ed MT	326
	327	if (divider->lock)
	328	spin_lock_irqsave(divider->lock, flags);
	329
d57dfe75 HZ	330	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
	331	val = div_mask(divider) << (divider->shift + 16);
	332	} else {
aa514ce3	333	val = clk_readl(divider->reg);
d57dfe75 HZ	334	val &= ~(div_mask(divider) << divider->shift);
d57dfe75 HZ	335	}
6d9252bd	336	val \|= value << divider->shift;
aa514ce3	337	clk_writel(val, divider->reg);
9d9f78ed MT	338
	339	if (divider->lock)
	340	spin_unlock_irqrestore(divider->lock, flags);
	341
	342	return 0;
	343	}
9d9f78ed	344
822c250e	345	const struct clk_ops clk_divider_ops = {
9d9f78ed MT	346	.recalc_rate = clk_divider_recalc_rate,
	347	.round_rate = clk_divider_round_rate,
	348	.set_rate = clk_divider_set_rate,
	349	};
	350	EXPORT_SYMBOL_GPL(clk_divider_ops);
	351
357c3f0a	352	static struct clk _register_divider(struct device dev, const char *name,
9d9f78ed MT	353	const char *parent_name, unsigned long flags,
9d9f78ed MT	354	void __iomem *reg, u8 shift, u8 width,
357c3f0a RN	355	u8 clk_divider_flags, const struct clk_div_table *table,
357c3f0a RN	356	spinlock_t *lock)
9d9f78ed MT	357	{
	358	struct clk_divider *div;
	359	struct clk *clk;
0197b3ea	360	struct clk_init_data init;
9d9f78ed	361
d57dfe75 HZ	362	if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
	363	if (width + shift > 16) {
	364	pr_warn("divider value exceeds LOWORD field\n");
	365	return ERR_PTR(-EINVAL);
	366	}
	367	}
	368
27d54591	369	/* allocate the divider */
9d9f78ed	370	div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
9d9f78ed MT	371	if (!div) {
9d9f78ed MT	372	pr_err("%s: could not allocate divider clk\n", __func__);
27d54591	373	return ERR_PTR(-ENOMEM);
9d9f78ed MT	374	}
9d9f78ed MT	375
0197b3ea SK	376	init.name = name;
0197b3ea SK	377	init.ops = &clk_divider_ops;
f7d8caad	378	init.flags = flags \| CLK_IS_BASIC;
0197b3ea SK	379	init.parent_names = (parent_name ? &parent_name: NULL);
	380	init.num_parents = (parent_name ? 1 : 0);
	381
9d9f78ed MT	382	/* struct clk_divider assignments */
	383	div->reg = reg;
	384	div->shift = shift;
	385	div->width = width;
	386	div->flags = clk_divider_flags;
	387	div->lock = lock;
0197b3ea	388	div->hw.init = &init;
357c3f0a	389	div->table = table;
9d9f78ed	390
27d54591	391	/* register the clock */
0197b3ea	392	clk = clk_register(dev, &div->hw);
9d9f78ed	393
27d54591 MT	394	if (IS_ERR(clk))
27d54591 MT	395	kfree(div);
9d9f78ed	396
27d54591	397	return clk;
9d9f78ed	398	}
357c3f0a RN	399
	400	/**
	401	* clk_register_divider - register a divider clock with the clock framework
	402	* @dev: device registering this clock
	403	* @name: name of this clock
	404	* @parent_name: name of clock's parent
	405	* @flags: framework-specific flags
	406	* @reg: register address to adjust divider
	407	* @shift: number of bits to shift the bitfield
	408	* @width: width of the bitfield
	409	* @clk_divider_flags: divider-specific flags for this clock
	410	* @lock: shared register lock for this clock
	411	*/
	412	struct clk clk_register_divider(struct device dev, const char *name,
	413	const char *parent_name, unsigned long flags,
	414	void __iomem *reg, u8 shift, u8 width,
	415	u8 clk_divider_flags, spinlock_t *lock)
	416	{
	417	return _register_divider(dev, name, parent_name, flags, reg, shift,
	418	width, clk_divider_flags, NULL, lock);
	419	}
4c5eeea9	420	EXPORT_SYMBOL_GPL(clk_register_divider);
357c3f0a RN	421
	422	/**
	423	* clk_register_divider_table - register a table based divider clock with
	424	* the clock framework
	425	* @dev: device registering this clock
	426	* @name: name of this clock
	427	* @parent_name: name of clock's parent
	428	* @flags: framework-specific flags
	429	* @reg: register address to adjust divider
	430	* @shift: number of bits to shift the bitfield
	431	* @width: width of the bitfield
	432	* @clk_divider_flags: divider-specific flags for this clock
	433	* @table: array of divider/value pairs ending with a div set to 0
	434	* @lock: shared register lock for this clock
	435	*/
	436	struct clk clk_register_divider_table(struct device dev, const char *name,
	437	const char *parent_name, unsigned long flags,
	438	void __iomem *reg, u8 shift, u8 width,
	439	u8 clk_divider_flags, const struct clk_div_table *table,
	440	spinlock_t *lock)
	441	{
	442	return _register_divider(dev, name, parent_name, flags, reg, shift,
	443	width, clk_divider_flags, table, lock);
	444	}
4c5eeea9	445	EXPORT_SYMBOL_GPL(clk_register_divider_table);