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f0948f59 SH |
1 | /* |
2 | * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Standard functionality for the common clock API. | |
9 | */ | |
10 | #include <linux/module.h> | |
11 | #include <linux/clk-provider.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/err.h> | |
79b16641 | 14 | #include <linux/of.h> |
f0948f59 SH |
15 | |
16 | /* | |
17 | * DOC: basic fixed multiplier and divider clock that cannot gate | |
18 | * | |
19 | * Traits of this clock: | |
20 | * prepare - clk_prepare only ensures that parents are prepared | |
21 | * enable - clk_enable only ensures that parents are enabled | |
22 | * rate - rate is fixed. clk->rate = parent->rate / div * mult | |
23 | * parent - fixed parent. No clk_set_parent support | |
24 | */ | |
25 | ||
f0948f59 SH |
26 | static unsigned long clk_factor_recalc_rate(struct clk_hw *hw, |
27 | unsigned long parent_rate) | |
28 | { | |
29 | struct clk_fixed_factor *fix = to_clk_fixed_factor(hw); | |
bab53301 | 30 | unsigned long long int rate; |
f0948f59 | 31 | |
bab53301 HZ |
32 | rate = (unsigned long long int)parent_rate * fix->mult; |
33 | do_div(rate, fix->div); | |
34 | return (unsigned long)rate; | |
f0948f59 SH |
35 | } |
36 | ||
37 | static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate, | |
38 | unsigned long *prate) | |
39 | { | |
40 | struct clk_fixed_factor *fix = to_clk_fixed_factor(hw); | |
41 | ||
98d8a60e | 42 | if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { |
f0948f59 SH |
43 | unsigned long best_parent; |
44 | ||
45 | best_parent = (rate / fix->mult) * fix->div; | |
2f508a95 | 46 | *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); |
f0948f59 SH |
47 | } |
48 | ||
49 | return (*prate / fix->div) * fix->mult; | |
50 | } | |
51 | ||
52 | static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate, | |
53 | unsigned long parent_rate) | |
54 | { | |
3037e9ea DT |
55 | /* |
56 | * We must report success but we can do so unconditionally because | |
57 | * clk_factor_round_rate returns values that ensure this call is a | |
58 | * nop. | |
59 | */ | |
60 | ||
f0948f59 SH |
61 | return 0; |
62 | } | |
63 | ||
3037e9ea | 64 | const struct clk_ops clk_fixed_factor_ops = { |
f0948f59 SH |
65 | .round_rate = clk_factor_round_rate, |
66 | .set_rate = clk_factor_set_rate, | |
67 | .recalc_rate = clk_factor_recalc_rate, | |
68 | }; | |
69 | EXPORT_SYMBOL_GPL(clk_fixed_factor_ops); | |
70 | ||
71 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, | |
72 | const char *parent_name, unsigned long flags, | |
73 | unsigned int mult, unsigned int div) | |
74 | { | |
75 | struct clk_fixed_factor *fix; | |
76 | struct clk_init_data init; | |
77 | struct clk *clk; | |
78 | ||
79 | fix = kmalloc(sizeof(*fix), GFP_KERNEL); | |
d122db7e | 80 | if (!fix) |
f0948f59 | 81 | return ERR_PTR(-ENOMEM); |
f0948f59 SH |
82 | |
83 | /* struct clk_fixed_factor assignments */ | |
84 | fix->mult = mult; | |
85 | fix->div = div; | |
86 | fix->hw.init = &init; | |
87 | ||
88 | init.name = name; | |
89 | init.ops = &clk_fixed_factor_ops; | |
f7d8caad | 90 | init.flags = flags | CLK_IS_BASIC; |
f0948f59 SH |
91 | init.parent_names = &parent_name; |
92 | init.num_parents = 1; | |
93 | ||
94 | clk = clk_register(dev, &fix->hw); | |
95 | ||
96 | if (IS_ERR(clk)) | |
97 | kfree(fix); | |
98 | ||
99 | return clk; | |
100 | } | |
5cfe10bb | 101 | EXPORT_SYMBOL_GPL(clk_register_fixed_factor); |
cbf9591f MY |
102 | |
103 | void clk_unregister_fixed_factor(struct clk *clk) | |
104 | { | |
105 | struct clk_hw *hw; | |
106 | ||
107 | hw = __clk_get_hw(clk); | |
108 | if (!hw) | |
109 | return; | |
110 | ||
111 | clk_unregister(clk); | |
112 | kfree(to_clk_fixed_factor(hw)); | |
113 | } | |
114 | EXPORT_SYMBOL_GPL(clk_unregister_fixed_factor); | |
5cfe10bb | 115 | |
79b16641 GC |
116 | #ifdef CONFIG_OF |
117 | /** | |
118 | * of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock | |
119 | */ | |
120 | void __init of_fixed_factor_clk_setup(struct device_node *node) | |
121 | { | |
122 | struct clk *clk; | |
123 | const char *clk_name = node->name; | |
124 | const char *parent_name; | |
125 | u32 div, mult; | |
126 | ||
127 | if (of_property_read_u32(node, "clock-div", &div)) { | |
128 | pr_err("%s Fixed factor clock <%s> must have a clock-div property\n", | |
129 | __func__, node->name); | |
130 | return; | |
131 | } | |
132 | ||
133 | if (of_property_read_u32(node, "clock-mult", &mult)) { | |
fe2fd5cc | 134 | pr_err("%s Fixed factor clock <%s> must have a clock-mult property\n", |
79b16641 GC |
135 | __func__, node->name); |
136 | return; | |
137 | } | |
138 | ||
139 | of_property_read_string(node, "clock-output-names", &clk_name); | |
140 | parent_name = of_clk_get_parent_name(node, 0); | |
141 | ||
142 | clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, | |
143 | mult, div); | |
144 | if (!IS_ERR(clk)) | |
145 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | |
146 | } | |
147 | EXPORT_SYMBOL_GPL(of_fixed_factor_clk_setup); | |
148 | CLK_OF_DECLARE(fixed_factor_clk, "fixed-factor-clock", | |
149 | of_fixed_factor_clk_setup); | |
150 | #endif |