]>
Commit | Line | Data |
---|---|---|
ef3c613c LP |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * RZ/G2L Clock Pulse Generator | |
4 | * | |
5 | * Copyright (C) 2021 Renesas Electronics Corp. | |
6 | * | |
7 | */ | |
8 | ||
9 | #ifndef __RENESAS_RZG2L_CPG_H__ | |
10 | #define __RENESAS_RZG2L_CPG_H__ | |
11 | ||
12 | #define CPG_PL2_DDIV (0x204) | |
13 | #define CPG_PL3A_DDIV (0x208) | |
14 | ||
15 | /* n = 0/1/2 for PLL1/4/6 */ | |
16 | #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) | |
17 | #define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n)) | |
18 | ||
19 | #define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12) | |
20 | ||
21 | #define DDIV_PACK(offset, bitpos, size) \ | |
22 | (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) | |
23 | #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) | |
24 | #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) | |
25 | ||
26 | /** | |
27 | * Definitions of CPG Core Clocks | |
28 | * | |
29 | * These include: | |
30 | * - Clock outputs exported to DT | |
31 | * - External input clocks | |
32 | * - Internal CPG clocks | |
33 | */ | |
34 | struct cpg_core_clk { | |
35 | const char *name; | |
36 | unsigned int id; | |
37 | unsigned int parent; | |
38 | unsigned int div; | |
39 | unsigned int mult; | |
40 | unsigned int type; | |
41 | unsigned int conf; | |
42 | const struct clk_div_table *dtable; | |
43 | const char * const *parent_names; | |
44 | int flag; | |
45 | int num_parents; | |
46 | }; | |
47 | ||
48 | enum clk_types { | |
49 | /* Generic */ | |
50 | CLK_TYPE_IN, /* External Clock Input */ | |
51 | CLK_TYPE_FF, /* Fixed Factor Clock */ | |
52 | CLK_TYPE_SAM_PLL, | |
53 | ||
54 | /* Clock with divider */ | |
55 | CLK_TYPE_DIV, | |
56 | }; | |
57 | ||
58 | #define DEF_TYPE(_name, _id, _type...) \ | |
59 | { .name = _name, .id = _id, .type = _type } | |
60 | #define DEF_BASE(_name, _id, _type, _parent...) \ | |
61 | DEF_TYPE(_name, _id, _type, .parent = _parent) | |
62 | #define DEF_SAMPLL(_name, _id, _parent, _conf) \ | |
63 | DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) | |
64 | #define DEF_INPUT(_name, _id) \ | |
65 | DEF_TYPE(_name, _id, CLK_TYPE_IN) | |
66 | #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ | |
67 | DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) | |
68 | #define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \ | |
69 | DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ | |
70 | .parent = _parent, .dtable = _dtable, .flag = _flag) | |
71 | ||
72 | /** | |
73 | * struct rzg2l_mod_clk - Module Clocks definitions | |
74 | * | |
75 | * @name: handle between common and hardware-specific interfaces | |
76 | * @id: clock index in array containing all Core and Module Clocks | |
77 | * @parent: id of parent clock | |
78 | * @off: register offset | |
79 | * @onoff: ON/MON bits | |
80 | * @reset: reset bits | |
81 | */ | |
82 | struct rzg2l_mod_clk { | |
83 | const char *name; | |
84 | unsigned int id; | |
85 | unsigned int parent; | |
86 | u16 off; | |
87 | u8 onoff; | |
88 | u8 reset; | |
89 | }; | |
90 | ||
91 | #define DEF_MOD(_name, _id, _parent, _off, _onoff, _reset) \ | |
92 | [_id] = { \ | |
93 | .name = _name, \ | |
94 | .id = MOD_CLK_BASE + _id, \ | |
95 | .parent = (_parent), \ | |
96 | .off = (_off), \ | |
97 | .onoff = (_onoff), \ | |
98 | .reset = (_reset) \ | |
99 | } | |
100 | ||
101 | /** | |
102 | * struct rzg2l_cpg_info - SoC-specific CPG Description | |
103 | * | |
104 | * @core_clks: Array of Core Clock definitions | |
105 | * @num_core_clks: Number of entries in core_clks[] | |
106 | * @last_dt_core_clk: ID of the last Core Clock exported to DT | |
107 | * @num_total_core_clks: Total number of Core Clocks (exported + internal) | |
108 | * | |
109 | * @mod_clks: Array of Module Clock definitions | |
110 | * @num_mod_clks: Number of entries in mod_clks[] | |
111 | * @num_hw_mod_clks: Number of Module Clocks supported by the hardware | |
112 | * | |
113 | * @crit_mod_clks: Array with Module Clock IDs of critical clocks that | |
114 | * should not be disabled without a knowledgeable driver | |
115 | * @num_crit_mod_clks: Number of entries in crit_mod_clks[] | |
116 | */ | |
117 | struct rzg2l_cpg_info { | |
118 | /* Core Clocks */ | |
119 | const struct cpg_core_clk *core_clks; | |
120 | unsigned int num_core_clks; | |
121 | unsigned int last_dt_core_clk; | |
122 | unsigned int num_total_core_clks; | |
123 | ||
124 | /* Module Clocks */ | |
125 | const struct rzg2l_mod_clk *mod_clks; | |
126 | unsigned int num_mod_clks; | |
127 | unsigned int num_hw_mod_clks; | |
128 | ||
129 | /* Critical Module Clocks that should not be disabled */ | |
130 | const unsigned int *crit_mod_clks; | |
131 | unsigned int num_crit_mod_clks; | |
132 | }; | |
133 | ||
17f0ff3d LP |
134 | extern const struct rzg2l_cpg_info r9a07g044_cpg_info; |
135 | ||
ef3c613c | 136 | #endif |