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Commit | Line | Data |
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8a4da6e3 MR |
1 | /* |
2 | * linux/drivers/clocksource/arm_arch_timer.c | |
3 | * | |
4 | * Copyright (C) 2011 ARM Ltd. | |
5 | * All Rights Reserved | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
f005bd7e MZ |
11 | |
12 | #define pr_fmt(fmt) "arm_arch_timer: " fmt | |
13 | ||
8a4da6e3 MR |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/smp.h> | |
18 | #include <linux/cpu.h> | |
346e7480 | 19 | #include <linux/cpu_pm.h> |
8a4da6e3 | 20 | #include <linux/clockchips.h> |
7c8f1e78 | 21 | #include <linux/clocksource.h> |
8a4da6e3 MR |
22 | #include <linux/interrupt.h> |
23 | #include <linux/of_irq.h> | |
22006994 | 24 | #include <linux/of_address.h> |
8a4da6e3 | 25 | #include <linux/io.h> |
22006994 | 26 | #include <linux/slab.h> |
e6017571 | 27 | #include <linux/sched/clock.h> |
65cd4f6c | 28 | #include <linux/sched_clock.h> |
b09ca1ec | 29 | #include <linux/acpi.h> |
8a4da6e3 MR |
30 | |
31 | #include <asm/arch_timer.h> | |
8266891e | 32 | #include <asm/virt.h> |
8a4da6e3 MR |
33 | |
34 | #include <clocksource/arm_arch_timer.h> | |
35 | ||
ded24019 FW |
36 | #undef pr_fmt |
37 | #define pr_fmt(fmt) "arch_timer: " fmt | |
38 | ||
22006994 SB |
39 | #define CNTTIDR 0x08 |
40 | #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4)) | |
41 | ||
e392d603 RM |
42 | #define CNTACR(n) (0x40 + ((n) * 4)) |
43 | #define CNTACR_RPCT BIT(0) | |
44 | #define CNTACR_RVCT BIT(1) | |
45 | #define CNTACR_RFRQ BIT(2) | |
46 | #define CNTACR_RVOFF BIT(3) | |
47 | #define CNTACR_RWVT BIT(4) | |
48 | #define CNTACR_RWPT BIT(5) | |
49 | ||
22006994 SB |
50 | #define CNTVCT_LO 0x08 |
51 | #define CNTVCT_HI 0x0c | |
52 | #define CNTFRQ 0x10 | |
53 | #define CNTP_TVAL 0x28 | |
54 | #define CNTP_CTL 0x2c | |
55 | #define CNTV_TVAL 0x38 | |
56 | #define CNTV_CTL 0x3c | |
57 | ||
22006994 SB |
58 | static unsigned arch_timers_present __initdata; |
59 | ||
60 | static void __iomem *arch_counter_base; | |
61 | ||
62 | struct arch_timer { | |
63 | void __iomem *base; | |
64 | struct clock_event_device evt; | |
65 | }; | |
66 | ||
67 | #define to_arch_timer(e) container_of(e, struct arch_timer, evt) | |
68 | ||
8a4da6e3 | 69 | static u32 arch_timer_rate; |
ee34f1e6 | 70 | static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI]; |
8a4da6e3 MR |
71 | |
72 | static struct clock_event_device __percpu *arch_timer_evt; | |
73 | ||
ee34f1e6 | 74 | static enum arch_timer_ppi_nr arch_timer_uses_ppi = ARCH_TIMER_VIRT_PPI; |
82a56194 | 75 | static bool arch_timer_c3stop; |
22006994 | 76 | static bool arch_timer_mem_use_virtual; |
d8ec7595 | 77 | static bool arch_counter_suspend_stop; |
a86bd139 | 78 | static bool vdso_default = true; |
8a4da6e3 | 79 | |
46fd5c6b WD |
80 | static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM); |
81 | ||
82 | static int __init early_evtstrm_cfg(char *buf) | |
83 | { | |
84 | return strtobool(buf, &evtstrm_enable); | |
85 | } | |
86 | early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg); | |
87 | ||
8a4da6e3 MR |
88 | /* |
89 | * Architected system timer support. | |
90 | */ | |
91 | ||
f4e00a1a MZ |
92 | static __always_inline |
93 | void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, | |
94 | struct clock_event_device *clk) | |
95 | { | |
96 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { | |
97 | struct arch_timer *timer = to_arch_timer(clk); | |
98 | switch (reg) { | |
99 | case ARCH_TIMER_REG_CTRL: | |
100 | writel_relaxed(val, timer->base + CNTP_CTL); | |
101 | break; | |
102 | case ARCH_TIMER_REG_TVAL: | |
103 | writel_relaxed(val, timer->base + CNTP_TVAL); | |
104 | break; | |
105 | } | |
106 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
107 | struct arch_timer *timer = to_arch_timer(clk); | |
108 | switch (reg) { | |
109 | case ARCH_TIMER_REG_CTRL: | |
110 | writel_relaxed(val, timer->base + CNTV_CTL); | |
111 | break; | |
112 | case ARCH_TIMER_REG_TVAL: | |
113 | writel_relaxed(val, timer->base + CNTV_TVAL); | |
114 | break; | |
115 | } | |
116 | } else { | |
117 | arch_timer_reg_write_cp15(access, reg, val); | |
118 | } | |
119 | } | |
120 | ||
121 | static __always_inline | |
122 | u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, | |
123 | struct clock_event_device *clk) | |
124 | { | |
125 | u32 val; | |
126 | ||
127 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { | |
128 | struct arch_timer *timer = to_arch_timer(clk); | |
129 | switch (reg) { | |
130 | case ARCH_TIMER_REG_CTRL: | |
131 | val = readl_relaxed(timer->base + CNTP_CTL); | |
132 | break; | |
133 | case ARCH_TIMER_REG_TVAL: | |
134 | val = readl_relaxed(timer->base + CNTP_TVAL); | |
135 | break; | |
136 | } | |
137 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
138 | struct arch_timer *timer = to_arch_timer(clk); | |
139 | switch (reg) { | |
140 | case ARCH_TIMER_REG_CTRL: | |
141 | val = readl_relaxed(timer->base + CNTV_CTL); | |
142 | break; | |
143 | case ARCH_TIMER_REG_TVAL: | |
144 | val = readl_relaxed(timer->base + CNTV_TVAL); | |
145 | break; | |
146 | } | |
147 | } else { | |
148 | val = arch_timer_reg_read_cp15(access, reg); | |
149 | } | |
150 | ||
151 | return val; | |
152 | } | |
153 | ||
992dd16f MZ |
154 | /* |
155 | * Default to cp15 based access because arm64 uses this function for | |
156 | * sched_clock() before DT is probed and the cp15 method is guaranteed | |
157 | * to exist on arm64. arm doesn't use this before DT is probed so even | |
158 | * if we don't have the cp15 accessors we won't have a problem. | |
159 | */ | |
160 | u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct; | |
161 | ||
162 | static u64 arch_counter_read(struct clocksource *cs) | |
163 | { | |
164 | return arch_timer_read_counter(); | |
165 | } | |
166 | ||
167 | static u64 arch_counter_read_cc(const struct cyclecounter *cc) | |
168 | { | |
169 | return arch_timer_read_counter(); | |
170 | } | |
171 | ||
172 | static struct clocksource clocksource_counter = { | |
173 | .name = "arch_sys_counter", | |
174 | .rating = 400, | |
175 | .read = arch_counter_read, | |
176 | .mask = CLOCKSOURCE_MASK(56), | |
177 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
178 | }; | |
179 | ||
180 | static struct cyclecounter cyclecounter __ro_after_init = { | |
181 | .read = arch_counter_read_cc, | |
182 | .mask = CLOCKSOURCE_MASK(56), | |
183 | }; | |
184 | ||
5a38bcac MZ |
185 | struct ate_acpi_oem_info { |
186 | char oem_id[ACPI_OEM_ID_SIZE + 1]; | |
187 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; | |
188 | u32 oem_revision; | |
189 | }; | |
190 | ||
f6dc1576 | 191 | #ifdef CONFIG_FSL_ERRATUM_A008585 |
16d10ef2 DT |
192 | /* |
193 | * The number of retries is an arbitrary value well beyond the highest number | |
194 | * of iterations the loop has been observed to take. | |
195 | */ | |
196 | #define __fsl_a008585_read_reg(reg) ({ \ | |
197 | u64 _old, _new; \ | |
198 | int _retries = 200; \ | |
199 | \ | |
200 | do { \ | |
201 | _old = read_sysreg(reg); \ | |
202 | _new = read_sysreg(reg); \ | |
203 | _retries--; \ | |
204 | } while (unlikely(_old != _new) && _retries); \ | |
205 | \ | |
206 | WARN_ON_ONCE(!_retries); \ | |
207 | _new; \ | |
208 | }) | |
209 | ||
210 | static u32 notrace fsl_a008585_read_cntp_tval_el0(void) | |
f6dc1576 SW |
211 | { |
212 | return __fsl_a008585_read_reg(cntp_tval_el0); | |
213 | } | |
214 | ||
16d10ef2 | 215 | static u32 notrace fsl_a008585_read_cntv_tval_el0(void) |
f6dc1576 SW |
216 | { |
217 | return __fsl_a008585_read_reg(cntv_tval_el0); | |
218 | } | |
219 | ||
16d10ef2 | 220 | static u64 notrace fsl_a008585_read_cntvct_el0(void) |
f6dc1576 SW |
221 | { |
222 | return __fsl_a008585_read_reg(cntvct_el0); | |
223 | } | |
16d10ef2 DT |
224 | #endif |
225 | ||
bb42ca47 DT |
226 | #ifdef CONFIG_HISILICON_ERRATUM_161010101 |
227 | /* | |
228 | * Verify whether the value of the second read is larger than the first by | |
229 | * less than 32 is the only way to confirm the value is correct, so clear the | |
230 | * lower 5 bits to check whether the difference is greater than 32 or not. | |
231 | * Theoretically the erratum should not occur more than twice in succession | |
232 | * when reading the system counter, but it is possible that some interrupts | |
233 | * may lead to more than twice read errors, triggering the warning, so setting | |
234 | * the number of retries far beyond the number of iterations the loop has been | |
235 | * observed to take. | |
236 | */ | |
237 | #define __hisi_161010101_read_reg(reg) ({ \ | |
238 | u64 _old, _new; \ | |
239 | int _retries = 50; \ | |
240 | \ | |
241 | do { \ | |
242 | _old = read_sysreg(reg); \ | |
243 | _new = read_sysreg(reg); \ | |
244 | _retries--; \ | |
245 | } while (unlikely((_new - _old) >> 5) && _retries); \ | |
246 | \ | |
247 | WARN_ON_ONCE(!_retries); \ | |
248 | _new; \ | |
249 | }) | |
250 | ||
251 | static u32 notrace hisi_161010101_read_cntp_tval_el0(void) | |
252 | { | |
253 | return __hisi_161010101_read_reg(cntp_tval_el0); | |
254 | } | |
255 | ||
256 | static u32 notrace hisi_161010101_read_cntv_tval_el0(void) | |
257 | { | |
258 | return __hisi_161010101_read_reg(cntv_tval_el0); | |
259 | } | |
260 | ||
261 | static u64 notrace hisi_161010101_read_cntvct_el0(void) | |
262 | { | |
263 | return __hisi_161010101_read_reg(cntvct_el0); | |
264 | } | |
d003d029 MZ |
265 | |
266 | static struct ate_acpi_oem_info hisi_161010101_oem_info[] = { | |
267 | /* | |
268 | * Note that trailing spaces are required to properly match | |
269 | * the OEM table information. | |
270 | */ | |
271 | { | |
272 | .oem_id = "HISI ", | |
273 | .oem_table_id = "HIP05 ", | |
274 | .oem_revision = 0, | |
275 | }, | |
276 | { | |
277 | .oem_id = "HISI ", | |
278 | .oem_table_id = "HIP06 ", | |
279 | .oem_revision = 0, | |
280 | }, | |
281 | { | |
282 | .oem_id = "HISI ", | |
283 | .oem_table_id = "HIP07 ", | |
284 | .oem_revision = 0, | |
285 | }, | |
286 | { /* Sentinel indicating the end of the OEM array */ }, | |
287 | }; | |
bb42ca47 DT |
288 | #endif |
289 | ||
fa8d815f MZ |
290 | #ifdef CONFIG_ARM64_ERRATUM_858921 |
291 | static u64 notrace arm64_858921_read_cntvct_el0(void) | |
292 | { | |
293 | u64 old, new; | |
294 | ||
295 | old = read_sysreg(cntvct_el0); | |
296 | new = read_sysreg(cntvct_el0); | |
297 | return (((old ^ new) >> 32) & 1) ? old : new; | |
298 | } | |
299 | #endif | |
300 | ||
16d10ef2 | 301 | #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND |
6acc71cc MZ |
302 | DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, |
303 | timer_unstable_counter_workaround); | |
16d10ef2 DT |
304 | EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); |
305 | ||
306 | DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled); | |
307 | EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled); | |
308 | ||
8328089f MZ |
309 | static void erratum_set_next_event_tval_generic(const int access, unsigned long evt, |
310 | struct clock_event_device *clk) | |
311 | { | |
312 | unsigned long ctrl; | |
313 | u64 cval = evt + arch_counter_get_cntvct(); | |
314 | ||
315 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); | |
316 | ctrl |= ARCH_TIMER_CTRL_ENABLE; | |
317 | ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; | |
318 | ||
319 | if (access == ARCH_TIMER_PHYS_ACCESS) | |
320 | write_sysreg(cval, cntp_cval_el0); | |
321 | else | |
322 | write_sysreg(cval, cntv_cval_el0); | |
323 | ||
324 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
325 | } | |
326 | ||
327 | static int erratum_set_next_event_tval_virt(unsigned long evt, | |
328 | struct clock_event_device *clk) | |
329 | { | |
330 | erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk); | |
331 | return 0; | |
332 | } | |
333 | ||
334 | static int erratum_set_next_event_tval_phys(unsigned long evt, | |
335 | struct clock_event_device *clk) | |
336 | { | |
337 | erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk); | |
338 | return 0; | |
339 | } | |
340 | ||
16d10ef2 DT |
341 | static const struct arch_timer_erratum_workaround ool_workarounds[] = { |
342 | #ifdef CONFIG_FSL_ERRATUM_A008585 | |
343 | { | |
651bb2e9 | 344 | .match_type = ate_match_dt, |
16d10ef2 | 345 | .id = "fsl,erratum-a008585", |
651bb2e9 | 346 | .desc = "Freescale erratum a005858", |
16d10ef2 DT |
347 | .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0, |
348 | .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0, | |
349 | .read_cntvct_el0 = fsl_a008585_read_cntvct_el0, | |
01d3e3ff MZ |
350 | .set_next_event_phys = erratum_set_next_event_tval_phys, |
351 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
16d10ef2 DT |
352 | }, |
353 | #endif | |
bb42ca47 DT |
354 | #ifdef CONFIG_HISILICON_ERRATUM_161010101 |
355 | { | |
651bb2e9 | 356 | .match_type = ate_match_dt, |
bb42ca47 | 357 | .id = "hisilicon,erratum-161010101", |
651bb2e9 | 358 | .desc = "HiSilicon erratum 161010101", |
bb42ca47 DT |
359 | .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, |
360 | .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, | |
361 | .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, | |
01d3e3ff MZ |
362 | .set_next_event_phys = erratum_set_next_event_tval_phys, |
363 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
d003d029 MZ |
364 | }, |
365 | { | |
366 | .match_type = ate_match_acpi_oem_info, | |
367 | .id = hisi_161010101_oem_info, | |
368 | .desc = "HiSilicon erratum 161010101", | |
369 | .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, | |
370 | .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, | |
371 | .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, | |
372 | .set_next_event_phys = erratum_set_next_event_tval_phys, | |
373 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
bb42ca47 DT |
374 | }, |
375 | #endif | |
fa8d815f MZ |
376 | #ifdef CONFIG_ARM64_ERRATUM_858921 |
377 | { | |
378 | .match_type = ate_match_local_cap_id, | |
379 | .id = (void *)ARM64_WORKAROUND_858921, | |
380 | .desc = "ARM erratum 858921", | |
381 | .read_cntvct_el0 = arm64_858921_read_cntvct_el0, | |
382 | }, | |
383 | #endif | |
16d10ef2 | 384 | }; |
651bb2e9 MZ |
385 | |
386 | typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *, | |
387 | const void *); | |
388 | ||
389 | static | |
390 | bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa, | |
391 | const void *arg) | |
392 | { | |
393 | const struct device_node *np = arg; | |
394 | ||
395 | return of_property_read_bool(np, wa->id); | |
396 | } | |
397 | ||
0064030c MZ |
398 | static |
399 | bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa, | |
400 | const void *arg) | |
401 | { | |
402 | return this_cpu_has_cap((uintptr_t)wa->id); | |
403 | } | |
404 | ||
5a38bcac MZ |
405 | |
406 | static | |
407 | bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa, | |
408 | const void *arg) | |
409 | { | |
410 | static const struct ate_acpi_oem_info empty_oem_info = {}; | |
411 | const struct ate_acpi_oem_info *info = wa->id; | |
412 | const struct acpi_table_header *table = arg; | |
413 | ||
414 | /* Iterate over the ACPI OEM info array, looking for a match */ | |
415 | while (memcmp(info, &empty_oem_info, sizeof(*info))) { | |
416 | if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) && | |
417 | !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) && | |
418 | info->oem_revision == table->oem_revision) | |
419 | return true; | |
420 | ||
421 | info++; | |
422 | } | |
423 | ||
424 | return false; | |
425 | } | |
426 | ||
651bb2e9 MZ |
427 | static const struct arch_timer_erratum_workaround * |
428 | arch_timer_iterate_errata(enum arch_timer_erratum_match_type type, | |
429 | ate_match_fn_t match_fn, | |
430 | void *arg) | |
431 | { | |
432 | int i; | |
433 | ||
434 | for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) { | |
435 | if (ool_workarounds[i].match_type != type) | |
436 | continue; | |
437 | ||
438 | if (match_fn(&ool_workarounds[i], arg)) | |
439 | return &ool_workarounds[i]; | |
440 | } | |
441 | ||
442 | return NULL; | |
443 | } | |
444 | ||
445 | static | |
6acc71cc MZ |
446 | void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa, |
447 | bool local) | |
651bb2e9 | 448 | { |
6acc71cc MZ |
449 | int i; |
450 | ||
451 | if (local) { | |
452 | __this_cpu_write(timer_unstable_counter_workaround, wa); | |
453 | } else { | |
454 | for_each_possible_cpu(i) | |
455 | per_cpu(timer_unstable_counter_workaround, i) = wa; | |
456 | } | |
457 | ||
651bb2e9 | 458 | static_branch_enable(&arch_timer_read_ool_enabled); |
a86bd139 MZ |
459 | |
460 | /* | |
461 | * Don't use the vdso fastpath if errata require using the | |
462 | * out-of-line counter accessor. We may change our mind pretty | |
463 | * late in the game (with a per-CPU erratum, for example), so | |
464 | * change both the default value and the vdso itself. | |
465 | */ | |
466 | if (wa->read_cntvct_el0) { | |
467 | clocksource_counter.archdata.vdso_direct = false; | |
468 | vdso_default = false; | |
469 | } | |
651bb2e9 MZ |
470 | } |
471 | ||
472 | static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type, | |
473 | void *arg) | |
474 | { | |
475 | const struct arch_timer_erratum_workaround *wa; | |
476 | ate_match_fn_t match_fn = NULL; | |
0064030c | 477 | bool local = false; |
651bb2e9 MZ |
478 | |
479 | switch (type) { | |
480 | case ate_match_dt: | |
481 | match_fn = arch_timer_check_dt_erratum; | |
482 | break; | |
0064030c MZ |
483 | case ate_match_local_cap_id: |
484 | match_fn = arch_timer_check_local_cap_erratum; | |
485 | local = true; | |
486 | break; | |
5a38bcac MZ |
487 | case ate_match_acpi_oem_info: |
488 | match_fn = arch_timer_check_acpi_oem_erratum; | |
489 | break; | |
651bb2e9 MZ |
490 | default: |
491 | WARN_ON(1); | |
492 | return; | |
493 | } | |
494 | ||
495 | wa = arch_timer_iterate_errata(type, match_fn, arg); | |
496 | if (!wa) | |
497 | return; | |
498 | ||
0064030c | 499 | if (needs_unstable_timer_counter_workaround()) { |
6acc71cc MZ |
500 | const struct arch_timer_erratum_workaround *__wa; |
501 | __wa = __this_cpu_read(timer_unstable_counter_workaround); | |
502 | if (__wa && wa != __wa) | |
0064030c | 503 | pr_warn("Can't enable workaround for %s (clashes with %s\n)", |
6acc71cc MZ |
504 | wa->desc, __wa->desc); |
505 | ||
506 | if (__wa) | |
507 | return; | |
0064030c MZ |
508 | } |
509 | ||
6acc71cc | 510 | arch_timer_enable_workaround(wa, local); |
0064030c MZ |
511 | pr_info("Enabling %s workaround for %s\n", |
512 | local ? "local" : "global", wa->desc); | |
651bb2e9 MZ |
513 | } |
514 | ||
01d3e3ff MZ |
515 | #define erratum_handler(fn, r, ...) \ |
516 | ({ \ | |
517 | bool __val; \ | |
6acc71cc MZ |
518 | if (needs_unstable_timer_counter_workaround()) { \ |
519 | const struct arch_timer_erratum_workaround *__wa; \ | |
520 | __wa = __this_cpu_read(timer_unstable_counter_workaround); \ | |
521 | if (__wa && __wa->fn) { \ | |
522 | r = __wa->fn(__VA_ARGS__); \ | |
523 | __val = true; \ | |
524 | } else { \ | |
525 | __val = false; \ | |
526 | } \ | |
01d3e3ff MZ |
527 | } else { \ |
528 | __val = false; \ | |
529 | } \ | |
530 | __val; \ | |
531 | }) | |
532 | ||
a86bd139 MZ |
533 | static bool arch_timer_this_cpu_has_cntvct_wa(void) |
534 | { | |
535 | const struct arch_timer_erratum_workaround *wa; | |
536 | ||
537 | wa = __this_cpu_read(timer_unstable_counter_workaround); | |
538 | return wa && wa->read_cntvct_el0; | |
539 | } | |
651bb2e9 MZ |
540 | #else |
541 | #define arch_timer_check_ool_workaround(t,a) do { } while(0) | |
8328089f MZ |
542 | #define erratum_set_next_event_tval_virt(...) ({BUG(); 0;}) |
543 | #define erratum_set_next_event_tval_phys(...) ({BUG(); 0;}) | |
01d3e3ff | 544 | #define erratum_handler(fn, r, ...) ({false;}) |
a86bd139 | 545 | #define arch_timer_this_cpu_has_cntvct_wa() ({false;}) |
16d10ef2 | 546 | #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */ |
f6dc1576 | 547 | |
e09f3cc0 | 548 | static __always_inline irqreturn_t timer_handler(const int access, |
8a4da6e3 MR |
549 | struct clock_event_device *evt) |
550 | { | |
551 | unsigned long ctrl; | |
cfb6d656 | 552 | |
60faddf6 | 553 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt); |
8a4da6e3 MR |
554 | if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { |
555 | ctrl |= ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 | 556 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt); |
8a4da6e3 MR |
557 | evt->event_handler(evt); |
558 | return IRQ_HANDLED; | |
559 | } | |
560 | ||
561 | return IRQ_NONE; | |
562 | } | |
563 | ||
564 | static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id) | |
565 | { | |
566 | struct clock_event_device *evt = dev_id; | |
567 | ||
568 | return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt); | |
569 | } | |
570 | ||
571 | static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id) | |
572 | { | |
573 | struct clock_event_device *evt = dev_id; | |
574 | ||
575 | return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt); | |
576 | } | |
577 | ||
22006994 SB |
578 | static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id) |
579 | { | |
580 | struct clock_event_device *evt = dev_id; | |
581 | ||
582 | return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt); | |
583 | } | |
584 | ||
585 | static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id) | |
586 | { | |
587 | struct clock_event_device *evt = dev_id; | |
588 | ||
589 | return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt); | |
590 | } | |
591 | ||
46c5bfdd VK |
592 | static __always_inline int timer_shutdown(const int access, |
593 | struct clock_event_device *clk) | |
8a4da6e3 MR |
594 | { |
595 | unsigned long ctrl; | |
46c5bfdd VK |
596 | |
597 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); | |
598 | ctrl &= ~ARCH_TIMER_CTRL_ENABLE; | |
599 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
600 | ||
601 | return 0; | |
8a4da6e3 MR |
602 | } |
603 | ||
46c5bfdd | 604 | static int arch_timer_shutdown_virt(struct clock_event_device *clk) |
8a4da6e3 | 605 | { |
46c5bfdd | 606 | return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk); |
8a4da6e3 MR |
607 | } |
608 | ||
46c5bfdd | 609 | static int arch_timer_shutdown_phys(struct clock_event_device *clk) |
8a4da6e3 | 610 | { |
46c5bfdd | 611 | return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk); |
8a4da6e3 MR |
612 | } |
613 | ||
46c5bfdd | 614 | static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk) |
22006994 | 615 | { |
46c5bfdd | 616 | return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk); |
8a4da6e3 MR |
617 | } |
618 | ||
46c5bfdd | 619 | static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk) |
22006994 | 620 | { |
46c5bfdd | 621 | return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk); |
22006994 SB |
622 | } |
623 | ||
60faddf6 | 624 | static __always_inline void set_next_event(const int access, unsigned long evt, |
cfb6d656 | 625 | struct clock_event_device *clk) |
8a4da6e3 MR |
626 | { |
627 | unsigned long ctrl; | |
60faddf6 | 628 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); |
8a4da6e3 MR |
629 | ctrl |= ARCH_TIMER_CTRL_ENABLE; |
630 | ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 SB |
631 | arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk); |
632 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
8a4da6e3 MR |
633 | } |
634 | ||
635 | static int arch_timer_set_next_event_virt(unsigned long evt, | |
60faddf6 | 636 | struct clock_event_device *clk) |
8a4da6e3 | 637 | { |
01d3e3ff MZ |
638 | int ret; |
639 | ||
640 | if (erratum_handler(set_next_event_virt, ret, evt, clk)) | |
641 | return ret; | |
8328089f | 642 | |
60faddf6 | 643 | set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk); |
8a4da6e3 MR |
644 | return 0; |
645 | } | |
646 | ||
647 | static int arch_timer_set_next_event_phys(unsigned long evt, | |
60faddf6 | 648 | struct clock_event_device *clk) |
8a4da6e3 | 649 | { |
01d3e3ff MZ |
650 | int ret; |
651 | ||
652 | if (erratum_handler(set_next_event_phys, ret, evt, clk)) | |
653 | return ret; | |
8328089f | 654 | |
60faddf6 | 655 | set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk); |
8a4da6e3 MR |
656 | return 0; |
657 | } | |
658 | ||
22006994 SB |
659 | static int arch_timer_set_next_event_virt_mem(unsigned long evt, |
660 | struct clock_event_device *clk) | |
8a4da6e3 | 661 | { |
22006994 SB |
662 | set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk); |
663 | return 0; | |
664 | } | |
665 | ||
666 | static int arch_timer_set_next_event_phys_mem(unsigned long evt, | |
667 | struct clock_event_device *clk) | |
668 | { | |
669 | set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk); | |
670 | return 0; | |
671 | } | |
672 | ||
cfb6d656 TG |
673 | static void __arch_timer_setup(unsigned type, |
674 | struct clock_event_device *clk) | |
22006994 SB |
675 | { |
676 | clk->features = CLOCK_EVT_FEAT_ONESHOT; | |
677 | ||
8a5c21dc | 678 | if (type == ARCH_TIMER_TYPE_CP15) { |
82a56194 LP |
679 | if (arch_timer_c3stop) |
680 | clk->features |= CLOCK_EVT_FEAT_C3STOP; | |
22006994 SB |
681 | clk->name = "arch_sys_timer"; |
682 | clk->rating = 450; | |
683 | clk->cpumask = cpumask_of(smp_processor_id()); | |
f81f03fa MZ |
684 | clk->irq = arch_timer_ppi[arch_timer_uses_ppi]; |
685 | switch (arch_timer_uses_ppi) { | |
ee34f1e6 | 686 | case ARCH_TIMER_VIRT_PPI: |
46c5bfdd | 687 | clk->set_state_shutdown = arch_timer_shutdown_virt; |
cf8c5009 | 688 | clk->set_state_oneshot_stopped = arch_timer_shutdown_virt; |
22006994 | 689 | clk->set_next_event = arch_timer_set_next_event_virt; |
f81f03fa | 690 | break; |
ee34f1e6 FW |
691 | case ARCH_TIMER_PHYS_SECURE_PPI: |
692 | case ARCH_TIMER_PHYS_NONSECURE_PPI: | |
693 | case ARCH_TIMER_HYP_PPI: | |
46c5bfdd | 694 | clk->set_state_shutdown = arch_timer_shutdown_phys; |
cf8c5009 | 695 | clk->set_state_oneshot_stopped = arch_timer_shutdown_phys; |
22006994 | 696 | clk->set_next_event = arch_timer_set_next_event_phys; |
f81f03fa MZ |
697 | break; |
698 | default: | |
699 | BUG(); | |
22006994 | 700 | } |
f6dc1576 | 701 | |
0064030c | 702 | arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL); |
8a4da6e3 | 703 | } else { |
7b52ad2e | 704 | clk->features |= CLOCK_EVT_FEAT_DYNIRQ; |
22006994 SB |
705 | clk->name = "arch_mem_timer"; |
706 | clk->rating = 400; | |
707 | clk->cpumask = cpu_all_mask; | |
708 | if (arch_timer_mem_use_virtual) { | |
46c5bfdd | 709 | clk->set_state_shutdown = arch_timer_shutdown_virt_mem; |
cf8c5009 | 710 | clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem; |
22006994 SB |
711 | clk->set_next_event = |
712 | arch_timer_set_next_event_virt_mem; | |
713 | } else { | |
46c5bfdd | 714 | clk->set_state_shutdown = arch_timer_shutdown_phys_mem; |
cf8c5009 | 715 | clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem; |
22006994 SB |
716 | clk->set_next_event = |
717 | arch_timer_set_next_event_phys_mem; | |
718 | } | |
8a4da6e3 MR |
719 | } |
720 | ||
46c5bfdd | 721 | clk->set_state_shutdown(clk); |
8a4da6e3 | 722 | |
22006994 SB |
723 | clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff); |
724 | } | |
8a4da6e3 | 725 | |
e1ce5c7a NL |
726 | static void arch_timer_evtstrm_enable(int divider) |
727 | { | |
728 | u32 cntkctl = arch_timer_get_cntkctl(); | |
729 | ||
730 | cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK; | |
731 | /* Set the divider and enable virtual event stream */ | |
732 | cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT) | |
733 | | ARCH_TIMER_VIRT_EVT_EN; | |
734 | arch_timer_set_cntkctl(cntkctl); | |
735 | elf_hwcap |= HWCAP_EVTSTRM; | |
736 | #ifdef CONFIG_COMPAT | |
737 | compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM; | |
738 | #endif | |
739 | } | |
740 | ||
037f6377 WD |
741 | static void arch_timer_configure_evtstream(void) |
742 | { | |
743 | int evt_stream_div, pos; | |
744 | ||
745 | /* Find the closest power of two to the divisor */ | |
746 | evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ; | |
747 | pos = fls(evt_stream_div); | |
748 | if (pos > 1 && !(evt_stream_div & (1 << (pos - 2)))) | |
749 | pos--; | |
750 | /* enable event stream */ | |
751 | arch_timer_evtstrm_enable(min(pos, 15)); | |
752 | } | |
753 | ||
8b8dde00 NL |
754 | static void arch_counter_set_user_access(void) |
755 | { | |
756 | u32 cntkctl = arch_timer_get_cntkctl(); | |
757 | ||
a86bd139 | 758 | /* Disable user access to the timers and both counters */ |
8b8dde00 NL |
759 | /* Also disable virtual event stream */ |
760 | cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN | |
761 | | ARCH_TIMER_USR_VT_ACCESS_EN | |
a86bd139 | 762 | | ARCH_TIMER_USR_VCT_ACCESS_EN |
8b8dde00 NL |
763 | | ARCH_TIMER_VIRT_EVT_EN |
764 | | ARCH_TIMER_USR_PCT_ACCESS_EN); | |
765 | ||
a86bd139 MZ |
766 | /* |
767 | * Enable user access to the virtual counter if it doesn't | |
768 | * need to be workaround. The vdso may have been already | |
769 | * disabled though. | |
770 | */ | |
771 | if (arch_timer_this_cpu_has_cntvct_wa()) | |
772 | pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id()); | |
773 | else | |
774 | cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN; | |
8b8dde00 NL |
775 | |
776 | arch_timer_set_cntkctl(cntkctl); | |
777 | } | |
778 | ||
f81f03fa MZ |
779 | static bool arch_timer_has_nonsecure_ppi(void) |
780 | { | |
ee34f1e6 FW |
781 | return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI && |
782 | arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]); | |
f81f03fa MZ |
783 | } |
784 | ||
f005bd7e MZ |
785 | static u32 check_ppi_trigger(int irq) |
786 | { | |
787 | u32 flags = irq_get_trigger_type(irq); | |
788 | ||
789 | if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) { | |
790 | pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq); | |
791 | pr_warn("WARNING: Please fix your firmware\n"); | |
792 | flags = IRQF_TRIGGER_LOW; | |
793 | } | |
794 | ||
795 | return flags; | |
796 | } | |
797 | ||
7e86e8bd | 798 | static int arch_timer_starting_cpu(unsigned int cpu) |
22006994 | 799 | { |
7e86e8bd | 800 | struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); |
f005bd7e | 801 | u32 flags; |
7e86e8bd | 802 | |
8a5c21dc | 803 | __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk); |
8a4da6e3 | 804 | |
f005bd7e MZ |
805 | flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]); |
806 | enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags); | |
f81f03fa | 807 | |
f005bd7e | 808 | if (arch_timer_has_nonsecure_ppi()) { |
ee34f1e6 FW |
809 | flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]); |
810 | enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI], | |
811 | flags); | |
f005bd7e | 812 | } |
8a4da6e3 MR |
813 | |
814 | arch_counter_set_user_access(); | |
46fd5c6b | 815 | if (evtstrm_enable) |
037f6377 | 816 | arch_timer_configure_evtstream(); |
8a4da6e3 MR |
817 | |
818 | return 0; | |
819 | } | |
820 | ||
22006994 SB |
821 | static void |
822 | arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np) | |
8a4da6e3 | 823 | { |
22006994 SB |
824 | /* Who has more than one independent system counter? */ |
825 | if (arch_timer_rate) | |
826 | return; | |
8a4da6e3 | 827 | |
b09ca1ec HG |
828 | /* |
829 | * Try to determine the frequency from the device tree or CNTFRQ, | |
830 | * if ACPI is enabled, get the frequency from CNTFRQ ONLY. | |
831 | */ | |
832 | if (!acpi_disabled || | |
833 | of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) { | |
22006994 SB |
834 | if (cntbase) |
835 | arch_timer_rate = readl_relaxed(cntbase + CNTFRQ); | |
836 | else | |
837 | arch_timer_rate = arch_timer_get_cntfrq(); | |
8a4da6e3 MR |
838 | } |
839 | ||
22006994 SB |
840 | /* Check the timer frequency. */ |
841 | if (arch_timer_rate == 0) | |
ded24019 | 842 | pr_warn("frequency not available\n"); |
22006994 SB |
843 | } |
844 | ||
845 | static void arch_timer_banner(unsigned type) | |
846 | { | |
ded24019 | 847 | pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n", |
8a5c21dc FW |
848 | type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "", |
849 | type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? | |
850 | " and " : "", | |
851 | type & ARCH_TIMER_TYPE_MEM ? "mmio" : "", | |
ded24019 FW |
852 | (unsigned long)arch_timer_rate / 1000000, |
853 | (unsigned long)(arch_timer_rate / 10000) % 100, | |
8a5c21dc | 854 | type & ARCH_TIMER_TYPE_CP15 ? |
ee34f1e6 | 855 | (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" : |
22006994 | 856 | "", |
8a5c21dc FW |
857 | type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "", |
858 | type & ARCH_TIMER_TYPE_MEM ? | |
22006994 SB |
859 | arch_timer_mem_use_virtual ? "virt" : "phys" : |
860 | ""); | |
8a4da6e3 MR |
861 | } |
862 | ||
863 | u32 arch_timer_get_rate(void) | |
864 | { | |
865 | return arch_timer_rate; | |
866 | } | |
867 | ||
22006994 | 868 | static u64 arch_counter_get_cntvct_mem(void) |
8a4da6e3 | 869 | { |
22006994 SB |
870 | u32 vct_lo, vct_hi, tmp_hi; |
871 | ||
872 | do { | |
873 | vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
874 | vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO); | |
875 | tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
876 | } while (vct_hi != tmp_hi); | |
877 | ||
878 | return ((u64) vct_hi << 32) | vct_lo; | |
8a4da6e3 MR |
879 | } |
880 | ||
b4d6ce97 JG |
881 | static struct arch_timer_kvm_info arch_timer_kvm_info; |
882 | ||
883 | struct arch_timer_kvm_info *arch_timer_get_kvm_info(void) | |
884 | { | |
885 | return &arch_timer_kvm_info; | |
886 | } | |
8a4da6e3 | 887 | |
22006994 SB |
888 | static void __init arch_counter_register(unsigned type) |
889 | { | |
890 | u64 start_count; | |
891 | ||
892 | /* Register the CP15 based counter if we have one */ | |
8a5c21dc | 893 | if (type & ARCH_TIMER_TYPE_CP15) { |
ee34f1e6 FW |
894 | if (IS_ENABLED(CONFIG_ARM64) || |
895 | arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) | |
0b46b8a7 SR |
896 | arch_timer_read_counter = arch_counter_get_cntvct; |
897 | else | |
898 | arch_timer_read_counter = arch_counter_get_cntpct; | |
f6dc1576 | 899 | |
a86bd139 | 900 | clocksource_counter.archdata.vdso_direct = vdso_default; |
423bd69e | 901 | } else { |
22006994 | 902 | arch_timer_read_counter = arch_counter_get_cntvct_mem; |
423bd69e NL |
903 | } |
904 | ||
d8ec7595 BN |
905 | if (!arch_counter_suspend_stop) |
906 | clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; | |
22006994 SB |
907 | start_count = arch_timer_read_counter(); |
908 | clocksource_register_hz(&clocksource_counter, arch_timer_rate); | |
909 | cyclecounter.mult = clocksource_counter.mult; | |
910 | cyclecounter.shift = clocksource_counter.shift; | |
b4d6ce97 JG |
911 | timecounter_init(&arch_timer_kvm_info.timecounter, |
912 | &cyclecounter, start_count); | |
4a7d3e8a TR |
913 | |
914 | /* 56 bits minimum, so we assume worst case rollover */ | |
915 | sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate); | |
22006994 SB |
916 | } |
917 | ||
8c37bb3a | 918 | static void arch_timer_stop(struct clock_event_device *clk) |
8a4da6e3 | 919 | { |
ded24019 | 920 | pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id()); |
8a4da6e3 | 921 | |
f81f03fa MZ |
922 | disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]); |
923 | if (arch_timer_has_nonsecure_ppi()) | |
ee34f1e6 | 924 | disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]); |
8a4da6e3 | 925 | |
46c5bfdd | 926 | clk->set_state_shutdown(clk); |
8a4da6e3 MR |
927 | } |
928 | ||
7e86e8bd | 929 | static int arch_timer_dying_cpu(unsigned int cpu) |
8a4da6e3 | 930 | { |
7e86e8bd | 931 | struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); |
8a4da6e3 | 932 | |
7e86e8bd RC |
933 | arch_timer_stop(clk); |
934 | return 0; | |
8a4da6e3 MR |
935 | } |
936 | ||
346e7480 | 937 | #ifdef CONFIG_CPU_PM |
bee67c53 | 938 | static DEFINE_PER_CPU(unsigned long, saved_cntkctl); |
346e7480 SH |
939 | static int arch_timer_cpu_pm_notify(struct notifier_block *self, |
940 | unsigned long action, void *hcpu) | |
941 | { | |
942 | if (action == CPU_PM_ENTER) | |
bee67c53 | 943 | __this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl()); |
346e7480 | 944 | else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) |
bee67c53 | 945 | arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl)); |
346e7480 SH |
946 | return NOTIFY_OK; |
947 | } | |
948 | ||
949 | static struct notifier_block arch_timer_cpu_pm_notifier = { | |
950 | .notifier_call = arch_timer_cpu_pm_notify, | |
951 | }; | |
952 | ||
953 | static int __init arch_timer_cpu_pm_init(void) | |
954 | { | |
955 | return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier); | |
956 | } | |
7e86e8bd RC |
957 | |
958 | static void __init arch_timer_cpu_pm_deinit(void) | |
959 | { | |
960 | WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier)); | |
961 | } | |
962 | ||
346e7480 SH |
963 | #else |
964 | static int __init arch_timer_cpu_pm_init(void) | |
965 | { | |
966 | return 0; | |
967 | } | |
7e86e8bd RC |
968 | |
969 | static void __init arch_timer_cpu_pm_deinit(void) | |
970 | { | |
971 | } | |
346e7480 SH |
972 | #endif |
973 | ||
8a4da6e3 MR |
974 | static int __init arch_timer_register(void) |
975 | { | |
976 | int err; | |
977 | int ppi; | |
978 | ||
8a4da6e3 MR |
979 | arch_timer_evt = alloc_percpu(struct clock_event_device); |
980 | if (!arch_timer_evt) { | |
981 | err = -ENOMEM; | |
982 | goto out; | |
983 | } | |
984 | ||
f81f03fa MZ |
985 | ppi = arch_timer_ppi[arch_timer_uses_ppi]; |
986 | switch (arch_timer_uses_ppi) { | |
ee34f1e6 | 987 | case ARCH_TIMER_VIRT_PPI: |
8a4da6e3 MR |
988 | err = request_percpu_irq(ppi, arch_timer_handler_virt, |
989 | "arch_timer", arch_timer_evt); | |
f81f03fa | 990 | break; |
ee34f1e6 FW |
991 | case ARCH_TIMER_PHYS_SECURE_PPI: |
992 | case ARCH_TIMER_PHYS_NONSECURE_PPI: | |
8a4da6e3 MR |
993 | err = request_percpu_irq(ppi, arch_timer_handler_phys, |
994 | "arch_timer", arch_timer_evt); | |
ee34f1e6 FW |
995 | if (!err && arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]) { |
996 | ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]; | |
8a4da6e3 MR |
997 | err = request_percpu_irq(ppi, arch_timer_handler_phys, |
998 | "arch_timer", arch_timer_evt); | |
999 | if (err) | |
ee34f1e6 | 1000 | free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI], |
8a4da6e3 MR |
1001 | arch_timer_evt); |
1002 | } | |
f81f03fa | 1003 | break; |
ee34f1e6 | 1004 | case ARCH_TIMER_HYP_PPI: |
f81f03fa MZ |
1005 | err = request_percpu_irq(ppi, arch_timer_handler_phys, |
1006 | "arch_timer", arch_timer_evt); | |
1007 | break; | |
1008 | default: | |
1009 | BUG(); | |
8a4da6e3 MR |
1010 | } |
1011 | ||
1012 | if (err) { | |
ded24019 | 1013 | pr_err("can't register interrupt %d (%d)\n", ppi, err); |
8a4da6e3 MR |
1014 | goto out_free; |
1015 | } | |
1016 | ||
346e7480 SH |
1017 | err = arch_timer_cpu_pm_init(); |
1018 | if (err) | |
1019 | goto out_unreg_notify; | |
1020 | ||
8a4da6e3 | 1021 | |
7e86e8bd RC |
1022 | /* Register and immediately configure the timer on the boot CPU */ |
1023 | err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING, | |
73c1b41e | 1024 | "clockevents/arm/arch_timer:starting", |
7e86e8bd RC |
1025 | arch_timer_starting_cpu, arch_timer_dying_cpu); |
1026 | if (err) | |
1027 | goto out_unreg_cpupm; | |
8a4da6e3 MR |
1028 | return 0; |
1029 | ||
7e86e8bd RC |
1030 | out_unreg_cpupm: |
1031 | arch_timer_cpu_pm_deinit(); | |
1032 | ||
346e7480 | 1033 | out_unreg_notify: |
f81f03fa MZ |
1034 | free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt); |
1035 | if (arch_timer_has_nonsecure_ppi()) | |
ee34f1e6 | 1036 | free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI], |
8a4da6e3 | 1037 | arch_timer_evt); |
8a4da6e3 MR |
1038 | |
1039 | out_free: | |
1040 | free_percpu(arch_timer_evt); | |
1041 | out: | |
1042 | return err; | |
1043 | } | |
1044 | ||
22006994 SB |
1045 | static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq) |
1046 | { | |
1047 | int ret; | |
1048 | irq_handler_t func; | |
1049 | struct arch_timer *t; | |
1050 | ||
1051 | t = kzalloc(sizeof(*t), GFP_KERNEL); | |
1052 | if (!t) | |
1053 | return -ENOMEM; | |
1054 | ||
1055 | t->base = base; | |
1056 | t->evt.irq = irq; | |
8a5c21dc | 1057 | __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &t->evt); |
22006994 SB |
1058 | |
1059 | if (arch_timer_mem_use_virtual) | |
1060 | func = arch_timer_handler_virt_mem; | |
1061 | else | |
1062 | func = arch_timer_handler_phys_mem; | |
1063 | ||
1064 | ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt); | |
1065 | if (ret) { | |
ded24019 | 1066 | pr_err("Failed to request mem timer irq\n"); |
22006994 SB |
1067 | kfree(t); |
1068 | } | |
1069 | ||
1070 | return ret; | |
1071 | } | |
1072 | ||
1073 | static const struct of_device_id arch_timer_of_match[] __initconst = { | |
1074 | { .compatible = "arm,armv7-timer", }, | |
1075 | { .compatible = "arm,armv8-timer", }, | |
1076 | {}, | |
1077 | }; | |
1078 | ||
1079 | static const struct of_device_id arch_timer_mem_of_match[] __initconst = { | |
1080 | { .compatible = "arm,armv7-timer-mem", }, | |
1081 | {}, | |
1082 | }; | |
1083 | ||
c387f07e | 1084 | static bool __init |
566e6dfa | 1085 | arch_timer_needs_probing(int type, const struct of_device_id *matches) |
c387f07e SH |
1086 | { |
1087 | struct device_node *dn; | |
566e6dfa | 1088 | bool needs_probing = false; |
c387f07e SH |
1089 | |
1090 | dn = of_find_matching_node(NULL, matches); | |
59aa896d | 1091 | if (dn && of_device_is_available(dn) && !(arch_timers_present & type)) |
566e6dfa | 1092 | needs_probing = true; |
c387f07e SH |
1093 | of_node_put(dn); |
1094 | ||
566e6dfa | 1095 | return needs_probing; |
c387f07e SH |
1096 | } |
1097 | ||
3c0731db | 1098 | static int __init arch_timer_common_init(void) |
22006994 | 1099 | { |
8a5c21dc | 1100 | unsigned mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM; |
22006994 SB |
1101 | |
1102 | /* Wait until both nodes are probed if we have two timers */ | |
1103 | if ((arch_timers_present & mask) != mask) { | |
8a5c21dc FW |
1104 | if (arch_timer_needs_probing(ARCH_TIMER_TYPE_MEM, |
1105 | arch_timer_mem_of_match)) | |
3c0731db | 1106 | return 0; |
8a5c21dc FW |
1107 | if (arch_timer_needs_probing(ARCH_TIMER_TYPE_CP15, |
1108 | arch_timer_of_match)) | |
3c0731db | 1109 | return 0; |
22006994 SB |
1110 | } |
1111 | ||
1112 | arch_timer_banner(arch_timers_present); | |
1113 | arch_counter_register(arch_timers_present); | |
3c0731db | 1114 | return arch_timer_arch_init(); |
22006994 SB |
1115 | } |
1116 | ||
3c0731db | 1117 | static int __init arch_timer_init(void) |
8a4da6e3 | 1118 | { |
3c0731db | 1119 | int ret; |
8a4da6e3 | 1120 | /* |
8266891e MZ |
1121 | * If HYP mode is available, we know that the physical timer |
1122 | * has been configured to be accessible from PL1. Use it, so | |
1123 | * that a guest can use the virtual timer instead. | |
1124 | * | |
8a4da6e3 MR |
1125 | * If no interrupt provided for virtual timer, we'll have to |
1126 | * stick to the physical timer. It'd better be accessible... | |
f81f03fa MZ |
1127 | * |
1128 | * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE | |
1129 | * accesses to CNTP_*_EL1 registers are silently redirected to | |
1130 | * their CNTHP_*_EL2 counterparts, and use a different PPI | |
1131 | * number. | |
8a4da6e3 | 1132 | */ |
ee34f1e6 | 1133 | if (is_hyp_mode_available() || !arch_timer_ppi[ARCH_TIMER_VIRT_PPI]) { |
f81f03fa MZ |
1134 | bool has_ppi; |
1135 | ||
1136 | if (is_kernel_in_hyp_mode()) { | |
ee34f1e6 FW |
1137 | arch_timer_uses_ppi = ARCH_TIMER_HYP_PPI; |
1138 | has_ppi = !!arch_timer_ppi[ARCH_TIMER_HYP_PPI]; | |
f81f03fa | 1139 | } else { |
ee34f1e6 FW |
1140 | arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI; |
1141 | has_ppi = (!!arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI] || | |
1142 | !!arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]); | |
f81f03fa | 1143 | } |
8a4da6e3 | 1144 | |
f81f03fa | 1145 | if (!has_ppi) { |
ded24019 | 1146 | pr_warn("No interrupt available, giving up\n"); |
3c0731db | 1147 | return -EINVAL; |
8a4da6e3 MR |
1148 | } |
1149 | } | |
1150 | ||
3c0731db DL |
1151 | ret = arch_timer_register(); |
1152 | if (ret) | |
1153 | return ret; | |
1154 | ||
1155 | ret = arch_timer_common_init(); | |
1156 | if (ret) | |
1157 | return ret; | |
d9b5e415 | 1158 | |
ee34f1e6 | 1159 | arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI]; |
ded24019 | 1160 | |
3c0731db | 1161 | return 0; |
8a4da6e3 | 1162 | } |
b09ca1ec | 1163 | |
3c0731db | 1164 | static int __init arch_timer_of_init(struct device_node *np) |
b09ca1ec HG |
1165 | { |
1166 | int i; | |
1167 | ||
8a5c21dc | 1168 | if (arch_timers_present & ARCH_TIMER_TYPE_CP15) { |
ded24019 | 1169 | pr_warn("multiple nodes in dt, skipping\n"); |
3c0731db | 1170 | return 0; |
b09ca1ec HG |
1171 | } |
1172 | ||
8a5c21dc | 1173 | arch_timers_present |= ARCH_TIMER_TYPE_CP15; |
ee34f1e6 | 1174 | for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++) |
b09ca1ec HG |
1175 | arch_timer_ppi[i] = irq_of_parse_and_map(np, i); |
1176 | ||
1177 | arch_timer_detect_rate(NULL, np); | |
1178 | ||
1179 | arch_timer_c3stop = !of_property_read_bool(np, "always-on"); | |
1180 | ||
651bb2e9 MZ |
1181 | /* Check for globally applicable workarounds */ |
1182 | arch_timer_check_ool_workaround(ate_match_dt, np); | |
f6dc1576 | 1183 | |
b09ca1ec HG |
1184 | /* |
1185 | * If we cannot rely on firmware initializing the timer registers then | |
1186 | * we should use the physical timers instead. | |
1187 | */ | |
1188 | if (IS_ENABLED(CONFIG_ARM) && | |
1189 | of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) | |
ee34f1e6 | 1190 | arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI; |
b09ca1ec | 1191 | |
d8ec7595 BN |
1192 | /* On some systems, the counter stops ticking when in suspend. */ |
1193 | arch_counter_suspend_stop = of_property_read_bool(np, | |
1194 | "arm,no-tick-in-suspend"); | |
1195 | ||
3c0731db | 1196 | return arch_timer_init(); |
b09ca1ec | 1197 | } |
177cf6e5 DL |
1198 | CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init); |
1199 | CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init); | |
22006994 | 1200 | |
3c0731db | 1201 | static int __init arch_timer_mem_init(struct device_node *np) |
22006994 SB |
1202 | { |
1203 | struct device_node *frame, *best_frame = NULL; | |
1204 | void __iomem *cntctlbase, *base; | |
3c0731db | 1205 | unsigned int irq, ret = -EINVAL; |
22006994 SB |
1206 | u32 cnttidr; |
1207 | ||
8a5c21dc | 1208 | arch_timers_present |= ARCH_TIMER_TYPE_MEM; |
22006994 SB |
1209 | cntctlbase = of_iomap(np, 0); |
1210 | if (!cntctlbase) { | |
ded24019 | 1211 | pr_err("Can't find CNTCTLBase\n"); |
3c0731db | 1212 | return -ENXIO; |
22006994 SB |
1213 | } |
1214 | ||
1215 | cnttidr = readl_relaxed(cntctlbase + CNTTIDR); | |
22006994 SB |
1216 | |
1217 | /* | |
1218 | * Try to find a virtual capable frame. Otherwise fall back to a | |
1219 | * physical capable frame. | |
1220 | */ | |
1221 | for_each_available_child_of_node(np, frame) { | |
1222 | int n; | |
e392d603 | 1223 | u32 cntacr; |
22006994 SB |
1224 | |
1225 | if (of_property_read_u32(frame, "frame-number", &n)) { | |
ded24019 | 1226 | pr_err("Missing frame-number\n"); |
22006994 | 1227 | of_node_put(frame); |
e392d603 | 1228 | goto out; |
22006994 SB |
1229 | } |
1230 | ||
e392d603 RM |
1231 | /* Try enabling everything, and see what sticks */ |
1232 | cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT | | |
1233 | CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT; | |
1234 | writel_relaxed(cntacr, cntctlbase + CNTACR(n)); | |
1235 | cntacr = readl_relaxed(cntctlbase + CNTACR(n)); | |
1236 | ||
1237 | if ((cnttidr & CNTTIDR_VIRT(n)) && | |
1238 | !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) { | |
22006994 SB |
1239 | of_node_put(best_frame); |
1240 | best_frame = frame; | |
1241 | arch_timer_mem_use_virtual = true; | |
1242 | break; | |
1243 | } | |
e392d603 RM |
1244 | |
1245 | if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT)) | |
1246 | continue; | |
1247 | ||
22006994 SB |
1248 | of_node_put(best_frame); |
1249 | best_frame = of_node_get(frame); | |
1250 | } | |
1251 | ||
3c0731db | 1252 | ret= -ENXIO; |
f947ee14 SB |
1253 | base = arch_counter_base = of_io_request_and_map(best_frame, 0, |
1254 | "arch_mem_timer"); | |
1255 | if (IS_ERR(base)) { | |
ded24019 | 1256 | pr_err("Can't map frame's registers\n"); |
e392d603 | 1257 | goto out; |
22006994 SB |
1258 | } |
1259 | ||
1260 | if (arch_timer_mem_use_virtual) | |
097cd143 | 1261 | irq = irq_of_parse_and_map(best_frame, ARCH_TIMER_VIRT_SPI); |
22006994 | 1262 | else |
097cd143 | 1263 | irq = irq_of_parse_and_map(best_frame, ARCH_TIMER_PHYS_SPI); |
e392d603 | 1264 | |
3c0731db | 1265 | ret = -EINVAL; |
22006994 | 1266 | if (!irq) { |
ded24019 | 1267 | pr_err("Frame missing %s irq.\n", |
cfb6d656 | 1268 | arch_timer_mem_use_virtual ? "virt" : "phys"); |
e392d603 | 1269 | goto out; |
22006994 SB |
1270 | } |
1271 | ||
1272 | arch_timer_detect_rate(base, np); | |
3c0731db DL |
1273 | ret = arch_timer_mem_register(base, irq); |
1274 | if (ret) | |
1275 | goto out; | |
1276 | ||
1277 | return arch_timer_common_init(); | |
e392d603 RM |
1278 | out: |
1279 | iounmap(cntctlbase); | |
1280 | of_node_put(best_frame); | |
3c0731db | 1281 | return ret; |
22006994 | 1282 | } |
177cf6e5 | 1283 | CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem", |
22006994 | 1284 | arch_timer_mem_init); |
b09ca1ec HG |
1285 | |
1286 | #ifdef CONFIG_ACPI | |
1287 | static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags) | |
1288 | { | |
1289 | int trigger, polarity; | |
1290 | ||
1291 | if (!interrupt) | |
1292 | return 0; | |
1293 | ||
1294 | trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE | |
1295 | : ACPI_LEVEL_SENSITIVE; | |
1296 | ||
1297 | polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW | |
1298 | : ACPI_ACTIVE_HIGH; | |
1299 | ||
1300 | return acpi_register_gsi(NULL, interrupt, trigger, polarity); | |
1301 | } | |
1302 | ||
1303 | /* Initialize per-processor generic timer */ | |
1304 | static int __init arch_timer_acpi_init(struct acpi_table_header *table) | |
1305 | { | |
1306 | struct acpi_table_gtdt *gtdt; | |
1307 | ||
8a5c21dc | 1308 | if (arch_timers_present & ARCH_TIMER_TYPE_CP15) { |
ded24019 | 1309 | pr_warn("already initialized, skipping\n"); |
b09ca1ec HG |
1310 | return -EINVAL; |
1311 | } | |
1312 | ||
1313 | gtdt = container_of(table, struct acpi_table_gtdt, header); | |
1314 | ||
8a5c21dc | 1315 | arch_timers_present |= ARCH_TIMER_TYPE_CP15; |
b09ca1ec | 1316 | |
ee34f1e6 | 1317 | arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI] = |
b09ca1ec HG |
1318 | map_generic_timer_interrupt(gtdt->secure_el1_interrupt, |
1319 | gtdt->secure_el1_flags); | |
1320 | ||
ee34f1e6 | 1321 | arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] = |
b09ca1ec HG |
1322 | map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt, |
1323 | gtdt->non_secure_el1_flags); | |
1324 | ||
ee34f1e6 | 1325 | arch_timer_ppi[ARCH_TIMER_VIRT_PPI] = |
b09ca1ec HG |
1326 | map_generic_timer_interrupt(gtdt->virtual_timer_interrupt, |
1327 | gtdt->virtual_timer_flags); | |
1328 | ||
ee34f1e6 | 1329 | arch_timer_ppi[ARCH_TIMER_HYP_PPI] = |
b09ca1ec HG |
1330 | map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt, |
1331 | gtdt->non_secure_el2_flags); | |
1332 | ||
1333 | /* Get the frequency from CNTFRQ */ | |
1334 | arch_timer_detect_rate(NULL, NULL); | |
1335 | ||
1336 | /* Always-on capability */ | |
1337 | arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON); | |
1338 | ||
5a38bcac MZ |
1339 | /* Check for globally applicable workarounds */ |
1340 | arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table); | |
1341 | ||
b09ca1ec HG |
1342 | arch_timer_init(); |
1343 | return 0; | |
1344 | } | |
ae281cbd | 1345 | CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init); |
b09ca1ec | 1346 | #endif |