[mirror_ubuntu-zesty-kernel.git] / drivers / clocksource / clksrc-dbx500-prcmu.c

/*
 * Copyright (C) ST-Ericsson SA 2011
 *
 * License Terms: GNU General Public License v2
 * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
 * Author: Sundar Iyer for ST-Ericsson
 * sched_clock implementation is based on:
 * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
 *
 * DBx500-PRCMU Timer
 * The PRCMU has 5 timers which are available in a always-on
 * power domain.  We use the Timer 4 for our always-on clock
 * source on DB8500 and Timer 3 on DB5500.
 */
#include <linux/clockchips.h>
#include <linux/clksrc-dbx500-prcmu.h>
#include <linux/sched_clock.h>

#define RATE_32K		32768

#define TIMER_MODE_CONTINOUS	0x1
#define TIMER_DOWNCOUNT_VAL	0xffffffff

#define PRCMU_TIMER_REF		0
#define PRCMU_TIMER_DOWNCOUNT	0x4
#define PRCMU_TIMER_MODE	0x8

#define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */

static void __iomem *clksrc_dbx500_timer_base;

static cycle_t clksrc_dbx500_prcmu_read(struct clocksource *cs)
{
	u32 count, count2;

	do {
		count = readl(clksrc_dbx500_timer_base +
			      PRCMU_TIMER_DOWNCOUNT);
		count2 = readl(clksrc_dbx500_timer_base +
			       PRCMU_TIMER_DOWNCOUNT);
	} while (count2 != count);

	/* Negate because the timer is a decrementing counter */
	return ~count;
}

static struct clocksource clocksource_dbx500_prcmu = {
	.name		= "dbx500-prcmu-timer",
	.rating		= 300,
	.read		= clksrc_dbx500_prcmu_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK

static u32 notrace dbx500_prcmu_sched_clock_read(void)
{
	if (unlikely(!clksrc_dbx500_timer_base))
		return 0;

	return clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu);
}

#endif

void __init clksrc_dbx500_prcmu_init(void __iomem *base)
{
	clksrc_dbx500_timer_base = base;

	/*
	 * The A9 sub system expects the timer to be configured as
	 * a continous looping timer.
	 * The PRCMU should configure it but if it for some reason
	 * don't we do it here.
	 */
	if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
	    TIMER_MODE_CONTINOUS) {
		writel(TIMER_MODE_CONTINOUS,
		       clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
		writel(TIMER_DOWNCOUNT_VAL,
		       clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
	}
#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
	setup_sched_clock(dbx500_prcmu_sched_clock_read,
			 32, RATE_32K);
#endif
	clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
}
Commit	Line	Data
489bccea MW	1	/*
	2	* Copyright (C) ST-Ericsson SA 2011
	3	*
	4	* License Terms: GNU General Public License v2
	5	* Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
	6	* Author: Sundar Iyer for ST-Ericsson
	7	* sched_clock implementation is based on:
	8	* plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
	9	*
	10	* DBx500-PRCMU Timer
	11	* The PRCMU has 5 timers which are available in a always-on
	12	* power domain. We use the Timer 4 for our always-on clock
	13	* source on DB8500 and Timer 3 on DB5500.
	14	*/
	15	#include <linux/clockchips.h>
	16	#include <linux/clksrc-dbx500-prcmu.h>
38ff87f7	17	#include <linux/sched_clock.h>
489bccea	18
489bccea MW	19	#define RATE_32K 32768
	20
	21	#define TIMER_MODE_CONTINOUS 0x1
	22	#define TIMER_DOWNCOUNT_VAL 0xffffffff
	23
	24	#define PRCMU_TIMER_REF 0
	25	#define PRCMU_TIMER_DOWNCOUNT 0x4
	26	#define PRCMU_TIMER_MODE 0x8
	27
	28	#define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */
	29
b1e3be06	30	static void __iomem *clksrc_dbx500_timer_base;
489bccea MW	31
	32	static cycle_t clksrc_dbx500_prcmu_read(struct clocksource *cs)
	33	{
	34	u32 count, count2;
	35
	36	do {
	37	count = readl(clksrc_dbx500_timer_base +
	38	PRCMU_TIMER_DOWNCOUNT);
	39	count2 = readl(clksrc_dbx500_timer_base +
	40	PRCMU_TIMER_DOWNCOUNT);
	41	} while (count2 != count);
	42
	43	/* Negate because the timer is a decrementing counter */
	44	return ~count;
	45	}
	46
	47	static struct clocksource clocksource_dbx500_prcmu = {
	48	.name = "dbx500-prcmu-timer",
	49	.rating = 300,
	50	.read = clksrc_dbx500_prcmu_read,
489bccea MW	51	.mask = CLOCKSOURCE_MASK(32),
	52	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	53	};
	54
	55	#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
489bccea	56
cfef0320	57	static u32 notrace dbx500_prcmu_sched_clock_read(void)
489bccea	58	{
489bccea MW	59	if (unlikely(!clksrc_dbx500_timer_base))
	60	return 0;
	61
cfef0320	62	return clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu);
489bccea MW	63	}
489bccea MW	64
489bccea MW	65	#endif
489bccea MW	66
b1e3be06	67	void __init clksrc_dbx500_prcmu_init(void __iomem *base)
489bccea	68	{
b1e3be06 LW	69	clksrc_dbx500_timer_base = base;
b1e3be06 LW	70
489bccea MW	71	/*
	72	* The A9 sub system expects the timer to be configured as
	73	* a continous looping timer.
	74	* The PRCMU should configure it but if it for some reason
	75	* don't we do it here.
	76	*/
	77	if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
	78	TIMER_MODE_CONTINOUS) {
	79	writel(TIMER_MODE_CONTINOUS,
	80	clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
	81	writel(TIMER_DOWNCOUNT_VAL,
	82	clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
	83	}
	84	#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
cfef0320	85	setup_sched_clock(dbx500_prcmu_sched_clock_read,
489bccea MW	86	32, RATE_32K);
489bccea MW	87	#endif
13f0f030	88	clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
489bccea	89	}