[mirror_ubuntu-zesty-kernel.git] / drivers / clocksource / h8300_timer8.c

/*
 *  linux/arch/h8300/kernel/cpu/timer/timer8.c
 *
 *  Yoshinori Sato <ysato@users.sourcefoge.jp>
 *
 *  8bit Timer driver
 *
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define _8TCR	0
#define _8TCSR	2
#define TCORA	4
#define TCORB	6
#define _8TCNT	8

#define FLAG_STARTED (1 << 3)

#define SCALE 64

struct timer8_priv {
	struct clock_event_device ced;
	void __iomem *mapbase;
	unsigned long flags;
	unsigned int rate;
	unsigned int tcora;
};

static irqreturn_t timer8_interrupt(int irq, void *dev_id)
{
	struct timer8_priv *p = dev_id;

	if (clockevent_state_oneshot(&p->ced))
		writew(0x0000, p->mapbase + _8TCR);

	p->ced.event_handler(&p->ced);

	writeb(readb(p->mapbase + _8TCSR) & ~0x40,
		  p->mapbase + _8TCSR);

	return IRQ_HANDLED;
}

static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
{
	if (delta >= 0x10000)
		pr_warn("delta out of range\n");
	writeb(readb(p->mapbase + _8TCR) & ~0x40, p->mapbase + _8TCR);
	writew(0, p->mapbase + _8TCNT);
	writew(delta, p->mapbase + TCORA);
	writeb(readb(p->mapbase + _8TCR) | 0x40, p->mapbase + _8TCR);
}

static int timer8_enable(struct timer8_priv *p)
{
	writew(0xffff, p->mapbase + TCORA);
	writew(0x0000, p->mapbase + _8TCNT);
	writew(0x0c02, p->mapbase + _8TCR);

	return 0;
}

static int timer8_start(struct timer8_priv *p)
{
	int ret;

	if ((p->flags & FLAG_STARTED))
		return 0;

	ret = timer8_enable(p);
	if (!ret)
		p->flags |= FLAG_STARTED;

	return ret;
}

static void timer8_stop(struct timer8_priv *p)
{
	writew(0x0000, p->mapbase + _8TCR);
}

static inline struct timer8_priv *ced_to_priv(struct clock_event_device *ced)
{
	return container_of(ced, struct timer8_priv, ced);
}

static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
{
	struct clock_event_device *ced = &p->ced;

	timer8_start(p);

	ced->shift = 32;
	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	ced->max_delta_ns = clockevent_delta2ns(0xffff, ced);
	ced->min_delta_ns = clockevent_delta2ns(0x0001, ced);

	timer8_set_next(p, delta);
}

static int timer8_clock_event_shutdown(struct clock_event_device *ced)
{
	timer8_stop(ced_to_priv(ced));
	return 0;
}

static int timer8_clock_event_periodic(struct clock_event_device *ced)
{
	struct timer8_priv *p = ced_to_priv(ced);

	pr_info("%s: used for periodic clock events\n", ced->name);
	timer8_stop(p);
	timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);

	return 0;
}

static int timer8_clock_event_oneshot(struct clock_event_device *ced)
{
	struct timer8_priv *p = ced_to_priv(ced);

	pr_info("%s: used for oneshot clock events\n", ced->name);
	timer8_stop(p);
	timer8_clock_event_start(p, 0x10000);

	return 0;
}

static int timer8_clock_event_next(unsigned long delta,
				   struct clock_event_device *ced)
{
	struct timer8_priv *p = ced_to_priv(ced);

	BUG_ON(!clockevent_state_oneshot(ced));
	timer8_set_next(p, delta - 1);

	return 0;
}

static struct timer8_priv timer8_priv = {
	.ced = {
		.name = "h8300_8timer",
		.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
		.rating = 200,
		.set_next_event = timer8_clock_event_next,
		.set_state_shutdown = timer8_clock_event_shutdown,
		.set_state_periodic = timer8_clock_event_periodic,
		.set_state_oneshot = timer8_clock_event_oneshot,
	},
};

static void __init h8300_8timer_init(struct device_node *node)
{
	void __iomem *base;
	int irq;
	int ret = 0;
	int rate;
	struct clk *clk;

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_err("failed to get clock for clockevent\n");
		return;
	}

	base = of_iomap(node, 0);
	if (!base) {
		pr_err("failed to map registers for clockevent\n");
		goto free_clk;
	}

	irq = irq_of_parse_and_map(node, 0);
	if (!irq) {
		pr_err("failed to get irq for clockevent\n");
		goto unmap_reg;
	}

	timer8_priv.mapbase = base;

	rate = clk_get_rate(clk) / SCALE;
	if (!rate) {
		pr_err("Failed to get rate for the clocksource\n");
		goto unmap_reg;
	}

	ret = request_irq(irq, timer8_interrupt,
			  IRQF_TIMER, timer8_priv.ced.name, &timer8_priv);
	if (ret < 0) {
		pr_err("failed to request irq %d for clockevent\n", irq);
		goto unmap_reg;
	}

	clockevents_config_and_register(&timer8_priv.ced, rate, 1, 0x0000ffff);

	return;
unmap_reg:
	iounmap(base);
free_clk:
	clk_put(clk);
}

CLOCKSOURCE_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);
Commit	Line	Data
618b902d YS	1	/*
	2	* linux/arch/h8300/kernel/cpu/timer/timer8.c
	3	*
	4	* Yoshinori Sato <ysato@users.sourcefoge.jp>
	5	*
	6	* 8bit Timer driver
	7	*
	8	*/
	9
	10	#include <linux/errno.h>
618b902d YS	11	#include <linux/kernel.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/init.h>
618b902d	14	#include <linux/clockchips.h>
618b902d YS	15	#include <linux/clk.h>
	16	#include <linux/io.h>
	17	#include <linux/of.h>
4633f4ca YS	18	#include <linux/of_address.h>
4633f4ca YS	19	#include <linux/of_irq.h>
618b902d	20
618b902d YS	21	#define _8TCR 0
	22	#define _8TCSR 2
	23	#define TCORA 4
	24	#define TCORB 6
	25	#define _8TCNT 8
	26
618b902d YS	27	#define FLAG_STARTED (1 << 3)
618b902d YS	28
4633f4ca YS	29	#define SCALE 64
4633f4ca YS	30
618b902d	31	struct timer8_priv {
618b902d	32	struct clock_event_device ced;
75160515	33	void __iomem *mapbase;
618b902d YS	34	unsigned long flags;
	35	unsigned int rate;
	36	unsigned int tcora;
618b902d YS	37	};
618b902d YS	38
618b902d YS	39	static irqreturn_t timer8_interrupt(int irq, void *dev_id)
	40	{
	41	struct timer8_priv *p = dev_id;
	42
7053fdac	43	if (clockevent_state_oneshot(&p->ced))
75160515	44	writew(0x0000, p->mapbase + _8TCR);
7053fdac DL	45
7053fdac DL	46	p->ced.event_handler(&p->ced);
618b902d	47
f37632d1 YS	48	writeb(readb(p->mapbase + _8TCSR) & ~0x40,
	49	p->mapbase + _8TCSR);
	50
618b902d YS	51	return IRQ_HANDLED;
	52	}
	53
	54	static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
	55	{
618b902d	56	if (delta >= 0x10000)
8c09b7d6	57	pr_warn("delta out of range\n");
f37632d1 YS	58	writeb(readb(p->mapbase + _8TCR) & ~0x40, p->mapbase + _8TCR);
	59	writew(0, p->mapbase + _8TCNT);
	60	writew(delta, p->mapbase + TCORA);
75160515	61	writeb(readb(p->mapbase + _8TCR) \| 0x40, p->mapbase + _8TCR);
618b902d YS	62	}
	63
	64	static int timer8_enable(struct timer8_priv *p)
	65	{
75160515 DL	66	writew(0xffff, p->mapbase + TCORA);
	67	writew(0x0000, p->mapbase + _8TCNT);
	68	writew(0x0c02, p->mapbase + _8TCR);
618b902d YS	69
	70	return 0;
	71	}
	72
	73	static int timer8_start(struct timer8_priv *p)
	74	{
cce483e0	75	int ret;
618b902d	76
cce483e0 DL	77	if ((p->flags & FLAG_STARTED))
cce483e0 DL	78	return 0;
618b902d	79
cce483e0 DL	80	ret = timer8_enable(p);
	81	if (!ret)
	82	p->flags \|= FLAG_STARTED;
618b902d	83
618b902d YS	84	return ret;
	85	}
	86
	87	static void timer8_stop(struct timer8_priv *p)
	88	{
75160515	89	writew(0x0000, p->mapbase + _8TCR);
618b902d YS	90	}
	91
	92	static inline struct timer8_priv ced_to_priv(struct clock_event_device ced)
	93	{
	94	return container_of(ced, struct timer8_priv, ced);
	95	}
	96
1f058d52	97	static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
618b902d YS	98	{
	99	struct clock_event_device *ced = &p->ced;
	100
	101	timer8_start(p);
	102
	103	ced->shift = 32;
	104	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	105	ced->max_delta_ns = clockevent_delta2ns(0xffff, ced);
	106	ced->min_delta_ns = clockevent_delta2ns(0x0001, ced);
	107
1f058d52	108	timer8_set_next(p, delta);
618b902d YS	109	}
618b902d YS	110
fc2b2f5d VK	111	static int timer8_clock_event_shutdown(struct clock_event_device *ced)
	112	{
	113	timer8_stop(ced_to_priv(ced));
	114	return 0;
	115	}
	116
	117	static int timer8_clock_event_periodic(struct clock_event_device *ced)
618b902d YS	118	{
	119	struct timer8_priv *p = ced_to_priv(ced);
	120
4633f4ca	121	pr_info("%s: used for periodic clock events\n", ced->name);
fc2b2f5d	122	timer8_stop(p);
1f058d52	123	timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);
fc2b2f5d VK	124
	125	return 0;
	126	}
	127
	128	static int timer8_clock_event_oneshot(struct clock_event_device *ced)
	129	{
	130	struct timer8_priv *p = ced_to_priv(ced);
	131
4633f4ca	132	pr_info("%s: used for oneshot clock events\n", ced->name);
fc2b2f5d	133	timer8_stop(p);
1f058d52	134	timer8_clock_event_start(p, 0x10000);
fc2b2f5d VK	135
fc2b2f5d VK	136	return 0;
618b902d YS	137	}
	138
	139	static int timer8_clock_event_next(unsigned long delta,
	140	struct clock_event_device *ced)
	141	{
	142	struct timer8_priv *p = ced_to_priv(ced);
	143
fc2b2f5d	144	BUG_ON(!clockevent_state_oneshot(ced));
618b902d YS	145	timer8_set_next(p, delta - 1);
	146
	147	return 0;
	148	}
	149
4633f4ca YS	150	static struct timer8_priv timer8_priv = {
	151	.ced = {
	152	.name = "h8300_8timer",
	153	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	154	.rating = 200,
	155	.set_next_event = timer8_clock_event_next,
	156	.set_state_shutdown = timer8_clock_event_shutdown,
	157	.set_state_periodic = timer8_clock_event_periodic,
	158	.set_state_oneshot = timer8_clock_event_oneshot,
	159	},
	160	};
	161
	162	static void __init h8300_8timer_init(struct device_node *node)
618b902d	163	{
4633f4ca	164	void __iomem *base;
618b902d	165	int irq;
4633f4ca YS	166	int ret = 0;
	167	int rate;
	168	struct clk *clk;
618b902d	169
4633f4ca YS	170	clk = of_clk_get(node, 0);
	171	if (IS_ERR(clk)) {
	172	pr_err("failed to get clock for clockevent\n");
	173	return;
	174	}
618b902d	175
4633f4ca YS	176	base = of_iomap(node, 0);
	177	if (!base) {
	178	pr_err("failed to map registers for clockevent\n");
	179	goto free_clk;
618b902d YS	180	}
618b902d YS	181
4633f4ca	182	irq = irq_of_parse_and_map(node, 0);
54a0cd5a	183	if (!irq) {
4633f4ca YS	184	pr_err("failed to get irq for clockevent\n");
4633f4ca YS	185	goto unmap_reg;
618b902d YS	186	}
618b902d YS	187
75160515	188	timer8_priv.mapbase = base;
cce483e0 DL	189
	190	rate = clk_get_rate(clk) / SCALE;
	191	if (!rate) {
	192	pr_err("Failed to get rate for the clocksource\n");
	193	goto unmap_reg;
	194	}
618b902d	195
4633f4ca YS	196	ret = request_irq(irq, timer8_interrupt,
4633f4ca YS	197	IRQF_TIMER, timer8_priv.ced.name, &timer8_priv);
618b902d	198	if (ret < 0) {
4633f4ca YS	199	pr_err("failed to request irq %d for clockevent\n", irq);
4633f4ca YS	200	goto unmap_reg;
618b902d	201	}
cce483e0	202
4633f4ca	203	clockevents_config_and_register(&timer8_priv.ced, rate, 1, 0x0000ffff);
4633f4ca	204
cce483e0	205	return;
4633f4ca YS	206	unmap_reg:
	207	iounmap(base);
	208	free_clk:
	209	clk_put(clk);
618b902d YS	210	}
618b902d YS	211
4633f4ca	212	CLOCKSOURCE_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);