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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
035e111f JN |
2 | #include <linux/init.h> |
3 | #include <linux/module.h> | |
4 | #include <linux/cpufreq.h> | |
5 | #include <hwregs/reg_map.h> | |
6 | #include <hwregs/reg_rdwr.h> | |
7 | #include <hwregs/clkgen_defs.h> | |
8 | #include <hwregs/ddr2_defs.h> | |
9 | ||
10 | static int | |
11 | cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val, | |
12 | void *data); | |
13 | ||
14 | static struct notifier_block cris_sdram_freq_notifier_block = { | |
15 | .notifier_call = cris_sdram_freq_notifier | |
16 | }; | |
17 | ||
18 | static struct cpufreq_frequency_table cris_freq_table[] = { | |
7f4b0461 VK |
19 | {0, 0x01, 6000}, |
20 | {0, 0x02, 200000}, | |
21 | {0, 0, CPUFREQ_TABLE_END}, | |
035e111f JN |
22 | }; |
23 | ||
24 | static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu) | |
25 | { | |
26 | reg_clkgen_rw_clk_ctrl clk_ctrl; | |
27 | clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); | |
28 | return clk_ctrl.pll ? 200000 : 6000; | |
29 | } | |
30 | ||
9c0ebcf7 | 31 | static int cris_freq_target(struct cpufreq_policy *policy, unsigned int state) |
035e111f | 32 | { |
035e111f JN |
33 | reg_clkgen_rw_clk_ctrl clk_ctrl; |
34 | clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); | |
35 | ||
035e111f JN |
36 | local_irq_disable(); |
37 | ||
38 | /* Even though we may be SMP they will share the same clock | |
39 | * so all settings are made on CPU0. */ | |
40 | if (cris_freq_table[state].frequency == 200000) | |
41 | clk_ctrl.pll = 1; | |
42 | else | |
43 | clk_ctrl.pll = 0; | |
44 | REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); | |
45 | ||
46 | local_irq_enable(); | |
47 | ||
035e111f JN |
48 | return 0; |
49 | } | |
50 | ||
51 | static int cris_freq_cpu_init(struct cpufreq_policy *policy) | |
52 | { | |
1870e111 | 53 | return cpufreq_generic_init(policy, cris_freq_table, 1000000); |
035e111f JN |
54 | } |
55 | ||
035e111f JN |
56 | static struct cpufreq_driver cris_freq_driver = { |
57 | .get = cris_freq_get_cpu_frequency, | |
361db10f | 58 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 59 | .target_index = cris_freq_target, |
035e111f | 60 | .init = cris_freq_cpu_init, |
035e111f | 61 | .name = "cris_freq", |
361db10f | 62 | .attr = cpufreq_generic_attr, |
035e111f JN |
63 | }; |
64 | ||
65 | static int __init cris_freq_init(void) | |
66 | { | |
67 | int ret; | |
68 | ret = cpufreq_register_driver(&cris_freq_driver); | |
69 | cpufreq_register_notifier(&cris_sdram_freq_notifier_block, | |
70 | CPUFREQ_TRANSITION_NOTIFIER); | |
71 | return ret; | |
72 | } | |
73 | ||
74 | static int | |
75 | cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val, | |
76 | void *data) | |
77 | { | |
78 | int i; | |
79 | struct cpufreq_freqs *freqs = data; | |
80 | if (val == CPUFREQ_PRECHANGE) { | |
81 | reg_ddr2_rw_cfg cfg = | |
82 | REG_RD(ddr2, regi_ddr2_ctrl, rw_cfg); | |
83 | cfg.ref_interval = (freqs->new == 200000 ? 1560 : 46); | |
84 | ||
85 | if (freqs->new == 200000) | |
86 | for (i = 0; i < 50000; i++); | |
87 | REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing); | |
88 | } | |
89 | return 0; | |
90 | } | |
91 | ||
92 | ||
93 | module_init(cris_freq_init); |