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Commit | Line | Data |
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1dd538f0 SG |
1 | /* |
2 | * Copyright (C) 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <linux/clk.h> | |
b494b48d | 10 | #include <linux/cpu.h> |
1dd538f0 | 11 | #include <linux/cpufreq.h> |
1dd538f0 SG |
12 | #include <linux/err.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/of.h> | |
2b3d58a3 | 15 | #include <linux/of_address.h> |
e4db1c74 | 16 | #include <linux/pm_opp.h> |
1dd538f0 SG |
17 | #include <linux/platform_device.h> |
18 | #include <linux/regulator/consumer.h> | |
19 | ||
20 | #define PU_SOC_VOLTAGE_NORMAL 1250000 | |
21 | #define PU_SOC_VOLTAGE_HIGH 1275000 | |
22 | #define FREQ_1P2_GHZ 1200000000 | |
23 | ||
24 | static struct regulator *arm_reg; | |
25 | static struct regulator *pu_reg; | |
26 | static struct regulator *soc_reg; | |
27 | ||
28 | static struct clk *arm_clk; | |
29 | static struct clk *pll1_sys_clk; | |
30 | static struct clk *pll1_sw_clk; | |
31 | static struct clk *step_clk; | |
32 | static struct clk *pll2_pfd2_396m_clk; | |
33 | ||
a35fc5a3 BP |
34 | /* clk used by i.MX6UL */ |
35 | static struct clk *pll2_bus_clk; | |
36 | static struct clk *secondary_sel_clk; | |
37 | ||
1dd538f0 | 38 | static struct device *cpu_dev; |
cc87b8a8 | 39 | static bool free_opp; |
1dd538f0 SG |
40 | static struct cpufreq_frequency_table *freq_table; |
41 | static unsigned int transition_latency; | |
42 | ||
b4573d1d AH |
43 | static u32 *imx6_soc_volt; |
44 | static u32 soc_opp_count; | |
45 | ||
9c0ebcf7 | 46 | static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) |
1dd538f0 | 47 | { |
47d43ba7 | 48 | struct dev_pm_opp *opp; |
1dd538f0 | 49 | unsigned long freq_hz, volt, volt_old; |
d4019f0a | 50 | unsigned int old_freq, new_freq; |
fded5fc8 | 51 | bool pll1_sys_temp_enabled = false; |
1dd538f0 SG |
52 | int ret; |
53 | ||
d4019f0a VK |
54 | new_freq = freq_table[index].frequency; |
55 | freq_hz = new_freq * 1000; | |
56 | old_freq = clk_get_rate(arm_clk) / 1000; | |
1dd538f0 | 57 | |
5d4879cd | 58 | opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); |
1dd538f0 | 59 | if (IS_ERR(opp)) { |
1dd538f0 SG |
60 | dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); |
61 | return PTR_ERR(opp); | |
62 | } | |
63 | ||
5d4879cd | 64 | volt = dev_pm_opp_get_voltage(opp); |
8a31d9d9 VK |
65 | dev_pm_opp_put(opp); |
66 | ||
1dd538f0 SG |
67 | volt_old = regulator_get_voltage(arm_reg); |
68 | ||
69 | dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", | |
d4019f0a VK |
70 | old_freq / 1000, volt_old / 1000, |
71 | new_freq / 1000, volt / 1000); | |
5a571c35 | 72 | |
1dd538f0 | 73 | /* scaling up? scale voltage before frequency */ |
d4019f0a | 74 | if (new_freq > old_freq) { |
22d0628a AH |
75 | if (!IS_ERR(pu_reg)) { |
76 | ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); | |
77 | if (ret) { | |
78 | dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); | |
79 | return ret; | |
80 | } | |
b4573d1d AH |
81 | } |
82 | ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); | |
83 | if (ret) { | |
84 | dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret); | |
85 | return ret; | |
86 | } | |
1dd538f0 SG |
87 | ret = regulator_set_voltage_tol(arm_reg, volt, 0); |
88 | if (ret) { | |
89 | dev_err(cpu_dev, | |
90 | "failed to scale vddarm up: %d\n", ret); | |
d4019f0a | 91 | return ret; |
1dd538f0 | 92 | } |
1dd538f0 SG |
93 | } |
94 | ||
95 | /* | |
96 | * The setpoints are selected per PLL/PDF frequencies, so we need to | |
97 | * reprogram PLL for frequency scaling. The procedure of reprogramming | |
98 | * PLL1 is as below. | |
a35fc5a3 BP |
99 | * For i.MX6UL, it has a secondary clk mux, the cpu frequency change |
100 | * flow is slightly different from other i.MX6 OSC. | |
101 | * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below: | |
1dd538f0 SG |
102 | * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it |
103 | * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it | |
104 | * - Disable pll2_pfd2_396m_clk | |
105 | */ | |
3fafb4e7 OP |
106 | if (of_machine_is_compatible("fsl,imx6ul") || |
107 | of_machine_is_compatible("fsl,imx6ull")) { | |
a35fc5a3 BP |
108 | /* |
109 | * When changing pll1_sw_clk's parent to pll1_sys_clk, | |
110 | * CPU may run at higher than 528MHz, this will lead to | |
111 | * the system unstable if the voltage is lower than the | |
112 | * voltage of 528MHz, so lower the CPU frequency to one | |
113 | * half before changing CPU frequency. | |
114 | */ | |
115 | clk_set_rate(arm_clk, (old_freq >> 1) * 1000); | |
1dd538f0 | 116 | clk_set_parent(pll1_sw_clk, pll1_sys_clk); |
a35fc5a3 BP |
117 | if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) |
118 | clk_set_parent(secondary_sel_clk, pll2_bus_clk); | |
119 | else | |
120 | clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk); | |
121 | clk_set_parent(step_clk, secondary_sel_clk); | |
122 | clk_set_parent(pll1_sw_clk, step_clk); | |
123 | } else { | |
124 | clk_set_parent(step_clk, pll2_pfd2_396m_clk); | |
125 | clk_set_parent(pll1_sw_clk, step_clk); | |
126 | if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { | |
127 | clk_set_rate(pll1_sys_clk, new_freq * 1000); | |
128 | clk_set_parent(pll1_sw_clk, pll1_sys_clk); | |
fded5fc8 LC |
129 | } else { |
130 | /* pll1_sys needs to be enabled for divider rate change to work. */ | |
131 | pll1_sys_temp_enabled = true; | |
132 | clk_prepare_enable(pll1_sys_clk); | |
a35fc5a3 | 133 | } |
1dd538f0 SG |
134 | } |
135 | ||
136 | /* Ensure the arm clock divider is what we expect */ | |
d4019f0a | 137 | ret = clk_set_rate(arm_clk, new_freq * 1000); |
1dd538f0 SG |
138 | if (ret) { |
139 | dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); | |
140 | regulator_set_voltage_tol(arm_reg, volt_old, 0); | |
d4019f0a | 141 | return ret; |
1dd538f0 SG |
142 | } |
143 | ||
fded5fc8 LC |
144 | /* PLL1 is only needed until after ARM-PODF is set. */ |
145 | if (pll1_sys_temp_enabled) | |
146 | clk_disable_unprepare(pll1_sys_clk); | |
147 | ||
1dd538f0 | 148 | /* scaling down? scale voltage after frequency */ |
d4019f0a | 149 | if (new_freq < old_freq) { |
1dd538f0 | 150 | ret = regulator_set_voltage_tol(arm_reg, volt, 0); |
5a571c35 | 151 | if (ret) { |
1dd538f0 SG |
152 | dev_warn(cpu_dev, |
153 | "failed to scale vddarm down: %d\n", ret); | |
5a571c35 VK |
154 | ret = 0; |
155 | } | |
b4573d1d AH |
156 | ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); |
157 | if (ret) { | |
158 | dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret); | |
159 | ret = 0; | |
160 | } | |
22d0628a AH |
161 | if (!IS_ERR(pu_reg)) { |
162 | ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); | |
163 | if (ret) { | |
164 | dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret); | |
165 | ret = 0; | |
166 | } | |
1dd538f0 SG |
167 | } |
168 | } | |
169 | ||
d4019f0a | 170 | return 0; |
1dd538f0 SG |
171 | } |
172 | ||
173 | static int imx6q_cpufreq_init(struct cpufreq_policy *policy) | |
174 | { | |
5aa1599f LC |
175 | int ret; |
176 | ||
652ed95d | 177 | policy->clk = arm_clk; |
5aa1599f LC |
178 | ret = cpufreq_generic_init(policy, freq_table, transition_latency); |
179 | policy->suspend_freq = policy->max; | |
180 | ||
181 | return ret; | |
1dd538f0 SG |
182 | } |
183 | ||
1dd538f0 | 184 | static struct cpufreq_driver imx6q_cpufreq_driver = { |
ae6b4271 | 185 | .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
4f6ba385 | 186 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 187 | .target_index = imx6q_set_target, |
652ed95d | 188 | .get = cpufreq_generic_get, |
1dd538f0 | 189 | .init = imx6q_cpufreq_init, |
1dd538f0 | 190 | .name = "imx6q-cpufreq", |
4f6ba385 | 191 | .attr = cpufreq_generic_attr, |
5aa1599f | 192 | .suspend = cpufreq_generic_suspend, |
1dd538f0 SG |
193 | }; |
194 | ||
2b3d58a3 FE |
195 | #define OCOTP_CFG3 0x440 |
196 | #define OCOTP_CFG3_SPEED_SHIFT 16 | |
197 | #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 | |
198 | #define OCOTP_CFG3_SPEED_996MHZ 0x2 | |
199 | #define OCOTP_CFG3_SPEED_852MHZ 0x1 | |
200 | ||
201 | static void imx6q_opp_check_speed_grading(struct device *dev) | |
202 | { | |
203 | struct device_node *np; | |
204 | void __iomem *base; | |
205 | u32 val; | |
206 | ||
207 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); | |
208 | if (!np) | |
209 | return; | |
210 | ||
211 | base = of_iomap(np, 0); | |
212 | if (!base) { | |
213 | dev_err(dev, "failed to map ocotp\n"); | |
214 | goto put_node; | |
215 | } | |
216 | ||
217 | /* | |
218 | * SPEED_GRADING[1:0] defines the max speed of ARM: | |
219 | * 2b'11: 1200000000Hz; | |
220 | * 2b'10: 996000000Hz; | |
221 | * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. | |
222 | * 2b'00: 792000000Hz; | |
223 | * We need to set the max speed of ARM according to fuse map. | |
224 | */ | |
225 | val = readl_relaxed(base + OCOTP_CFG3); | |
226 | val >>= OCOTP_CFG3_SPEED_SHIFT; | |
227 | val &= 0x3; | |
228 | ||
2b3d58a3 FE |
229 | if (val < OCOTP_CFG3_SPEED_996MHZ) |
230 | if (dev_pm_opp_disable(dev, 996000000)) | |
231 | dev_warn(dev, "failed to disable 996MHz OPP\n"); | |
ccc153a6 LS |
232 | |
233 | if (of_machine_is_compatible("fsl,imx6q") || | |
234 | of_machine_is_compatible("fsl,imx6qp")) { | |
2b3d58a3 FE |
235 | if (val != OCOTP_CFG3_SPEED_852MHZ) |
236 | if (dev_pm_opp_disable(dev, 852000000)) | |
237 | dev_warn(dev, "failed to disable 852MHz OPP\n"); | |
ccc153a6 LS |
238 | if (val != OCOTP_CFG3_SPEED_1P2GHZ) |
239 | if (dev_pm_opp_disable(dev, 1200000000)) | |
240 | dev_warn(dev, "failed to disable 1.2GHz OPP\n"); | |
2b3d58a3 FE |
241 | } |
242 | iounmap(base); | |
243 | put_node: | |
244 | of_node_put(np); | |
245 | } | |
246 | ||
1dd538f0 SG |
247 | static int imx6q_cpufreq_probe(struct platform_device *pdev) |
248 | { | |
249 | struct device_node *np; | |
47d43ba7 | 250 | struct dev_pm_opp *opp; |
1dd538f0 SG |
251 | unsigned long min_volt, max_volt; |
252 | int num, ret; | |
b4573d1d AH |
253 | const struct property *prop; |
254 | const __be32 *val; | |
255 | u32 nr, i, j; | |
1dd538f0 | 256 | |
b494b48d SH |
257 | cpu_dev = get_cpu_device(0); |
258 | if (!cpu_dev) { | |
259 | pr_err("failed to get cpu0 device\n"); | |
260 | return -ENODEV; | |
261 | } | |
1dd538f0 | 262 | |
cdc58d60 | 263 | np = of_node_get(cpu_dev->of_node); |
1dd538f0 SG |
264 | if (!np) { |
265 | dev_err(cpu_dev, "failed to find cpu0 node\n"); | |
266 | return -ENOENT; | |
267 | } | |
268 | ||
f8269c19 PZ |
269 | arm_clk = clk_get(cpu_dev, "arm"); |
270 | pll1_sys_clk = clk_get(cpu_dev, "pll1_sys"); | |
271 | pll1_sw_clk = clk_get(cpu_dev, "pll1_sw"); | |
272 | step_clk = clk_get(cpu_dev, "step"); | |
273 | pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m"); | |
1dd538f0 SG |
274 | if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) || |
275 | IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) { | |
276 | dev_err(cpu_dev, "failed to get clocks\n"); | |
277 | ret = -ENOENT; | |
f8269c19 | 278 | goto put_clk; |
1dd538f0 SG |
279 | } |
280 | ||
3fafb4e7 OP |
281 | if (of_machine_is_compatible("fsl,imx6ul") || |
282 | of_machine_is_compatible("fsl,imx6ull")) { | |
a35fc5a3 BP |
283 | pll2_bus_clk = clk_get(cpu_dev, "pll2_bus"); |
284 | secondary_sel_clk = clk_get(cpu_dev, "secondary_sel"); | |
285 | if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) { | |
286 | dev_err(cpu_dev, "failed to get clocks specific to imx6ul\n"); | |
287 | ret = -ENOENT; | |
288 | goto put_clk; | |
289 | } | |
290 | } | |
291 | ||
f8269c19 | 292 | arm_reg = regulator_get(cpu_dev, "arm"); |
22d0628a | 293 | pu_reg = regulator_get_optional(cpu_dev, "pu"); |
f8269c19 | 294 | soc_reg = regulator_get(cpu_dev, "soc"); |
54cad2fc IT |
295 | if (PTR_ERR(arm_reg) == -EPROBE_DEFER || |
296 | PTR_ERR(soc_reg) == -EPROBE_DEFER || | |
297 | PTR_ERR(pu_reg) == -EPROBE_DEFER) { | |
298 | ret = -EPROBE_DEFER; | |
299 | dev_dbg(cpu_dev, "regulators not ready, defer\n"); | |
300 | goto put_reg; | |
301 | } | |
22d0628a | 302 | if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) { |
1dd538f0 SG |
303 | dev_err(cpu_dev, "failed to get regulators\n"); |
304 | ret = -ENOENT; | |
f8269c19 | 305 | goto put_reg; |
1dd538f0 SG |
306 | } |
307 | ||
2b3d58a3 FE |
308 | ret = dev_pm_opp_of_add_table(cpu_dev); |
309 | if (ret < 0) { | |
310 | dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); | |
311 | goto put_reg; | |
312 | } | |
20b7cbe2 | 313 | |
2b3d58a3 | 314 | imx6q_opp_check_speed_grading(cpu_dev); |
cc87b8a8 | 315 | |
2b3d58a3 FE |
316 | /* Because we have added the OPPs here, we must free them */ |
317 | free_opp = true; | |
318 | num = dev_pm_opp_get_opp_count(cpu_dev); | |
319 | if (num < 0) { | |
320 | ret = num; | |
321 | dev_err(cpu_dev, "no OPP table is found: %d\n", ret); | |
322 | goto out_free_opp; | |
1dd538f0 SG |
323 | } |
324 | ||
5d4879cd | 325 | ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); |
1dd538f0 SG |
326 | if (ret) { |
327 | dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); | |
eafca851 | 328 | goto out_free_opp; |
1dd538f0 SG |
329 | } |
330 | ||
b4573d1d AH |
331 | /* Make imx6_soc_volt array's size same as arm opp number */ |
332 | imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL); | |
333 | if (imx6_soc_volt == NULL) { | |
334 | ret = -ENOMEM; | |
335 | goto free_freq_table; | |
336 | } | |
337 | ||
338 | prop = of_find_property(np, "fsl,soc-operating-points", NULL); | |
339 | if (!prop || !prop->value) | |
340 | goto soc_opp_out; | |
341 | ||
342 | /* | |
343 | * Each OPP is a set of tuples consisting of frequency and | |
344 | * voltage like <freq-kHz vol-uV>. | |
345 | */ | |
346 | nr = prop->length / sizeof(u32); | |
347 | if (nr % 2 || (nr / 2) < num) | |
348 | goto soc_opp_out; | |
349 | ||
350 | for (j = 0; j < num; j++) { | |
351 | val = prop->value; | |
352 | for (i = 0; i < nr / 2; i++) { | |
353 | unsigned long freq = be32_to_cpup(val++); | |
354 | unsigned long volt = be32_to_cpup(val++); | |
355 | if (freq_table[j].frequency == freq) { | |
356 | imx6_soc_volt[soc_opp_count++] = volt; | |
357 | break; | |
358 | } | |
359 | } | |
360 | } | |
361 | ||
362 | soc_opp_out: | |
363 | /* use fixed soc opp volt if no valid soc opp info found in dtb */ | |
364 | if (soc_opp_count != num) { | |
365 | dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n"); | |
366 | for (j = 0; j < num; j++) | |
367 | imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL; | |
368 | if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ) | |
369 | imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH; | |
370 | } | |
371 | ||
1dd538f0 SG |
372 | if (of_property_read_u32(np, "clock-latency", &transition_latency)) |
373 | transition_latency = CPUFREQ_ETERNAL; | |
374 | ||
b4573d1d AH |
375 | /* |
376 | * Calculate the ramp time for max voltage change in the | |
377 | * VDDSOC and VDDPU regulators. | |
378 | */ | |
379 | ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); | |
380 | if (ret > 0) | |
381 | transition_latency += ret * 1000; | |
22d0628a AH |
382 | if (!IS_ERR(pu_reg)) { |
383 | ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); | |
384 | if (ret > 0) | |
385 | transition_latency += ret * 1000; | |
386 | } | |
b4573d1d | 387 | |
1dd538f0 SG |
388 | /* |
389 | * OPP is maintained in order of increasing frequency, and | |
390 | * freq_table initialised from OPP is therefore sorted in the | |
391 | * same order. | |
392 | */ | |
5d4879cd | 393 | opp = dev_pm_opp_find_freq_exact(cpu_dev, |
1dd538f0 | 394 | freq_table[0].frequency * 1000, true); |
5d4879cd | 395 | min_volt = dev_pm_opp_get_voltage(opp); |
8a31d9d9 | 396 | dev_pm_opp_put(opp); |
5d4879cd | 397 | opp = dev_pm_opp_find_freq_exact(cpu_dev, |
1dd538f0 | 398 | freq_table[--num].frequency * 1000, true); |
5d4879cd | 399 | max_volt = dev_pm_opp_get_voltage(opp); |
8a31d9d9 VK |
400 | dev_pm_opp_put(opp); |
401 | ||
1dd538f0 SG |
402 | ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); |
403 | if (ret > 0) | |
404 | transition_latency += ret * 1000; | |
405 | ||
1dd538f0 SG |
406 | ret = cpufreq_register_driver(&imx6q_cpufreq_driver); |
407 | if (ret) { | |
408 | dev_err(cpu_dev, "failed register driver: %d\n", ret); | |
409 | goto free_freq_table; | |
410 | } | |
411 | ||
412 | of_node_put(np); | |
413 | return 0; | |
414 | ||
415 | free_freq_table: | |
5d4879cd | 416 | dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); |
cc87b8a8 VK |
417 | out_free_opp: |
418 | if (free_opp) | |
8f8d37b2 | 419 | dev_pm_opp_of_remove_table(cpu_dev); |
f8269c19 PZ |
420 | put_reg: |
421 | if (!IS_ERR(arm_reg)) | |
422 | regulator_put(arm_reg); | |
423 | if (!IS_ERR(pu_reg)) | |
424 | regulator_put(pu_reg); | |
425 | if (!IS_ERR(soc_reg)) | |
426 | regulator_put(soc_reg); | |
427 | put_clk: | |
428 | if (!IS_ERR(arm_clk)) | |
429 | clk_put(arm_clk); | |
430 | if (!IS_ERR(pll1_sys_clk)) | |
431 | clk_put(pll1_sys_clk); | |
432 | if (!IS_ERR(pll1_sw_clk)) | |
433 | clk_put(pll1_sw_clk); | |
434 | if (!IS_ERR(step_clk)) | |
435 | clk_put(step_clk); | |
436 | if (!IS_ERR(pll2_pfd2_396m_clk)) | |
437 | clk_put(pll2_pfd2_396m_clk); | |
a35fc5a3 BP |
438 | if (!IS_ERR(pll2_bus_clk)) |
439 | clk_put(pll2_bus_clk); | |
440 | if (!IS_ERR(secondary_sel_clk)) | |
441 | clk_put(secondary_sel_clk); | |
1dd538f0 SG |
442 | of_node_put(np); |
443 | return ret; | |
444 | } | |
445 | ||
446 | static int imx6q_cpufreq_remove(struct platform_device *pdev) | |
447 | { | |
448 | cpufreq_unregister_driver(&imx6q_cpufreq_driver); | |
5d4879cd | 449 | dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); |
cc87b8a8 | 450 | if (free_opp) |
8f8d37b2 | 451 | dev_pm_opp_of_remove_table(cpu_dev); |
f8269c19 | 452 | regulator_put(arm_reg); |
22d0628a AH |
453 | if (!IS_ERR(pu_reg)) |
454 | regulator_put(pu_reg); | |
f8269c19 PZ |
455 | regulator_put(soc_reg); |
456 | clk_put(arm_clk); | |
457 | clk_put(pll1_sys_clk); | |
458 | clk_put(pll1_sw_clk); | |
459 | clk_put(step_clk); | |
460 | clk_put(pll2_pfd2_396m_clk); | |
a35fc5a3 BP |
461 | clk_put(pll2_bus_clk); |
462 | clk_put(secondary_sel_clk); | |
1dd538f0 SG |
463 | |
464 | return 0; | |
465 | } | |
466 | ||
467 | static struct platform_driver imx6q_cpufreq_platdrv = { | |
468 | .driver = { | |
469 | .name = "imx6q-cpufreq", | |
1dd538f0 SG |
470 | }, |
471 | .probe = imx6q_cpufreq_probe, | |
472 | .remove = imx6q_cpufreq_remove, | |
473 | }; | |
474 | module_platform_driver(imx6q_cpufreq_platdrv); | |
475 | ||
476 | MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); | |
477 | MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); | |
478 | MODULE_LICENSE("GPL"); |