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Commit | Line | Data |
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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
4836df17 JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
93f0822d DB |
15 | #include <linux/kernel.h> |
16 | #include <linux/kernel_stat.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/ktime.h> | |
19 | #include <linux/hrtimer.h> | |
20 | #include <linux/tick.h> | |
21 | #include <linux/slab.h> | |
55687da1 | 22 | #include <linux/sched/cpufreq.h> |
93f0822d DB |
23 | #include <linux/list.h> |
24 | #include <linux/cpu.h> | |
25 | #include <linux/cpufreq.h> | |
26 | #include <linux/sysfs.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/fs.h> | |
29 | #include <linux/debugfs.h> | |
fbbcdc07 | 30 | #include <linux/acpi.h> |
d6472302 | 31 | #include <linux/vmalloc.h> |
93f0822d DB |
32 | #include <trace/events/power.h> |
33 | ||
34 | #include <asm/div64.h> | |
35 | #include <asm/msr.h> | |
36 | #include <asm/cpu_device_id.h> | |
64df1fdf | 37 | #include <asm/cpufeature.h> |
5b20c944 | 38 | #include <asm/intel-family.h> |
93f0822d | 39 | |
d77d4888 | 40 | #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) |
eabd22c6 | 41 | |
001c76f0 | 42 | #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 |
1b72e7fd | 43 | #define INTEL_CPUFREQ_TRANSITION_DELAY 500 |
001c76f0 | 44 | |
9522a2ff SP |
45 | #ifdef CONFIG_ACPI |
46 | #include <acpi/processor.h> | |
17669006 | 47 | #include <acpi/cppc_acpi.h> |
9522a2ff SP |
48 | #endif |
49 | ||
f0fe3cd7 | 50 | #define FRAC_BITS 8 |
93f0822d DB |
51 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
52 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
f0fe3cd7 | 53 | |
a1c9787d RW |
54 | #define EXT_BITS 6 |
55 | #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) | |
d5dd33d9 SP |
56 | #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) |
57 | #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) | |
a1c9787d | 58 | |
93f0822d DB |
59 | static inline int32_t mul_fp(int32_t x, int32_t y) |
60 | { | |
61 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
62 | } | |
63 | ||
7180dddf | 64 | static inline int32_t div_fp(s64 x, s64 y) |
93f0822d | 65 | { |
7180dddf | 66 | return div64_s64((int64_t)x << FRAC_BITS, y); |
93f0822d DB |
67 | } |
68 | ||
d022a65e DB |
69 | static inline int ceiling_fp(int32_t x) |
70 | { | |
71 | int mask, ret; | |
72 | ||
73 | ret = fp_toint(x); | |
74 | mask = (1 << FRAC_BITS) - 1; | |
75 | if (x & mask) | |
76 | ret += 1; | |
77 | return ret; | |
78 | } | |
79 | ||
ff35f02e RW |
80 | static inline int32_t percent_fp(int percent) |
81 | { | |
82 | return div_fp(percent, 100); | |
83 | } | |
84 | ||
a1c9787d RW |
85 | static inline u64 mul_ext_fp(u64 x, u64 y) |
86 | { | |
87 | return (x * y) >> EXT_FRAC_BITS; | |
88 | } | |
89 | ||
90 | static inline u64 div_ext_fp(u64 x, u64 y) | |
91 | { | |
92 | return div64_u64(x << EXT_FRAC_BITS, y); | |
93 | } | |
94 | ||
e4c204ce RW |
95 | static inline int32_t percent_ext_fp(int percent) |
96 | { | |
97 | return div_ext_fp(percent, 100); | |
98 | } | |
99 | ||
13ad7701 SP |
100 | /** |
101 | * struct sample - Store performance sample | |
a1c9787d | 102 | * @core_avg_perf: Ratio of APERF/MPERF which is the actual average |
13ad7701 SP |
103 | * performance during last sample period |
104 | * @busy_scaled: Scaled busy value which is used to calculate next | |
a1c9787d | 105 | * P state. This can be different than core_avg_perf |
13ad7701 SP |
106 | * to account for cpu idle period |
107 | * @aperf: Difference of actual performance frequency clock count | |
108 | * read from APERF MSR between last and current sample | |
109 | * @mperf: Difference of maximum performance frequency clock count | |
110 | * read from MPERF MSR between last and current sample | |
111 | * @tsc: Difference of time stamp counter between last and | |
112 | * current sample | |
13ad7701 SP |
113 | * @time: Current time from scheduler |
114 | * | |
115 | * This structure is used in the cpudata structure to store performance sample | |
116 | * data for choosing next P State. | |
117 | */ | |
93f0822d | 118 | struct sample { |
a1c9787d | 119 | int32_t core_avg_perf; |
157386b6 | 120 | int32_t busy_scaled; |
93f0822d DB |
121 | u64 aperf; |
122 | u64 mperf; | |
4055fad3 | 123 | u64 tsc; |
a4675fbc | 124 | u64 time; |
93f0822d DB |
125 | }; |
126 | ||
13ad7701 SP |
127 | /** |
128 | * struct pstate_data - Store P state data | |
129 | * @current_pstate: Current requested P state | |
130 | * @min_pstate: Min P state possible for this platform | |
131 | * @max_pstate: Max P state possible for this platform | |
132 | * @max_pstate_physical:This is physical Max P state for a processor | |
133 | * This can be higher than the max_pstate which can | |
134 | * be limited by platform thermal design power limits | |
135 | * @scaling: Scaling factor to convert frequency to cpufreq | |
136 | * frequency units | |
137 | * @turbo_pstate: Max Turbo P state possible for this platform | |
001c76f0 RW |
138 | * @max_freq: @max_pstate frequency in cpufreq units |
139 | * @turbo_freq: @turbo_pstate frequency in cpufreq units | |
13ad7701 SP |
140 | * |
141 | * Stores the per cpu model P state limits and current P state. | |
142 | */ | |
93f0822d DB |
143 | struct pstate_data { |
144 | int current_pstate; | |
145 | int min_pstate; | |
146 | int max_pstate; | |
3bcc6fa9 | 147 | int max_pstate_physical; |
b27580b0 | 148 | int scaling; |
93f0822d | 149 | int turbo_pstate; |
001c76f0 RW |
150 | unsigned int max_freq; |
151 | unsigned int turbo_freq; | |
93f0822d DB |
152 | }; |
153 | ||
13ad7701 SP |
154 | /** |
155 | * struct vid_data - Stores voltage information data | |
156 | * @min: VID data for this platform corresponding to | |
157 | * the lowest P state | |
158 | * @max: VID data corresponding to the highest P State. | |
159 | * @turbo: VID data for turbo P state | |
160 | * @ratio: Ratio of (vid max - vid min) / | |
161 | * (max P state - Min P State) | |
162 | * | |
163 | * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) | |
164 | * This data is used in Atom platforms, where in addition to target P state, | |
165 | * the voltage data needs to be specified to select next P State. | |
166 | */ | |
007bea09 | 167 | struct vid_data { |
21855ff5 DB |
168 | int min; |
169 | int max; | |
170 | int turbo; | |
007bea09 DB |
171 | int32_t ratio; |
172 | }; | |
173 | ||
c5a2ee7d RW |
174 | /** |
175 | * struct global_params - Global parameters, mostly tunable via sysfs. | |
176 | * @no_turbo: Whether or not to use turbo P-states. | |
177 | * @turbo_disabled: Whethet or not turbo P-states are available at all, | |
178 | * based on the MSR_IA32_MISC_ENABLE value and whether or | |
179 | * not the maximum reported turbo P-state is different from | |
180 | * the maximum reported non-turbo one. | |
181 | * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo | |
182 | * P-state capacity. | |
183 | * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo | |
184 | * P-state capacity. | |
185 | */ | |
186 | struct global_params { | |
187 | bool no_turbo; | |
188 | bool turbo_disabled; | |
189 | int max_perf_pct; | |
190 | int min_perf_pct; | |
eae48f04 SP |
191 | }; |
192 | ||
13ad7701 SP |
193 | /** |
194 | * struct cpudata - Per CPU instance data storage | |
195 | * @cpu: CPU number for this instance data | |
2f1d407a | 196 | * @policy: CPUFreq policy value |
13ad7701 | 197 | * @update_util: CPUFreq utility callback information |
4578ee7e | 198 | * @update_util_set: CPUFreq utility callback is set |
09c448d3 RW |
199 | * @iowait_boost: iowait-related boost fraction |
200 | * @last_update: Time of the last update. | |
13ad7701 SP |
201 | * @pstate: Stores P state limits for this CPU |
202 | * @vid: Stores VID limits for this CPU | |
13ad7701 | 203 | * @last_sample_time: Last Sample time |
6e34e1f2 SP |
204 | * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented |
205 | * This shift is a multiplier to mperf delta to | |
206 | * calculate CPU busy. | |
13ad7701 SP |
207 | * @prev_aperf: Last APERF value read from APERF MSR |
208 | * @prev_mperf: Last MPERF value read from MPERF MSR | |
209 | * @prev_tsc: Last timestamp counter (TSC) value | |
210 | * @prev_cummulative_iowait: IO Wait time difference from last and | |
211 | * current sample | |
212 | * @sample: Storage for storing last Sample data | |
1a4fe38a SP |
213 | * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios |
214 | * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios | |
9522a2ff SP |
215 | * @acpi_perf_data: Stores ACPI perf information read from _PSS |
216 | * @valid_pss_table: Set to true for valid ACPI _PSS entries found | |
984edbdc SP |
217 | * @epp_powersave: Last saved HWP energy performance preference |
218 | * (EPP) or energy performance bias (EPB), | |
219 | * when policy switched to performance | |
8442885f | 220 | * @epp_policy: Last saved policy used to set EPP/EPB |
984edbdc SP |
221 | * @epp_default: Power on default HWP energy performance |
222 | * preference/bias | |
223 | * @epp_saved: Saved EPP/EPB during system suspend or CPU offline | |
224 | * operation | |
13ad7701 SP |
225 | * |
226 | * This structure stores per CPU instance data for all CPUs. | |
227 | */ | |
93f0822d DB |
228 | struct cpudata { |
229 | int cpu; | |
230 | ||
2f1d407a | 231 | unsigned int policy; |
a4675fbc | 232 | struct update_util_data update_util; |
4578ee7e | 233 | bool update_util_set; |
93f0822d | 234 | |
93f0822d | 235 | struct pstate_data pstate; |
007bea09 | 236 | struct vid_data vid; |
93f0822d | 237 | |
09c448d3 | 238 | u64 last_update; |
a4675fbc | 239 | u64 last_sample_time; |
6e34e1f2 | 240 | u64 aperf_mperf_shift; |
93f0822d DB |
241 | u64 prev_aperf; |
242 | u64 prev_mperf; | |
4055fad3 | 243 | u64 prev_tsc; |
63d1d656 | 244 | u64 prev_cummulative_iowait; |
d37e2b76 | 245 | struct sample sample; |
1a4fe38a SP |
246 | int32_t min_perf_ratio; |
247 | int32_t max_perf_ratio; | |
9522a2ff SP |
248 | #ifdef CONFIG_ACPI |
249 | struct acpi_processor_performance acpi_perf_data; | |
250 | bool valid_pss_table; | |
251 | #endif | |
09c448d3 | 252 | unsigned int iowait_boost; |
984edbdc | 253 | s16 epp_powersave; |
8442885f | 254 | s16 epp_policy; |
984edbdc SP |
255 | s16 epp_default; |
256 | s16 epp_saved; | |
93f0822d DB |
257 | }; |
258 | ||
259 | static struct cpudata **all_cpu_data; | |
13ad7701 | 260 | |
13ad7701 SP |
261 | /** |
262 | * struct pstate_funcs - Per CPU model specific callbacks | |
263 | * @get_max: Callback to get maximum non turbo effective P state | |
264 | * @get_max_physical: Callback to get maximum non turbo physical P state | |
265 | * @get_min: Callback to get minimum P state | |
266 | * @get_turbo: Callback to get turbo P state | |
267 | * @get_scaling: Callback to get frequency scaling factor | |
268 | * @get_val: Callback to convert P state to actual MSR write value | |
269 | * @get_vid: Callback to get VID data for Atom platforms | |
13ad7701 SP |
270 | * |
271 | * Core and Atom CPU models have different way to get P State limits. This | |
272 | * structure is used to store those callbacks. | |
273 | */ | |
016c8150 DB |
274 | struct pstate_funcs { |
275 | int (*get_max)(void); | |
3bcc6fa9 | 276 | int (*get_max_physical)(void); |
016c8150 DB |
277 | int (*get_min)(void); |
278 | int (*get_turbo)(void); | |
b27580b0 | 279 | int (*get_scaling)(void); |
6e34e1f2 | 280 | int (*get_aperf_mperf_shift)(void); |
fdfdb2b1 | 281 | u64 (*get_val)(struct cpudata*, int pstate); |
007bea09 | 282 | void (*get_vid)(struct cpudata *); |
93f0822d DB |
283 | }; |
284 | ||
4a7cb7a9 | 285 | static struct pstate_funcs pstate_funcs __read_mostly; |
5c439053 | 286 | |
4a7cb7a9 | 287 | static int hwp_active __read_mostly; |
eae48f04 | 288 | static bool per_cpu_limits __read_mostly; |
016c8150 | 289 | |
ee8df89a | 290 | static struct cpufreq_driver *intel_pstate_driver __read_mostly; |
0c30b65b | 291 | |
9522a2ff SP |
292 | #ifdef CONFIG_ACPI |
293 | static bool acpi_ppc; | |
294 | #endif | |
13ad7701 | 295 | |
c5a2ee7d | 296 | static struct global_params global; |
93f0822d | 297 | |
0c30b65b | 298 | static DEFINE_MUTEX(intel_pstate_driver_lock); |
a410c03d SP |
299 | static DEFINE_MUTEX(intel_pstate_limits_lock); |
300 | ||
9522a2ff | 301 | #ifdef CONFIG_ACPI |
2b3ec765 SP |
302 | |
303 | static bool intel_pstate_get_ppc_enable_status(void) | |
304 | { | |
305 | if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || | |
306 | acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) | |
307 | return true; | |
308 | ||
309 | return acpi_ppc; | |
310 | } | |
311 | ||
17669006 RW |
312 | #ifdef CONFIG_ACPI_CPPC_LIB |
313 | ||
314 | /* The work item is needed to avoid CPU hotplug locking issues */ | |
315 | static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) | |
316 | { | |
317 | sched_set_itmt_support(); | |
318 | } | |
319 | ||
320 | static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); | |
321 | ||
322 | static void intel_pstate_set_itmt_prio(int cpu) | |
323 | { | |
324 | struct cppc_perf_caps cppc_perf; | |
325 | static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; | |
326 | int ret; | |
327 | ||
328 | ret = cppc_get_perf_caps(cpu, &cppc_perf); | |
329 | if (ret) | |
330 | return; | |
331 | ||
332 | /* | |
333 | * The priorities can be set regardless of whether or not | |
334 | * sched_set_itmt_support(true) has been called and it is valid to | |
335 | * update them at any time after it has been called. | |
336 | */ | |
337 | sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); | |
338 | ||
339 | if (max_highest_perf <= min_highest_perf) { | |
340 | if (cppc_perf.highest_perf > max_highest_perf) | |
341 | max_highest_perf = cppc_perf.highest_perf; | |
342 | ||
343 | if (cppc_perf.highest_perf < min_highest_perf) | |
344 | min_highest_perf = cppc_perf.highest_perf; | |
345 | ||
346 | if (max_highest_perf > min_highest_perf) { | |
347 | /* | |
348 | * This code can be run during CPU online under the | |
349 | * CPU hotplug locks, so sched_set_itmt_support() | |
350 | * cannot be called from here. Queue up a work item | |
351 | * to invoke it. | |
352 | */ | |
353 | schedule_work(&sched_itmt_work); | |
354 | } | |
355 | } | |
356 | } | |
357 | #else | |
358 | static void intel_pstate_set_itmt_prio(int cpu) | |
359 | { | |
360 | } | |
361 | #endif | |
362 | ||
9522a2ff SP |
363 | static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) |
364 | { | |
365 | struct cpudata *cpu; | |
9522a2ff SP |
366 | int ret; |
367 | int i; | |
368 | ||
17669006 RW |
369 | if (hwp_active) { |
370 | intel_pstate_set_itmt_prio(policy->cpu); | |
e59a8f7f | 371 | return; |
17669006 | 372 | } |
e59a8f7f | 373 | |
2b3ec765 | 374 | if (!intel_pstate_get_ppc_enable_status()) |
9522a2ff SP |
375 | return; |
376 | ||
377 | cpu = all_cpu_data[policy->cpu]; | |
378 | ||
379 | ret = acpi_processor_register_performance(&cpu->acpi_perf_data, | |
380 | policy->cpu); | |
381 | if (ret) | |
382 | return; | |
383 | ||
384 | /* | |
385 | * Check if the control value in _PSS is for PERF_CTL MSR, which should | |
386 | * guarantee that the states returned by it map to the states in our | |
387 | * list directly. | |
388 | */ | |
389 | if (cpu->acpi_perf_data.control_register.space_id != | |
390 | ACPI_ADR_SPACE_FIXED_HARDWARE) | |
391 | goto err; | |
392 | ||
393 | /* | |
394 | * If there is only one entry _PSS, simply ignore _PSS and continue as | |
395 | * usual without taking _PSS into account | |
396 | */ | |
397 | if (cpu->acpi_perf_data.state_count < 2) | |
398 | goto err; | |
399 | ||
400 | pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); | |
401 | for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { | |
402 | pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", | |
403 | (i == cpu->acpi_perf_data.state ? '*' : ' '), i, | |
404 | (u32) cpu->acpi_perf_data.states[i].core_frequency, | |
405 | (u32) cpu->acpi_perf_data.states[i].power, | |
406 | (u32) cpu->acpi_perf_data.states[i].control); | |
407 | } | |
408 | ||
409 | /* | |
410 | * The _PSS table doesn't contain whole turbo frequency range. | |
411 | * This just contains +1 MHZ above the max non turbo frequency, | |
412 | * with control value corresponding to max turbo ratio. But | |
413 | * when cpufreq set policy is called, it will call with this | |
414 | * max frequency, which will cause a reduced performance as | |
415 | * this driver uses real max turbo frequency as the max | |
416 | * frequency. So correct this frequency in _PSS table to | |
b00345d1 | 417 | * correct max turbo frequency based on the turbo state. |
9522a2ff SP |
418 | * Also need to convert to MHz as _PSS freq is in MHz. |
419 | */ | |
7de32556 | 420 | if (!global.turbo_disabled) |
9522a2ff SP |
421 | cpu->acpi_perf_data.states[0].core_frequency = |
422 | policy->cpuinfo.max_freq / 1000; | |
423 | cpu->valid_pss_table = true; | |
6cacd115 | 424 | pr_debug("_PPC limits will be enforced\n"); |
9522a2ff SP |
425 | |
426 | return; | |
427 | ||
428 | err: | |
429 | cpu->valid_pss_table = false; | |
430 | acpi_processor_unregister_performance(policy->cpu); | |
431 | } | |
432 | ||
433 | static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) | |
434 | { | |
435 | struct cpudata *cpu; | |
436 | ||
437 | cpu = all_cpu_data[policy->cpu]; | |
438 | if (!cpu->valid_pss_table) | |
439 | return; | |
440 | ||
441 | acpi_processor_unregister_performance(policy->cpu); | |
442 | } | |
9522a2ff | 443 | #else |
7a3ba767 | 444 | static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) |
9522a2ff SP |
445 | { |
446 | } | |
447 | ||
7a3ba767 | 448 | static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) |
9522a2ff SP |
449 | { |
450 | } | |
451 | #endif | |
452 | ||
4521e1a0 GM |
453 | static inline void update_turbo_state(void) |
454 | { | |
455 | u64 misc_en; | |
456 | struct cpudata *cpu; | |
457 | ||
458 | cpu = all_cpu_data[0]; | |
459 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); | |
7de32556 | 460 | global.turbo_disabled = |
4521e1a0 GM |
461 | (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || |
462 | cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); | |
463 | } | |
464 | ||
c5a2ee7d RW |
465 | static int min_perf_pct_min(void) |
466 | { | |
467 | struct cpudata *cpu = all_cpu_data[0]; | |
57caf4ec | 468 | int turbo_pstate = cpu->pstate.turbo_pstate; |
c5a2ee7d | 469 | |
57caf4ec | 470 | return turbo_pstate ? |
d4436c0d | 471 | (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; |
c5a2ee7d RW |
472 | } |
473 | ||
8442885f SP |
474 | static s16 intel_pstate_get_epb(struct cpudata *cpu_data) |
475 | { | |
476 | u64 epb; | |
477 | int ret; | |
478 | ||
479 | if (!static_cpu_has(X86_FEATURE_EPB)) | |
480 | return -ENXIO; | |
481 | ||
482 | ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); | |
483 | if (ret) | |
484 | return (s16)ret; | |
485 | ||
486 | return (s16)(epb & 0x0f); | |
487 | } | |
488 | ||
489 | static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) | |
490 | { | |
491 | s16 epp; | |
492 | ||
984edbdc SP |
493 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { |
494 | /* | |
495 | * When hwp_req_data is 0, means that caller didn't read | |
496 | * MSR_HWP_REQUEST, so need to read and get EPP. | |
497 | */ | |
498 | if (!hwp_req_data) { | |
499 | epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, | |
500 | &hwp_req_data); | |
501 | if (epp) | |
502 | return epp; | |
503 | } | |
8442885f | 504 | epp = (hwp_req_data >> 24) & 0xff; |
984edbdc | 505 | } else { |
8442885f SP |
506 | /* When there is no EPP present, HWP uses EPB settings */ |
507 | epp = intel_pstate_get_epb(cpu_data); | |
984edbdc | 508 | } |
8442885f SP |
509 | |
510 | return epp; | |
511 | } | |
512 | ||
984edbdc | 513 | static int intel_pstate_set_epb(int cpu, s16 pref) |
8442885f SP |
514 | { |
515 | u64 epb; | |
984edbdc | 516 | int ret; |
8442885f SP |
517 | |
518 | if (!static_cpu_has(X86_FEATURE_EPB)) | |
984edbdc | 519 | return -ENXIO; |
8442885f | 520 | |
984edbdc SP |
521 | ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); |
522 | if (ret) | |
523 | return ret; | |
8442885f SP |
524 | |
525 | epb = (epb & ~0x0f) | pref; | |
526 | wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); | |
984edbdc SP |
527 | |
528 | return 0; | |
8442885f SP |
529 | } |
530 | ||
984edbdc SP |
531 | /* |
532 | * EPP/EPB display strings corresponding to EPP index in the | |
533 | * energy_perf_strings[] | |
534 | * index String | |
535 | *------------------------------------- | |
536 | * 0 default | |
537 | * 1 performance | |
538 | * 2 balance_performance | |
539 | * 3 balance_power | |
540 | * 4 power | |
541 | */ | |
542 | static const char * const energy_perf_strings[] = { | |
543 | "default", | |
544 | "performance", | |
545 | "balance_performance", | |
546 | "balance_power", | |
547 | "power", | |
548 | NULL | |
549 | }; | |
3cedbc5a LB |
550 | static const unsigned int epp_values[] = { |
551 | HWP_EPP_PERFORMANCE, | |
552 | HWP_EPP_BALANCE_PERFORMANCE, | |
553 | HWP_EPP_BALANCE_POWERSAVE, | |
554 | HWP_EPP_POWERSAVE | |
555 | }; | |
984edbdc SP |
556 | |
557 | static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data) | |
558 | { | |
559 | s16 epp; | |
560 | int index = -EINVAL; | |
561 | ||
562 | epp = intel_pstate_get_epp(cpu_data, 0); | |
563 | if (epp < 0) | |
564 | return epp; | |
565 | ||
566 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { | |
3cedbc5a LB |
567 | if (epp == HWP_EPP_PERFORMANCE) |
568 | return 1; | |
569 | if (epp <= HWP_EPP_BALANCE_PERFORMANCE) | |
570 | return 2; | |
571 | if (epp <= HWP_EPP_BALANCE_POWERSAVE) | |
572 | return 3; | |
573 | else | |
574 | return 4; | |
984edbdc SP |
575 | } else if (static_cpu_has(X86_FEATURE_EPB)) { |
576 | /* | |
577 | * Range: | |
578 | * 0x00-0x03 : Performance | |
579 | * 0x04-0x07 : Balance performance | |
580 | * 0x08-0x0B : Balance power | |
581 | * 0x0C-0x0F : Power | |
582 | * The EPB is a 4 bit value, but our ranges restrict the | |
583 | * value which can be set. Here only using top two bits | |
584 | * effectively. | |
585 | */ | |
586 | index = (epp >> 2) + 1; | |
587 | } | |
588 | ||
589 | return index; | |
590 | } | |
591 | ||
592 | static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, | |
593 | int pref_index) | |
594 | { | |
595 | int epp = -EINVAL; | |
596 | int ret; | |
597 | ||
598 | if (!pref_index) | |
599 | epp = cpu_data->epp_default; | |
600 | ||
601 | mutex_lock(&intel_pstate_limits_lock); | |
602 | ||
603 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { | |
604 | u64 value; | |
605 | ||
606 | ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value); | |
607 | if (ret) | |
608 | goto return_pref; | |
609 | ||
610 | value &= ~GENMASK_ULL(31, 24); | |
611 | ||
984edbdc | 612 | if (epp == -EINVAL) |
3cedbc5a | 613 | epp = epp_values[pref_index - 1]; |
984edbdc SP |
614 | |
615 | value |= (u64)epp << 24; | |
616 | ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value); | |
617 | } else { | |
618 | if (epp == -EINVAL) | |
619 | epp = (pref_index - 1) << 2; | |
620 | ret = intel_pstate_set_epb(cpu_data->cpu, epp); | |
621 | } | |
622 | return_pref: | |
623 | mutex_unlock(&intel_pstate_limits_lock); | |
624 | ||
625 | return ret; | |
626 | } | |
627 | ||
628 | static ssize_t show_energy_performance_available_preferences( | |
629 | struct cpufreq_policy *policy, char *buf) | |
630 | { | |
631 | int i = 0; | |
632 | int ret = 0; | |
633 | ||
634 | while (energy_perf_strings[i] != NULL) | |
635 | ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); | |
636 | ||
637 | ret += sprintf(&buf[ret], "\n"); | |
638 | ||
639 | return ret; | |
640 | } | |
641 | ||
642 | cpufreq_freq_attr_ro(energy_performance_available_preferences); | |
643 | ||
644 | static ssize_t store_energy_performance_preference( | |
645 | struct cpufreq_policy *policy, const char *buf, size_t count) | |
646 | { | |
647 | struct cpudata *cpu_data = all_cpu_data[policy->cpu]; | |
648 | char str_preference[21]; | |
649 | int ret, i = 0; | |
650 | ||
651 | ret = sscanf(buf, "%20s", str_preference); | |
652 | if (ret != 1) | |
653 | return -EINVAL; | |
654 | ||
655 | while (energy_perf_strings[i] != NULL) { | |
656 | if (!strcmp(str_preference, energy_perf_strings[i])) { | |
657 | intel_pstate_set_energy_pref_index(cpu_data, i); | |
658 | return count; | |
659 | } | |
660 | ++i; | |
661 | } | |
662 | ||
663 | return -EINVAL; | |
664 | } | |
665 | ||
666 | static ssize_t show_energy_performance_preference( | |
667 | struct cpufreq_policy *policy, char *buf) | |
668 | { | |
669 | struct cpudata *cpu_data = all_cpu_data[policy->cpu]; | |
670 | int preference; | |
671 | ||
672 | preference = intel_pstate_get_energy_pref_index(cpu_data); | |
673 | if (preference < 0) | |
674 | return preference; | |
675 | ||
676 | return sprintf(buf, "%s\n", energy_perf_strings[preference]); | |
677 | } | |
678 | ||
679 | cpufreq_freq_attr_rw(energy_performance_preference); | |
680 | ||
681 | static struct freq_attr *hwp_cpufreq_attrs[] = { | |
682 | &energy_performance_preference, | |
683 | &energy_performance_available_preferences, | |
684 | NULL, | |
685 | }; | |
686 | ||
1a4fe38a SP |
687 | static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max, |
688 | int *current_max) | |
2f86dc4c | 689 | { |
1a4fe38a | 690 | u64 cap; |
74da56ce | 691 | |
2bfc4cbb | 692 | rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap); |
2bfc4cbb | 693 | if (global.no_turbo) |
1a4fe38a | 694 | *current_max = HWP_GUARANTEED_PERF(cap); |
2bfc4cbb | 695 | else |
1a4fe38a SP |
696 | *current_max = HWP_HIGHEST_PERF(cap); |
697 | ||
698 | *phy_max = HWP_HIGHEST_PERF(cap); | |
699 | } | |
700 | ||
701 | static void intel_pstate_hwp_set(unsigned int cpu) | |
702 | { | |
703 | struct cpudata *cpu_data = all_cpu_data[cpu]; | |
704 | int max, min; | |
705 | u64 value; | |
706 | s16 epp; | |
707 | ||
708 | max = cpu_data->max_perf_ratio; | |
709 | min = cpu_data->min_perf_ratio; | |
eae48f04 | 710 | |
2bfc4cbb RW |
711 | if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) |
712 | min = max; | |
3f8ed54a | 713 | |
2bfc4cbb | 714 | rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); |
2f86dc4c | 715 | |
2bfc4cbb RW |
716 | value &= ~HWP_MIN_PERF(~0L); |
717 | value |= HWP_MIN_PERF(min); | |
8442885f | 718 | |
2bfc4cbb RW |
719 | value &= ~HWP_MAX_PERF(~0L); |
720 | value |= HWP_MAX_PERF(max); | |
8442885f | 721 | |
2bfc4cbb RW |
722 | if (cpu_data->epp_policy == cpu_data->policy) |
723 | goto skip_epp; | |
8442885f | 724 | |
2bfc4cbb | 725 | cpu_data->epp_policy = cpu_data->policy; |
984edbdc | 726 | |
2bfc4cbb RW |
727 | if (cpu_data->epp_saved >= 0) { |
728 | epp = cpu_data->epp_saved; | |
729 | cpu_data->epp_saved = -EINVAL; | |
730 | goto update_epp; | |
731 | } | |
8442885f | 732 | |
2bfc4cbb RW |
733 | if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { |
734 | epp = intel_pstate_get_epp(cpu_data, value); | |
735 | cpu_data->epp_powersave = epp; | |
736 | /* If EPP read was failed, then don't try to write */ | |
737 | if (epp < 0) | |
738 | goto skip_epp; | |
8442885f | 739 | |
2bfc4cbb RW |
740 | epp = 0; |
741 | } else { | |
742 | /* skip setting EPP, when saved value is invalid */ | |
743 | if (cpu_data->epp_powersave < 0) | |
744 | goto skip_epp; | |
8442885f | 745 | |
2bfc4cbb RW |
746 | /* |
747 | * No need to restore EPP when it is not zero. This | |
748 | * means: | |
749 | * - Policy is not changed | |
750 | * - user has manually changed | |
751 | * - Error reading EPB | |
752 | */ | |
753 | epp = intel_pstate_get_epp(cpu_data, value); | |
754 | if (epp) | |
755 | goto skip_epp; | |
8442885f | 756 | |
2bfc4cbb RW |
757 | epp = cpu_data->epp_powersave; |
758 | } | |
984edbdc | 759 | update_epp: |
2bfc4cbb RW |
760 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { |
761 | value &= ~GENMASK_ULL(31, 24); | |
762 | value |= (u64)epp << 24; | |
763 | } else { | |
764 | intel_pstate_set_epb(cpu, epp); | |
2f86dc4c | 765 | } |
2bfc4cbb RW |
766 | skip_epp: |
767 | wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); | |
41cfd64c | 768 | } |
2f86dc4c | 769 | |
984edbdc SP |
770 | static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy) |
771 | { | |
772 | struct cpudata *cpu_data = all_cpu_data[policy->cpu]; | |
773 | ||
774 | if (!hwp_active) | |
775 | return 0; | |
776 | ||
777 | cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0); | |
778 | ||
779 | return 0; | |
780 | } | |
781 | ||
b672e570 CY |
782 | static void intel_pstate_hwp_enable(struct cpudata *cpudata); |
783 | ||
8442885f SP |
784 | static int intel_pstate_resume(struct cpufreq_policy *policy) |
785 | { | |
786 | if (!hwp_active) | |
787 | return 0; | |
788 | ||
aa439248 RW |
789 | mutex_lock(&intel_pstate_limits_lock); |
790 | ||
b672e570 CY |
791 | if (policy->cpu == 0) |
792 | intel_pstate_hwp_enable(all_cpu_data[policy->cpu]); | |
793 | ||
8442885f | 794 | all_cpu_data[policy->cpu]->epp_policy = 0; |
2bfc4cbb | 795 | intel_pstate_hwp_set(policy->cpu); |
aa439248 RW |
796 | |
797 | mutex_unlock(&intel_pstate_limits_lock); | |
798 | ||
5f98ced1 | 799 | return 0; |
8442885f SP |
800 | } |
801 | ||
111b8b3f | 802 | static void intel_pstate_update_policies(void) |
41cfd64c | 803 | { |
111b8b3f RW |
804 | int cpu; |
805 | ||
806 | for_each_possible_cpu(cpu) | |
807 | cpufreq_update_policy(cpu); | |
2f86dc4c DB |
808 | } |
809 | ||
93f0822d DB |
810 | /************************** sysfs begin ************************/ |
811 | #define show_one(file_name, object) \ | |
812 | static ssize_t show_##file_name \ | |
813 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
814 | { \ | |
7de32556 | 815 | return sprintf(buf, "%u\n", global.object); \ |
93f0822d DB |
816 | } |
817 | ||
fb1fe104 RW |
818 | static ssize_t intel_pstate_show_status(char *buf); |
819 | static int intel_pstate_update_status(const char *buf, size_t size); | |
820 | ||
821 | static ssize_t show_status(struct kobject *kobj, | |
822 | struct attribute *attr, char *buf) | |
823 | { | |
824 | ssize_t ret; | |
825 | ||
826 | mutex_lock(&intel_pstate_driver_lock); | |
827 | ret = intel_pstate_show_status(buf); | |
828 | mutex_unlock(&intel_pstate_driver_lock); | |
829 | ||
830 | return ret; | |
831 | } | |
832 | ||
833 | static ssize_t store_status(struct kobject *a, struct attribute *b, | |
834 | const char *buf, size_t count) | |
835 | { | |
836 | char *p = memchr(buf, '\n', count); | |
837 | int ret; | |
838 | ||
839 | mutex_lock(&intel_pstate_driver_lock); | |
840 | ret = intel_pstate_update_status(buf, p ? p - buf : count); | |
841 | mutex_unlock(&intel_pstate_driver_lock); | |
842 | ||
843 | return ret < 0 ? ret : count; | |
844 | } | |
845 | ||
d01b1f48 KCA |
846 | static ssize_t show_turbo_pct(struct kobject *kobj, |
847 | struct attribute *attr, char *buf) | |
848 | { | |
849 | struct cpudata *cpu; | |
850 | int total, no_turbo, turbo_pct; | |
851 | uint32_t turbo_fp; | |
852 | ||
0c30b65b RW |
853 | mutex_lock(&intel_pstate_driver_lock); |
854 | ||
ee8df89a | 855 | if (!intel_pstate_driver) { |
0c30b65b RW |
856 | mutex_unlock(&intel_pstate_driver_lock); |
857 | return -EAGAIN; | |
858 | } | |
859 | ||
d01b1f48 KCA |
860 | cpu = all_cpu_data[0]; |
861 | ||
862 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
863 | no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; | |
22590efb | 864 | turbo_fp = div_fp(no_turbo, total); |
d01b1f48 | 865 | turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); |
0c30b65b RW |
866 | |
867 | mutex_unlock(&intel_pstate_driver_lock); | |
868 | ||
d01b1f48 KCA |
869 | return sprintf(buf, "%u\n", turbo_pct); |
870 | } | |
871 | ||
0522424e KCA |
872 | static ssize_t show_num_pstates(struct kobject *kobj, |
873 | struct attribute *attr, char *buf) | |
874 | { | |
875 | struct cpudata *cpu; | |
876 | int total; | |
877 | ||
0c30b65b RW |
878 | mutex_lock(&intel_pstate_driver_lock); |
879 | ||
ee8df89a | 880 | if (!intel_pstate_driver) { |
0c30b65b RW |
881 | mutex_unlock(&intel_pstate_driver_lock); |
882 | return -EAGAIN; | |
883 | } | |
884 | ||
0522424e KCA |
885 | cpu = all_cpu_data[0]; |
886 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
0c30b65b RW |
887 | |
888 | mutex_unlock(&intel_pstate_driver_lock); | |
889 | ||
0522424e KCA |
890 | return sprintf(buf, "%u\n", total); |
891 | } | |
892 | ||
4521e1a0 GM |
893 | static ssize_t show_no_turbo(struct kobject *kobj, |
894 | struct attribute *attr, char *buf) | |
895 | { | |
896 | ssize_t ret; | |
897 | ||
0c30b65b RW |
898 | mutex_lock(&intel_pstate_driver_lock); |
899 | ||
ee8df89a | 900 | if (!intel_pstate_driver) { |
0c30b65b RW |
901 | mutex_unlock(&intel_pstate_driver_lock); |
902 | return -EAGAIN; | |
903 | } | |
904 | ||
4521e1a0 | 905 | update_turbo_state(); |
7de32556 RW |
906 | if (global.turbo_disabled) |
907 | ret = sprintf(buf, "%u\n", global.turbo_disabled); | |
4521e1a0 | 908 | else |
7de32556 | 909 | ret = sprintf(buf, "%u\n", global.no_turbo); |
4521e1a0 | 910 | |
0c30b65b RW |
911 | mutex_unlock(&intel_pstate_driver_lock); |
912 | ||
4521e1a0 GM |
913 | return ret; |
914 | } | |
915 | ||
93f0822d | 916 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, |
c410833a | 917 | const char *buf, size_t count) |
93f0822d DB |
918 | { |
919 | unsigned int input; | |
920 | int ret; | |
845c1cbe | 921 | |
93f0822d DB |
922 | ret = sscanf(buf, "%u", &input); |
923 | if (ret != 1) | |
924 | return -EINVAL; | |
4521e1a0 | 925 | |
0c30b65b RW |
926 | mutex_lock(&intel_pstate_driver_lock); |
927 | ||
ee8df89a | 928 | if (!intel_pstate_driver) { |
0c30b65b RW |
929 | mutex_unlock(&intel_pstate_driver_lock); |
930 | return -EAGAIN; | |
931 | } | |
932 | ||
a410c03d SP |
933 | mutex_lock(&intel_pstate_limits_lock); |
934 | ||
4521e1a0 | 935 | update_turbo_state(); |
7de32556 | 936 | if (global.turbo_disabled) { |
4836df17 | 937 | pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); |
a410c03d | 938 | mutex_unlock(&intel_pstate_limits_lock); |
0c30b65b | 939 | mutex_unlock(&intel_pstate_driver_lock); |
4521e1a0 | 940 | return -EPERM; |
dd5fbf70 | 941 | } |
2f86dc4c | 942 | |
7de32556 | 943 | global.no_turbo = clamp_t(int, input, 0, 1); |
111b8b3f | 944 | |
c5a2ee7d RW |
945 | if (global.no_turbo) { |
946 | struct cpudata *cpu = all_cpu_data[0]; | |
947 | int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; | |
948 | ||
949 | /* Squash the global minimum into the permitted range. */ | |
950 | if (global.min_perf_pct > pct) | |
951 | global.min_perf_pct = pct; | |
952 | } | |
953 | ||
cd59b4be RW |
954 | mutex_unlock(&intel_pstate_limits_lock); |
955 | ||
7de32556 RW |
956 | intel_pstate_update_policies(); |
957 | ||
0c30b65b RW |
958 | mutex_unlock(&intel_pstate_driver_lock); |
959 | ||
93f0822d DB |
960 | return count; |
961 | } | |
962 | ||
963 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 964 | const char *buf, size_t count) |
93f0822d DB |
965 | { |
966 | unsigned int input; | |
967 | int ret; | |
845c1cbe | 968 | |
93f0822d DB |
969 | ret = sscanf(buf, "%u", &input); |
970 | if (ret != 1) | |
971 | return -EINVAL; | |
972 | ||
0c30b65b RW |
973 | mutex_lock(&intel_pstate_driver_lock); |
974 | ||
ee8df89a | 975 | if (!intel_pstate_driver) { |
0c30b65b RW |
976 | mutex_unlock(&intel_pstate_driver_lock); |
977 | return -EAGAIN; | |
978 | } | |
979 | ||
a410c03d SP |
980 | mutex_lock(&intel_pstate_limits_lock); |
981 | ||
c5a2ee7d | 982 | global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); |
111b8b3f | 983 | |
cd59b4be RW |
984 | mutex_unlock(&intel_pstate_limits_lock); |
985 | ||
7de32556 RW |
986 | intel_pstate_update_policies(); |
987 | ||
0c30b65b RW |
988 | mutex_unlock(&intel_pstate_driver_lock); |
989 | ||
93f0822d DB |
990 | return count; |
991 | } | |
992 | ||
993 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 994 | const char *buf, size_t count) |
93f0822d DB |
995 | { |
996 | unsigned int input; | |
997 | int ret; | |
845c1cbe | 998 | |
93f0822d DB |
999 | ret = sscanf(buf, "%u", &input); |
1000 | if (ret != 1) | |
1001 | return -EINVAL; | |
a0475992 | 1002 | |
0c30b65b RW |
1003 | mutex_lock(&intel_pstate_driver_lock); |
1004 | ||
ee8df89a | 1005 | if (!intel_pstate_driver) { |
0c30b65b RW |
1006 | mutex_unlock(&intel_pstate_driver_lock); |
1007 | return -EAGAIN; | |
1008 | } | |
1009 | ||
a410c03d SP |
1010 | mutex_lock(&intel_pstate_limits_lock); |
1011 | ||
c5a2ee7d RW |
1012 | global.min_perf_pct = clamp_t(int, input, |
1013 | min_perf_pct_min(), global.max_perf_pct); | |
111b8b3f | 1014 | |
cd59b4be RW |
1015 | mutex_unlock(&intel_pstate_limits_lock); |
1016 | ||
7de32556 RW |
1017 | intel_pstate_update_policies(); |
1018 | ||
0c30b65b RW |
1019 | mutex_unlock(&intel_pstate_driver_lock); |
1020 | ||
93f0822d DB |
1021 | return count; |
1022 | } | |
1023 | ||
93f0822d DB |
1024 | show_one(max_perf_pct, max_perf_pct); |
1025 | show_one(min_perf_pct, min_perf_pct); | |
1026 | ||
fb1fe104 | 1027 | define_one_global_rw(status); |
93f0822d DB |
1028 | define_one_global_rw(no_turbo); |
1029 | define_one_global_rw(max_perf_pct); | |
1030 | define_one_global_rw(min_perf_pct); | |
d01b1f48 | 1031 | define_one_global_ro(turbo_pct); |
0522424e | 1032 | define_one_global_ro(num_pstates); |
93f0822d DB |
1033 | |
1034 | static struct attribute *intel_pstate_attributes[] = { | |
fb1fe104 | 1035 | &status.attr, |
93f0822d | 1036 | &no_turbo.attr, |
d01b1f48 | 1037 | &turbo_pct.attr, |
0522424e | 1038 | &num_pstates.attr, |
93f0822d DB |
1039 | NULL |
1040 | }; | |
1041 | ||
106c9c77 | 1042 | static const struct attribute_group intel_pstate_attr_group = { |
93f0822d DB |
1043 | .attrs = intel_pstate_attributes, |
1044 | }; | |
93f0822d | 1045 | |
317dd50e | 1046 | static void __init intel_pstate_sysfs_expose_params(void) |
93f0822d | 1047 | { |
317dd50e | 1048 | struct kobject *intel_pstate_kobject; |
93f0822d DB |
1049 | int rc; |
1050 | ||
1051 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
1052 | &cpu_subsys.dev_root->kobj); | |
eae48f04 SP |
1053 | if (WARN_ON(!intel_pstate_kobject)) |
1054 | return; | |
1055 | ||
2d8d1f18 | 1056 | rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); |
eae48f04 SP |
1057 | if (WARN_ON(rc)) |
1058 | return; | |
1059 | ||
1060 | /* | |
1061 | * If per cpu limits are enforced there are no global limits, so | |
1062 | * return without creating max/min_perf_pct attributes | |
1063 | */ | |
1064 | if (per_cpu_limits) | |
1065 | return; | |
1066 | ||
1067 | rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); | |
1068 | WARN_ON(rc); | |
1069 | ||
1070 | rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); | |
1071 | WARN_ON(rc); | |
1072 | ||
93f0822d | 1073 | } |
93f0822d | 1074 | /************************** sysfs end ************************/ |
2f86dc4c | 1075 | |
ba88d433 | 1076 | static void intel_pstate_hwp_enable(struct cpudata *cpudata) |
2f86dc4c | 1077 | { |
f05c9665 | 1078 | /* First disable HWP notification interrupt as we don't process them */ |
da7de91c SP |
1079 | if (static_cpu_has(X86_FEATURE_HWP_NOTIFY)) |
1080 | wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); | |
f05c9665 | 1081 | |
ba88d433 | 1082 | wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); |
8442885f | 1083 | cpudata->epp_policy = 0; |
984edbdc SP |
1084 | if (cpudata->epp_default == -EINVAL) |
1085 | cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); | |
2f86dc4c DB |
1086 | } |
1087 | ||
6e978b22 SP |
1088 | #define MSR_IA32_POWER_CTL_BIT_EE 19 |
1089 | ||
1090 | /* Disable energy efficiency optimization */ | |
1091 | static void intel_pstate_disable_ee(int cpu) | |
1092 | { | |
1093 | u64 power_ctl; | |
1094 | int ret; | |
1095 | ||
1096 | ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl); | |
1097 | if (ret) | |
1098 | return; | |
1099 | ||
1100 | if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) { | |
1101 | pr_info("Disabling energy efficiency optimization\n"); | |
1102 | power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); | |
1103 | wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl); | |
1104 | } | |
1105 | } | |
1106 | ||
938d21a2 | 1107 | static int atom_get_min_pstate(void) |
19e77c28 DB |
1108 | { |
1109 | u64 value; | |
845c1cbe | 1110 | |
92134bdb | 1111 | rdmsrl(MSR_ATOM_CORE_RATIOS, value); |
c16ed060 | 1112 | return (value >> 8) & 0x7F; |
19e77c28 DB |
1113 | } |
1114 | ||
938d21a2 | 1115 | static int atom_get_max_pstate(void) |
19e77c28 DB |
1116 | { |
1117 | u64 value; | |
845c1cbe | 1118 | |
92134bdb | 1119 | rdmsrl(MSR_ATOM_CORE_RATIOS, value); |
c16ed060 | 1120 | return (value >> 16) & 0x7F; |
19e77c28 | 1121 | } |
93f0822d | 1122 | |
938d21a2 | 1123 | static int atom_get_turbo_pstate(void) |
61d8d2ab DB |
1124 | { |
1125 | u64 value; | |
845c1cbe | 1126 | |
92134bdb | 1127 | rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); |
c16ed060 | 1128 | return value & 0x7F; |
61d8d2ab DB |
1129 | } |
1130 | ||
fdfdb2b1 | 1131 | static u64 atom_get_val(struct cpudata *cpudata, int pstate) |
007bea09 DB |
1132 | { |
1133 | u64 val; | |
1134 | int32_t vid_fp; | |
1135 | u32 vid; | |
1136 | ||
144c8e17 | 1137 | val = (u64)pstate << 8; |
7de32556 | 1138 | if (global.no_turbo && !global.turbo_disabled) |
007bea09 DB |
1139 | val |= (u64)1 << 32; |
1140 | ||
1141 | vid_fp = cpudata->vid.min + mul_fp( | |
1142 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
1143 | cpudata->vid.ratio); | |
1144 | ||
1145 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
d022a65e | 1146 | vid = ceiling_fp(vid_fp); |
007bea09 | 1147 | |
21855ff5 DB |
1148 | if (pstate > cpudata->pstate.max_pstate) |
1149 | vid = cpudata->vid.turbo; | |
1150 | ||
fdfdb2b1 | 1151 | return val | vid; |
007bea09 DB |
1152 | } |
1153 | ||
1421df63 | 1154 | static int silvermont_get_scaling(void) |
b27580b0 DB |
1155 | { |
1156 | u64 value; | |
1157 | int i; | |
1421df63 PL |
1158 | /* Defined in Table 35-6 from SDM (Sept 2015) */ |
1159 | static int silvermont_freq_table[] = { | |
1160 | 83300, 100000, 133300, 116700, 80000}; | |
b27580b0 DB |
1161 | |
1162 | rdmsrl(MSR_FSB_FREQ, value); | |
1421df63 PL |
1163 | i = value & 0x7; |
1164 | WARN_ON(i > 4); | |
b27580b0 | 1165 | |
1421df63 PL |
1166 | return silvermont_freq_table[i]; |
1167 | } | |
b27580b0 | 1168 | |
1421df63 PL |
1169 | static int airmont_get_scaling(void) |
1170 | { | |
1171 | u64 value; | |
1172 | int i; | |
1173 | /* Defined in Table 35-10 from SDM (Sept 2015) */ | |
1174 | static int airmont_freq_table[] = { | |
1175 | 83300, 100000, 133300, 116700, 80000, | |
1176 | 93300, 90000, 88900, 87500}; | |
1177 | ||
1178 | rdmsrl(MSR_FSB_FREQ, value); | |
1179 | i = value & 0xF; | |
1180 | WARN_ON(i > 8); | |
1181 | ||
1182 | return airmont_freq_table[i]; | |
b27580b0 DB |
1183 | } |
1184 | ||
938d21a2 | 1185 | static void atom_get_vid(struct cpudata *cpudata) |
007bea09 DB |
1186 | { |
1187 | u64 value; | |
1188 | ||
92134bdb | 1189 | rdmsrl(MSR_ATOM_CORE_VIDS, value); |
c16ed060 DB |
1190 | cpudata->vid.min = int_tofp((value >> 8) & 0x7f); |
1191 | cpudata->vid.max = int_tofp((value >> 16) & 0x7f); | |
007bea09 DB |
1192 | cpudata->vid.ratio = div_fp( |
1193 | cpudata->vid.max - cpudata->vid.min, | |
1194 | int_tofp(cpudata->pstate.max_pstate - | |
1195 | cpudata->pstate.min_pstate)); | |
21855ff5 | 1196 | |
92134bdb | 1197 | rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); |
21855ff5 | 1198 | cpudata->vid.turbo = value & 0x7f; |
007bea09 DB |
1199 | } |
1200 | ||
016c8150 | 1201 | static int core_get_min_pstate(void) |
93f0822d DB |
1202 | { |
1203 | u64 value; | |
845c1cbe | 1204 | |
05e99c8c | 1205 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
1206 | return (value >> 40) & 0xFF; |
1207 | } | |
1208 | ||
3bcc6fa9 | 1209 | static int core_get_max_pstate_physical(void) |
93f0822d DB |
1210 | { |
1211 | u64 value; | |
845c1cbe | 1212 | |
05e99c8c | 1213 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
1214 | return (value >> 8) & 0xFF; |
1215 | } | |
1216 | ||
8fc7554a SP |
1217 | static int core_get_tdp_ratio(u64 plat_info) |
1218 | { | |
1219 | /* Check how many TDP levels present */ | |
1220 | if (plat_info & 0x600000000) { | |
1221 | u64 tdp_ctrl; | |
1222 | u64 tdp_ratio; | |
1223 | int tdp_msr; | |
1224 | int err; | |
1225 | ||
1226 | /* Get the TDP level (0, 1, 2) to get ratios */ | |
1227 | err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); | |
1228 | if (err) | |
1229 | return err; | |
1230 | ||
1231 | /* TDP MSR are continuous starting at 0x648 */ | |
1232 | tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); | |
1233 | err = rdmsrl_safe(tdp_msr, &tdp_ratio); | |
1234 | if (err) | |
1235 | return err; | |
1236 | ||
1237 | /* For level 1 and 2, bits[23:16] contain the ratio */ | |
1238 | if (tdp_ctrl & 0x03) | |
1239 | tdp_ratio >>= 16; | |
1240 | ||
1241 | tdp_ratio &= 0xff; /* ratios are only 8 bits long */ | |
1242 | pr_debug("tdp_ratio %x\n", (int)tdp_ratio); | |
1243 | ||
1244 | return (int)tdp_ratio; | |
1245 | } | |
1246 | ||
1247 | return -ENXIO; | |
1248 | } | |
1249 | ||
016c8150 | 1250 | static int core_get_max_pstate(void) |
93f0822d | 1251 | { |
6a35fc2d SP |
1252 | u64 tar; |
1253 | u64 plat_info; | |
1254 | int max_pstate; | |
8fc7554a | 1255 | int tdp_ratio; |
6a35fc2d SP |
1256 | int err; |
1257 | ||
1258 | rdmsrl(MSR_PLATFORM_INFO, plat_info); | |
1259 | max_pstate = (plat_info >> 8) & 0xFF; | |
1260 | ||
8fc7554a SP |
1261 | tdp_ratio = core_get_tdp_ratio(plat_info); |
1262 | if (tdp_ratio <= 0) | |
1263 | return max_pstate; | |
1264 | ||
1265 | if (hwp_active) { | |
1266 | /* Turbo activation ratio is not used on HWP platforms */ | |
1267 | return tdp_ratio; | |
1268 | } | |
1269 | ||
6a35fc2d SP |
1270 | err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); |
1271 | if (!err) { | |
8fc7554a SP |
1272 | int tar_levels; |
1273 | ||
6a35fc2d | 1274 | /* Do some sanity checking for safety */ |
8fc7554a SP |
1275 | tar_levels = tar & 0xff; |
1276 | if (tdp_ratio - 1 == tar_levels) { | |
1277 | max_pstate = tar_levels; | |
1278 | pr_debug("max_pstate=TAC %x\n", max_pstate); | |
6a35fc2d SP |
1279 | } |
1280 | } | |
845c1cbe | 1281 | |
6a35fc2d | 1282 | return max_pstate; |
93f0822d DB |
1283 | } |
1284 | ||
016c8150 | 1285 | static int core_get_turbo_pstate(void) |
93f0822d DB |
1286 | { |
1287 | u64 value; | |
1288 | int nont, ret; | |
845c1cbe | 1289 | |
100cf6f2 | 1290 | rdmsrl(MSR_TURBO_RATIO_LIMIT, value); |
016c8150 | 1291 | nont = core_get_max_pstate(); |
285cb990 | 1292 | ret = (value) & 255; |
93f0822d DB |
1293 | if (ret <= nont) |
1294 | ret = nont; | |
1295 | return ret; | |
1296 | } | |
1297 | ||
b27580b0 DB |
1298 | static inline int core_get_scaling(void) |
1299 | { | |
1300 | return 100000; | |
1301 | } | |
1302 | ||
fdfdb2b1 | 1303 | static u64 core_get_val(struct cpudata *cpudata, int pstate) |
016c8150 DB |
1304 | { |
1305 | u64 val; | |
1306 | ||
144c8e17 | 1307 | val = (u64)pstate << 8; |
7de32556 | 1308 | if (global.no_turbo && !global.turbo_disabled) |
016c8150 DB |
1309 | val |= (u64)1 << 32; |
1310 | ||
fdfdb2b1 | 1311 | return val; |
016c8150 DB |
1312 | } |
1313 | ||
6e34e1f2 SP |
1314 | static int knl_get_aperf_mperf_shift(void) |
1315 | { | |
1316 | return 10; | |
1317 | } | |
1318 | ||
b34ef932 DC |
1319 | static int knl_get_turbo_pstate(void) |
1320 | { | |
1321 | u64 value; | |
1322 | int nont, ret; | |
1323 | ||
100cf6f2 | 1324 | rdmsrl(MSR_TURBO_RATIO_LIMIT, value); |
b34ef932 DC |
1325 | nont = core_get_max_pstate(); |
1326 | ret = (((value) >> 8) & 0xFF); | |
1327 | if (ret <= nont) | |
1328 | ret = nont; | |
1329 | return ret; | |
1330 | } | |
1331 | ||
b02aabe8 | 1332 | static int intel_pstate_get_base_pstate(struct cpudata *cpu) |
93f0822d | 1333 | { |
b02aabe8 RW |
1334 | return global.no_turbo || global.turbo_disabled ? |
1335 | cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; | |
93f0822d DB |
1336 | } |
1337 | ||
a6c6ead1 | 1338 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) |
fdfdb2b1 | 1339 | { |
bc95a454 RW |
1340 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
1341 | cpu->pstate.current_pstate = pstate; | |
fdfdb2b1 RW |
1342 | /* |
1343 | * Generally, there is no guarantee that this code will always run on | |
1344 | * the CPU being updated, so force the register update to run on the | |
1345 | * right CPU. | |
1346 | */ | |
1347 | wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, | |
1348 | pstate_funcs.get_val(cpu, pstate)); | |
93f0822d DB |
1349 | } |
1350 | ||
a6c6ead1 RW |
1351 | static void intel_pstate_set_min_pstate(struct cpudata *cpu) |
1352 | { | |
1353 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); | |
1354 | } | |
1355 | ||
1356 | static void intel_pstate_max_within_limits(struct cpudata *cpu) | |
1357 | { | |
b02aabe8 | 1358 | int pstate; |
a6c6ead1 RW |
1359 | |
1360 | update_turbo_state(); | |
b02aabe8 | 1361 | pstate = intel_pstate_get_base_pstate(cpu); |
1a4fe38a | 1362 | pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); |
b02aabe8 | 1363 | intel_pstate_set_pstate(cpu, pstate); |
a6c6ead1 RW |
1364 | } |
1365 | ||
93f0822d DB |
1366 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) |
1367 | { | |
016c8150 DB |
1368 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
1369 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
3bcc6fa9 | 1370 | cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); |
016c8150 | 1371 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); |
b27580b0 | 1372 | cpu->pstate.scaling = pstate_funcs.get_scaling(); |
001c76f0 RW |
1373 | cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling; |
1374 | cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d | 1375 | |
6e34e1f2 SP |
1376 | if (pstate_funcs.get_aperf_mperf_shift) |
1377 | cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); | |
1378 | ||
007bea09 DB |
1379 | if (pstate_funcs.get_vid) |
1380 | pstate_funcs.get_vid(cpu); | |
fdfdb2b1 RW |
1381 | |
1382 | intel_pstate_set_min_pstate(cpu); | |
93f0822d DB |
1383 | } |
1384 | ||
a1c9787d | 1385 | static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) |
93f0822d | 1386 | { |
6b17ddb2 | 1387 | struct sample *sample = &cpu->sample; |
e66c1768 | 1388 | |
a1c9787d | 1389 | sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); |
93f0822d DB |
1390 | } |
1391 | ||
4fec7ad5 | 1392 | static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) |
93f0822d | 1393 | { |
93f0822d | 1394 | u64 aperf, mperf; |
4ab60c3f | 1395 | unsigned long flags; |
4055fad3 | 1396 | u64 tsc; |
93f0822d | 1397 | |
4ab60c3f | 1398 | local_irq_save(flags); |
93f0822d DB |
1399 | rdmsrl(MSR_IA32_APERF, aperf); |
1400 | rdmsrl(MSR_IA32_MPERF, mperf); | |
e70eed2b | 1401 | tsc = rdtsc(); |
4fec7ad5 | 1402 | if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { |
8e601a9f | 1403 | local_irq_restore(flags); |
4fec7ad5 | 1404 | return false; |
8e601a9f | 1405 | } |
4ab60c3f | 1406 | local_irq_restore(flags); |
b69880f9 | 1407 | |
c4ee841f | 1408 | cpu->last_sample_time = cpu->sample.time; |
a4675fbc | 1409 | cpu->sample.time = time; |
d37e2b76 DB |
1410 | cpu->sample.aperf = aperf; |
1411 | cpu->sample.mperf = mperf; | |
4055fad3 | 1412 | cpu->sample.tsc = tsc; |
d37e2b76 DB |
1413 | cpu->sample.aperf -= cpu->prev_aperf; |
1414 | cpu->sample.mperf -= cpu->prev_mperf; | |
4055fad3 | 1415 | cpu->sample.tsc -= cpu->prev_tsc; |
1abc4b20 | 1416 | |
93f0822d DB |
1417 | cpu->prev_aperf = aperf; |
1418 | cpu->prev_mperf = mperf; | |
4055fad3 | 1419 | cpu->prev_tsc = tsc; |
febce40f RW |
1420 | /* |
1421 | * First time this function is invoked in a given cycle, all of the | |
1422 | * previous sample data fields are equal to zero or stale and they must | |
1423 | * be populated with meaningful numbers for things to work, so assume | |
1424 | * that sample.time will always be reset before setting the utilization | |
1425 | * update hook and make the caller skip the sample then. | |
1426 | */ | |
eabd22c6 RW |
1427 | if (cpu->last_sample_time) { |
1428 | intel_pstate_calc_avg_perf(cpu); | |
1429 | return true; | |
1430 | } | |
1431 | return false; | |
93f0822d DB |
1432 | } |
1433 | ||
8fa520af PL |
1434 | static inline int32_t get_avg_frequency(struct cpudata *cpu) |
1435 | { | |
c587c79f | 1436 | return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); |
8fa520af PL |
1437 | } |
1438 | ||
bdcaa23f PL |
1439 | static inline int32_t get_avg_pstate(struct cpudata *cpu) |
1440 | { | |
8edb0a6e RW |
1441 | return mul_ext_fp(cpu->pstate.max_pstate_physical, |
1442 | cpu->sample.core_avg_perf); | |
bdcaa23f PL |
1443 | } |
1444 | ||
d77d4888 | 1445 | static inline int32_t get_target_pstate(struct cpudata *cpu) |
e70eed2b PL |
1446 | { |
1447 | struct sample *sample = &cpu->sample; | |
09c448d3 | 1448 | int32_t busy_frac, boost; |
0843e83c | 1449 | int target, avg_pstate; |
e70eed2b | 1450 | |
6e34e1f2 SP |
1451 | busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, |
1452 | sample->tsc); | |
63d1d656 | 1453 | |
09c448d3 RW |
1454 | boost = cpu->iowait_boost; |
1455 | cpu->iowait_boost >>= 1; | |
63d1d656 | 1456 | |
09c448d3 RW |
1457 | if (busy_frac < boost) |
1458 | busy_frac = boost; | |
63d1d656 | 1459 | |
09c448d3 | 1460 | sample->busy_scaled = busy_frac * 100; |
0843e83c | 1461 | |
7de32556 | 1462 | target = global.no_turbo || global.turbo_disabled ? |
0843e83c RW |
1463 | cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; |
1464 | target += target >> 2; | |
1465 | target = mul_fp(target, busy_frac); | |
1466 | if (target < cpu->pstate.min_pstate) | |
1467 | target = cpu->pstate.min_pstate; | |
1468 | ||
1469 | /* | |
1470 | * If the average P-state during the previous cycle was higher than the | |
1471 | * current target, add 50% of the difference to the target to reduce | |
1472 | * possible performance oscillations and offset possible performance | |
1473 | * loss related to moving the workload from one CPU to another within | |
1474 | * a package/module. | |
1475 | */ | |
1476 | avg_pstate = get_avg_pstate(cpu); | |
1477 | if (avg_pstate > target) | |
1478 | target += (avg_pstate - target) >> 1; | |
1479 | ||
1480 | return target; | |
e70eed2b PL |
1481 | } |
1482 | ||
001c76f0 | 1483 | static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) |
fdfdb2b1 | 1484 | { |
b02aabe8 RW |
1485 | int max_pstate = intel_pstate_get_base_pstate(cpu); |
1486 | int min_pstate; | |
fdfdb2b1 | 1487 | |
1a4fe38a SP |
1488 | min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); |
1489 | max_pstate = max(min_pstate, cpu->max_perf_ratio); | |
b02aabe8 | 1490 | return clamp_t(int, pstate, min_pstate, max_pstate); |
001c76f0 RW |
1491 | } |
1492 | ||
1493 | static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) | |
1494 | { | |
fdfdb2b1 RW |
1495 | if (pstate == cpu->pstate.current_pstate) |
1496 | return; | |
1497 | ||
bc95a454 | 1498 | cpu->pstate.current_pstate = pstate; |
fdfdb2b1 RW |
1499 | wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); |
1500 | } | |
1501 | ||
a891283e | 1502 | static void intel_pstate_adjust_pstate(struct cpudata *cpu) |
93f0822d | 1503 | { |
67dd9bf4 | 1504 | int from = cpu->pstate.current_pstate; |
4055fad3 | 1505 | struct sample *sample; |
a891283e | 1506 | int target_pstate; |
4055fad3 | 1507 | |
001c76f0 RW |
1508 | update_turbo_state(); |
1509 | ||
d77d4888 | 1510 | target_pstate = get_target_pstate(cpu); |
64078299 RW |
1511 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); |
1512 | trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); | |
fdfdb2b1 | 1513 | intel_pstate_update_pstate(cpu, target_pstate); |
4055fad3 DS |
1514 | |
1515 | sample = &cpu->sample; | |
a1c9787d | 1516 | trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), |
157386b6 | 1517 | fp_toint(sample->busy_scaled), |
4055fad3 DS |
1518 | from, |
1519 | cpu->pstate.current_pstate, | |
1520 | sample->mperf, | |
1521 | sample->aperf, | |
1522 | sample->tsc, | |
3ba7bcaa SP |
1523 | get_avg_frequency(cpu), |
1524 | fp_toint(cpu->iowait_boost * 100)); | |
93f0822d DB |
1525 | } |
1526 | ||
a4675fbc | 1527 | static void intel_pstate_update_util(struct update_util_data *data, u64 time, |
58919e83 | 1528 | unsigned int flags) |
93f0822d | 1529 | { |
a4675fbc | 1530 | struct cpudata *cpu = container_of(data, struct cpudata, update_util); |
09c448d3 RW |
1531 | u64 delta_ns; |
1532 | ||
674e7541 VK |
1533 | /* Don't allow remote callbacks */ |
1534 | if (smp_processor_id() != cpu->cpu) | |
1535 | return; | |
1536 | ||
eabd22c6 RW |
1537 | if (flags & SCHED_CPUFREQ_IOWAIT) { |
1538 | cpu->iowait_boost = int_tofp(1); | |
7bde2d50 SP |
1539 | cpu->last_update = time; |
1540 | /* | |
1541 | * The last time the busy was 100% so P-state was max anyway | |
1542 | * so avoid overhead of computation. | |
1543 | */ | |
1544 | if (fp_toint(cpu->sample.busy_scaled) == 100) | |
1545 | return; | |
1546 | ||
1547 | goto set_pstate; | |
eabd22c6 RW |
1548 | } else if (cpu->iowait_boost) { |
1549 | /* Clear iowait_boost if the CPU may have been idle. */ | |
1550 | delta_ns = time - cpu->last_update; | |
1551 | if (delta_ns > TICK_NSEC) | |
1552 | cpu->iowait_boost = 0; | |
09c448d3 | 1553 | } |
eabd22c6 | 1554 | cpu->last_update = time; |
09c448d3 | 1555 | delta_ns = time - cpu->sample.time; |
d77d4888 | 1556 | if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) |
eabd22c6 | 1557 | return; |
4fec7ad5 | 1558 | |
7bde2d50 | 1559 | set_pstate: |
a891283e RW |
1560 | if (intel_pstate_sample(cpu, time)) |
1561 | intel_pstate_adjust_pstate(cpu); | |
67dd9bf4 | 1562 | } |
eabd22c6 | 1563 | |
2f49afc2 RW |
1564 | static struct pstate_funcs core_funcs = { |
1565 | .get_max = core_get_max_pstate, | |
1566 | .get_max_physical = core_get_max_pstate_physical, | |
1567 | .get_min = core_get_min_pstate, | |
1568 | .get_turbo = core_get_turbo_pstate, | |
1569 | .get_scaling = core_get_scaling, | |
1570 | .get_val = core_get_val, | |
de4a76cb RW |
1571 | }; |
1572 | ||
2f49afc2 RW |
1573 | static const struct pstate_funcs silvermont_funcs = { |
1574 | .get_max = atom_get_max_pstate, | |
1575 | .get_max_physical = atom_get_max_pstate, | |
1576 | .get_min = atom_get_min_pstate, | |
1577 | .get_turbo = atom_get_turbo_pstate, | |
1578 | .get_val = atom_get_val, | |
1579 | .get_scaling = silvermont_get_scaling, | |
1580 | .get_vid = atom_get_vid, | |
de4a76cb RW |
1581 | }; |
1582 | ||
2f49afc2 RW |
1583 | static const struct pstate_funcs airmont_funcs = { |
1584 | .get_max = atom_get_max_pstate, | |
1585 | .get_max_physical = atom_get_max_pstate, | |
1586 | .get_min = atom_get_min_pstate, | |
1587 | .get_turbo = atom_get_turbo_pstate, | |
1588 | .get_val = atom_get_val, | |
1589 | .get_scaling = airmont_get_scaling, | |
1590 | .get_vid = atom_get_vid, | |
de4a76cb RW |
1591 | }; |
1592 | ||
2f49afc2 RW |
1593 | static const struct pstate_funcs knl_funcs = { |
1594 | .get_max = core_get_max_pstate, | |
1595 | .get_max_physical = core_get_max_pstate_physical, | |
1596 | .get_min = core_get_min_pstate, | |
1597 | .get_turbo = knl_get_turbo_pstate, | |
6e34e1f2 | 1598 | .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, |
2f49afc2 RW |
1599 | .get_scaling = core_get_scaling, |
1600 | .get_val = core_get_val, | |
de4a76cb RW |
1601 | }; |
1602 | ||
2f49afc2 RW |
1603 | static const struct pstate_funcs bxt_funcs = { |
1604 | .get_max = core_get_max_pstate, | |
1605 | .get_max_physical = core_get_max_pstate_physical, | |
1606 | .get_min = core_get_min_pstate, | |
1607 | .get_turbo = core_get_turbo_pstate, | |
1608 | .get_scaling = core_get_scaling, | |
1609 | .get_val = core_get_val, | |
de4a76cb RW |
1610 | }; |
1611 | ||
93f0822d | 1612 | #define ICPU(model, policy) \ |
6cbd7ee1 DB |
1613 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
1614 | (unsigned long)&policy } | |
93f0822d DB |
1615 | |
1616 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
2f49afc2 RW |
1617 | ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs), |
1618 | ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs), | |
1619 | ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_funcs), | |
1620 | ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs), | |
1621 | ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs), | |
1622 | ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs), | |
1623 | ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs), | |
1624 | ICPU(INTEL_FAM6_HASWELL_X, core_funcs), | |
1625 | ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs), | |
1626 | ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs), | |
1627 | ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs), | |
1628 | ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs), | |
1629 | ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs), | |
1630 | ICPU(INTEL_FAM6_BROADWELL_X, core_funcs), | |
1631 | ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs), | |
1632 | ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs), | |
1633 | ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs), | |
1634 | ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs), | |
1635 | ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_funcs), | |
630e5757 | 1636 | ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE, bxt_funcs), |
93f0822d DB |
1637 | {} |
1638 | }; | |
1639 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
1640 | ||
29327c84 | 1641 | static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { |
2f49afc2 RW |
1642 | ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs), |
1643 | ICPU(INTEL_FAM6_BROADWELL_X, core_funcs), | |
1644 | ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs), | |
2f86dc4c DB |
1645 | {} |
1646 | }; | |
1647 | ||
6e978b22 | 1648 | static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { |
2f49afc2 | 1649 | ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs), |
6e978b22 SP |
1650 | {} |
1651 | }; | |
1652 | ||
93f0822d DB |
1653 | static int intel_pstate_init_cpu(unsigned int cpunum) |
1654 | { | |
93f0822d DB |
1655 | struct cpudata *cpu; |
1656 | ||
eae48f04 SP |
1657 | cpu = all_cpu_data[cpunum]; |
1658 | ||
1659 | if (!cpu) { | |
c5a2ee7d | 1660 | cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); |
eae48f04 SP |
1661 | if (!cpu) |
1662 | return -ENOMEM; | |
1663 | ||
1664 | all_cpu_data[cpunum] = cpu; | |
eae48f04 | 1665 | |
984edbdc SP |
1666 | cpu->epp_default = -EINVAL; |
1667 | cpu->epp_powersave = -EINVAL; | |
1668 | cpu->epp_saved = -EINVAL; | |
eae48f04 | 1669 | } |
93f0822d DB |
1670 | |
1671 | cpu = all_cpu_data[cpunum]; | |
1672 | ||
93f0822d | 1673 | cpu->cpu = cpunum; |
ba88d433 | 1674 | |
a4675fbc | 1675 | if (hwp_active) { |
6e978b22 SP |
1676 | const struct x86_cpu_id *id; |
1677 | ||
1678 | id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); | |
1679 | if (id) | |
1680 | intel_pstate_disable_ee(cpunum); | |
1681 | ||
ba88d433 | 1682 | intel_pstate_hwp_enable(cpu); |
a4675fbc | 1683 | } |
ba88d433 | 1684 | |
179e8471 | 1685 | intel_pstate_get_cpu_pstates(cpu); |
016c8150 | 1686 | |
4836df17 | 1687 | pr_debug("controlling: cpu %d\n", cpunum); |
93f0822d DB |
1688 | |
1689 | return 0; | |
1690 | } | |
1691 | ||
febce40f | 1692 | static void intel_pstate_set_update_util_hook(unsigned int cpu_num) |
bb6ab52f | 1693 | { |
febce40f RW |
1694 | struct cpudata *cpu = all_cpu_data[cpu_num]; |
1695 | ||
62611cb9 LB |
1696 | if (hwp_active) |
1697 | return; | |
1698 | ||
5ab666e0 RW |
1699 | if (cpu->update_util_set) |
1700 | return; | |
1701 | ||
febce40f RW |
1702 | /* Prevent intel_pstate_update_util() from using stale data. */ |
1703 | cpu->sample.time = 0; | |
67dd9bf4 | 1704 | cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, |
c4f3f70c | 1705 | intel_pstate_update_util); |
4578ee7e | 1706 | cpu->update_util_set = true; |
bb6ab52f RW |
1707 | } |
1708 | ||
1709 | static void intel_pstate_clear_update_util_hook(unsigned int cpu) | |
1710 | { | |
4578ee7e CY |
1711 | struct cpudata *cpu_data = all_cpu_data[cpu]; |
1712 | ||
1713 | if (!cpu_data->update_util_set) | |
1714 | return; | |
1715 | ||
0bed612b | 1716 | cpufreq_remove_update_util_hook(cpu); |
4578ee7e | 1717 | cpu_data->update_util_set = false; |
bb6ab52f RW |
1718 | synchronize_sched(); |
1719 | } | |
1720 | ||
80b120ca RW |
1721 | static int intel_pstate_get_max_freq(struct cpudata *cpu) |
1722 | { | |
1723 | return global.turbo_disabled || global.no_turbo ? | |
1724 | cpu->pstate.max_freq : cpu->pstate.turbo_freq; | |
1725 | } | |
1726 | ||
eae48f04 | 1727 | static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy, |
c5a2ee7d | 1728 | struct cpudata *cpu) |
eae48f04 | 1729 | { |
80b120ca | 1730 | int max_freq = intel_pstate_get_max_freq(cpu); |
e4c204ce | 1731 | int32_t max_policy_perf, min_policy_perf; |
1a4fe38a | 1732 | int max_state, turbo_max; |
a410c03d | 1733 | |
1a4fe38a SP |
1734 | /* |
1735 | * HWP needs some special consideration, because on BDX the | |
1736 | * HWP_REQUEST uses abstract value to represent performance | |
1737 | * rather than pure ratios. | |
1738 | */ | |
1739 | if (hwp_active) { | |
1740 | intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state); | |
1741 | } else { | |
1742 | max_state = intel_pstate_get_base_pstate(cpu); | |
1743 | turbo_max = cpu->pstate.turbo_pstate; | |
1744 | } | |
1745 | ||
1746 | max_policy_perf = max_state * policy->max / max_freq; | |
5879f877 | 1747 | if (policy->max == policy->min) { |
e4c204ce | 1748 | min_policy_perf = max_policy_perf; |
5879f877 | 1749 | } else { |
1a4fe38a | 1750 | min_policy_perf = max_state * policy->min / max_freq; |
e4c204ce RW |
1751 | min_policy_perf = clamp_t(int32_t, min_policy_perf, |
1752 | 0, max_policy_perf); | |
5879f877 | 1753 | } |
eae48f04 | 1754 | |
1a4fe38a SP |
1755 | pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n", |
1756 | policy->cpu, max_state, | |
1757 | min_policy_perf, max_policy_perf); | |
1758 | ||
e4c204ce | 1759 | /* Normalize user input to [min_perf, max_perf] */ |
c5a2ee7d | 1760 | if (per_cpu_limits) { |
1a4fe38a SP |
1761 | cpu->min_perf_ratio = min_policy_perf; |
1762 | cpu->max_perf_ratio = max_policy_perf; | |
c5a2ee7d RW |
1763 | } else { |
1764 | int32_t global_min, global_max; | |
1765 | ||
1766 | /* Global limits are in percent of the maximum turbo P-state. */ | |
1a4fe38a SP |
1767 | global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); |
1768 | global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); | |
c5a2ee7d | 1769 | global_min = clamp_t(int32_t, global_min, 0, global_max); |
eae48f04 | 1770 | |
1a4fe38a SP |
1771 | pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu, |
1772 | global_min, global_max); | |
c5a2ee7d | 1773 | |
1a4fe38a SP |
1774 | cpu->min_perf_ratio = max(min_policy_perf, global_min); |
1775 | cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); | |
1776 | cpu->max_perf_ratio = min(max_policy_perf, global_max); | |
1777 | cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); | |
eae48f04 | 1778 | |
1a4fe38a SP |
1779 | /* Make sure min_perf <= max_perf */ |
1780 | cpu->min_perf_ratio = min(cpu->min_perf_ratio, | |
1781 | cpu->max_perf_ratio); | |
eae48f04 | 1782 | |
1a4fe38a SP |
1783 | } |
1784 | pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu, | |
1785 | cpu->max_perf_ratio, | |
1786 | cpu->min_perf_ratio); | |
eae48f04 SP |
1787 | } |
1788 | ||
93f0822d DB |
1789 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) |
1790 | { | |
3be9200d SP |
1791 | struct cpudata *cpu; |
1792 | ||
d3929b83 DB |
1793 | if (!policy->cpuinfo.max_freq) |
1794 | return -ENODEV; | |
1795 | ||
2c2c1af4 SP |
1796 | pr_debug("set_policy cpuinfo.max %u policy->max %u\n", |
1797 | policy->cpuinfo.max_freq, policy->max); | |
1798 | ||
a6c6ead1 | 1799 | cpu = all_cpu_data[policy->cpu]; |
2f1d407a RW |
1800 | cpu->policy = policy->policy; |
1801 | ||
b59fe540 SP |
1802 | mutex_lock(&intel_pstate_limits_lock); |
1803 | ||
c5a2ee7d | 1804 | intel_pstate_update_perf_limits(policy, cpu); |
a240c4aa | 1805 | |
2f1d407a | 1806 | if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { |
a6c6ead1 RW |
1807 | /* |
1808 | * NOHZ_FULL CPUs need this as the governor callback may not | |
1809 | * be invoked on them. | |
1810 | */ | |
1811 | intel_pstate_clear_update_util_hook(policy->cpu); | |
1812 | intel_pstate_max_within_limits(cpu); | |
82b4e03e LB |
1813 | } else { |
1814 | intel_pstate_set_update_util_hook(policy->cpu); | |
a6c6ead1 RW |
1815 | } |
1816 | ||
5f98ced1 | 1817 | if (hwp_active) |
2bfc4cbb | 1818 | intel_pstate_hwp_set(policy->cpu); |
2f86dc4c | 1819 | |
b59fe540 SP |
1820 | mutex_unlock(&intel_pstate_limits_lock); |
1821 | ||
93f0822d DB |
1822 | return 0; |
1823 | } | |
1824 | ||
80b120ca RW |
1825 | static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy, |
1826 | struct cpudata *cpu) | |
1827 | { | |
1828 | if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && | |
1829 | policy->max < policy->cpuinfo.max_freq && | |
1830 | policy->max > cpu->pstate.max_freq) { | |
1831 | pr_debug("policy->max > max non turbo frequency\n"); | |
1832 | policy->max = policy->cpuinfo.max_freq; | |
1833 | } | |
1834 | } | |
1835 | ||
93f0822d DB |
1836 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) |
1837 | { | |
7d9a8a9f | 1838 | struct cpudata *cpu = all_cpu_data[policy->cpu]; |
7d9a8a9f SP |
1839 | |
1840 | update_turbo_state(); | |
80b120ca RW |
1841 | cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, |
1842 | intel_pstate_get_max_freq(cpu)); | |
93f0822d | 1843 | |
285cb990 | 1844 | if (policy->policy != CPUFREQ_POLICY_POWERSAVE && |
c410833a | 1845 | policy->policy != CPUFREQ_POLICY_PERFORMANCE) |
93f0822d DB |
1846 | return -EINVAL; |
1847 | ||
80b120ca RW |
1848 | intel_pstate_adjust_policy_max(policy, cpu); |
1849 | ||
93f0822d DB |
1850 | return 0; |
1851 | } | |
1852 | ||
001c76f0 RW |
1853 | static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy) |
1854 | { | |
1855 | intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]); | |
1856 | } | |
1857 | ||
bb18008f | 1858 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 1859 | { |
001c76f0 | 1860 | pr_debug("CPU %d exiting\n", policy->cpu); |
93f0822d | 1861 | |
001c76f0 | 1862 | intel_pstate_clear_update_util_hook(policy->cpu); |
984edbdc SP |
1863 | if (hwp_active) |
1864 | intel_pstate_hwp_save_state(policy); | |
1865 | else | |
001c76f0 RW |
1866 | intel_cpufreq_stop_cpu(policy); |
1867 | } | |
bb18008f | 1868 | |
001c76f0 RW |
1869 | static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) |
1870 | { | |
1871 | intel_pstate_exit_perf_limits(policy); | |
a4675fbc | 1872 | |
001c76f0 | 1873 | policy->fast_switch_possible = false; |
2f86dc4c | 1874 | |
001c76f0 | 1875 | return 0; |
93f0822d DB |
1876 | } |
1877 | ||
001c76f0 | 1878 | static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 1879 | { |
93f0822d | 1880 | struct cpudata *cpu; |
52e0a509 | 1881 | int rc; |
93f0822d DB |
1882 | |
1883 | rc = intel_pstate_init_cpu(policy->cpu); | |
1884 | if (rc) | |
1885 | return rc; | |
1886 | ||
1887 | cpu = all_cpu_data[policy->cpu]; | |
1888 | ||
1a4fe38a SP |
1889 | cpu->max_perf_ratio = 0xFF; |
1890 | cpu->min_perf_ratio = 0; | |
93f0822d | 1891 | |
b27580b0 DB |
1892 | policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1893 | policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1894 | |
1895 | /* cpuinfo and default policy values */ | |
b27580b0 | 1896 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; |
983e600e | 1897 | update_turbo_state(); |
7de32556 | 1898 | policy->cpuinfo.max_freq = global.turbo_disabled ? |
983e600e SP |
1899 | cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; |
1900 | policy->cpuinfo.max_freq *= cpu->pstate.scaling; | |
1901 | ||
9522a2ff | 1902 | intel_pstate_init_acpi_perf_limits(policy); |
93f0822d | 1903 | |
001c76f0 RW |
1904 | policy->fast_switch_possible = true; |
1905 | ||
93f0822d DB |
1906 | return 0; |
1907 | } | |
1908 | ||
001c76f0 | 1909 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
9522a2ff | 1910 | { |
001c76f0 RW |
1911 | int ret = __intel_pstate_cpu_init(policy); |
1912 | ||
1913 | if (ret) | |
1914 | return ret; | |
1915 | ||
7de32556 | 1916 | if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE)) |
001c76f0 RW |
1917 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; |
1918 | else | |
1919 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
9522a2ff SP |
1920 | |
1921 | return 0; | |
1922 | } | |
1923 | ||
001c76f0 | 1924 | static struct cpufreq_driver intel_pstate = { |
93f0822d DB |
1925 | .flags = CPUFREQ_CONST_LOOPS, |
1926 | .verify = intel_pstate_verify_policy, | |
1927 | .setpolicy = intel_pstate_set_policy, | |
984edbdc | 1928 | .suspend = intel_pstate_hwp_save_state, |
8442885f | 1929 | .resume = intel_pstate_resume, |
93f0822d | 1930 | .init = intel_pstate_cpu_init, |
9522a2ff | 1931 | .exit = intel_pstate_cpu_exit, |
bb18008f | 1932 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 1933 | .name = "intel_pstate", |
93f0822d DB |
1934 | }; |
1935 | ||
001c76f0 RW |
1936 | static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy) |
1937 | { | |
1938 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
001c76f0 RW |
1939 | |
1940 | update_turbo_state(); | |
80b120ca RW |
1941 | cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, |
1942 | intel_pstate_get_max_freq(cpu)); | |
001c76f0 | 1943 | |
80b120ca | 1944 | intel_pstate_adjust_policy_max(policy, cpu); |
001c76f0 | 1945 | |
c5a2ee7d RW |
1946 | intel_pstate_update_perf_limits(policy, cpu); |
1947 | ||
001c76f0 RW |
1948 | return 0; |
1949 | } | |
1950 | ||
001c76f0 RW |
1951 | static int intel_cpufreq_target(struct cpufreq_policy *policy, |
1952 | unsigned int target_freq, | |
1953 | unsigned int relation) | |
1954 | { | |
1955 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
1956 | struct cpufreq_freqs freqs; | |
1957 | int target_pstate; | |
1958 | ||
64897b20 RW |
1959 | update_turbo_state(); |
1960 | ||
001c76f0 | 1961 | freqs.old = policy->cur; |
64897b20 | 1962 | freqs.new = target_freq; |
001c76f0 RW |
1963 | |
1964 | cpufreq_freq_transition_begin(policy, &freqs); | |
1965 | switch (relation) { | |
1966 | case CPUFREQ_RELATION_L: | |
1967 | target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); | |
1968 | break; | |
1969 | case CPUFREQ_RELATION_H: | |
1970 | target_pstate = freqs.new / cpu->pstate.scaling; | |
1971 | break; | |
1972 | default: | |
1973 | target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); | |
1974 | break; | |
1975 | } | |
1976 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); | |
1977 | if (target_pstate != cpu->pstate.current_pstate) { | |
1978 | cpu->pstate.current_pstate = target_pstate; | |
1979 | wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL, | |
1980 | pstate_funcs.get_val(cpu, target_pstate)); | |
1981 | } | |
64078299 | 1982 | freqs.new = target_pstate * cpu->pstate.scaling; |
001c76f0 RW |
1983 | cpufreq_freq_transition_end(policy, &freqs, false); |
1984 | ||
1985 | return 0; | |
1986 | } | |
1987 | ||
1988 | static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, | |
1989 | unsigned int target_freq) | |
1990 | { | |
1991 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
1992 | int target_pstate; | |
1993 | ||
64897b20 RW |
1994 | update_turbo_state(); |
1995 | ||
001c76f0 | 1996 | target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); |
64078299 | 1997 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); |
001c76f0 | 1998 | intel_pstate_update_pstate(cpu, target_pstate); |
64078299 | 1999 | return target_pstate * cpu->pstate.scaling; |
001c76f0 RW |
2000 | } |
2001 | ||
2002 | static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) | |
2003 | { | |
2004 | int ret = __intel_pstate_cpu_init(policy); | |
2005 | ||
2006 | if (ret) | |
2007 | return ret; | |
2008 | ||
2009 | policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; | |
1b72e7fd | 2010 | policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; |
001c76f0 RW |
2011 | /* This reflects the intel_pstate_get_cpu_pstates() setting. */ |
2012 | policy->cur = policy->cpuinfo.min_freq; | |
2013 | ||
2014 | return 0; | |
2015 | } | |
2016 | ||
2017 | static struct cpufreq_driver intel_cpufreq = { | |
2018 | .flags = CPUFREQ_CONST_LOOPS, | |
2019 | .verify = intel_cpufreq_verify_policy, | |
2020 | .target = intel_cpufreq_target, | |
2021 | .fast_switch = intel_cpufreq_fast_switch, | |
2022 | .init = intel_cpufreq_cpu_init, | |
2023 | .exit = intel_pstate_cpu_exit, | |
2024 | .stop_cpu = intel_cpufreq_stop_cpu, | |
2025 | .name = "intel_cpufreq", | |
2026 | }; | |
2027 | ||
ee8df89a | 2028 | static struct cpufreq_driver *default_driver = &intel_pstate; |
001c76f0 | 2029 | |
fb1fe104 RW |
2030 | static void intel_pstate_driver_cleanup(void) |
2031 | { | |
2032 | unsigned int cpu; | |
2033 | ||
2034 | get_online_cpus(); | |
2035 | for_each_online_cpu(cpu) { | |
2036 | if (all_cpu_data[cpu]) { | |
2037 | if (intel_pstate_driver == &intel_pstate) | |
2038 | intel_pstate_clear_update_util_hook(cpu); | |
2039 | ||
2040 | kfree(all_cpu_data[cpu]); | |
2041 | all_cpu_data[cpu] = NULL; | |
2042 | } | |
2043 | } | |
2044 | put_online_cpus(); | |
ee8df89a | 2045 | intel_pstate_driver = NULL; |
fb1fe104 RW |
2046 | } |
2047 | ||
ee8df89a | 2048 | static int intel_pstate_register_driver(struct cpufreq_driver *driver) |
fb1fe104 RW |
2049 | { |
2050 | int ret; | |
2051 | ||
c5a2ee7d RW |
2052 | memset(&global, 0, sizeof(global)); |
2053 | global.max_perf_pct = 100; | |
c3a49c89 | 2054 | |
ee8df89a | 2055 | intel_pstate_driver = driver; |
fb1fe104 RW |
2056 | ret = cpufreq_register_driver(intel_pstate_driver); |
2057 | if (ret) { | |
2058 | intel_pstate_driver_cleanup(); | |
2059 | return ret; | |
2060 | } | |
2061 | ||
c5a2ee7d RW |
2062 | global.min_perf_pct = min_perf_pct_min(); |
2063 | ||
fb1fe104 RW |
2064 | return 0; |
2065 | } | |
2066 | ||
2067 | static int intel_pstate_unregister_driver(void) | |
2068 | { | |
2069 | if (hwp_active) | |
2070 | return -EBUSY; | |
2071 | ||
fb1fe104 RW |
2072 | cpufreq_unregister_driver(intel_pstate_driver); |
2073 | intel_pstate_driver_cleanup(); | |
2074 | ||
2075 | return 0; | |
2076 | } | |
2077 | ||
2078 | static ssize_t intel_pstate_show_status(char *buf) | |
2079 | { | |
ee8df89a | 2080 | if (!intel_pstate_driver) |
fb1fe104 RW |
2081 | return sprintf(buf, "off\n"); |
2082 | ||
2083 | return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? | |
2084 | "active" : "passive"); | |
2085 | } | |
2086 | ||
2087 | static int intel_pstate_update_status(const char *buf, size_t size) | |
2088 | { | |
2089 | int ret; | |
2090 | ||
2091 | if (size == 3 && !strncmp(buf, "off", size)) | |
ee8df89a | 2092 | return intel_pstate_driver ? |
fb1fe104 RW |
2093 | intel_pstate_unregister_driver() : -EINVAL; |
2094 | ||
2095 | if (size == 6 && !strncmp(buf, "active", size)) { | |
ee8df89a | 2096 | if (intel_pstate_driver) { |
fb1fe104 RW |
2097 | if (intel_pstate_driver == &intel_pstate) |
2098 | return 0; | |
2099 | ||
2100 | ret = intel_pstate_unregister_driver(); | |
2101 | if (ret) | |
2102 | return ret; | |
2103 | } | |
2104 | ||
ee8df89a | 2105 | return intel_pstate_register_driver(&intel_pstate); |
fb1fe104 RW |
2106 | } |
2107 | ||
2108 | if (size == 7 && !strncmp(buf, "passive", size)) { | |
ee8df89a | 2109 | if (intel_pstate_driver) { |
0042b2c0 | 2110 | if (intel_pstate_driver == &intel_cpufreq) |
fb1fe104 RW |
2111 | return 0; |
2112 | ||
2113 | ret = intel_pstate_unregister_driver(); | |
2114 | if (ret) | |
2115 | return ret; | |
2116 | } | |
2117 | ||
ee8df89a | 2118 | return intel_pstate_register_driver(&intel_cpufreq); |
fb1fe104 RW |
2119 | } |
2120 | ||
2121 | return -EINVAL; | |
2122 | } | |
2123 | ||
eed43609 JZ |
2124 | static int no_load __initdata; |
2125 | static int no_hwp __initdata; | |
2126 | static int hwp_only __initdata; | |
29327c84 | 2127 | static unsigned int force_load __initdata; |
6be26498 | 2128 | |
29327c84 | 2129 | static int __init intel_pstate_msrs_not_valid(void) |
b563b4e3 | 2130 | { |
016c8150 | 2131 | if (!pstate_funcs.get_max() || |
c410833a SK |
2132 | !pstate_funcs.get_min() || |
2133 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
2134 | return -ENODEV; |
2135 | ||
b563b4e3 DB |
2136 | return 0; |
2137 | } | |
016c8150 | 2138 | |
29327c84 | 2139 | static void __init copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
2140 | { |
2141 | pstate_funcs.get_max = funcs->get_max; | |
3bcc6fa9 | 2142 | pstate_funcs.get_max_physical = funcs->get_max_physical; |
016c8150 DB |
2143 | pstate_funcs.get_min = funcs->get_min; |
2144 | pstate_funcs.get_turbo = funcs->get_turbo; | |
b27580b0 | 2145 | pstate_funcs.get_scaling = funcs->get_scaling; |
fdfdb2b1 | 2146 | pstate_funcs.get_val = funcs->get_val; |
007bea09 | 2147 | pstate_funcs.get_vid = funcs->get_vid; |
6e34e1f2 | 2148 | pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; |
016c8150 DB |
2149 | } |
2150 | ||
9522a2ff | 2151 | #ifdef CONFIG_ACPI |
fbbcdc07 | 2152 | |
29327c84 | 2153 | static bool __init intel_pstate_no_acpi_pss(void) |
fbbcdc07 AH |
2154 | { |
2155 | int i; | |
2156 | ||
2157 | for_each_possible_cpu(i) { | |
2158 | acpi_status status; | |
2159 | union acpi_object *pss; | |
2160 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
2161 | struct acpi_processor *pr = per_cpu(processors, i); | |
2162 | ||
2163 | if (!pr) | |
2164 | continue; | |
2165 | ||
2166 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
2167 | if (ACPI_FAILURE(status)) | |
2168 | continue; | |
2169 | ||
2170 | pss = buffer.pointer; | |
2171 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
2172 | kfree(pss); | |
2173 | return false; | |
2174 | } | |
2175 | ||
2176 | kfree(pss); | |
2177 | } | |
2178 | ||
2179 | return true; | |
2180 | } | |
2181 | ||
29327c84 | 2182 | static bool __init intel_pstate_has_acpi_ppc(void) |
966916ea | 2183 | { |
2184 | int i; | |
2185 | ||
2186 | for_each_possible_cpu(i) { | |
2187 | struct acpi_processor *pr = per_cpu(processors, i); | |
2188 | ||
2189 | if (!pr) | |
2190 | continue; | |
2191 | if (acpi_has_method(pr->handle, "_PPC")) | |
2192 | return true; | |
2193 | } | |
2194 | return false; | |
2195 | } | |
2196 | ||
2197 | enum { | |
2198 | PSS, | |
2199 | PPC, | |
2200 | }; | |
2201 | ||
fbbcdc07 | 2202 | /* Hardware vendor-specific info that has its own power management modes */ |
5e932321 TK |
2203 | static struct acpi_platform_list plat_info[] __initdata = { |
2204 | {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS}, | |
2205 | {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2206 | {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2207 | {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2208 | {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2209 | {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2210 | {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2211 | {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2212 | {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2213 | {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2214 | {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2215 | {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2216 | {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2217 | {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2218 | {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2219 | { } /* End */ | |
fbbcdc07 AH |
2220 | }; |
2221 | ||
29327c84 | 2222 | static bool __init intel_pstate_platform_pwr_mgmt_exists(void) |
fbbcdc07 | 2223 | { |
2f86dc4c DB |
2224 | const struct x86_cpu_id *id; |
2225 | u64 misc_pwr; | |
5e932321 | 2226 | int idx; |
2f86dc4c DB |
2227 | |
2228 | id = x86_match_cpu(intel_pstate_cpu_oob_ids); | |
2229 | if (id) { | |
2230 | rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); | |
2231 | if ( misc_pwr & (1 << 8)) | |
2232 | return true; | |
2233 | } | |
fbbcdc07 | 2234 | |
5e932321 TK |
2235 | idx = acpi_match_platform_list(plat_info); |
2236 | if (idx < 0) | |
fbbcdc07 AH |
2237 | return false; |
2238 | ||
5e932321 TK |
2239 | switch (plat_info[idx].data) { |
2240 | case PSS: | |
2241 | return intel_pstate_no_acpi_pss(); | |
2242 | case PPC: | |
2243 | return intel_pstate_has_acpi_ppc() && !force_load; | |
fbbcdc07 AH |
2244 | } |
2245 | ||
2246 | return false; | |
2247 | } | |
d0ea59e1 RW |
2248 | |
2249 | static void intel_pstate_request_control_from_smm(void) | |
2250 | { | |
2251 | /* | |
2252 | * It may be unsafe to request P-states control from SMM if _PPC support | |
2253 | * has not been enabled. | |
2254 | */ | |
2255 | if (acpi_ppc) | |
2256 | acpi_processor_pstate_control(); | |
2257 | } | |
fbbcdc07 AH |
2258 | #else /* CONFIG_ACPI not enabled */ |
2259 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
966916ea | 2260 | static inline bool intel_pstate_has_acpi_ppc(void) { return false; } |
d0ea59e1 | 2261 | static inline void intel_pstate_request_control_from_smm(void) {} |
fbbcdc07 AH |
2262 | #endif /* CONFIG_ACPI */ |
2263 | ||
7791e4aa SP |
2264 | static const struct x86_cpu_id hwp_support_ids[] __initconst = { |
2265 | { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP }, | |
2266 | {} | |
2267 | }; | |
2268 | ||
93f0822d DB |
2269 | static int __init intel_pstate_init(void) |
2270 | { | |
eb5139d1 | 2271 | int rc; |
93f0822d | 2272 | |
6be26498 DB |
2273 | if (no_load) |
2274 | return -ENODEV; | |
2275 | ||
eb5139d1 | 2276 | if (x86_match_cpu(hwp_support_ids)) { |
2f49afc2 | 2277 | copy_cpu_funcs(&core_funcs); |
c4f3f70c | 2278 | if (!no_hwp) { |
eb5139d1 RW |
2279 | hwp_active++; |
2280 | intel_pstate.attr = hwp_cpufreq_attrs; | |
2281 | goto hwp_cpu_matched; | |
2282 | } | |
2283 | } else { | |
2284 | const struct x86_cpu_id *id; | |
7791e4aa | 2285 | |
eb5139d1 RW |
2286 | id = x86_match_cpu(intel_pstate_cpu_ids); |
2287 | if (!id) | |
2288 | return -ENODEV; | |
93f0822d | 2289 | |
2f49afc2 | 2290 | copy_cpu_funcs((struct pstate_funcs *)id->driver_data); |
eb5139d1 | 2291 | } |
016c8150 | 2292 | |
b563b4e3 DB |
2293 | if (intel_pstate_msrs_not_valid()) |
2294 | return -ENODEV; | |
2295 | ||
7791e4aa SP |
2296 | hwp_cpu_matched: |
2297 | /* | |
2298 | * The Intel pstate driver will be ignored if the platform | |
2299 | * firmware has its own power management modes. | |
2300 | */ | |
2301 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
2302 | return -ENODEV; | |
2303 | ||
fb1fe104 RW |
2304 | if (!hwp_active && hwp_only) |
2305 | return -ENOTSUPP; | |
2306 | ||
4836df17 | 2307 | pr_info("Intel P-state driver initializing\n"); |
93f0822d | 2308 | |
b57ffac5 | 2309 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
2310 | if (!all_cpu_data) |
2311 | return -ENOMEM; | |
93f0822d | 2312 | |
d0ea59e1 RW |
2313 | intel_pstate_request_control_from_smm(); |
2314 | ||
93f0822d | 2315 | intel_pstate_sysfs_expose_params(); |
b69880f9 | 2316 | |
0c30b65b | 2317 | mutex_lock(&intel_pstate_driver_lock); |
ee8df89a | 2318 | rc = intel_pstate_register_driver(default_driver); |
0c30b65b | 2319 | mutex_unlock(&intel_pstate_driver_lock); |
fb1fe104 RW |
2320 | if (rc) |
2321 | return rc; | |
366430b5 | 2322 | |
7791e4aa | 2323 | if (hwp_active) |
4836df17 | 2324 | pr_info("HWP enabled\n"); |
7791e4aa | 2325 | |
fb1fe104 | 2326 | return 0; |
93f0822d DB |
2327 | } |
2328 | device_initcall(intel_pstate_init); | |
2329 | ||
6be26498 DB |
2330 | static int __init intel_pstate_setup(char *str) |
2331 | { | |
2332 | if (!str) | |
2333 | return -EINVAL; | |
2334 | ||
001c76f0 | 2335 | if (!strcmp(str, "disable")) { |
6be26498 | 2336 | no_load = 1; |
001c76f0 RW |
2337 | } else if (!strcmp(str, "passive")) { |
2338 | pr_info("Passive mode enabled\n"); | |
ee8df89a | 2339 | default_driver = &intel_cpufreq; |
001c76f0 RW |
2340 | no_hwp = 1; |
2341 | } | |
539342f6 | 2342 | if (!strcmp(str, "no_hwp")) { |
4836df17 | 2343 | pr_info("HWP disabled\n"); |
2f86dc4c | 2344 | no_hwp = 1; |
539342f6 | 2345 | } |
aa4ea34d EZ |
2346 | if (!strcmp(str, "force")) |
2347 | force_load = 1; | |
d64c3b0b KCA |
2348 | if (!strcmp(str, "hwp_only")) |
2349 | hwp_only = 1; | |
eae48f04 SP |
2350 | if (!strcmp(str, "per_cpu_perf_limits")) |
2351 | per_cpu_limits = true; | |
9522a2ff SP |
2352 | |
2353 | #ifdef CONFIG_ACPI | |
2354 | if (!strcmp(str, "support_acpi_ppc")) | |
2355 | acpi_ppc = true; | |
2356 | #endif | |
2357 | ||
6be26498 DB |
2358 | return 0; |
2359 | } | |
2360 | early_param("intel_pstate", intel_pstate_setup); | |
2361 | ||
93f0822d DB |
2362 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
2363 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
2364 | MODULE_LICENSE("GPL"); |