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Commit | Line | Data |
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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/ktime.h> | |
17 | #include <linux/hrtimer.h> | |
18 | #include <linux/tick.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/cpu.h> | |
23 | #include <linux/cpufreq.h> | |
24 | #include <linux/sysfs.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/fs.h> | |
27 | #include <linux/debugfs.h> | |
fbbcdc07 | 28 | #include <linux/acpi.h> |
93f0822d DB |
29 | #include <trace/events/power.h> |
30 | ||
31 | #include <asm/div64.h> | |
32 | #include <asm/msr.h> | |
33 | #include <asm/cpu_device_id.h> | |
64df1fdf | 34 | #include <asm/cpufeature.h> |
93f0822d | 35 | |
61d8d2ab DB |
36 | #define BYT_RATIOS 0x66a |
37 | #define BYT_VIDS 0x66b | |
38 | #define BYT_TURBO_RATIOS 0x66c | |
21855ff5 | 39 | #define BYT_TURBO_VIDS 0x66d |
61d8d2ab | 40 | |
f0fe3cd7 | 41 | #define FRAC_BITS 8 |
93f0822d DB |
42 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
43 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
f0fe3cd7 | 44 | |
93f0822d DB |
45 | |
46 | static inline int32_t mul_fp(int32_t x, int32_t y) | |
47 | { | |
48 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
49 | } | |
50 | ||
51 | static inline int32_t div_fp(int32_t x, int32_t y) | |
52 | { | |
fa30dff9 | 53 | return div_s64((int64_t)x << FRAC_BITS, y); |
93f0822d DB |
54 | } |
55 | ||
d022a65e DB |
56 | static inline int ceiling_fp(int32_t x) |
57 | { | |
58 | int mask, ret; | |
59 | ||
60 | ret = fp_toint(x); | |
61 | mask = (1 << FRAC_BITS) - 1; | |
62 | if (x & mask) | |
63 | ret += 1; | |
64 | return ret; | |
65 | } | |
66 | ||
93f0822d | 67 | struct sample { |
d253d2a5 | 68 | int32_t core_pct_busy; |
93f0822d DB |
69 | u64 aperf; |
70 | u64 mperf; | |
4055fad3 | 71 | u64 tsc; |
93f0822d | 72 | int freq; |
c4ee841f | 73 | ktime_t time; |
93f0822d DB |
74 | }; |
75 | ||
76 | struct pstate_data { | |
77 | int current_pstate; | |
78 | int min_pstate; | |
79 | int max_pstate; | |
b27580b0 | 80 | int scaling; |
93f0822d DB |
81 | int turbo_pstate; |
82 | }; | |
83 | ||
007bea09 | 84 | struct vid_data { |
21855ff5 DB |
85 | int min; |
86 | int max; | |
87 | int turbo; | |
007bea09 DB |
88 | int32_t ratio; |
89 | }; | |
90 | ||
93f0822d DB |
91 | struct _pid { |
92 | int setpoint; | |
93 | int32_t integral; | |
94 | int32_t p_gain; | |
95 | int32_t i_gain; | |
96 | int32_t d_gain; | |
97 | int deadband; | |
d253d2a5 | 98 | int32_t last_err; |
93f0822d DB |
99 | }; |
100 | ||
101 | struct cpudata { | |
102 | int cpu; | |
103 | ||
93f0822d DB |
104 | struct timer_list timer; |
105 | ||
93f0822d | 106 | struct pstate_data pstate; |
007bea09 | 107 | struct vid_data vid; |
93f0822d | 108 | struct _pid pid; |
93f0822d | 109 | |
c4ee841f | 110 | ktime_t last_sample_time; |
93f0822d DB |
111 | u64 prev_aperf; |
112 | u64 prev_mperf; | |
4055fad3 | 113 | u64 prev_tsc; |
d37e2b76 | 114 | struct sample sample; |
93f0822d DB |
115 | }; |
116 | ||
117 | static struct cpudata **all_cpu_data; | |
118 | struct pstate_adjust_policy { | |
119 | int sample_rate_ms; | |
120 | int deadband; | |
121 | int setpoint; | |
122 | int p_gain_pct; | |
123 | int d_gain_pct; | |
124 | int i_gain_pct; | |
125 | }; | |
126 | ||
016c8150 DB |
127 | struct pstate_funcs { |
128 | int (*get_max)(void); | |
129 | int (*get_min)(void); | |
130 | int (*get_turbo)(void); | |
b27580b0 | 131 | int (*get_scaling)(void); |
007bea09 DB |
132 | void (*set)(struct cpudata*, int pstate); |
133 | void (*get_vid)(struct cpudata *); | |
93f0822d DB |
134 | }; |
135 | ||
016c8150 DB |
136 | struct cpu_defaults { |
137 | struct pstate_adjust_policy pid_policy; | |
138 | struct pstate_funcs funcs; | |
93f0822d DB |
139 | }; |
140 | ||
016c8150 DB |
141 | static struct pstate_adjust_policy pid_params; |
142 | static struct pstate_funcs pstate_funcs; | |
2f86dc4c | 143 | static int hwp_active; |
016c8150 | 144 | |
93f0822d DB |
145 | struct perf_limits { |
146 | int no_turbo; | |
dd5fbf70 | 147 | int turbo_disabled; |
93f0822d DB |
148 | int max_perf_pct; |
149 | int min_perf_pct; | |
150 | int32_t max_perf; | |
151 | int32_t min_perf; | |
d8f469e9 DB |
152 | int max_policy_pct; |
153 | int max_sysfs_pct; | |
a0475992 KCA |
154 | int min_policy_pct; |
155 | int min_sysfs_pct; | |
93f0822d DB |
156 | }; |
157 | ||
158 | static struct perf_limits limits = { | |
159 | .no_turbo = 0, | |
4521e1a0 | 160 | .turbo_disabled = 0, |
93f0822d DB |
161 | .max_perf_pct = 100, |
162 | .max_perf = int_tofp(1), | |
163 | .min_perf_pct = 0, | |
164 | .min_perf = 0, | |
d8f469e9 DB |
165 | .max_policy_pct = 100, |
166 | .max_sysfs_pct = 100, | |
a0475992 KCA |
167 | .min_policy_pct = 0, |
168 | .min_sysfs_pct = 0, | |
93f0822d DB |
169 | }; |
170 | ||
171 | static inline void pid_reset(struct _pid *pid, int setpoint, int busy, | |
c410833a | 172 | int deadband, int integral) { |
93f0822d DB |
173 | pid->setpoint = setpoint; |
174 | pid->deadband = deadband; | |
175 | pid->integral = int_tofp(integral); | |
d98d099b | 176 | pid->last_err = int_tofp(setpoint) - int_tofp(busy); |
93f0822d DB |
177 | } |
178 | ||
179 | static inline void pid_p_gain_set(struct _pid *pid, int percent) | |
180 | { | |
181 | pid->p_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
182 | } | |
183 | ||
184 | static inline void pid_i_gain_set(struct _pid *pid, int percent) | |
185 | { | |
186 | pid->i_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
187 | } | |
188 | ||
189 | static inline void pid_d_gain_set(struct _pid *pid, int percent) | |
190 | { | |
93f0822d DB |
191 | pid->d_gain = div_fp(int_tofp(percent), int_tofp(100)); |
192 | } | |
193 | ||
d253d2a5 | 194 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 195 | { |
d253d2a5 | 196 | signed int result; |
93f0822d DB |
197 | int32_t pterm, dterm, fp_error; |
198 | int32_t integral_limit; | |
199 | ||
d253d2a5 | 200 | fp_error = int_tofp(pid->setpoint) - busy; |
93f0822d | 201 | |
d253d2a5 | 202 | if (abs(fp_error) <= int_tofp(pid->deadband)) |
93f0822d DB |
203 | return 0; |
204 | ||
205 | pterm = mul_fp(pid->p_gain, fp_error); | |
206 | ||
207 | pid->integral += fp_error; | |
208 | ||
e0d4c8f8 KCA |
209 | /* |
210 | * We limit the integral here so that it will never | |
211 | * get higher than 30. This prevents it from becoming | |
212 | * too large an input over long periods of time and allows | |
213 | * it to get factored out sooner. | |
214 | * | |
215 | * The value of 30 was chosen through experimentation. | |
216 | */ | |
93f0822d DB |
217 | integral_limit = int_tofp(30); |
218 | if (pid->integral > integral_limit) | |
219 | pid->integral = integral_limit; | |
220 | if (pid->integral < -integral_limit) | |
221 | pid->integral = -integral_limit; | |
222 | ||
d253d2a5 BS |
223 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
224 | pid->last_err = fp_error; | |
93f0822d DB |
225 | |
226 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
51d211e9 | 227 | result = result + (1 << (FRAC_BITS-1)); |
93f0822d DB |
228 | return (signed int)fp_toint(result); |
229 | } | |
230 | ||
231 | static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) | |
232 | { | |
016c8150 DB |
233 | pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); |
234 | pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); | |
235 | pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); | |
93f0822d | 236 | |
2d8d1f18 | 237 | pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); |
93f0822d DB |
238 | } |
239 | ||
93f0822d DB |
240 | static inline void intel_pstate_reset_all_pid(void) |
241 | { | |
242 | unsigned int cpu; | |
845c1cbe | 243 | |
93f0822d DB |
244 | for_each_online_cpu(cpu) { |
245 | if (all_cpu_data[cpu]) | |
246 | intel_pstate_busy_pid_reset(all_cpu_data[cpu]); | |
247 | } | |
248 | } | |
249 | ||
4521e1a0 GM |
250 | static inline void update_turbo_state(void) |
251 | { | |
252 | u64 misc_en; | |
253 | struct cpudata *cpu; | |
254 | ||
255 | cpu = all_cpu_data[0]; | |
256 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); | |
257 | limits.turbo_disabled = | |
258 | (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || | |
259 | cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); | |
260 | } | |
261 | ||
2f86dc4c DB |
262 | #define PCT_TO_HWP(x) (x * 255 / 100) |
263 | static void intel_pstate_hwp_set(void) | |
264 | { | |
265 | int min, max, cpu; | |
266 | u64 value, freq; | |
267 | ||
268 | get_online_cpus(); | |
269 | ||
270 | for_each_online_cpu(cpu) { | |
271 | rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); | |
272 | min = PCT_TO_HWP(limits.min_perf_pct); | |
273 | value &= ~HWP_MIN_PERF(~0L); | |
274 | value |= HWP_MIN_PERF(min); | |
275 | ||
276 | max = PCT_TO_HWP(limits.max_perf_pct); | |
277 | if (limits.no_turbo) { | |
278 | rdmsrl( MSR_HWP_CAPABILITIES, freq); | |
279 | max = HWP_GUARANTEED_PERF(freq); | |
280 | } | |
281 | ||
282 | value &= ~HWP_MAX_PERF(~0L); | |
283 | value |= HWP_MAX_PERF(max); | |
284 | wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); | |
285 | } | |
286 | ||
287 | put_online_cpus(); | |
288 | } | |
289 | ||
93f0822d DB |
290 | /************************** debugfs begin ************************/ |
291 | static int pid_param_set(void *data, u64 val) | |
292 | { | |
293 | *(u32 *)data = val; | |
294 | intel_pstate_reset_all_pid(); | |
295 | return 0; | |
296 | } | |
845c1cbe | 297 | |
93f0822d DB |
298 | static int pid_param_get(void *data, u64 *val) |
299 | { | |
300 | *val = *(u32 *)data; | |
301 | return 0; | |
302 | } | |
2d8d1f18 | 303 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); |
93f0822d DB |
304 | |
305 | struct pid_param { | |
306 | char *name; | |
307 | void *value; | |
308 | }; | |
309 | ||
310 | static struct pid_param pid_files[] = { | |
016c8150 DB |
311 | {"sample_rate_ms", &pid_params.sample_rate_ms}, |
312 | {"d_gain_pct", &pid_params.d_gain_pct}, | |
313 | {"i_gain_pct", &pid_params.i_gain_pct}, | |
314 | {"deadband", &pid_params.deadband}, | |
315 | {"setpoint", &pid_params.setpoint}, | |
316 | {"p_gain_pct", &pid_params.p_gain_pct}, | |
93f0822d DB |
317 | {NULL, NULL} |
318 | }; | |
319 | ||
317dd50e | 320 | static void __init intel_pstate_debug_expose_params(void) |
93f0822d | 321 | { |
317dd50e | 322 | struct dentry *debugfs_parent; |
93f0822d DB |
323 | int i = 0; |
324 | ||
2f86dc4c DB |
325 | if (hwp_active) |
326 | return; | |
93f0822d DB |
327 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); |
328 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
329 | return; | |
330 | while (pid_files[i].name) { | |
331 | debugfs_create_file(pid_files[i].name, 0660, | |
c410833a SK |
332 | debugfs_parent, pid_files[i].value, |
333 | &fops_pid_param); | |
93f0822d DB |
334 | i++; |
335 | } | |
336 | } | |
337 | ||
338 | /************************** debugfs end ************************/ | |
339 | ||
340 | /************************** sysfs begin ************************/ | |
341 | #define show_one(file_name, object) \ | |
342 | static ssize_t show_##file_name \ | |
343 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
344 | { \ | |
345 | return sprintf(buf, "%u\n", limits.object); \ | |
346 | } | |
347 | ||
d01b1f48 KCA |
348 | static ssize_t show_turbo_pct(struct kobject *kobj, |
349 | struct attribute *attr, char *buf) | |
350 | { | |
351 | struct cpudata *cpu; | |
352 | int total, no_turbo, turbo_pct; | |
353 | uint32_t turbo_fp; | |
354 | ||
355 | cpu = all_cpu_data[0]; | |
356 | ||
357 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
358 | no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; | |
359 | turbo_fp = div_fp(int_tofp(no_turbo), int_tofp(total)); | |
360 | turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); | |
361 | return sprintf(buf, "%u\n", turbo_pct); | |
362 | } | |
363 | ||
0522424e KCA |
364 | static ssize_t show_num_pstates(struct kobject *kobj, |
365 | struct attribute *attr, char *buf) | |
366 | { | |
367 | struct cpudata *cpu; | |
368 | int total; | |
369 | ||
370 | cpu = all_cpu_data[0]; | |
371 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
372 | return sprintf(buf, "%u\n", total); | |
373 | } | |
374 | ||
4521e1a0 GM |
375 | static ssize_t show_no_turbo(struct kobject *kobj, |
376 | struct attribute *attr, char *buf) | |
377 | { | |
378 | ssize_t ret; | |
379 | ||
380 | update_turbo_state(); | |
381 | if (limits.turbo_disabled) | |
382 | ret = sprintf(buf, "%u\n", limits.turbo_disabled); | |
383 | else | |
384 | ret = sprintf(buf, "%u\n", limits.no_turbo); | |
385 | ||
386 | return ret; | |
387 | } | |
388 | ||
93f0822d | 389 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, |
c410833a | 390 | const char *buf, size_t count) |
93f0822d DB |
391 | { |
392 | unsigned int input; | |
393 | int ret; | |
845c1cbe | 394 | |
93f0822d DB |
395 | ret = sscanf(buf, "%u", &input); |
396 | if (ret != 1) | |
397 | return -EINVAL; | |
4521e1a0 GM |
398 | |
399 | update_turbo_state(); | |
dd5fbf70 DB |
400 | if (limits.turbo_disabled) { |
401 | pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); | |
4521e1a0 | 402 | return -EPERM; |
dd5fbf70 | 403 | } |
2f86dc4c | 404 | |
4521e1a0 GM |
405 | limits.no_turbo = clamp_t(int, input, 0, 1); |
406 | ||
2f86dc4c DB |
407 | if (hwp_active) |
408 | intel_pstate_hwp_set(); | |
409 | ||
93f0822d DB |
410 | return count; |
411 | } | |
412 | ||
413 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 414 | const char *buf, size_t count) |
93f0822d DB |
415 | { |
416 | unsigned int input; | |
417 | int ret; | |
845c1cbe | 418 | |
93f0822d DB |
419 | ret = sscanf(buf, "%u", &input); |
420 | if (ret != 1) | |
421 | return -EINVAL; | |
422 | ||
d8f469e9 DB |
423 | limits.max_sysfs_pct = clamp_t(int, input, 0 , 100); |
424 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); | |
93f0822d | 425 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
845c1cbe | 426 | |
2f86dc4c DB |
427 | if (hwp_active) |
428 | intel_pstate_hwp_set(); | |
93f0822d DB |
429 | return count; |
430 | } | |
431 | ||
432 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 433 | const char *buf, size_t count) |
93f0822d DB |
434 | { |
435 | unsigned int input; | |
436 | int ret; | |
845c1cbe | 437 | |
93f0822d DB |
438 | ret = sscanf(buf, "%u", &input); |
439 | if (ret != 1) | |
440 | return -EINVAL; | |
a0475992 KCA |
441 | |
442 | limits.min_sysfs_pct = clamp_t(int, input, 0 , 100); | |
443 | limits.min_perf_pct = max(limits.min_policy_pct, limits.min_sysfs_pct); | |
93f0822d DB |
444 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); |
445 | ||
2f86dc4c DB |
446 | if (hwp_active) |
447 | intel_pstate_hwp_set(); | |
93f0822d DB |
448 | return count; |
449 | } | |
450 | ||
93f0822d DB |
451 | show_one(max_perf_pct, max_perf_pct); |
452 | show_one(min_perf_pct, min_perf_pct); | |
453 | ||
454 | define_one_global_rw(no_turbo); | |
455 | define_one_global_rw(max_perf_pct); | |
456 | define_one_global_rw(min_perf_pct); | |
d01b1f48 | 457 | define_one_global_ro(turbo_pct); |
0522424e | 458 | define_one_global_ro(num_pstates); |
93f0822d DB |
459 | |
460 | static struct attribute *intel_pstate_attributes[] = { | |
461 | &no_turbo.attr, | |
462 | &max_perf_pct.attr, | |
463 | &min_perf_pct.attr, | |
d01b1f48 | 464 | &turbo_pct.attr, |
0522424e | 465 | &num_pstates.attr, |
93f0822d DB |
466 | NULL |
467 | }; | |
468 | ||
469 | static struct attribute_group intel_pstate_attr_group = { | |
470 | .attrs = intel_pstate_attributes, | |
471 | }; | |
93f0822d | 472 | |
317dd50e | 473 | static void __init intel_pstate_sysfs_expose_params(void) |
93f0822d | 474 | { |
317dd50e | 475 | struct kobject *intel_pstate_kobject; |
93f0822d DB |
476 | int rc; |
477 | ||
478 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
479 | &cpu_subsys.dev_root->kobj); | |
480 | BUG_ON(!intel_pstate_kobject); | |
2d8d1f18 | 481 | rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); |
93f0822d DB |
482 | BUG_ON(rc); |
483 | } | |
93f0822d | 484 | /************************** sysfs end ************************/ |
2f86dc4c DB |
485 | |
486 | static void intel_pstate_hwp_enable(void) | |
487 | { | |
488 | hwp_active++; | |
489 | pr_info("intel_pstate HWP enabled\n"); | |
490 | ||
491 | wrmsrl( MSR_PM_ENABLE, 0x1); | |
492 | } | |
493 | ||
19e77c28 DB |
494 | static int byt_get_min_pstate(void) |
495 | { | |
496 | u64 value; | |
845c1cbe | 497 | |
19e77c28 | 498 | rdmsrl(BYT_RATIOS, value); |
c16ed060 | 499 | return (value >> 8) & 0x7F; |
19e77c28 DB |
500 | } |
501 | ||
502 | static int byt_get_max_pstate(void) | |
503 | { | |
504 | u64 value; | |
845c1cbe | 505 | |
19e77c28 | 506 | rdmsrl(BYT_RATIOS, value); |
c16ed060 | 507 | return (value >> 16) & 0x7F; |
19e77c28 | 508 | } |
93f0822d | 509 | |
61d8d2ab DB |
510 | static int byt_get_turbo_pstate(void) |
511 | { | |
512 | u64 value; | |
845c1cbe | 513 | |
61d8d2ab | 514 | rdmsrl(BYT_TURBO_RATIOS, value); |
c16ed060 | 515 | return value & 0x7F; |
61d8d2ab DB |
516 | } |
517 | ||
007bea09 DB |
518 | static void byt_set_pstate(struct cpudata *cpudata, int pstate) |
519 | { | |
520 | u64 val; | |
521 | int32_t vid_fp; | |
522 | u32 vid; | |
523 | ||
524 | val = pstate << 8; | |
dd5fbf70 | 525 | if (limits.no_turbo && !limits.turbo_disabled) |
007bea09 DB |
526 | val |= (u64)1 << 32; |
527 | ||
528 | vid_fp = cpudata->vid.min + mul_fp( | |
529 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
530 | cpudata->vid.ratio); | |
531 | ||
532 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
d022a65e | 533 | vid = ceiling_fp(vid_fp); |
007bea09 | 534 | |
21855ff5 DB |
535 | if (pstate > cpudata->pstate.max_pstate) |
536 | vid = cpudata->vid.turbo; | |
537 | ||
007bea09 DB |
538 | val |= vid; |
539 | ||
540 | wrmsrl(MSR_IA32_PERF_CTL, val); | |
541 | } | |
542 | ||
b27580b0 DB |
543 | #define BYT_BCLK_FREQS 5 |
544 | static int byt_freq_table[BYT_BCLK_FREQS] = { 833, 1000, 1333, 1167, 800}; | |
545 | ||
546 | static int byt_get_scaling(void) | |
547 | { | |
548 | u64 value; | |
549 | int i; | |
550 | ||
551 | rdmsrl(MSR_FSB_FREQ, value); | |
552 | i = value & 0x3; | |
553 | ||
554 | BUG_ON(i > BYT_BCLK_FREQS); | |
555 | ||
556 | return byt_freq_table[i] * 100; | |
557 | } | |
558 | ||
007bea09 DB |
559 | static void byt_get_vid(struct cpudata *cpudata) |
560 | { | |
561 | u64 value; | |
562 | ||
563 | rdmsrl(BYT_VIDS, value); | |
c16ed060 DB |
564 | cpudata->vid.min = int_tofp((value >> 8) & 0x7f); |
565 | cpudata->vid.max = int_tofp((value >> 16) & 0x7f); | |
007bea09 DB |
566 | cpudata->vid.ratio = div_fp( |
567 | cpudata->vid.max - cpudata->vid.min, | |
568 | int_tofp(cpudata->pstate.max_pstate - | |
569 | cpudata->pstate.min_pstate)); | |
21855ff5 DB |
570 | |
571 | rdmsrl(BYT_TURBO_VIDS, value); | |
572 | cpudata->vid.turbo = value & 0x7f; | |
007bea09 DB |
573 | } |
574 | ||
016c8150 | 575 | static int core_get_min_pstate(void) |
93f0822d DB |
576 | { |
577 | u64 value; | |
845c1cbe | 578 | |
05e99c8c | 579 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
580 | return (value >> 40) & 0xFF; |
581 | } | |
582 | ||
016c8150 | 583 | static int core_get_max_pstate(void) |
93f0822d DB |
584 | { |
585 | u64 value; | |
845c1cbe | 586 | |
05e99c8c | 587 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
588 | return (value >> 8) & 0xFF; |
589 | } | |
590 | ||
016c8150 | 591 | static int core_get_turbo_pstate(void) |
93f0822d DB |
592 | { |
593 | u64 value; | |
594 | int nont, ret; | |
845c1cbe | 595 | |
05e99c8c | 596 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); |
016c8150 | 597 | nont = core_get_max_pstate(); |
285cb990 | 598 | ret = (value) & 255; |
93f0822d DB |
599 | if (ret <= nont) |
600 | ret = nont; | |
601 | return ret; | |
602 | } | |
603 | ||
b27580b0 DB |
604 | static inline int core_get_scaling(void) |
605 | { | |
606 | return 100000; | |
607 | } | |
608 | ||
007bea09 | 609 | static void core_set_pstate(struct cpudata *cpudata, int pstate) |
016c8150 DB |
610 | { |
611 | u64 val; | |
612 | ||
613 | val = pstate << 8; | |
dd5fbf70 | 614 | if (limits.no_turbo && !limits.turbo_disabled) |
016c8150 DB |
615 | val |= (u64)1 << 32; |
616 | ||
bb18008f | 617 | wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); |
016c8150 DB |
618 | } |
619 | ||
b34ef932 DC |
620 | static int knl_get_turbo_pstate(void) |
621 | { | |
622 | u64 value; | |
623 | int nont, ret; | |
624 | ||
625 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); | |
626 | nont = core_get_max_pstate(); | |
627 | ret = (((value) >> 8) & 0xFF); | |
628 | if (ret <= nont) | |
629 | ret = nont; | |
630 | return ret; | |
631 | } | |
632 | ||
016c8150 DB |
633 | static struct cpu_defaults core_params = { |
634 | .pid_policy = { | |
635 | .sample_rate_ms = 10, | |
636 | .deadband = 0, | |
637 | .setpoint = 97, | |
638 | .p_gain_pct = 20, | |
639 | .d_gain_pct = 0, | |
640 | .i_gain_pct = 0, | |
641 | }, | |
642 | .funcs = { | |
643 | .get_max = core_get_max_pstate, | |
644 | .get_min = core_get_min_pstate, | |
645 | .get_turbo = core_get_turbo_pstate, | |
b27580b0 | 646 | .get_scaling = core_get_scaling, |
016c8150 DB |
647 | .set = core_set_pstate, |
648 | }, | |
649 | }; | |
650 | ||
19e77c28 DB |
651 | static struct cpu_defaults byt_params = { |
652 | .pid_policy = { | |
653 | .sample_rate_ms = 10, | |
654 | .deadband = 0, | |
6a82ba6d | 655 | .setpoint = 60, |
19e77c28 DB |
656 | .p_gain_pct = 14, |
657 | .d_gain_pct = 0, | |
658 | .i_gain_pct = 4, | |
659 | }, | |
660 | .funcs = { | |
661 | .get_max = byt_get_max_pstate, | |
662 | .get_min = byt_get_min_pstate, | |
61d8d2ab | 663 | .get_turbo = byt_get_turbo_pstate, |
007bea09 | 664 | .set = byt_set_pstate, |
b27580b0 | 665 | .get_scaling = byt_get_scaling, |
007bea09 | 666 | .get_vid = byt_get_vid, |
19e77c28 DB |
667 | }, |
668 | }; | |
669 | ||
b34ef932 DC |
670 | static struct cpu_defaults knl_params = { |
671 | .pid_policy = { | |
672 | .sample_rate_ms = 10, | |
673 | .deadband = 0, | |
674 | .setpoint = 97, | |
675 | .p_gain_pct = 20, | |
676 | .d_gain_pct = 0, | |
677 | .i_gain_pct = 0, | |
678 | }, | |
679 | .funcs = { | |
680 | .get_max = core_get_max_pstate, | |
681 | .get_min = core_get_min_pstate, | |
682 | .get_turbo = knl_get_turbo_pstate, | |
683 | .set = core_set_pstate, | |
684 | }, | |
685 | }; | |
686 | ||
93f0822d DB |
687 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) |
688 | { | |
689 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 690 | int max_perf_adj; |
93f0822d | 691 | int min_perf; |
845c1cbe | 692 | |
4521e1a0 | 693 | if (limits.no_turbo || limits.turbo_disabled) |
93f0822d DB |
694 | max_perf = cpu->pstate.max_pstate; |
695 | ||
e0d4c8f8 KCA |
696 | /* |
697 | * performance can be limited by user through sysfs, by cpufreq | |
698 | * policy, or by cpu specific default values determined through | |
699 | * experimentation. | |
700 | */ | |
7244cb62 DB |
701 | max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf)); |
702 | *max = clamp_t(int, max_perf_adj, | |
93f0822d DB |
703 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); |
704 | ||
705 | min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf)); | |
2d8d1f18 | 706 | *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); |
93f0822d DB |
707 | } |
708 | ||
709 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) | |
710 | { | |
711 | int max_perf, min_perf; | |
712 | ||
4521e1a0 GM |
713 | update_turbo_state(); |
714 | ||
93f0822d DB |
715 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); |
716 | ||
717 | pstate = clamp_t(int, pstate, min_perf, max_perf); | |
718 | ||
719 | if (pstate == cpu->pstate.current_pstate) | |
720 | return; | |
721 | ||
b27580b0 | 722 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
35363e94 | 723 | |
93f0822d | 724 | cpu->pstate.current_pstate = pstate; |
93f0822d | 725 | |
007bea09 | 726 | pstate_funcs.set(cpu, pstate); |
93f0822d DB |
727 | } |
728 | ||
93f0822d DB |
729 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) |
730 | { | |
016c8150 DB |
731 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
732 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
733 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); | |
b27580b0 | 734 | cpu->pstate.scaling = pstate_funcs.get_scaling(); |
93f0822d | 735 | |
007bea09 DB |
736 | if (pstate_funcs.get_vid) |
737 | pstate_funcs.get_vid(cpu); | |
d40a63c4 | 738 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); |
93f0822d DB |
739 | } |
740 | ||
6b17ddb2 | 741 | static inline void intel_pstate_calc_busy(struct cpudata *cpu) |
93f0822d | 742 | { |
6b17ddb2 | 743 | struct sample *sample = &cpu->sample; |
bf810222 | 744 | int64_t core_pct; |
93f0822d | 745 | |
bf810222 | 746 | core_pct = int_tofp(sample->aperf) * int_tofp(100); |
78e27086 | 747 | core_pct = div64_u64(core_pct, int_tofp(sample->mperf)); |
e66c1768 | 748 | |
fcb6a15c | 749 | sample->freq = fp_toint( |
b27580b0 DB |
750 | mul_fp(int_tofp( |
751 | cpu->pstate.max_pstate * cpu->pstate.scaling / 100), | |
752 | core_pct)); | |
fcb6a15c | 753 | |
bf810222 | 754 | sample->core_pct_busy = (int32_t)core_pct; |
93f0822d DB |
755 | } |
756 | ||
757 | static inline void intel_pstate_sample(struct cpudata *cpu) | |
758 | { | |
93f0822d | 759 | u64 aperf, mperf; |
4ab60c3f | 760 | unsigned long flags; |
4055fad3 | 761 | u64 tsc; |
93f0822d | 762 | |
4ab60c3f | 763 | local_irq_save(flags); |
93f0822d DB |
764 | rdmsrl(MSR_IA32_APERF, aperf); |
765 | rdmsrl(MSR_IA32_MPERF, mperf); | |
4055fad3 | 766 | tsc = native_read_tsc(); |
4ab60c3f | 767 | local_irq_restore(flags); |
b69880f9 | 768 | |
c4ee841f DB |
769 | cpu->last_sample_time = cpu->sample.time; |
770 | cpu->sample.time = ktime_get(); | |
d37e2b76 DB |
771 | cpu->sample.aperf = aperf; |
772 | cpu->sample.mperf = mperf; | |
4055fad3 | 773 | cpu->sample.tsc = tsc; |
d37e2b76 DB |
774 | cpu->sample.aperf -= cpu->prev_aperf; |
775 | cpu->sample.mperf -= cpu->prev_mperf; | |
4055fad3 | 776 | cpu->sample.tsc -= cpu->prev_tsc; |
1abc4b20 | 777 | |
6b17ddb2 | 778 | intel_pstate_calc_busy(cpu); |
93f0822d | 779 | |
93f0822d DB |
780 | cpu->prev_aperf = aperf; |
781 | cpu->prev_mperf = mperf; | |
4055fad3 | 782 | cpu->prev_tsc = tsc; |
93f0822d DB |
783 | } |
784 | ||
2f86dc4c DB |
785 | static inline void intel_hwp_set_sample_time(struct cpudata *cpu) |
786 | { | |
787 | int delay; | |
788 | ||
789 | delay = msecs_to_jiffies(50); | |
790 | mod_timer_pinned(&cpu->timer, jiffies + delay); | |
791 | } | |
792 | ||
93f0822d DB |
793 | static inline void intel_pstate_set_sample_time(struct cpudata *cpu) |
794 | { | |
abf013bf | 795 | int delay; |
93f0822d | 796 | |
abf013bf | 797 | delay = msecs_to_jiffies(pid_params.sample_rate_ms); |
93f0822d DB |
798 | mod_timer_pinned(&cpu->timer, jiffies + delay); |
799 | } | |
800 | ||
d253d2a5 | 801 | static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu) |
93f0822d | 802 | { |
c4ee841f DB |
803 | int32_t core_busy, max_pstate, current_pstate, sample_ratio; |
804 | u32 duration_us; | |
805 | u32 sample_time; | |
93f0822d | 806 | |
e0d4c8f8 KCA |
807 | /* |
808 | * core_busy is the ratio of actual performance to max | |
809 | * max_pstate is the max non turbo pstate available | |
810 | * current_pstate was the pstate that was requested during | |
811 | * the last sample period. | |
812 | * | |
813 | * We normalize core_busy, which was our actual percent | |
814 | * performance to what we requested during the last sample | |
815 | * period. The result will be a percentage of busy at a | |
816 | * specified pstate. | |
817 | */ | |
d37e2b76 | 818 | core_busy = cpu->sample.core_pct_busy; |
2134ed4d | 819 | max_pstate = int_tofp(cpu->pstate.max_pstate); |
93f0822d | 820 | current_pstate = int_tofp(cpu->pstate.current_pstate); |
e66c1768 | 821 | core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate)); |
c4ee841f | 822 | |
e0d4c8f8 KCA |
823 | /* |
824 | * Since we have a deferred timer, it will not fire unless | |
825 | * we are in C0. So, determine if the actual elapsed time | |
826 | * is significantly greater (3x) than our sample interval. If it | |
827 | * is, then we were idle for a long enough period of time | |
828 | * to adjust our busyness. | |
829 | */ | |
285cb990 | 830 | sample_time = pid_params.sample_rate_ms * USEC_PER_MSEC; |
c4ee841f | 831 | duration_us = (u32) ktime_us_delta(cpu->sample.time, |
c410833a | 832 | cpu->last_sample_time); |
c4ee841f DB |
833 | if (duration_us > sample_time * 3) { |
834 | sample_ratio = div_fp(int_tofp(sample_time), | |
c410833a | 835 | int_tofp(duration_us)); |
c4ee841f DB |
836 | core_busy = mul_fp(core_busy, sample_ratio); |
837 | } | |
838 | ||
f0fe3cd7 | 839 | return core_busy; |
93f0822d DB |
840 | } |
841 | ||
842 | static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) | |
843 | { | |
d253d2a5 | 844 | int32_t busy_scaled; |
93f0822d | 845 | struct _pid *pid; |
4b707c89 | 846 | signed int ctl; |
4055fad3 DS |
847 | int from; |
848 | struct sample *sample; | |
849 | ||
850 | from = cpu->pstate.current_pstate; | |
93f0822d DB |
851 | |
852 | pid = &cpu->pid; | |
853 | busy_scaled = intel_pstate_get_scaled_busy(cpu); | |
854 | ||
855 | ctl = pid_calc(pid, busy_scaled); | |
856 | ||
4b707c89 SK |
857 | /* Negative values of ctl increase the pstate and vice versa */ |
858 | intel_pstate_set_pstate(cpu, cpu->pstate.current_pstate - ctl); | |
4055fad3 DS |
859 | |
860 | sample = &cpu->sample; | |
861 | trace_pstate_sample(fp_toint(sample->core_pct_busy), | |
862 | fp_toint(busy_scaled), | |
863 | from, | |
864 | cpu->pstate.current_pstate, | |
865 | sample->mperf, | |
866 | sample->aperf, | |
867 | sample->tsc, | |
868 | sample->freq); | |
93f0822d DB |
869 | } |
870 | ||
2f86dc4c DB |
871 | static void intel_hwp_timer_func(unsigned long __data) |
872 | { | |
873 | struct cpudata *cpu = (struct cpudata *) __data; | |
874 | ||
875 | intel_pstate_sample(cpu); | |
876 | intel_hwp_set_sample_time(cpu); | |
877 | } | |
878 | ||
93f0822d DB |
879 | static void intel_pstate_timer_func(unsigned long __data) |
880 | { | |
881 | struct cpudata *cpu = (struct cpudata *) __data; | |
882 | ||
883 | intel_pstate_sample(cpu); | |
b69880f9 | 884 | |
ca182aee | 885 | intel_pstate_adjust_busy_pstate(cpu); |
b69880f9 | 886 | |
93f0822d DB |
887 | intel_pstate_set_sample_time(cpu); |
888 | } | |
889 | ||
890 | #define ICPU(model, policy) \ | |
6cbd7ee1 DB |
891 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
892 | (unsigned long)&policy } | |
93f0822d DB |
893 | |
894 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
016c8150 DB |
895 | ICPU(0x2a, core_params), |
896 | ICPU(0x2d, core_params), | |
19e77c28 | 897 | ICPU(0x37, byt_params), |
016c8150 DB |
898 | ICPU(0x3a, core_params), |
899 | ICPU(0x3c, core_params), | |
c7e241df | 900 | ICPU(0x3d, core_params), |
016c8150 DB |
901 | ICPU(0x3e, core_params), |
902 | ICPU(0x3f, core_params), | |
903 | ICPU(0x45, core_params), | |
904 | ICPU(0x46, core_params), | |
43f8a966 | 905 | ICPU(0x47, core_params), |
16405f98 | 906 | ICPU(0x4c, byt_params), |
7ab0256e | 907 | ICPU(0x4e, core_params), |
c7e241df DB |
908 | ICPU(0x4f, core_params), |
909 | ICPU(0x56, core_params), | |
b34ef932 | 910 | ICPU(0x57, knl_params), |
93f0822d DB |
911 | {} |
912 | }; | |
913 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
914 | ||
2f86dc4c DB |
915 | static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = { |
916 | ICPU(0x56, core_params), | |
917 | {} | |
918 | }; | |
919 | ||
93f0822d DB |
920 | static int intel_pstate_init_cpu(unsigned int cpunum) |
921 | { | |
93f0822d DB |
922 | struct cpudata *cpu; |
923 | ||
c0348717 DB |
924 | if (!all_cpu_data[cpunum]) |
925 | all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), | |
926 | GFP_KERNEL); | |
93f0822d DB |
927 | if (!all_cpu_data[cpunum]) |
928 | return -ENOMEM; | |
929 | ||
930 | cpu = all_cpu_data[cpunum]; | |
931 | ||
93f0822d | 932 | cpu->cpu = cpunum; |
179e8471 | 933 | intel_pstate_get_cpu_pstates(cpu); |
016c8150 | 934 | |
93f0822d | 935 | init_timer_deferrable(&cpu->timer); |
2d8d1f18 | 936 | cpu->timer.data = (unsigned long)cpu; |
93f0822d | 937 | cpu->timer.expires = jiffies + HZ/100; |
2f86dc4c DB |
938 | |
939 | if (!hwp_active) | |
940 | cpu->timer.function = intel_pstate_timer_func; | |
941 | else | |
942 | cpu->timer.function = intel_hwp_timer_func; | |
943 | ||
93f0822d | 944 | intel_pstate_busy_pid_reset(cpu); |
93f0822d | 945 | intel_pstate_sample(cpu); |
93f0822d DB |
946 | |
947 | add_timer_on(&cpu->timer, cpunum); | |
948 | ||
ce717613 | 949 | pr_debug("Intel pstate controlling: cpu %d\n", cpunum); |
93f0822d DB |
950 | |
951 | return 0; | |
952 | } | |
953 | ||
954 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
955 | { | |
956 | struct sample *sample; | |
957 | struct cpudata *cpu; | |
958 | ||
959 | cpu = all_cpu_data[cpu_num]; | |
960 | if (!cpu) | |
961 | return 0; | |
d37e2b76 | 962 | sample = &cpu->sample; |
93f0822d DB |
963 | return sample->freq; |
964 | } | |
965 | ||
966 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) | |
967 | { | |
d3929b83 DB |
968 | if (!policy->cpuinfo.max_freq) |
969 | return -ENODEV; | |
970 | ||
630ec286 SP |
971 | if (policy->policy == CPUFREQ_POLICY_PERFORMANCE && |
972 | policy->max >= policy->cpuinfo.max_freq) { | |
a0475992 | 973 | limits.min_policy_pct = 100; |
93f0822d DB |
974 | limits.min_perf_pct = 100; |
975 | limits.min_perf = int_tofp(1); | |
36b4bed5 | 976 | limits.max_policy_pct = 100; |
93f0822d DB |
977 | limits.max_perf_pct = 100; |
978 | limits.max_perf = int_tofp(1); | |
4521e1a0 | 979 | limits.no_turbo = 0; |
d1b68485 | 980 | return 0; |
93f0822d | 981 | } |
2f86dc4c | 982 | |
a0475992 KCA |
983 | limits.min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq; |
984 | limits.min_policy_pct = clamp_t(int, limits.min_policy_pct, 0 , 100); | |
985 | limits.min_perf_pct = max(limits.min_policy_pct, limits.min_sysfs_pct); | |
d1b68485 SP |
986 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); |
987 | ||
285cb990 | 988 | limits.max_policy_pct = (policy->max * 100) / policy->cpuinfo.max_freq; |
d8f469e9 DB |
989 | limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100); |
990 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); | |
d1b68485 | 991 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
93f0822d | 992 | |
2f86dc4c DB |
993 | if (hwp_active) |
994 | intel_pstate_hwp_set(); | |
995 | ||
93f0822d DB |
996 | return 0; |
997 | } | |
998 | ||
999 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) | |
1000 | { | |
be49e346 | 1001 | cpufreq_verify_within_cpu_limits(policy); |
93f0822d | 1002 | |
285cb990 | 1003 | if (policy->policy != CPUFREQ_POLICY_POWERSAVE && |
c410833a | 1004 | policy->policy != CPUFREQ_POLICY_PERFORMANCE) |
93f0822d DB |
1005 | return -EINVAL; |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | ||
bb18008f | 1010 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 1011 | { |
bb18008f DB |
1012 | int cpu_num = policy->cpu; |
1013 | struct cpudata *cpu = all_cpu_data[cpu_num]; | |
93f0822d | 1014 | |
bb18008f DB |
1015 | pr_info("intel_pstate CPU %d exiting\n", cpu_num); |
1016 | ||
c2294a2f | 1017 | del_timer_sync(&all_cpu_data[cpu_num]->timer); |
2f86dc4c DB |
1018 | if (hwp_active) |
1019 | return; | |
1020 | ||
bb18008f | 1021 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); |
93f0822d DB |
1022 | } |
1023 | ||
2760984f | 1024 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 1025 | { |
93f0822d | 1026 | struct cpudata *cpu; |
52e0a509 | 1027 | int rc; |
93f0822d DB |
1028 | |
1029 | rc = intel_pstate_init_cpu(policy->cpu); | |
1030 | if (rc) | |
1031 | return rc; | |
1032 | ||
1033 | cpu = all_cpu_data[policy->cpu]; | |
1034 | ||
dd5fbf70 | 1035 | if (limits.min_perf_pct == 100 && limits.max_perf_pct == 100) |
93f0822d DB |
1036 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; |
1037 | else | |
1038 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
1039 | ||
b27580b0 DB |
1040 | policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1041 | policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1042 | |
1043 | /* cpuinfo and default policy values */ | |
b27580b0 DB |
1044 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1045 | policy->cpuinfo.max_freq = | |
1046 | cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1047 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; |
1048 | cpumask_set_cpu(policy->cpu, policy->cpus); | |
1049 | ||
1050 | return 0; | |
1051 | } | |
1052 | ||
1053 | static struct cpufreq_driver intel_pstate_driver = { | |
1054 | .flags = CPUFREQ_CONST_LOOPS, | |
1055 | .verify = intel_pstate_verify_policy, | |
1056 | .setpolicy = intel_pstate_set_policy, | |
1057 | .get = intel_pstate_get, | |
1058 | .init = intel_pstate_cpu_init, | |
bb18008f | 1059 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 1060 | .name = "intel_pstate", |
93f0822d DB |
1061 | }; |
1062 | ||
6be26498 | 1063 | static int __initdata no_load; |
2f86dc4c | 1064 | static int __initdata no_hwp; |
d64c3b0b | 1065 | static int __initdata hwp_only; |
aa4ea34d | 1066 | static unsigned int force_load; |
6be26498 | 1067 | |
b563b4e3 DB |
1068 | static int intel_pstate_msrs_not_valid(void) |
1069 | { | |
016c8150 | 1070 | if (!pstate_funcs.get_max() || |
c410833a SK |
1071 | !pstate_funcs.get_min() || |
1072 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
1073 | return -ENODEV; |
1074 | ||
b563b4e3 DB |
1075 | return 0; |
1076 | } | |
016c8150 | 1077 | |
e0a261a2 | 1078 | static void copy_pid_params(struct pstate_adjust_policy *policy) |
016c8150 DB |
1079 | { |
1080 | pid_params.sample_rate_ms = policy->sample_rate_ms; | |
1081 | pid_params.p_gain_pct = policy->p_gain_pct; | |
1082 | pid_params.i_gain_pct = policy->i_gain_pct; | |
1083 | pid_params.d_gain_pct = policy->d_gain_pct; | |
1084 | pid_params.deadband = policy->deadband; | |
1085 | pid_params.setpoint = policy->setpoint; | |
1086 | } | |
1087 | ||
e0a261a2 | 1088 | static void copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
1089 | { |
1090 | pstate_funcs.get_max = funcs->get_max; | |
1091 | pstate_funcs.get_min = funcs->get_min; | |
1092 | pstate_funcs.get_turbo = funcs->get_turbo; | |
b27580b0 | 1093 | pstate_funcs.get_scaling = funcs->get_scaling; |
016c8150 | 1094 | pstate_funcs.set = funcs->set; |
007bea09 | 1095 | pstate_funcs.get_vid = funcs->get_vid; |
016c8150 DB |
1096 | } |
1097 | ||
fbbcdc07 AH |
1098 | #if IS_ENABLED(CONFIG_ACPI) |
1099 | #include <acpi/processor.h> | |
1100 | ||
1101 | static bool intel_pstate_no_acpi_pss(void) | |
1102 | { | |
1103 | int i; | |
1104 | ||
1105 | for_each_possible_cpu(i) { | |
1106 | acpi_status status; | |
1107 | union acpi_object *pss; | |
1108 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1109 | struct acpi_processor *pr = per_cpu(processors, i); | |
1110 | ||
1111 | if (!pr) | |
1112 | continue; | |
1113 | ||
1114 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
1115 | if (ACPI_FAILURE(status)) | |
1116 | continue; | |
1117 | ||
1118 | pss = buffer.pointer; | |
1119 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
1120 | kfree(pss); | |
1121 | return false; | |
1122 | } | |
1123 | ||
1124 | kfree(pss); | |
1125 | } | |
1126 | ||
1127 | return true; | |
1128 | } | |
1129 | ||
966916ea | 1130 | static bool intel_pstate_has_acpi_ppc(void) |
1131 | { | |
1132 | int i; | |
1133 | ||
1134 | for_each_possible_cpu(i) { | |
1135 | struct acpi_processor *pr = per_cpu(processors, i); | |
1136 | ||
1137 | if (!pr) | |
1138 | continue; | |
1139 | if (acpi_has_method(pr->handle, "_PPC")) | |
1140 | return true; | |
1141 | } | |
1142 | return false; | |
1143 | } | |
1144 | ||
1145 | enum { | |
1146 | PSS, | |
1147 | PPC, | |
1148 | }; | |
1149 | ||
fbbcdc07 AH |
1150 | struct hw_vendor_info { |
1151 | u16 valid; | |
1152 | char oem_id[ACPI_OEM_ID_SIZE]; | |
1153 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
966916ea | 1154 | int oem_pwr_table; |
fbbcdc07 AH |
1155 | }; |
1156 | ||
1157 | /* Hardware vendor-specific info that has its own power management modes */ | |
1158 | static struct hw_vendor_info vendor_info[] = { | |
966916ea | 1159 | {1, "HP ", "ProLiant", PSS}, |
1160 | {1, "ORACLE", "X4-2 ", PPC}, | |
1161 | {1, "ORACLE", "X4-2L ", PPC}, | |
1162 | {1, "ORACLE", "X4-2B ", PPC}, | |
1163 | {1, "ORACLE", "X3-2 ", PPC}, | |
1164 | {1, "ORACLE", "X3-2L ", PPC}, | |
1165 | {1, "ORACLE", "X3-2B ", PPC}, | |
1166 | {1, "ORACLE", "X4470M2 ", PPC}, | |
1167 | {1, "ORACLE", "X4270M3 ", PPC}, | |
1168 | {1, "ORACLE", "X4270M2 ", PPC}, | |
1169 | {1, "ORACLE", "X4170M2 ", PPC}, | |
fbbcdc07 AH |
1170 | {0, "", ""}, |
1171 | }; | |
1172 | ||
1173 | static bool intel_pstate_platform_pwr_mgmt_exists(void) | |
1174 | { | |
1175 | struct acpi_table_header hdr; | |
1176 | struct hw_vendor_info *v_info; | |
2f86dc4c DB |
1177 | const struct x86_cpu_id *id; |
1178 | u64 misc_pwr; | |
1179 | ||
1180 | id = x86_match_cpu(intel_pstate_cpu_oob_ids); | |
1181 | if (id) { | |
1182 | rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); | |
1183 | if ( misc_pwr & (1 << 8)) | |
1184 | return true; | |
1185 | } | |
fbbcdc07 | 1186 | |
c410833a SK |
1187 | if (acpi_disabled || |
1188 | ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) | |
fbbcdc07 AH |
1189 | return false; |
1190 | ||
1191 | for (v_info = vendor_info; v_info->valid; v_info++) { | |
c410833a | 1192 | if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && |
966916ea | 1193 | !strncmp(hdr.oem_table_id, v_info->oem_table_id, |
1194 | ACPI_OEM_TABLE_ID_SIZE)) | |
1195 | switch (v_info->oem_pwr_table) { | |
1196 | case PSS: | |
1197 | return intel_pstate_no_acpi_pss(); | |
1198 | case PPC: | |
aa4ea34d EZ |
1199 | return intel_pstate_has_acpi_ppc() && |
1200 | (!force_load); | |
966916ea | 1201 | } |
fbbcdc07 AH |
1202 | } |
1203 | ||
1204 | return false; | |
1205 | } | |
1206 | #else /* CONFIG_ACPI not enabled */ | |
1207 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
966916ea | 1208 | static inline bool intel_pstate_has_acpi_ppc(void) { return false; } |
fbbcdc07 AH |
1209 | #endif /* CONFIG_ACPI */ |
1210 | ||
93f0822d DB |
1211 | static int __init intel_pstate_init(void) |
1212 | { | |
907cc908 | 1213 | int cpu, rc = 0; |
93f0822d | 1214 | const struct x86_cpu_id *id; |
64df1fdf | 1215 | struct cpu_defaults *cpu_def; |
93f0822d | 1216 | |
6be26498 DB |
1217 | if (no_load) |
1218 | return -ENODEV; | |
1219 | ||
93f0822d DB |
1220 | id = x86_match_cpu(intel_pstate_cpu_ids); |
1221 | if (!id) | |
1222 | return -ENODEV; | |
1223 | ||
fbbcdc07 AH |
1224 | /* |
1225 | * The Intel pstate driver will be ignored if the platform | |
1226 | * firmware has its own power management modes. | |
1227 | */ | |
1228 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
1229 | return -ENODEV; | |
1230 | ||
64df1fdf | 1231 | cpu_def = (struct cpu_defaults *)id->driver_data; |
016c8150 | 1232 | |
64df1fdf BP |
1233 | copy_pid_params(&cpu_def->pid_policy); |
1234 | copy_cpu_funcs(&cpu_def->funcs); | |
016c8150 | 1235 | |
b563b4e3 DB |
1236 | if (intel_pstate_msrs_not_valid()) |
1237 | return -ENODEV; | |
1238 | ||
93f0822d DB |
1239 | pr_info("Intel P-state driver initializing.\n"); |
1240 | ||
b57ffac5 | 1241 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
1242 | if (!all_cpu_data) |
1243 | return -ENOMEM; | |
93f0822d | 1244 | |
64df1fdf | 1245 | if (static_cpu_has_safe(X86_FEATURE_HWP) && !no_hwp) |
2f86dc4c DB |
1246 | intel_pstate_hwp_enable(); |
1247 | ||
d64c3b0b KCA |
1248 | if (!hwp_active && hwp_only) |
1249 | goto out; | |
1250 | ||
93f0822d DB |
1251 | rc = cpufreq_register_driver(&intel_pstate_driver); |
1252 | if (rc) | |
1253 | goto out; | |
1254 | ||
1255 | intel_pstate_debug_expose_params(); | |
1256 | intel_pstate_sysfs_expose_params(); | |
b69880f9 | 1257 | |
93f0822d DB |
1258 | return rc; |
1259 | out: | |
907cc908 DB |
1260 | get_online_cpus(); |
1261 | for_each_online_cpu(cpu) { | |
1262 | if (all_cpu_data[cpu]) { | |
1263 | del_timer_sync(&all_cpu_data[cpu]->timer); | |
1264 | kfree(all_cpu_data[cpu]); | |
1265 | } | |
1266 | } | |
1267 | ||
1268 | put_online_cpus(); | |
1269 | vfree(all_cpu_data); | |
93f0822d DB |
1270 | return -ENODEV; |
1271 | } | |
1272 | device_initcall(intel_pstate_init); | |
1273 | ||
6be26498 DB |
1274 | static int __init intel_pstate_setup(char *str) |
1275 | { | |
1276 | if (!str) | |
1277 | return -EINVAL; | |
1278 | ||
1279 | if (!strcmp(str, "disable")) | |
1280 | no_load = 1; | |
2f86dc4c DB |
1281 | if (!strcmp(str, "no_hwp")) |
1282 | no_hwp = 1; | |
aa4ea34d EZ |
1283 | if (!strcmp(str, "force")) |
1284 | force_load = 1; | |
d64c3b0b KCA |
1285 | if (!strcmp(str, "hwp_only")) |
1286 | hwp_only = 1; | |
6be26498 DB |
1287 | return 0; |
1288 | } | |
1289 | early_param("intel_pstate", intel_pstate_setup); | |
1290 | ||
93f0822d DB |
1291 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
1292 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
1293 | MODULE_LICENSE("GPL"); |