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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
4836df17 JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
93f0822d DB |
15 | #include <linux/kernel.h> |
16 | #include <linux/kernel_stat.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/ktime.h> | |
19 | #include <linux/hrtimer.h> | |
20 | #include <linux/tick.h> | |
21 | #include <linux/slab.h> | |
55687da1 | 22 | #include <linux/sched/cpufreq.h> |
93f0822d DB |
23 | #include <linux/list.h> |
24 | #include <linux/cpu.h> | |
25 | #include <linux/cpufreq.h> | |
26 | #include <linux/sysfs.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/fs.h> | |
29 | #include <linux/debugfs.h> | |
fbbcdc07 | 30 | #include <linux/acpi.h> |
d6472302 | 31 | #include <linux/vmalloc.h> |
93f0822d DB |
32 | #include <trace/events/power.h> |
33 | ||
34 | #include <asm/div64.h> | |
35 | #include <asm/msr.h> | |
36 | #include <asm/cpu_device_id.h> | |
64df1fdf | 37 | #include <asm/cpufeature.h> |
5b20c944 | 38 | #include <asm/intel-family.h> |
93f0822d | 39 | |
001c76f0 RW |
40 | #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 |
41 | ||
9522a2ff SP |
42 | #ifdef CONFIG_ACPI |
43 | #include <acpi/processor.h> | |
17669006 | 44 | #include <acpi/cppc_acpi.h> |
9522a2ff SP |
45 | #endif |
46 | ||
f0fe3cd7 | 47 | #define FRAC_BITS 8 |
93f0822d DB |
48 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
49 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
f0fe3cd7 | 50 | |
a1c9787d RW |
51 | #define EXT_BITS 6 |
52 | #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) | |
d5dd33d9 SP |
53 | #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) |
54 | #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) | |
a1c9787d | 55 | |
93f0822d DB |
56 | static inline int32_t mul_fp(int32_t x, int32_t y) |
57 | { | |
58 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
59 | } | |
60 | ||
7180dddf | 61 | static inline int32_t div_fp(s64 x, s64 y) |
93f0822d | 62 | { |
7180dddf | 63 | return div64_s64((int64_t)x << FRAC_BITS, y); |
93f0822d DB |
64 | } |
65 | ||
d022a65e DB |
66 | static inline int ceiling_fp(int32_t x) |
67 | { | |
68 | int mask, ret; | |
69 | ||
70 | ret = fp_toint(x); | |
71 | mask = (1 << FRAC_BITS) - 1; | |
72 | if (x & mask) | |
73 | ret += 1; | |
74 | return ret; | |
75 | } | |
76 | ||
a1c9787d RW |
77 | static inline u64 mul_ext_fp(u64 x, u64 y) |
78 | { | |
79 | return (x * y) >> EXT_FRAC_BITS; | |
80 | } | |
81 | ||
82 | static inline u64 div_ext_fp(u64 x, u64 y) | |
83 | { | |
84 | return div64_u64(x << EXT_FRAC_BITS, y); | |
85 | } | |
86 | ||
e4c204ce RW |
87 | static inline int32_t percent_ext_fp(int percent) |
88 | { | |
89 | return div_ext_fp(percent, 100); | |
90 | } | |
91 | ||
13ad7701 SP |
92 | /** |
93 | * struct sample - Store performance sample | |
a1c9787d | 94 | * @core_avg_perf: Ratio of APERF/MPERF which is the actual average |
13ad7701 SP |
95 | * performance during last sample period |
96 | * @busy_scaled: Scaled busy value which is used to calculate next | |
a1c9787d | 97 | * P state. This can be different than core_avg_perf |
13ad7701 SP |
98 | * to account for cpu idle period |
99 | * @aperf: Difference of actual performance frequency clock count | |
100 | * read from APERF MSR between last and current sample | |
101 | * @mperf: Difference of maximum performance frequency clock count | |
102 | * read from MPERF MSR between last and current sample | |
103 | * @tsc: Difference of time stamp counter between last and | |
104 | * current sample | |
13ad7701 SP |
105 | * @time: Current time from scheduler |
106 | * | |
107 | * This structure is used in the cpudata structure to store performance sample | |
108 | * data for choosing next P State. | |
109 | */ | |
93f0822d | 110 | struct sample { |
a1c9787d | 111 | int32_t core_avg_perf; |
157386b6 | 112 | int32_t busy_scaled; |
93f0822d DB |
113 | u64 aperf; |
114 | u64 mperf; | |
4055fad3 | 115 | u64 tsc; |
a4675fbc | 116 | u64 time; |
93f0822d DB |
117 | }; |
118 | ||
13ad7701 SP |
119 | /** |
120 | * struct pstate_data - Store P state data | |
121 | * @current_pstate: Current requested P state | |
122 | * @min_pstate: Min P state possible for this platform | |
123 | * @max_pstate: Max P state possible for this platform | |
124 | * @max_pstate_physical:This is physical Max P state for a processor | |
125 | * This can be higher than the max_pstate which can | |
126 | * be limited by platform thermal design power limits | |
127 | * @scaling: Scaling factor to convert frequency to cpufreq | |
128 | * frequency units | |
129 | * @turbo_pstate: Max Turbo P state possible for this platform | |
001c76f0 RW |
130 | * @max_freq: @max_pstate frequency in cpufreq units |
131 | * @turbo_freq: @turbo_pstate frequency in cpufreq units | |
13ad7701 SP |
132 | * |
133 | * Stores the per cpu model P state limits and current P state. | |
134 | */ | |
93f0822d DB |
135 | struct pstate_data { |
136 | int current_pstate; | |
137 | int min_pstate; | |
138 | int max_pstate; | |
3bcc6fa9 | 139 | int max_pstate_physical; |
b27580b0 | 140 | int scaling; |
93f0822d | 141 | int turbo_pstate; |
001c76f0 RW |
142 | unsigned int max_freq; |
143 | unsigned int turbo_freq; | |
93f0822d DB |
144 | }; |
145 | ||
13ad7701 SP |
146 | /** |
147 | * struct vid_data - Stores voltage information data | |
148 | * @min: VID data for this platform corresponding to | |
149 | * the lowest P state | |
150 | * @max: VID data corresponding to the highest P State. | |
151 | * @turbo: VID data for turbo P state | |
152 | * @ratio: Ratio of (vid max - vid min) / | |
153 | * (max P state - Min P State) | |
154 | * | |
155 | * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) | |
156 | * This data is used in Atom platforms, where in addition to target P state, | |
157 | * the voltage data needs to be specified to select next P State. | |
158 | */ | |
007bea09 | 159 | struct vid_data { |
21855ff5 DB |
160 | int min; |
161 | int max; | |
162 | int turbo; | |
007bea09 DB |
163 | int32_t ratio; |
164 | }; | |
165 | ||
13ad7701 SP |
166 | /** |
167 | * struct _pid - Stores PID data | |
168 | * @setpoint: Target set point for busyness or performance | |
169 | * @integral: Storage for accumulated error values | |
170 | * @p_gain: PID proportional gain | |
171 | * @i_gain: PID integral gain | |
172 | * @d_gain: PID derivative gain | |
173 | * @deadband: PID deadband | |
174 | * @last_err: Last error storage for integral part of PID calculation | |
175 | * | |
176 | * Stores PID coefficients and last error for PID controller. | |
177 | */ | |
93f0822d DB |
178 | struct _pid { |
179 | int setpoint; | |
180 | int32_t integral; | |
181 | int32_t p_gain; | |
182 | int32_t i_gain; | |
183 | int32_t d_gain; | |
184 | int deadband; | |
d253d2a5 | 185 | int32_t last_err; |
93f0822d DB |
186 | }; |
187 | ||
c5a2ee7d RW |
188 | /** |
189 | * struct global_params - Global parameters, mostly tunable via sysfs. | |
190 | * @no_turbo: Whether or not to use turbo P-states. | |
191 | * @turbo_disabled: Whethet or not turbo P-states are available at all, | |
192 | * based on the MSR_IA32_MISC_ENABLE value and whether or | |
193 | * not the maximum reported turbo P-state is different from | |
194 | * the maximum reported non-turbo one. | |
195 | * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo | |
196 | * P-state capacity. | |
197 | * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo | |
198 | * P-state capacity. | |
199 | */ | |
200 | struct global_params { | |
201 | bool no_turbo; | |
202 | bool turbo_disabled; | |
203 | int max_perf_pct; | |
204 | int min_perf_pct; | |
eae48f04 SP |
205 | }; |
206 | ||
13ad7701 SP |
207 | /** |
208 | * struct cpudata - Per CPU instance data storage | |
209 | * @cpu: CPU number for this instance data | |
2f1d407a | 210 | * @policy: CPUFreq policy value |
13ad7701 | 211 | * @update_util: CPUFreq utility callback information |
4578ee7e | 212 | * @update_util_set: CPUFreq utility callback is set |
09c448d3 RW |
213 | * @iowait_boost: iowait-related boost fraction |
214 | * @last_update: Time of the last update. | |
13ad7701 SP |
215 | * @pstate: Stores P state limits for this CPU |
216 | * @vid: Stores VID limits for this CPU | |
217 | * @pid: Stores PID parameters for this CPU | |
218 | * @last_sample_time: Last Sample time | |
219 | * @prev_aperf: Last APERF value read from APERF MSR | |
220 | * @prev_mperf: Last MPERF value read from MPERF MSR | |
221 | * @prev_tsc: Last timestamp counter (TSC) value | |
222 | * @prev_cummulative_iowait: IO Wait time difference from last and | |
223 | * current sample | |
224 | * @sample: Storage for storing last Sample data | |
e14cf885 RW |
225 | * @min_perf: Minimum capacity limit as a fraction of the maximum |
226 | * turbo P-state capacity. | |
227 | * @max_perf: Maximum capacity limit as a fraction of the maximum | |
228 | * turbo P-state capacity. | |
9522a2ff SP |
229 | * @acpi_perf_data: Stores ACPI perf information read from _PSS |
230 | * @valid_pss_table: Set to true for valid ACPI _PSS entries found | |
984edbdc SP |
231 | * @epp_powersave: Last saved HWP energy performance preference |
232 | * (EPP) or energy performance bias (EPB), | |
233 | * when policy switched to performance | |
8442885f | 234 | * @epp_policy: Last saved policy used to set EPP/EPB |
984edbdc SP |
235 | * @epp_default: Power on default HWP energy performance |
236 | * preference/bias | |
237 | * @epp_saved: Saved EPP/EPB during system suspend or CPU offline | |
238 | * operation | |
13ad7701 SP |
239 | * |
240 | * This structure stores per CPU instance data for all CPUs. | |
241 | */ | |
93f0822d DB |
242 | struct cpudata { |
243 | int cpu; | |
244 | ||
2f1d407a | 245 | unsigned int policy; |
a4675fbc | 246 | struct update_util_data update_util; |
4578ee7e | 247 | bool update_util_set; |
93f0822d | 248 | |
93f0822d | 249 | struct pstate_data pstate; |
007bea09 | 250 | struct vid_data vid; |
93f0822d | 251 | struct _pid pid; |
93f0822d | 252 | |
09c448d3 | 253 | u64 last_update; |
a4675fbc | 254 | u64 last_sample_time; |
93f0822d DB |
255 | u64 prev_aperf; |
256 | u64 prev_mperf; | |
4055fad3 | 257 | u64 prev_tsc; |
63d1d656 | 258 | u64 prev_cummulative_iowait; |
d37e2b76 | 259 | struct sample sample; |
e14cf885 RW |
260 | int32_t min_perf; |
261 | int32_t max_perf; | |
9522a2ff SP |
262 | #ifdef CONFIG_ACPI |
263 | struct acpi_processor_performance acpi_perf_data; | |
264 | bool valid_pss_table; | |
265 | #endif | |
09c448d3 | 266 | unsigned int iowait_boost; |
984edbdc | 267 | s16 epp_powersave; |
8442885f | 268 | s16 epp_policy; |
984edbdc SP |
269 | s16 epp_default; |
270 | s16 epp_saved; | |
93f0822d DB |
271 | }; |
272 | ||
273 | static struct cpudata **all_cpu_data; | |
13ad7701 SP |
274 | |
275 | /** | |
3954517e | 276 | * struct pstate_adjust_policy - Stores static PID configuration data |
13ad7701 SP |
277 | * @sample_rate_ms: PID calculation sample rate in ms |
278 | * @sample_rate_ns: Sample rate calculation in ns | |
279 | * @deadband: PID deadband | |
280 | * @setpoint: PID Setpoint | |
281 | * @p_gain_pct: PID proportional gain | |
282 | * @i_gain_pct: PID integral gain | |
283 | * @d_gain_pct: PID derivative gain | |
284 | * | |
285 | * Stores per CPU model static PID configuration data. | |
286 | */ | |
93f0822d DB |
287 | struct pstate_adjust_policy { |
288 | int sample_rate_ms; | |
a4675fbc | 289 | s64 sample_rate_ns; |
93f0822d DB |
290 | int deadband; |
291 | int setpoint; | |
292 | int p_gain_pct; | |
293 | int d_gain_pct; | |
294 | int i_gain_pct; | |
295 | }; | |
296 | ||
13ad7701 SP |
297 | /** |
298 | * struct pstate_funcs - Per CPU model specific callbacks | |
299 | * @get_max: Callback to get maximum non turbo effective P state | |
300 | * @get_max_physical: Callback to get maximum non turbo physical P state | |
301 | * @get_min: Callback to get minimum P state | |
302 | * @get_turbo: Callback to get turbo P state | |
303 | * @get_scaling: Callback to get frequency scaling factor | |
304 | * @get_val: Callback to convert P state to actual MSR write value | |
305 | * @get_vid: Callback to get VID data for Atom platforms | |
306 | * @get_target_pstate: Callback to a function to calculate next P state to use | |
307 | * | |
308 | * Core and Atom CPU models have different way to get P State limits. This | |
309 | * structure is used to store those callbacks. | |
310 | */ | |
016c8150 DB |
311 | struct pstate_funcs { |
312 | int (*get_max)(void); | |
3bcc6fa9 | 313 | int (*get_max_physical)(void); |
016c8150 DB |
314 | int (*get_min)(void); |
315 | int (*get_turbo)(void); | |
b27580b0 | 316 | int (*get_scaling)(void); |
fdfdb2b1 | 317 | u64 (*get_val)(struct cpudata*, int pstate); |
007bea09 | 318 | void (*get_vid)(struct cpudata *); |
157386b6 | 319 | int32_t (*get_target_pstate)(struct cpudata *); |
93f0822d DB |
320 | }; |
321 | ||
13ad7701 SP |
322 | /** |
323 | * struct cpu_defaults- Per CPU model default config data | |
13ad7701 SP |
324 | * @funcs: Callback function data |
325 | */ | |
016c8150 | 326 | struct cpu_defaults { |
016c8150 | 327 | struct pstate_funcs funcs; |
93f0822d DB |
328 | }; |
329 | ||
157386b6 | 330 | static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu); |
e70eed2b | 331 | static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu); |
157386b6 | 332 | |
4a7cb7a9 | 333 | static struct pstate_funcs pstate_funcs __read_mostly; |
5c439053 RW |
334 | static struct pstate_adjust_policy pid_params __read_mostly = { |
335 | .sample_rate_ms = 10, | |
336 | .sample_rate_ns = 10 * NSEC_PER_MSEC, | |
337 | .deadband = 0, | |
338 | .setpoint = 97, | |
339 | .p_gain_pct = 20, | |
340 | .d_gain_pct = 0, | |
341 | .i_gain_pct = 0, | |
342 | }; | |
343 | ||
4a7cb7a9 | 344 | static int hwp_active __read_mostly; |
eae48f04 | 345 | static bool per_cpu_limits __read_mostly; |
016c8150 | 346 | |
0c30b65b RW |
347 | static bool driver_registered __read_mostly; |
348 | ||
9522a2ff SP |
349 | #ifdef CONFIG_ACPI |
350 | static bool acpi_ppc; | |
351 | #endif | |
13ad7701 | 352 | |
c5a2ee7d | 353 | static struct global_params global; |
93f0822d | 354 | |
0c30b65b | 355 | static DEFINE_MUTEX(intel_pstate_driver_lock); |
a410c03d SP |
356 | static DEFINE_MUTEX(intel_pstate_limits_lock); |
357 | ||
9522a2ff | 358 | #ifdef CONFIG_ACPI |
2b3ec765 SP |
359 | |
360 | static bool intel_pstate_get_ppc_enable_status(void) | |
361 | { | |
362 | if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || | |
363 | acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) | |
364 | return true; | |
365 | ||
366 | return acpi_ppc; | |
367 | } | |
368 | ||
17669006 RW |
369 | #ifdef CONFIG_ACPI_CPPC_LIB |
370 | ||
371 | /* The work item is needed to avoid CPU hotplug locking issues */ | |
372 | static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) | |
373 | { | |
374 | sched_set_itmt_support(); | |
375 | } | |
376 | ||
377 | static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); | |
378 | ||
379 | static void intel_pstate_set_itmt_prio(int cpu) | |
380 | { | |
381 | struct cppc_perf_caps cppc_perf; | |
382 | static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; | |
383 | int ret; | |
384 | ||
385 | ret = cppc_get_perf_caps(cpu, &cppc_perf); | |
386 | if (ret) | |
387 | return; | |
388 | ||
389 | /* | |
390 | * The priorities can be set regardless of whether or not | |
391 | * sched_set_itmt_support(true) has been called and it is valid to | |
392 | * update them at any time after it has been called. | |
393 | */ | |
394 | sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); | |
395 | ||
396 | if (max_highest_perf <= min_highest_perf) { | |
397 | if (cppc_perf.highest_perf > max_highest_perf) | |
398 | max_highest_perf = cppc_perf.highest_perf; | |
399 | ||
400 | if (cppc_perf.highest_perf < min_highest_perf) | |
401 | min_highest_perf = cppc_perf.highest_perf; | |
402 | ||
403 | if (max_highest_perf > min_highest_perf) { | |
404 | /* | |
405 | * This code can be run during CPU online under the | |
406 | * CPU hotplug locks, so sched_set_itmt_support() | |
407 | * cannot be called from here. Queue up a work item | |
408 | * to invoke it. | |
409 | */ | |
410 | schedule_work(&sched_itmt_work); | |
411 | } | |
412 | } | |
413 | } | |
414 | #else | |
415 | static void intel_pstate_set_itmt_prio(int cpu) | |
416 | { | |
417 | } | |
418 | #endif | |
419 | ||
9522a2ff SP |
420 | static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) |
421 | { | |
422 | struct cpudata *cpu; | |
9522a2ff SP |
423 | int ret; |
424 | int i; | |
425 | ||
17669006 RW |
426 | if (hwp_active) { |
427 | intel_pstate_set_itmt_prio(policy->cpu); | |
e59a8f7f | 428 | return; |
17669006 | 429 | } |
e59a8f7f | 430 | |
2b3ec765 | 431 | if (!intel_pstate_get_ppc_enable_status()) |
9522a2ff SP |
432 | return; |
433 | ||
434 | cpu = all_cpu_data[policy->cpu]; | |
435 | ||
436 | ret = acpi_processor_register_performance(&cpu->acpi_perf_data, | |
437 | policy->cpu); | |
438 | if (ret) | |
439 | return; | |
440 | ||
441 | /* | |
442 | * Check if the control value in _PSS is for PERF_CTL MSR, which should | |
443 | * guarantee that the states returned by it map to the states in our | |
444 | * list directly. | |
445 | */ | |
446 | if (cpu->acpi_perf_data.control_register.space_id != | |
447 | ACPI_ADR_SPACE_FIXED_HARDWARE) | |
448 | goto err; | |
449 | ||
450 | /* | |
451 | * If there is only one entry _PSS, simply ignore _PSS and continue as | |
452 | * usual without taking _PSS into account | |
453 | */ | |
454 | if (cpu->acpi_perf_data.state_count < 2) | |
455 | goto err; | |
456 | ||
457 | pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); | |
458 | for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { | |
459 | pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", | |
460 | (i == cpu->acpi_perf_data.state ? '*' : ' '), i, | |
461 | (u32) cpu->acpi_perf_data.states[i].core_frequency, | |
462 | (u32) cpu->acpi_perf_data.states[i].power, | |
463 | (u32) cpu->acpi_perf_data.states[i].control); | |
464 | } | |
465 | ||
466 | /* | |
467 | * The _PSS table doesn't contain whole turbo frequency range. | |
468 | * This just contains +1 MHZ above the max non turbo frequency, | |
469 | * with control value corresponding to max turbo ratio. But | |
470 | * when cpufreq set policy is called, it will call with this | |
471 | * max frequency, which will cause a reduced performance as | |
472 | * this driver uses real max turbo frequency as the max | |
473 | * frequency. So correct this frequency in _PSS table to | |
b00345d1 | 474 | * correct max turbo frequency based on the turbo state. |
9522a2ff SP |
475 | * Also need to convert to MHz as _PSS freq is in MHz. |
476 | */ | |
7de32556 | 477 | if (!global.turbo_disabled) |
9522a2ff SP |
478 | cpu->acpi_perf_data.states[0].core_frequency = |
479 | policy->cpuinfo.max_freq / 1000; | |
480 | cpu->valid_pss_table = true; | |
6cacd115 | 481 | pr_debug("_PPC limits will be enforced\n"); |
9522a2ff SP |
482 | |
483 | return; | |
484 | ||
485 | err: | |
486 | cpu->valid_pss_table = false; | |
487 | acpi_processor_unregister_performance(policy->cpu); | |
488 | } | |
489 | ||
490 | static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) | |
491 | { | |
492 | struct cpudata *cpu; | |
493 | ||
494 | cpu = all_cpu_data[policy->cpu]; | |
495 | if (!cpu->valid_pss_table) | |
496 | return; | |
497 | ||
498 | acpi_processor_unregister_performance(policy->cpu); | |
499 | } | |
9522a2ff | 500 | #else |
7a3ba767 | 501 | static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) |
9522a2ff SP |
502 | { |
503 | } | |
504 | ||
7a3ba767 | 505 | static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) |
9522a2ff SP |
506 | { |
507 | } | |
508 | #endif | |
509 | ||
93f0822d | 510 | static inline void pid_reset(struct _pid *pid, int setpoint, int busy, |
c410833a | 511 | int deadband, int integral) { |
b54a0dfd PL |
512 | pid->setpoint = int_tofp(setpoint); |
513 | pid->deadband = int_tofp(deadband); | |
93f0822d | 514 | pid->integral = int_tofp(integral); |
d98d099b | 515 | pid->last_err = int_tofp(setpoint) - int_tofp(busy); |
93f0822d DB |
516 | } |
517 | ||
518 | static inline void pid_p_gain_set(struct _pid *pid, int percent) | |
519 | { | |
22590efb | 520 | pid->p_gain = div_fp(percent, 100); |
93f0822d DB |
521 | } |
522 | ||
523 | static inline void pid_i_gain_set(struct _pid *pid, int percent) | |
524 | { | |
22590efb | 525 | pid->i_gain = div_fp(percent, 100); |
93f0822d DB |
526 | } |
527 | ||
528 | static inline void pid_d_gain_set(struct _pid *pid, int percent) | |
529 | { | |
22590efb | 530 | pid->d_gain = div_fp(percent, 100); |
93f0822d DB |
531 | } |
532 | ||
d253d2a5 | 533 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 534 | { |
d253d2a5 | 535 | signed int result; |
93f0822d DB |
536 | int32_t pterm, dterm, fp_error; |
537 | int32_t integral_limit; | |
538 | ||
b54a0dfd | 539 | fp_error = pid->setpoint - busy; |
93f0822d | 540 | |
b54a0dfd | 541 | if (abs(fp_error) <= pid->deadband) |
93f0822d DB |
542 | return 0; |
543 | ||
544 | pterm = mul_fp(pid->p_gain, fp_error); | |
545 | ||
546 | pid->integral += fp_error; | |
547 | ||
e0d4c8f8 KCA |
548 | /* |
549 | * We limit the integral here so that it will never | |
550 | * get higher than 30. This prevents it from becoming | |
551 | * too large an input over long periods of time and allows | |
552 | * it to get factored out sooner. | |
553 | * | |
554 | * The value of 30 was chosen through experimentation. | |
555 | */ | |
93f0822d DB |
556 | integral_limit = int_tofp(30); |
557 | if (pid->integral > integral_limit) | |
558 | pid->integral = integral_limit; | |
559 | if (pid->integral < -integral_limit) | |
560 | pid->integral = -integral_limit; | |
561 | ||
d253d2a5 BS |
562 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
563 | pid->last_err = fp_error; | |
93f0822d DB |
564 | |
565 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
51d211e9 | 566 | result = result + (1 << (FRAC_BITS-1)); |
93f0822d DB |
567 | return (signed int)fp_toint(result); |
568 | } | |
569 | ||
570 | static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) | |
571 | { | |
016c8150 DB |
572 | pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); |
573 | pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); | |
574 | pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); | |
93f0822d | 575 | |
2d8d1f18 | 576 | pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); |
93f0822d DB |
577 | } |
578 | ||
4521e1a0 GM |
579 | static inline void update_turbo_state(void) |
580 | { | |
581 | u64 misc_en; | |
582 | struct cpudata *cpu; | |
583 | ||
584 | cpu = all_cpu_data[0]; | |
585 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); | |
7de32556 | 586 | global.turbo_disabled = |
4521e1a0 GM |
587 | (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || |
588 | cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); | |
589 | } | |
590 | ||
c5a2ee7d RW |
591 | static int min_perf_pct_min(void) |
592 | { | |
593 | struct cpudata *cpu = all_cpu_data[0]; | |
594 | ||
595 | return DIV_ROUND_UP(cpu->pstate.min_pstate * 100, | |
596 | cpu->pstate.turbo_pstate); | |
597 | } | |
598 | ||
8442885f SP |
599 | static s16 intel_pstate_get_epb(struct cpudata *cpu_data) |
600 | { | |
601 | u64 epb; | |
602 | int ret; | |
603 | ||
604 | if (!static_cpu_has(X86_FEATURE_EPB)) | |
605 | return -ENXIO; | |
606 | ||
607 | ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); | |
608 | if (ret) | |
609 | return (s16)ret; | |
610 | ||
611 | return (s16)(epb & 0x0f); | |
612 | } | |
613 | ||
614 | static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) | |
615 | { | |
616 | s16 epp; | |
617 | ||
984edbdc SP |
618 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { |
619 | /* | |
620 | * When hwp_req_data is 0, means that caller didn't read | |
621 | * MSR_HWP_REQUEST, so need to read and get EPP. | |
622 | */ | |
623 | if (!hwp_req_data) { | |
624 | epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, | |
625 | &hwp_req_data); | |
626 | if (epp) | |
627 | return epp; | |
628 | } | |
8442885f | 629 | epp = (hwp_req_data >> 24) & 0xff; |
984edbdc | 630 | } else { |
8442885f SP |
631 | /* When there is no EPP present, HWP uses EPB settings */ |
632 | epp = intel_pstate_get_epb(cpu_data); | |
984edbdc | 633 | } |
8442885f SP |
634 | |
635 | return epp; | |
636 | } | |
637 | ||
984edbdc | 638 | static int intel_pstate_set_epb(int cpu, s16 pref) |
8442885f SP |
639 | { |
640 | u64 epb; | |
984edbdc | 641 | int ret; |
8442885f SP |
642 | |
643 | if (!static_cpu_has(X86_FEATURE_EPB)) | |
984edbdc | 644 | return -ENXIO; |
8442885f | 645 | |
984edbdc SP |
646 | ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); |
647 | if (ret) | |
648 | return ret; | |
8442885f SP |
649 | |
650 | epb = (epb & ~0x0f) | pref; | |
651 | wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); | |
984edbdc SP |
652 | |
653 | return 0; | |
8442885f SP |
654 | } |
655 | ||
984edbdc SP |
656 | /* |
657 | * EPP/EPB display strings corresponding to EPP index in the | |
658 | * energy_perf_strings[] | |
659 | * index String | |
660 | *------------------------------------- | |
661 | * 0 default | |
662 | * 1 performance | |
663 | * 2 balance_performance | |
664 | * 3 balance_power | |
665 | * 4 power | |
666 | */ | |
667 | static const char * const energy_perf_strings[] = { | |
668 | "default", | |
669 | "performance", | |
670 | "balance_performance", | |
671 | "balance_power", | |
672 | "power", | |
673 | NULL | |
674 | }; | |
675 | ||
676 | static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data) | |
677 | { | |
678 | s16 epp; | |
679 | int index = -EINVAL; | |
680 | ||
681 | epp = intel_pstate_get_epp(cpu_data, 0); | |
682 | if (epp < 0) | |
683 | return epp; | |
684 | ||
685 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { | |
686 | /* | |
687 | * Range: | |
688 | * 0x00-0x3F : Performance | |
689 | * 0x40-0x7F : Balance performance | |
690 | * 0x80-0xBF : Balance power | |
691 | * 0xC0-0xFF : Power | |
692 | * The EPP is a 8 bit value, but our ranges restrict the | |
693 | * value which can be set. Here only using top two bits | |
694 | * effectively. | |
695 | */ | |
696 | index = (epp >> 6) + 1; | |
697 | } else if (static_cpu_has(X86_FEATURE_EPB)) { | |
698 | /* | |
699 | * Range: | |
700 | * 0x00-0x03 : Performance | |
701 | * 0x04-0x07 : Balance performance | |
702 | * 0x08-0x0B : Balance power | |
703 | * 0x0C-0x0F : Power | |
704 | * The EPB is a 4 bit value, but our ranges restrict the | |
705 | * value which can be set. Here only using top two bits | |
706 | * effectively. | |
707 | */ | |
708 | index = (epp >> 2) + 1; | |
709 | } | |
710 | ||
711 | return index; | |
712 | } | |
713 | ||
714 | static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, | |
715 | int pref_index) | |
716 | { | |
717 | int epp = -EINVAL; | |
718 | int ret; | |
719 | ||
720 | if (!pref_index) | |
721 | epp = cpu_data->epp_default; | |
722 | ||
723 | mutex_lock(&intel_pstate_limits_lock); | |
724 | ||
725 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { | |
726 | u64 value; | |
727 | ||
728 | ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value); | |
729 | if (ret) | |
730 | goto return_pref; | |
731 | ||
732 | value &= ~GENMASK_ULL(31, 24); | |
733 | ||
734 | /* | |
735 | * If epp is not default, convert from index into | |
736 | * energy_perf_strings to epp value, by shifting 6 | |
737 | * bits left to use only top two bits in epp. | |
738 | * The resultant epp need to shifted by 24 bits to | |
739 | * epp position in MSR_HWP_REQUEST. | |
740 | */ | |
741 | if (epp == -EINVAL) | |
742 | epp = (pref_index - 1) << 6; | |
743 | ||
744 | value |= (u64)epp << 24; | |
745 | ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value); | |
746 | } else { | |
747 | if (epp == -EINVAL) | |
748 | epp = (pref_index - 1) << 2; | |
749 | ret = intel_pstate_set_epb(cpu_data->cpu, epp); | |
750 | } | |
751 | return_pref: | |
752 | mutex_unlock(&intel_pstate_limits_lock); | |
753 | ||
754 | return ret; | |
755 | } | |
756 | ||
757 | static ssize_t show_energy_performance_available_preferences( | |
758 | struct cpufreq_policy *policy, char *buf) | |
759 | { | |
760 | int i = 0; | |
761 | int ret = 0; | |
762 | ||
763 | while (energy_perf_strings[i] != NULL) | |
764 | ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); | |
765 | ||
766 | ret += sprintf(&buf[ret], "\n"); | |
767 | ||
768 | return ret; | |
769 | } | |
770 | ||
771 | cpufreq_freq_attr_ro(energy_performance_available_preferences); | |
772 | ||
773 | static ssize_t store_energy_performance_preference( | |
774 | struct cpufreq_policy *policy, const char *buf, size_t count) | |
775 | { | |
776 | struct cpudata *cpu_data = all_cpu_data[policy->cpu]; | |
777 | char str_preference[21]; | |
778 | int ret, i = 0; | |
779 | ||
780 | ret = sscanf(buf, "%20s", str_preference); | |
781 | if (ret != 1) | |
782 | return -EINVAL; | |
783 | ||
784 | while (energy_perf_strings[i] != NULL) { | |
785 | if (!strcmp(str_preference, energy_perf_strings[i])) { | |
786 | intel_pstate_set_energy_pref_index(cpu_data, i); | |
787 | return count; | |
788 | } | |
789 | ++i; | |
790 | } | |
791 | ||
792 | return -EINVAL; | |
793 | } | |
794 | ||
795 | static ssize_t show_energy_performance_preference( | |
796 | struct cpufreq_policy *policy, char *buf) | |
797 | { | |
798 | struct cpudata *cpu_data = all_cpu_data[policy->cpu]; | |
799 | int preference; | |
800 | ||
801 | preference = intel_pstate_get_energy_pref_index(cpu_data); | |
802 | if (preference < 0) | |
803 | return preference; | |
804 | ||
805 | return sprintf(buf, "%s\n", energy_perf_strings[preference]); | |
806 | } | |
807 | ||
808 | cpufreq_freq_attr_rw(energy_performance_preference); | |
809 | ||
810 | static struct freq_attr *hwp_cpufreq_attrs[] = { | |
811 | &energy_performance_preference, | |
812 | &energy_performance_available_preferences, | |
813 | NULL, | |
814 | }; | |
815 | ||
111b8b3f | 816 | static void intel_pstate_hwp_set(struct cpufreq_policy *policy) |
2f86dc4c | 817 | { |
3f8ed54a | 818 | int min, hw_min, max, hw_max, cpu; |
74da56ce KCA |
819 | u64 value, cap; |
820 | ||
111b8b3f | 821 | for_each_cpu(cpu, policy->cpus) { |
8442885f SP |
822 | struct cpudata *cpu_data = all_cpu_data[cpu]; |
823 | s16 epp; | |
eae48f04 | 824 | |
f9f4872d SP |
825 | rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap); |
826 | hw_min = HWP_LOWEST_PERF(cap); | |
7de32556 | 827 | if (global.no_turbo) |
4e5d3f71 SP |
828 | hw_max = HWP_GUARANTEED_PERF(cap); |
829 | else | |
830 | hw_max = HWP_HIGHEST_PERF(cap); | |
f9f4872d | 831 | |
e14cf885 | 832 | max = fp_ext_toint(hw_max * cpu_data->max_perf); |
7de32556 RW |
833 | if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) |
834 | min = max; | |
835 | else | |
e14cf885 | 836 | min = fp_ext_toint(hw_max * cpu_data->min_perf); |
eae48f04 | 837 | |
2f86dc4c | 838 | rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); |
3f8ed54a | 839 | |
2f86dc4c DB |
840 | value &= ~HWP_MIN_PERF(~0L); |
841 | value |= HWP_MIN_PERF(min); | |
842 | ||
2f86dc4c DB |
843 | value &= ~HWP_MAX_PERF(~0L); |
844 | value |= HWP_MAX_PERF(max); | |
8442885f SP |
845 | |
846 | if (cpu_data->epp_policy == cpu_data->policy) | |
847 | goto skip_epp; | |
848 | ||
849 | cpu_data->epp_policy = cpu_data->policy; | |
850 | ||
984edbdc SP |
851 | if (cpu_data->epp_saved >= 0) { |
852 | epp = cpu_data->epp_saved; | |
853 | cpu_data->epp_saved = -EINVAL; | |
854 | goto update_epp; | |
855 | } | |
856 | ||
8442885f SP |
857 | if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { |
858 | epp = intel_pstate_get_epp(cpu_data, value); | |
984edbdc | 859 | cpu_data->epp_powersave = epp; |
8442885f | 860 | /* If EPP read was failed, then don't try to write */ |
984edbdc | 861 | if (epp < 0) |
8442885f | 862 | goto skip_epp; |
8442885f | 863 | |
8442885f SP |
864 | |
865 | epp = 0; | |
866 | } else { | |
867 | /* skip setting EPP, when saved value is invalid */ | |
984edbdc | 868 | if (cpu_data->epp_powersave < 0) |
8442885f SP |
869 | goto skip_epp; |
870 | ||
871 | /* | |
872 | * No need to restore EPP when it is not zero. This | |
873 | * means: | |
874 | * - Policy is not changed | |
875 | * - user has manually changed | |
876 | * - Error reading EPB | |
877 | */ | |
878 | epp = intel_pstate_get_epp(cpu_data, value); | |
879 | if (epp) | |
880 | goto skip_epp; | |
881 | ||
984edbdc | 882 | epp = cpu_data->epp_powersave; |
8442885f | 883 | } |
984edbdc | 884 | update_epp: |
8442885f SP |
885 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { |
886 | value &= ~GENMASK_ULL(31, 24); | |
887 | value |= (u64)epp << 24; | |
888 | } else { | |
889 | intel_pstate_set_epb(cpu, epp); | |
890 | } | |
891 | skip_epp: | |
2f86dc4c DB |
892 | wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); |
893 | } | |
41cfd64c | 894 | } |
2f86dc4c | 895 | |
984edbdc SP |
896 | static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy) |
897 | { | |
898 | struct cpudata *cpu_data = all_cpu_data[policy->cpu]; | |
899 | ||
900 | if (!hwp_active) | |
901 | return 0; | |
902 | ||
903 | cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0); | |
904 | ||
905 | return 0; | |
906 | } | |
907 | ||
8442885f SP |
908 | static int intel_pstate_resume(struct cpufreq_policy *policy) |
909 | { | |
910 | if (!hwp_active) | |
911 | return 0; | |
912 | ||
aa439248 RW |
913 | mutex_lock(&intel_pstate_limits_lock); |
914 | ||
8442885f | 915 | all_cpu_data[policy->cpu]->epp_policy = 0; |
5f98ced1 | 916 | intel_pstate_hwp_set(policy); |
aa439248 RW |
917 | |
918 | mutex_unlock(&intel_pstate_limits_lock); | |
919 | ||
5f98ced1 | 920 | return 0; |
8442885f SP |
921 | } |
922 | ||
111b8b3f | 923 | static void intel_pstate_update_policies(void) |
41cfd64c | 924 | { |
111b8b3f RW |
925 | int cpu; |
926 | ||
927 | for_each_possible_cpu(cpu) | |
928 | cpufreq_update_policy(cpu); | |
2f86dc4c DB |
929 | } |
930 | ||
93f0822d DB |
931 | /************************** debugfs begin ************************/ |
932 | static int pid_param_set(void *data, u64 val) | |
933 | { | |
4ddd0146 RW |
934 | unsigned int cpu; |
935 | ||
93f0822d | 936 | *(u32 *)data = val; |
6e7408ac | 937 | pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC; |
4ddd0146 RW |
938 | for_each_possible_cpu(cpu) |
939 | if (all_cpu_data[cpu]) | |
940 | intel_pstate_busy_pid_reset(all_cpu_data[cpu]); | |
941 | ||
93f0822d DB |
942 | return 0; |
943 | } | |
845c1cbe | 944 | |
93f0822d DB |
945 | static int pid_param_get(void *data, u64 *val) |
946 | { | |
947 | *val = *(u32 *)data; | |
948 | return 0; | |
949 | } | |
2d8d1f18 | 950 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); |
93f0822d | 951 | |
fb1fe104 RW |
952 | static struct dentry *debugfs_parent; |
953 | ||
93f0822d DB |
954 | struct pid_param { |
955 | char *name; | |
956 | void *value; | |
fb1fe104 | 957 | struct dentry *dentry; |
93f0822d DB |
958 | }; |
959 | ||
960 | static struct pid_param pid_files[] = { | |
fb1fe104 RW |
961 | {"sample_rate_ms", &pid_params.sample_rate_ms, }, |
962 | {"d_gain_pct", &pid_params.d_gain_pct, }, | |
963 | {"i_gain_pct", &pid_params.i_gain_pct, }, | |
964 | {"deadband", &pid_params.deadband, }, | |
965 | {"setpoint", &pid_params.setpoint, }, | |
966 | {"p_gain_pct", &pid_params.p_gain_pct, }, | |
967 | {NULL, NULL, } | |
93f0822d DB |
968 | }; |
969 | ||
fb1fe104 | 970 | static void intel_pstate_debug_expose_params(void) |
93f0822d | 971 | { |
fb1fe104 | 972 | int i; |
93f0822d DB |
973 | |
974 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); | |
975 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
976 | return; | |
fb1fe104 RW |
977 | |
978 | for (i = 0; pid_files[i].name; i++) { | |
979 | struct dentry *dentry; | |
980 | ||
981 | dentry = debugfs_create_file(pid_files[i].name, 0660, | |
982 | debugfs_parent, pid_files[i].value, | |
983 | &fops_pid_param); | |
984 | if (!IS_ERR(dentry)) | |
985 | pid_files[i].dentry = dentry; | |
93f0822d DB |
986 | } |
987 | } | |
988 | ||
fb1fe104 RW |
989 | static void intel_pstate_debug_hide_params(void) |
990 | { | |
991 | int i; | |
992 | ||
993 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
994 | return; | |
995 | ||
996 | for (i = 0; pid_files[i].name; i++) { | |
997 | debugfs_remove(pid_files[i].dentry); | |
998 | pid_files[i].dentry = NULL; | |
93f0822d | 999 | } |
fb1fe104 RW |
1000 | |
1001 | debugfs_remove(debugfs_parent); | |
1002 | debugfs_parent = NULL; | |
93f0822d DB |
1003 | } |
1004 | ||
1005 | /************************** debugfs end ************************/ | |
1006 | ||
1007 | /************************** sysfs begin ************************/ | |
1008 | #define show_one(file_name, object) \ | |
1009 | static ssize_t show_##file_name \ | |
1010 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
1011 | { \ | |
7de32556 | 1012 | return sprintf(buf, "%u\n", global.object); \ |
93f0822d DB |
1013 | } |
1014 | ||
fb1fe104 RW |
1015 | static ssize_t intel_pstate_show_status(char *buf); |
1016 | static int intel_pstate_update_status(const char *buf, size_t size); | |
1017 | ||
1018 | static ssize_t show_status(struct kobject *kobj, | |
1019 | struct attribute *attr, char *buf) | |
1020 | { | |
1021 | ssize_t ret; | |
1022 | ||
1023 | mutex_lock(&intel_pstate_driver_lock); | |
1024 | ret = intel_pstate_show_status(buf); | |
1025 | mutex_unlock(&intel_pstate_driver_lock); | |
1026 | ||
1027 | return ret; | |
1028 | } | |
1029 | ||
1030 | static ssize_t store_status(struct kobject *a, struct attribute *b, | |
1031 | const char *buf, size_t count) | |
1032 | { | |
1033 | char *p = memchr(buf, '\n', count); | |
1034 | int ret; | |
1035 | ||
1036 | mutex_lock(&intel_pstate_driver_lock); | |
1037 | ret = intel_pstate_update_status(buf, p ? p - buf : count); | |
1038 | mutex_unlock(&intel_pstate_driver_lock); | |
1039 | ||
1040 | return ret < 0 ? ret : count; | |
1041 | } | |
1042 | ||
d01b1f48 KCA |
1043 | static ssize_t show_turbo_pct(struct kobject *kobj, |
1044 | struct attribute *attr, char *buf) | |
1045 | { | |
1046 | struct cpudata *cpu; | |
1047 | int total, no_turbo, turbo_pct; | |
1048 | uint32_t turbo_fp; | |
1049 | ||
0c30b65b RW |
1050 | mutex_lock(&intel_pstate_driver_lock); |
1051 | ||
1052 | if (!driver_registered) { | |
1053 | mutex_unlock(&intel_pstate_driver_lock); | |
1054 | return -EAGAIN; | |
1055 | } | |
1056 | ||
d01b1f48 KCA |
1057 | cpu = all_cpu_data[0]; |
1058 | ||
1059 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
1060 | no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; | |
22590efb | 1061 | turbo_fp = div_fp(no_turbo, total); |
d01b1f48 | 1062 | turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); |
0c30b65b RW |
1063 | |
1064 | mutex_unlock(&intel_pstate_driver_lock); | |
1065 | ||
d01b1f48 KCA |
1066 | return sprintf(buf, "%u\n", turbo_pct); |
1067 | } | |
1068 | ||
0522424e KCA |
1069 | static ssize_t show_num_pstates(struct kobject *kobj, |
1070 | struct attribute *attr, char *buf) | |
1071 | { | |
1072 | struct cpudata *cpu; | |
1073 | int total; | |
1074 | ||
0c30b65b RW |
1075 | mutex_lock(&intel_pstate_driver_lock); |
1076 | ||
1077 | if (!driver_registered) { | |
1078 | mutex_unlock(&intel_pstate_driver_lock); | |
1079 | return -EAGAIN; | |
1080 | } | |
1081 | ||
0522424e KCA |
1082 | cpu = all_cpu_data[0]; |
1083 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
0c30b65b RW |
1084 | |
1085 | mutex_unlock(&intel_pstate_driver_lock); | |
1086 | ||
0522424e KCA |
1087 | return sprintf(buf, "%u\n", total); |
1088 | } | |
1089 | ||
4521e1a0 GM |
1090 | static ssize_t show_no_turbo(struct kobject *kobj, |
1091 | struct attribute *attr, char *buf) | |
1092 | { | |
1093 | ssize_t ret; | |
1094 | ||
0c30b65b RW |
1095 | mutex_lock(&intel_pstate_driver_lock); |
1096 | ||
1097 | if (!driver_registered) { | |
1098 | mutex_unlock(&intel_pstate_driver_lock); | |
1099 | return -EAGAIN; | |
1100 | } | |
1101 | ||
4521e1a0 | 1102 | update_turbo_state(); |
7de32556 RW |
1103 | if (global.turbo_disabled) |
1104 | ret = sprintf(buf, "%u\n", global.turbo_disabled); | |
4521e1a0 | 1105 | else |
7de32556 | 1106 | ret = sprintf(buf, "%u\n", global.no_turbo); |
4521e1a0 | 1107 | |
0c30b65b RW |
1108 | mutex_unlock(&intel_pstate_driver_lock); |
1109 | ||
4521e1a0 GM |
1110 | return ret; |
1111 | } | |
1112 | ||
93f0822d | 1113 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, |
c410833a | 1114 | const char *buf, size_t count) |
93f0822d DB |
1115 | { |
1116 | unsigned int input; | |
1117 | int ret; | |
845c1cbe | 1118 | |
93f0822d DB |
1119 | ret = sscanf(buf, "%u", &input); |
1120 | if (ret != 1) | |
1121 | return -EINVAL; | |
4521e1a0 | 1122 | |
0c30b65b RW |
1123 | mutex_lock(&intel_pstate_driver_lock); |
1124 | ||
1125 | if (!driver_registered) { | |
1126 | mutex_unlock(&intel_pstate_driver_lock); | |
1127 | return -EAGAIN; | |
1128 | } | |
1129 | ||
a410c03d SP |
1130 | mutex_lock(&intel_pstate_limits_lock); |
1131 | ||
4521e1a0 | 1132 | update_turbo_state(); |
7de32556 | 1133 | if (global.turbo_disabled) { |
4836df17 | 1134 | pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); |
a410c03d | 1135 | mutex_unlock(&intel_pstate_limits_lock); |
0c30b65b | 1136 | mutex_unlock(&intel_pstate_driver_lock); |
4521e1a0 | 1137 | return -EPERM; |
dd5fbf70 | 1138 | } |
2f86dc4c | 1139 | |
7de32556 | 1140 | global.no_turbo = clamp_t(int, input, 0, 1); |
111b8b3f | 1141 | |
c5a2ee7d RW |
1142 | if (global.no_turbo) { |
1143 | struct cpudata *cpu = all_cpu_data[0]; | |
1144 | int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; | |
1145 | ||
1146 | /* Squash the global minimum into the permitted range. */ | |
1147 | if (global.min_perf_pct > pct) | |
1148 | global.min_perf_pct = pct; | |
1149 | } | |
1150 | ||
cd59b4be RW |
1151 | mutex_unlock(&intel_pstate_limits_lock); |
1152 | ||
7de32556 RW |
1153 | intel_pstate_update_policies(); |
1154 | ||
0c30b65b RW |
1155 | mutex_unlock(&intel_pstate_driver_lock); |
1156 | ||
93f0822d DB |
1157 | return count; |
1158 | } | |
1159 | ||
1160 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 1161 | const char *buf, size_t count) |
93f0822d DB |
1162 | { |
1163 | unsigned int input; | |
1164 | int ret; | |
845c1cbe | 1165 | |
93f0822d DB |
1166 | ret = sscanf(buf, "%u", &input); |
1167 | if (ret != 1) | |
1168 | return -EINVAL; | |
1169 | ||
0c30b65b RW |
1170 | mutex_lock(&intel_pstate_driver_lock); |
1171 | ||
1172 | if (!driver_registered) { | |
1173 | mutex_unlock(&intel_pstate_driver_lock); | |
1174 | return -EAGAIN; | |
1175 | } | |
1176 | ||
a410c03d SP |
1177 | mutex_lock(&intel_pstate_limits_lock); |
1178 | ||
c5a2ee7d | 1179 | global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); |
111b8b3f | 1180 | |
cd59b4be RW |
1181 | mutex_unlock(&intel_pstate_limits_lock); |
1182 | ||
7de32556 RW |
1183 | intel_pstate_update_policies(); |
1184 | ||
0c30b65b RW |
1185 | mutex_unlock(&intel_pstate_driver_lock); |
1186 | ||
93f0822d DB |
1187 | return count; |
1188 | } | |
1189 | ||
1190 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 1191 | const char *buf, size_t count) |
93f0822d DB |
1192 | { |
1193 | unsigned int input; | |
1194 | int ret; | |
845c1cbe | 1195 | |
93f0822d DB |
1196 | ret = sscanf(buf, "%u", &input); |
1197 | if (ret != 1) | |
1198 | return -EINVAL; | |
a0475992 | 1199 | |
0c30b65b RW |
1200 | mutex_lock(&intel_pstate_driver_lock); |
1201 | ||
1202 | if (!driver_registered) { | |
1203 | mutex_unlock(&intel_pstate_driver_lock); | |
1204 | return -EAGAIN; | |
1205 | } | |
1206 | ||
a410c03d SP |
1207 | mutex_lock(&intel_pstate_limits_lock); |
1208 | ||
c5a2ee7d RW |
1209 | global.min_perf_pct = clamp_t(int, input, |
1210 | min_perf_pct_min(), global.max_perf_pct); | |
111b8b3f | 1211 | |
cd59b4be RW |
1212 | mutex_unlock(&intel_pstate_limits_lock); |
1213 | ||
7de32556 RW |
1214 | intel_pstate_update_policies(); |
1215 | ||
0c30b65b RW |
1216 | mutex_unlock(&intel_pstate_driver_lock); |
1217 | ||
93f0822d DB |
1218 | return count; |
1219 | } | |
1220 | ||
93f0822d DB |
1221 | show_one(max_perf_pct, max_perf_pct); |
1222 | show_one(min_perf_pct, min_perf_pct); | |
1223 | ||
fb1fe104 | 1224 | define_one_global_rw(status); |
93f0822d DB |
1225 | define_one_global_rw(no_turbo); |
1226 | define_one_global_rw(max_perf_pct); | |
1227 | define_one_global_rw(min_perf_pct); | |
d01b1f48 | 1228 | define_one_global_ro(turbo_pct); |
0522424e | 1229 | define_one_global_ro(num_pstates); |
93f0822d DB |
1230 | |
1231 | static struct attribute *intel_pstate_attributes[] = { | |
fb1fe104 | 1232 | &status.attr, |
93f0822d | 1233 | &no_turbo.attr, |
d01b1f48 | 1234 | &turbo_pct.attr, |
0522424e | 1235 | &num_pstates.attr, |
93f0822d DB |
1236 | NULL |
1237 | }; | |
1238 | ||
1239 | static struct attribute_group intel_pstate_attr_group = { | |
1240 | .attrs = intel_pstate_attributes, | |
1241 | }; | |
93f0822d | 1242 | |
317dd50e | 1243 | static void __init intel_pstate_sysfs_expose_params(void) |
93f0822d | 1244 | { |
317dd50e | 1245 | struct kobject *intel_pstate_kobject; |
93f0822d DB |
1246 | int rc; |
1247 | ||
1248 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
1249 | &cpu_subsys.dev_root->kobj); | |
eae48f04 SP |
1250 | if (WARN_ON(!intel_pstate_kobject)) |
1251 | return; | |
1252 | ||
2d8d1f18 | 1253 | rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); |
eae48f04 SP |
1254 | if (WARN_ON(rc)) |
1255 | return; | |
1256 | ||
1257 | /* | |
1258 | * If per cpu limits are enforced there are no global limits, so | |
1259 | * return without creating max/min_perf_pct attributes | |
1260 | */ | |
1261 | if (per_cpu_limits) | |
1262 | return; | |
1263 | ||
1264 | rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); | |
1265 | WARN_ON(rc); | |
1266 | ||
1267 | rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); | |
1268 | WARN_ON(rc); | |
1269 | ||
93f0822d | 1270 | } |
93f0822d | 1271 | /************************** sysfs end ************************/ |
2f86dc4c | 1272 | |
ba88d433 | 1273 | static void intel_pstate_hwp_enable(struct cpudata *cpudata) |
2f86dc4c | 1274 | { |
f05c9665 | 1275 | /* First disable HWP notification interrupt as we don't process them */ |
da7de91c SP |
1276 | if (static_cpu_has(X86_FEATURE_HWP_NOTIFY)) |
1277 | wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); | |
f05c9665 | 1278 | |
ba88d433 | 1279 | wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); |
8442885f | 1280 | cpudata->epp_policy = 0; |
984edbdc SP |
1281 | if (cpudata->epp_default == -EINVAL) |
1282 | cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); | |
2f86dc4c DB |
1283 | } |
1284 | ||
6e978b22 SP |
1285 | #define MSR_IA32_POWER_CTL_BIT_EE 19 |
1286 | ||
1287 | /* Disable energy efficiency optimization */ | |
1288 | static void intel_pstate_disable_ee(int cpu) | |
1289 | { | |
1290 | u64 power_ctl; | |
1291 | int ret; | |
1292 | ||
1293 | ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl); | |
1294 | if (ret) | |
1295 | return; | |
1296 | ||
1297 | if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) { | |
1298 | pr_info("Disabling energy efficiency optimization\n"); | |
1299 | power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); | |
1300 | wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl); | |
1301 | } | |
1302 | } | |
1303 | ||
938d21a2 | 1304 | static int atom_get_min_pstate(void) |
19e77c28 DB |
1305 | { |
1306 | u64 value; | |
845c1cbe | 1307 | |
92134bdb | 1308 | rdmsrl(MSR_ATOM_CORE_RATIOS, value); |
c16ed060 | 1309 | return (value >> 8) & 0x7F; |
19e77c28 DB |
1310 | } |
1311 | ||
938d21a2 | 1312 | static int atom_get_max_pstate(void) |
19e77c28 DB |
1313 | { |
1314 | u64 value; | |
845c1cbe | 1315 | |
92134bdb | 1316 | rdmsrl(MSR_ATOM_CORE_RATIOS, value); |
c16ed060 | 1317 | return (value >> 16) & 0x7F; |
19e77c28 | 1318 | } |
93f0822d | 1319 | |
938d21a2 | 1320 | static int atom_get_turbo_pstate(void) |
61d8d2ab DB |
1321 | { |
1322 | u64 value; | |
845c1cbe | 1323 | |
92134bdb | 1324 | rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); |
c16ed060 | 1325 | return value & 0x7F; |
61d8d2ab DB |
1326 | } |
1327 | ||
fdfdb2b1 | 1328 | static u64 atom_get_val(struct cpudata *cpudata, int pstate) |
007bea09 DB |
1329 | { |
1330 | u64 val; | |
1331 | int32_t vid_fp; | |
1332 | u32 vid; | |
1333 | ||
144c8e17 | 1334 | val = (u64)pstate << 8; |
7de32556 | 1335 | if (global.no_turbo && !global.turbo_disabled) |
007bea09 DB |
1336 | val |= (u64)1 << 32; |
1337 | ||
1338 | vid_fp = cpudata->vid.min + mul_fp( | |
1339 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
1340 | cpudata->vid.ratio); | |
1341 | ||
1342 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
d022a65e | 1343 | vid = ceiling_fp(vid_fp); |
007bea09 | 1344 | |
21855ff5 DB |
1345 | if (pstate > cpudata->pstate.max_pstate) |
1346 | vid = cpudata->vid.turbo; | |
1347 | ||
fdfdb2b1 | 1348 | return val | vid; |
007bea09 DB |
1349 | } |
1350 | ||
1421df63 | 1351 | static int silvermont_get_scaling(void) |
b27580b0 DB |
1352 | { |
1353 | u64 value; | |
1354 | int i; | |
1421df63 PL |
1355 | /* Defined in Table 35-6 from SDM (Sept 2015) */ |
1356 | static int silvermont_freq_table[] = { | |
1357 | 83300, 100000, 133300, 116700, 80000}; | |
b27580b0 DB |
1358 | |
1359 | rdmsrl(MSR_FSB_FREQ, value); | |
1421df63 PL |
1360 | i = value & 0x7; |
1361 | WARN_ON(i > 4); | |
b27580b0 | 1362 | |
1421df63 PL |
1363 | return silvermont_freq_table[i]; |
1364 | } | |
b27580b0 | 1365 | |
1421df63 PL |
1366 | static int airmont_get_scaling(void) |
1367 | { | |
1368 | u64 value; | |
1369 | int i; | |
1370 | /* Defined in Table 35-10 from SDM (Sept 2015) */ | |
1371 | static int airmont_freq_table[] = { | |
1372 | 83300, 100000, 133300, 116700, 80000, | |
1373 | 93300, 90000, 88900, 87500}; | |
1374 | ||
1375 | rdmsrl(MSR_FSB_FREQ, value); | |
1376 | i = value & 0xF; | |
1377 | WARN_ON(i > 8); | |
1378 | ||
1379 | return airmont_freq_table[i]; | |
b27580b0 DB |
1380 | } |
1381 | ||
938d21a2 | 1382 | static void atom_get_vid(struct cpudata *cpudata) |
007bea09 DB |
1383 | { |
1384 | u64 value; | |
1385 | ||
92134bdb | 1386 | rdmsrl(MSR_ATOM_CORE_VIDS, value); |
c16ed060 DB |
1387 | cpudata->vid.min = int_tofp((value >> 8) & 0x7f); |
1388 | cpudata->vid.max = int_tofp((value >> 16) & 0x7f); | |
007bea09 DB |
1389 | cpudata->vid.ratio = div_fp( |
1390 | cpudata->vid.max - cpudata->vid.min, | |
1391 | int_tofp(cpudata->pstate.max_pstate - | |
1392 | cpudata->pstate.min_pstate)); | |
21855ff5 | 1393 | |
92134bdb | 1394 | rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); |
21855ff5 | 1395 | cpudata->vid.turbo = value & 0x7f; |
007bea09 DB |
1396 | } |
1397 | ||
016c8150 | 1398 | static int core_get_min_pstate(void) |
93f0822d DB |
1399 | { |
1400 | u64 value; | |
845c1cbe | 1401 | |
05e99c8c | 1402 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
1403 | return (value >> 40) & 0xFF; |
1404 | } | |
1405 | ||
3bcc6fa9 | 1406 | static int core_get_max_pstate_physical(void) |
93f0822d DB |
1407 | { |
1408 | u64 value; | |
845c1cbe | 1409 | |
05e99c8c | 1410 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
1411 | return (value >> 8) & 0xFF; |
1412 | } | |
1413 | ||
8fc7554a SP |
1414 | static int core_get_tdp_ratio(u64 plat_info) |
1415 | { | |
1416 | /* Check how many TDP levels present */ | |
1417 | if (plat_info & 0x600000000) { | |
1418 | u64 tdp_ctrl; | |
1419 | u64 tdp_ratio; | |
1420 | int tdp_msr; | |
1421 | int err; | |
1422 | ||
1423 | /* Get the TDP level (0, 1, 2) to get ratios */ | |
1424 | err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); | |
1425 | if (err) | |
1426 | return err; | |
1427 | ||
1428 | /* TDP MSR are continuous starting at 0x648 */ | |
1429 | tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); | |
1430 | err = rdmsrl_safe(tdp_msr, &tdp_ratio); | |
1431 | if (err) | |
1432 | return err; | |
1433 | ||
1434 | /* For level 1 and 2, bits[23:16] contain the ratio */ | |
1435 | if (tdp_ctrl & 0x03) | |
1436 | tdp_ratio >>= 16; | |
1437 | ||
1438 | tdp_ratio &= 0xff; /* ratios are only 8 bits long */ | |
1439 | pr_debug("tdp_ratio %x\n", (int)tdp_ratio); | |
1440 | ||
1441 | return (int)tdp_ratio; | |
1442 | } | |
1443 | ||
1444 | return -ENXIO; | |
1445 | } | |
1446 | ||
016c8150 | 1447 | static int core_get_max_pstate(void) |
93f0822d | 1448 | { |
6a35fc2d SP |
1449 | u64 tar; |
1450 | u64 plat_info; | |
1451 | int max_pstate; | |
8fc7554a | 1452 | int tdp_ratio; |
6a35fc2d SP |
1453 | int err; |
1454 | ||
1455 | rdmsrl(MSR_PLATFORM_INFO, plat_info); | |
1456 | max_pstate = (plat_info >> 8) & 0xFF; | |
1457 | ||
8fc7554a SP |
1458 | tdp_ratio = core_get_tdp_ratio(plat_info); |
1459 | if (tdp_ratio <= 0) | |
1460 | return max_pstate; | |
1461 | ||
1462 | if (hwp_active) { | |
1463 | /* Turbo activation ratio is not used on HWP platforms */ | |
1464 | return tdp_ratio; | |
1465 | } | |
1466 | ||
6a35fc2d SP |
1467 | err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); |
1468 | if (!err) { | |
8fc7554a SP |
1469 | int tar_levels; |
1470 | ||
6a35fc2d | 1471 | /* Do some sanity checking for safety */ |
8fc7554a SP |
1472 | tar_levels = tar & 0xff; |
1473 | if (tdp_ratio - 1 == tar_levels) { | |
1474 | max_pstate = tar_levels; | |
1475 | pr_debug("max_pstate=TAC %x\n", max_pstate); | |
6a35fc2d SP |
1476 | } |
1477 | } | |
845c1cbe | 1478 | |
6a35fc2d | 1479 | return max_pstate; |
93f0822d DB |
1480 | } |
1481 | ||
016c8150 | 1482 | static int core_get_turbo_pstate(void) |
93f0822d DB |
1483 | { |
1484 | u64 value; | |
1485 | int nont, ret; | |
845c1cbe | 1486 | |
100cf6f2 | 1487 | rdmsrl(MSR_TURBO_RATIO_LIMIT, value); |
016c8150 | 1488 | nont = core_get_max_pstate(); |
285cb990 | 1489 | ret = (value) & 255; |
93f0822d DB |
1490 | if (ret <= nont) |
1491 | ret = nont; | |
1492 | return ret; | |
1493 | } | |
1494 | ||
b27580b0 DB |
1495 | static inline int core_get_scaling(void) |
1496 | { | |
1497 | return 100000; | |
1498 | } | |
1499 | ||
fdfdb2b1 | 1500 | static u64 core_get_val(struct cpudata *cpudata, int pstate) |
016c8150 DB |
1501 | { |
1502 | u64 val; | |
1503 | ||
144c8e17 | 1504 | val = (u64)pstate << 8; |
7de32556 | 1505 | if (global.no_turbo && !global.turbo_disabled) |
016c8150 DB |
1506 | val |= (u64)1 << 32; |
1507 | ||
fdfdb2b1 | 1508 | return val; |
016c8150 DB |
1509 | } |
1510 | ||
b34ef932 DC |
1511 | static int knl_get_turbo_pstate(void) |
1512 | { | |
1513 | u64 value; | |
1514 | int nont, ret; | |
1515 | ||
100cf6f2 | 1516 | rdmsrl(MSR_TURBO_RATIO_LIMIT, value); |
b34ef932 DC |
1517 | nont = core_get_max_pstate(); |
1518 | ret = (((value) >> 8) & 0xFF); | |
1519 | if (ret <= nont) | |
1520 | ret = nont; | |
1521 | return ret; | |
1522 | } | |
1523 | ||
016c8150 | 1524 | static struct cpu_defaults core_params = { |
016c8150 DB |
1525 | .funcs = { |
1526 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 1527 | .get_max_physical = core_get_max_pstate_physical, |
016c8150 DB |
1528 | .get_min = core_get_min_pstate, |
1529 | .get_turbo = core_get_turbo_pstate, | |
b27580b0 | 1530 | .get_scaling = core_get_scaling, |
fdfdb2b1 | 1531 | .get_val = core_get_val, |
157386b6 | 1532 | .get_target_pstate = get_target_pstate_use_performance, |
016c8150 DB |
1533 | }, |
1534 | }; | |
1535 | ||
42ce8921 | 1536 | static const struct cpu_defaults silvermont_params = { |
1421df63 PL |
1537 | .funcs = { |
1538 | .get_max = atom_get_max_pstate, | |
1539 | .get_max_physical = atom_get_max_pstate, | |
1540 | .get_min = atom_get_min_pstate, | |
1541 | .get_turbo = atom_get_turbo_pstate, | |
fdfdb2b1 | 1542 | .get_val = atom_get_val, |
1421df63 PL |
1543 | .get_scaling = silvermont_get_scaling, |
1544 | .get_vid = atom_get_vid, | |
e70eed2b | 1545 | .get_target_pstate = get_target_pstate_use_cpu_load, |
1421df63 PL |
1546 | }, |
1547 | }; | |
1548 | ||
42ce8921 | 1549 | static const struct cpu_defaults airmont_params = { |
19e77c28 | 1550 | .funcs = { |
938d21a2 PL |
1551 | .get_max = atom_get_max_pstate, |
1552 | .get_max_physical = atom_get_max_pstate, | |
1553 | .get_min = atom_get_min_pstate, | |
1554 | .get_turbo = atom_get_turbo_pstate, | |
fdfdb2b1 | 1555 | .get_val = atom_get_val, |
1421df63 | 1556 | .get_scaling = airmont_get_scaling, |
938d21a2 | 1557 | .get_vid = atom_get_vid, |
e70eed2b | 1558 | .get_target_pstate = get_target_pstate_use_cpu_load, |
19e77c28 DB |
1559 | }, |
1560 | }; | |
1561 | ||
42ce8921 | 1562 | static const struct cpu_defaults knl_params = { |
b34ef932 DC |
1563 | .funcs = { |
1564 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 1565 | .get_max_physical = core_get_max_pstate_physical, |
b34ef932 DC |
1566 | .get_min = core_get_min_pstate, |
1567 | .get_turbo = knl_get_turbo_pstate, | |
69cefc27 | 1568 | .get_scaling = core_get_scaling, |
fdfdb2b1 | 1569 | .get_val = core_get_val, |
157386b6 | 1570 | .get_target_pstate = get_target_pstate_use_performance, |
b34ef932 DC |
1571 | }, |
1572 | }; | |
1573 | ||
42ce8921 | 1574 | static const struct cpu_defaults bxt_params = { |
41bad47f SP |
1575 | .funcs = { |
1576 | .get_max = core_get_max_pstate, | |
1577 | .get_max_physical = core_get_max_pstate_physical, | |
1578 | .get_min = core_get_min_pstate, | |
1579 | .get_turbo = core_get_turbo_pstate, | |
1580 | .get_scaling = core_get_scaling, | |
1581 | .get_val = core_get_val, | |
1582 | .get_target_pstate = get_target_pstate_use_cpu_load, | |
1583 | }, | |
1584 | }; | |
1585 | ||
93f0822d DB |
1586 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) |
1587 | { | |
1588 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 1589 | int max_perf_adj; |
93f0822d | 1590 | int min_perf; |
845c1cbe | 1591 | |
7de32556 | 1592 | if (global.no_turbo || global.turbo_disabled) |
93f0822d DB |
1593 | max_perf = cpu->pstate.max_pstate; |
1594 | ||
e0d4c8f8 KCA |
1595 | /* |
1596 | * performance can be limited by user through sysfs, by cpufreq | |
1597 | * policy, or by cpu specific default values determined through | |
1598 | * experimentation. | |
1599 | */ | |
e14cf885 | 1600 | max_perf_adj = fp_ext_toint(max_perf * cpu->max_perf); |
799281a3 RW |
1601 | *max = clamp_t(int, max_perf_adj, |
1602 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); | |
93f0822d | 1603 | |
e14cf885 | 1604 | min_perf = fp_ext_toint(max_perf * cpu->min_perf); |
799281a3 | 1605 | *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); |
93f0822d DB |
1606 | } |
1607 | ||
a6c6ead1 | 1608 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) |
fdfdb2b1 | 1609 | { |
bc95a454 RW |
1610 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
1611 | cpu->pstate.current_pstate = pstate; | |
fdfdb2b1 RW |
1612 | /* |
1613 | * Generally, there is no guarantee that this code will always run on | |
1614 | * the CPU being updated, so force the register update to run on the | |
1615 | * right CPU. | |
1616 | */ | |
1617 | wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, | |
1618 | pstate_funcs.get_val(cpu, pstate)); | |
93f0822d DB |
1619 | } |
1620 | ||
a6c6ead1 RW |
1621 | static void intel_pstate_set_min_pstate(struct cpudata *cpu) |
1622 | { | |
1623 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); | |
1624 | } | |
1625 | ||
1626 | static void intel_pstate_max_within_limits(struct cpudata *cpu) | |
1627 | { | |
1628 | int min_pstate, max_pstate; | |
1629 | ||
1630 | update_turbo_state(); | |
1631 | intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate); | |
1632 | intel_pstate_set_pstate(cpu, max_pstate); | |
1633 | } | |
1634 | ||
93f0822d DB |
1635 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) |
1636 | { | |
016c8150 DB |
1637 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
1638 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
3bcc6fa9 | 1639 | cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); |
016c8150 | 1640 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); |
b27580b0 | 1641 | cpu->pstate.scaling = pstate_funcs.get_scaling(); |
001c76f0 RW |
1642 | cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling; |
1643 | cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d | 1644 | |
007bea09 DB |
1645 | if (pstate_funcs.get_vid) |
1646 | pstate_funcs.get_vid(cpu); | |
fdfdb2b1 RW |
1647 | |
1648 | intel_pstate_set_min_pstate(cpu); | |
93f0822d DB |
1649 | } |
1650 | ||
a1c9787d | 1651 | static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) |
93f0822d | 1652 | { |
6b17ddb2 | 1653 | struct sample *sample = &cpu->sample; |
e66c1768 | 1654 | |
a1c9787d | 1655 | sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); |
93f0822d DB |
1656 | } |
1657 | ||
4fec7ad5 | 1658 | static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) |
93f0822d | 1659 | { |
93f0822d | 1660 | u64 aperf, mperf; |
4ab60c3f | 1661 | unsigned long flags; |
4055fad3 | 1662 | u64 tsc; |
93f0822d | 1663 | |
4ab60c3f | 1664 | local_irq_save(flags); |
93f0822d DB |
1665 | rdmsrl(MSR_IA32_APERF, aperf); |
1666 | rdmsrl(MSR_IA32_MPERF, mperf); | |
e70eed2b | 1667 | tsc = rdtsc(); |
4fec7ad5 | 1668 | if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { |
8e601a9f | 1669 | local_irq_restore(flags); |
4fec7ad5 | 1670 | return false; |
8e601a9f | 1671 | } |
4ab60c3f | 1672 | local_irq_restore(flags); |
b69880f9 | 1673 | |
c4ee841f | 1674 | cpu->last_sample_time = cpu->sample.time; |
a4675fbc | 1675 | cpu->sample.time = time; |
d37e2b76 DB |
1676 | cpu->sample.aperf = aperf; |
1677 | cpu->sample.mperf = mperf; | |
4055fad3 | 1678 | cpu->sample.tsc = tsc; |
d37e2b76 DB |
1679 | cpu->sample.aperf -= cpu->prev_aperf; |
1680 | cpu->sample.mperf -= cpu->prev_mperf; | |
4055fad3 | 1681 | cpu->sample.tsc -= cpu->prev_tsc; |
1abc4b20 | 1682 | |
93f0822d DB |
1683 | cpu->prev_aperf = aperf; |
1684 | cpu->prev_mperf = mperf; | |
4055fad3 | 1685 | cpu->prev_tsc = tsc; |
febce40f RW |
1686 | /* |
1687 | * First time this function is invoked in a given cycle, all of the | |
1688 | * previous sample data fields are equal to zero or stale and they must | |
1689 | * be populated with meaningful numbers for things to work, so assume | |
1690 | * that sample.time will always be reset before setting the utilization | |
1691 | * update hook and make the caller skip the sample then. | |
1692 | */ | |
1693 | return !!cpu->last_sample_time; | |
93f0822d DB |
1694 | } |
1695 | ||
8fa520af PL |
1696 | static inline int32_t get_avg_frequency(struct cpudata *cpu) |
1697 | { | |
a1c9787d RW |
1698 | return mul_ext_fp(cpu->sample.core_avg_perf, |
1699 | cpu->pstate.max_pstate_physical * cpu->pstate.scaling); | |
8fa520af PL |
1700 | } |
1701 | ||
bdcaa23f PL |
1702 | static inline int32_t get_avg_pstate(struct cpudata *cpu) |
1703 | { | |
8edb0a6e RW |
1704 | return mul_ext_fp(cpu->pstate.max_pstate_physical, |
1705 | cpu->sample.core_avg_perf); | |
bdcaa23f PL |
1706 | } |
1707 | ||
e70eed2b PL |
1708 | static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu) |
1709 | { | |
1710 | struct sample *sample = &cpu->sample; | |
09c448d3 | 1711 | int32_t busy_frac, boost; |
0843e83c | 1712 | int target, avg_pstate; |
e70eed2b | 1713 | |
09c448d3 | 1714 | busy_frac = div_fp(sample->mperf, sample->tsc); |
63d1d656 | 1715 | |
09c448d3 RW |
1716 | boost = cpu->iowait_boost; |
1717 | cpu->iowait_boost >>= 1; | |
63d1d656 | 1718 | |
09c448d3 RW |
1719 | if (busy_frac < boost) |
1720 | busy_frac = boost; | |
63d1d656 | 1721 | |
09c448d3 | 1722 | sample->busy_scaled = busy_frac * 100; |
0843e83c | 1723 | |
7de32556 | 1724 | target = global.no_turbo || global.turbo_disabled ? |
0843e83c RW |
1725 | cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; |
1726 | target += target >> 2; | |
1727 | target = mul_fp(target, busy_frac); | |
1728 | if (target < cpu->pstate.min_pstate) | |
1729 | target = cpu->pstate.min_pstate; | |
1730 | ||
1731 | /* | |
1732 | * If the average P-state during the previous cycle was higher than the | |
1733 | * current target, add 50% of the difference to the target to reduce | |
1734 | * possible performance oscillations and offset possible performance | |
1735 | * loss related to moving the workload from one CPU to another within | |
1736 | * a package/module. | |
1737 | */ | |
1738 | avg_pstate = get_avg_pstate(cpu); | |
1739 | if (avg_pstate > target) | |
1740 | target += (avg_pstate - target) >> 1; | |
1741 | ||
1742 | return target; | |
e70eed2b PL |
1743 | } |
1744 | ||
157386b6 | 1745 | static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) |
93f0822d | 1746 | { |
1aa7a6e2 | 1747 | int32_t perf_scaled, max_pstate, current_pstate, sample_ratio; |
a4675fbc | 1748 | u64 duration_ns; |
93f0822d | 1749 | |
e0d4c8f8 | 1750 | /* |
f00593a4 RW |
1751 | * perf_scaled is the ratio of the average P-state during the last |
1752 | * sampling period to the P-state requested last time (in percent). | |
1753 | * | |
1754 | * That measures the system's response to the previous P-state | |
1755 | * selection. | |
e0d4c8f8 | 1756 | */ |
22590efb RW |
1757 | max_pstate = cpu->pstate.max_pstate_physical; |
1758 | current_pstate = cpu->pstate.current_pstate; | |
1aa7a6e2 | 1759 | perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf, |
a1c9787d | 1760 | div_fp(100 * max_pstate, current_pstate)); |
c4ee841f | 1761 | |
e0d4c8f8 | 1762 | /* |
a4675fbc RW |
1763 | * Since our utilization update callback will not run unless we are |
1764 | * in C0, check if the actual elapsed time is significantly greater (3x) | |
1765 | * than our sample interval. If it is, then we were idle for a long | |
1aa7a6e2 | 1766 | * enough period of time to adjust our performance metric. |
e0d4c8f8 | 1767 | */ |
a4675fbc | 1768 | duration_ns = cpu->sample.time - cpu->last_sample_time; |
febce40f | 1769 | if ((s64)duration_ns > pid_params.sample_rate_ns * 3) { |
22590efb | 1770 | sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns); |
1aa7a6e2 | 1771 | perf_scaled = mul_fp(perf_scaled, sample_ratio); |
ffb81056 RW |
1772 | } else { |
1773 | sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc); | |
1774 | if (sample_ratio < int_tofp(1)) | |
1aa7a6e2 | 1775 | perf_scaled = 0; |
c4ee841f DB |
1776 | } |
1777 | ||
1aa7a6e2 RW |
1778 | cpu->sample.busy_scaled = perf_scaled; |
1779 | return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled); | |
93f0822d DB |
1780 | } |
1781 | ||
001c76f0 | 1782 | static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) |
fdfdb2b1 RW |
1783 | { |
1784 | int max_perf, min_perf; | |
1785 | ||
fdfdb2b1 RW |
1786 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); |
1787 | pstate = clamp_t(int, pstate, min_perf, max_perf); | |
001c76f0 RW |
1788 | return pstate; |
1789 | } | |
1790 | ||
1791 | static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) | |
1792 | { | |
fdfdb2b1 RW |
1793 | if (pstate == cpu->pstate.current_pstate) |
1794 | return; | |
1795 | ||
bc95a454 | 1796 | cpu->pstate.current_pstate = pstate; |
fdfdb2b1 RW |
1797 | wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); |
1798 | } | |
1799 | ||
93f0822d DB |
1800 | static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) |
1801 | { | |
157386b6 | 1802 | int from, target_pstate; |
4055fad3 DS |
1803 | struct sample *sample; |
1804 | ||
1805 | from = cpu->pstate.current_pstate; | |
93f0822d | 1806 | |
2f1d407a RW |
1807 | target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ? |
1808 | cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu); | |
93f0822d | 1809 | |
001c76f0 RW |
1810 | update_turbo_state(); |
1811 | ||
64078299 RW |
1812 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); |
1813 | trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); | |
fdfdb2b1 | 1814 | intel_pstate_update_pstate(cpu, target_pstate); |
4055fad3 DS |
1815 | |
1816 | sample = &cpu->sample; | |
a1c9787d | 1817 | trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), |
157386b6 | 1818 | fp_toint(sample->busy_scaled), |
4055fad3 DS |
1819 | from, |
1820 | cpu->pstate.current_pstate, | |
1821 | sample->mperf, | |
1822 | sample->aperf, | |
1823 | sample->tsc, | |
3ba7bcaa SP |
1824 | get_avg_frequency(cpu), |
1825 | fp_toint(cpu->iowait_boost * 100)); | |
93f0822d DB |
1826 | } |
1827 | ||
a4675fbc | 1828 | static void intel_pstate_update_util(struct update_util_data *data, u64 time, |
58919e83 | 1829 | unsigned int flags) |
93f0822d | 1830 | { |
a4675fbc | 1831 | struct cpudata *cpu = container_of(data, struct cpudata, update_util); |
09c448d3 RW |
1832 | u64 delta_ns; |
1833 | ||
1d29815e | 1834 | if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) { |
09c448d3 RW |
1835 | if (flags & SCHED_CPUFREQ_IOWAIT) { |
1836 | cpu->iowait_boost = int_tofp(1); | |
1837 | } else if (cpu->iowait_boost) { | |
1838 | /* Clear iowait_boost if the CPU may have been idle. */ | |
1839 | delta_ns = time - cpu->last_update; | |
1840 | if (delta_ns > TICK_NSEC) | |
1841 | cpu->iowait_boost = 0; | |
1842 | } | |
1843 | cpu->last_update = time; | |
1844 | } | |
b69880f9 | 1845 | |
09c448d3 | 1846 | delta_ns = time - cpu->sample.time; |
a4675fbc | 1847 | if ((s64)delta_ns >= pid_params.sample_rate_ns) { |
4fec7ad5 RW |
1848 | bool sample_taken = intel_pstate_sample(cpu, time); |
1849 | ||
6d45b719 | 1850 | if (sample_taken) { |
a1c9787d | 1851 | intel_pstate_calc_avg_perf(cpu); |
6d45b719 RW |
1852 | if (!hwp_active) |
1853 | intel_pstate_adjust_busy_pstate(cpu); | |
1854 | } | |
a4675fbc | 1855 | } |
93f0822d DB |
1856 | } |
1857 | ||
1858 | #define ICPU(model, policy) \ | |
6cbd7ee1 DB |
1859 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
1860 | (unsigned long)&policy } | |
93f0822d DB |
1861 | |
1862 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
5b20c944 DH |
1863 | ICPU(INTEL_FAM6_SANDYBRIDGE, core_params), |
1864 | ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params), | |
1865 | ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params), | |
1866 | ICPU(INTEL_FAM6_IVYBRIDGE, core_params), | |
1867 | ICPU(INTEL_FAM6_HASWELL_CORE, core_params), | |
1868 | ICPU(INTEL_FAM6_BROADWELL_CORE, core_params), | |
1869 | ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params), | |
1870 | ICPU(INTEL_FAM6_HASWELL_X, core_params), | |
1871 | ICPU(INTEL_FAM6_HASWELL_ULT, core_params), | |
1872 | ICPU(INTEL_FAM6_HASWELL_GT3E, core_params), | |
1873 | ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params), | |
1874 | ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params), | |
1875 | ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params), | |
1876 | ICPU(INTEL_FAM6_BROADWELL_X, core_params), | |
1877 | ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params), | |
1878 | ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), | |
1879 | ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params), | |
58bf4542 | 1880 | ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_params), |
41bad47f | 1881 | ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params), |
93f0822d DB |
1882 | {} |
1883 | }; | |
1884 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
1885 | ||
29327c84 | 1886 | static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { |
5b20c944 | 1887 | ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), |
65c1262f SP |
1888 | ICPU(INTEL_FAM6_BROADWELL_X, core_params), |
1889 | ICPU(INTEL_FAM6_SKYLAKE_X, core_params), | |
2f86dc4c DB |
1890 | {} |
1891 | }; | |
1892 | ||
6e978b22 SP |
1893 | static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { |
1894 | ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_params), | |
1895 | {} | |
1896 | }; | |
1897 | ||
93f0822d DB |
1898 | static int intel_pstate_init_cpu(unsigned int cpunum) |
1899 | { | |
93f0822d DB |
1900 | struct cpudata *cpu; |
1901 | ||
eae48f04 SP |
1902 | cpu = all_cpu_data[cpunum]; |
1903 | ||
1904 | if (!cpu) { | |
c5a2ee7d | 1905 | cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); |
eae48f04 SP |
1906 | if (!cpu) |
1907 | return -ENOMEM; | |
1908 | ||
1909 | all_cpu_data[cpunum] = cpu; | |
eae48f04 | 1910 | |
984edbdc SP |
1911 | cpu->epp_default = -EINVAL; |
1912 | cpu->epp_powersave = -EINVAL; | |
1913 | cpu->epp_saved = -EINVAL; | |
eae48f04 | 1914 | } |
93f0822d DB |
1915 | |
1916 | cpu = all_cpu_data[cpunum]; | |
1917 | ||
93f0822d | 1918 | cpu->cpu = cpunum; |
ba88d433 | 1919 | |
a4675fbc | 1920 | if (hwp_active) { |
6e978b22 SP |
1921 | const struct x86_cpu_id *id; |
1922 | ||
1923 | id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); | |
1924 | if (id) | |
1925 | intel_pstate_disable_ee(cpunum); | |
1926 | ||
ba88d433 | 1927 | intel_pstate_hwp_enable(cpu); |
a4675fbc RW |
1928 | pid_params.sample_rate_ms = 50; |
1929 | pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC; | |
1930 | } | |
ba88d433 | 1931 | |
179e8471 | 1932 | intel_pstate_get_cpu_pstates(cpu); |
016c8150 | 1933 | |
93f0822d | 1934 | intel_pstate_busy_pid_reset(cpu); |
93f0822d | 1935 | |
4836df17 | 1936 | pr_debug("controlling: cpu %d\n", cpunum); |
93f0822d DB |
1937 | |
1938 | return 0; | |
1939 | } | |
1940 | ||
1941 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
1942 | { | |
f96fd0c8 | 1943 | struct cpudata *cpu = all_cpu_data[cpu_num]; |
93f0822d | 1944 | |
f96fd0c8 | 1945 | return cpu ? get_avg_frequency(cpu) : 0; |
93f0822d DB |
1946 | } |
1947 | ||
febce40f | 1948 | static void intel_pstate_set_update_util_hook(unsigned int cpu_num) |
bb6ab52f | 1949 | { |
febce40f RW |
1950 | struct cpudata *cpu = all_cpu_data[cpu_num]; |
1951 | ||
5ab666e0 RW |
1952 | if (cpu->update_util_set) |
1953 | return; | |
1954 | ||
febce40f RW |
1955 | /* Prevent intel_pstate_update_util() from using stale data. */ |
1956 | cpu->sample.time = 0; | |
0bed612b RW |
1957 | cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, |
1958 | intel_pstate_update_util); | |
4578ee7e | 1959 | cpu->update_util_set = true; |
bb6ab52f RW |
1960 | } |
1961 | ||
1962 | static void intel_pstate_clear_update_util_hook(unsigned int cpu) | |
1963 | { | |
4578ee7e CY |
1964 | struct cpudata *cpu_data = all_cpu_data[cpu]; |
1965 | ||
1966 | if (!cpu_data->update_util_set) | |
1967 | return; | |
1968 | ||
0bed612b | 1969 | cpufreq_remove_update_util_hook(cpu); |
4578ee7e | 1970 | cpu_data->update_util_set = false; |
bb6ab52f RW |
1971 | synchronize_sched(); |
1972 | } | |
1973 | ||
80b120ca RW |
1974 | static int intel_pstate_get_max_freq(struct cpudata *cpu) |
1975 | { | |
1976 | return global.turbo_disabled || global.no_turbo ? | |
1977 | cpu->pstate.max_freq : cpu->pstate.turbo_freq; | |
1978 | } | |
1979 | ||
eae48f04 | 1980 | static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy, |
c5a2ee7d | 1981 | struct cpudata *cpu) |
eae48f04 | 1982 | { |
80b120ca | 1983 | int max_freq = intel_pstate_get_max_freq(cpu); |
e4c204ce | 1984 | int32_t max_policy_perf, min_policy_perf; |
a410c03d | 1985 | |
80b120ca | 1986 | max_policy_perf = div_ext_fp(policy->max, max_freq); |
e4c204ce | 1987 | max_policy_perf = clamp_t(int32_t, max_policy_perf, 0, int_ext_tofp(1)); |
5879f877 | 1988 | if (policy->max == policy->min) { |
e4c204ce | 1989 | min_policy_perf = max_policy_perf; |
5879f877 | 1990 | } else { |
80b120ca | 1991 | min_policy_perf = div_ext_fp(policy->min, max_freq); |
e4c204ce RW |
1992 | min_policy_perf = clamp_t(int32_t, min_policy_perf, |
1993 | 0, max_policy_perf); | |
5879f877 | 1994 | } |
eae48f04 | 1995 | |
e4c204ce | 1996 | /* Normalize user input to [min_perf, max_perf] */ |
c5a2ee7d | 1997 | if (per_cpu_limits) { |
e14cf885 RW |
1998 | cpu->min_perf = min_policy_perf; |
1999 | cpu->max_perf = max_policy_perf; | |
c5a2ee7d RW |
2000 | } else { |
2001 | int32_t global_min, global_max; | |
2002 | ||
2003 | /* Global limits are in percent of the maximum turbo P-state. */ | |
2004 | global_max = percent_ext_fp(global.max_perf_pct); | |
2005 | global_min = percent_ext_fp(global.min_perf_pct); | |
80b120ca | 2006 | if (max_freq != cpu->pstate.turbo_freq) { |
c5a2ee7d RW |
2007 | int32_t turbo_factor; |
2008 | ||
2009 | turbo_factor = div_ext_fp(cpu->pstate.turbo_pstate, | |
2010 | cpu->pstate.max_pstate); | |
2011 | global_min = mul_ext_fp(global_min, turbo_factor); | |
2012 | global_max = mul_ext_fp(global_max, turbo_factor); | |
2013 | } | |
2014 | global_min = clamp_t(int32_t, global_min, 0, global_max); | |
eae48f04 | 2015 | |
e14cf885 RW |
2016 | cpu->min_perf = max(min_policy_perf, global_min); |
2017 | cpu->min_perf = min(cpu->min_perf, max_policy_perf); | |
2018 | cpu->max_perf = min(max_policy_perf, global_max); | |
2019 | cpu->max_perf = max(min_policy_perf, cpu->max_perf); | |
c5a2ee7d RW |
2020 | |
2021 | /* Make sure min_perf <= max_perf */ | |
e14cf885 | 2022 | cpu->min_perf = min(cpu->min_perf, cpu->max_perf); |
c5a2ee7d | 2023 | } |
eae48f04 | 2024 | |
e14cf885 RW |
2025 | cpu->max_perf = round_up(cpu->max_perf, EXT_FRAC_BITS); |
2026 | cpu->min_perf = round_up(cpu->min_perf, EXT_FRAC_BITS); | |
eae48f04 SP |
2027 | |
2028 | pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu, | |
e14cf885 RW |
2029 | fp_ext_toint(cpu->max_perf * 100), |
2030 | fp_ext_toint(cpu->min_perf * 100)); | |
eae48f04 SP |
2031 | } |
2032 | ||
93f0822d DB |
2033 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) |
2034 | { | |
3be9200d SP |
2035 | struct cpudata *cpu; |
2036 | ||
d3929b83 DB |
2037 | if (!policy->cpuinfo.max_freq) |
2038 | return -ENODEV; | |
2039 | ||
2c2c1af4 SP |
2040 | pr_debug("set_policy cpuinfo.max %u policy->max %u\n", |
2041 | policy->cpuinfo.max_freq, policy->max); | |
2042 | ||
a6c6ead1 | 2043 | cpu = all_cpu_data[policy->cpu]; |
2f1d407a RW |
2044 | cpu->policy = policy->policy; |
2045 | ||
b59fe540 SP |
2046 | mutex_lock(&intel_pstate_limits_lock); |
2047 | ||
c5a2ee7d | 2048 | intel_pstate_update_perf_limits(policy, cpu); |
a240c4aa | 2049 | |
2f1d407a | 2050 | if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { |
a6c6ead1 RW |
2051 | /* |
2052 | * NOHZ_FULL CPUs need this as the governor callback may not | |
2053 | * be invoked on them. | |
2054 | */ | |
2055 | intel_pstate_clear_update_util_hook(policy->cpu); | |
2056 | intel_pstate_max_within_limits(cpu); | |
2057 | } | |
2058 | ||
bb6ab52f RW |
2059 | intel_pstate_set_update_util_hook(policy->cpu); |
2060 | ||
5f98ced1 RW |
2061 | if (hwp_active) |
2062 | intel_pstate_hwp_set(policy); | |
2f86dc4c | 2063 | |
b59fe540 SP |
2064 | mutex_unlock(&intel_pstate_limits_lock); |
2065 | ||
93f0822d DB |
2066 | return 0; |
2067 | } | |
2068 | ||
80b120ca RW |
2069 | static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy, |
2070 | struct cpudata *cpu) | |
2071 | { | |
2072 | if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && | |
2073 | policy->max < policy->cpuinfo.max_freq && | |
2074 | policy->max > cpu->pstate.max_freq) { | |
2075 | pr_debug("policy->max > max non turbo frequency\n"); | |
2076 | policy->max = policy->cpuinfo.max_freq; | |
2077 | } | |
2078 | } | |
2079 | ||
93f0822d DB |
2080 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) |
2081 | { | |
7d9a8a9f | 2082 | struct cpudata *cpu = all_cpu_data[policy->cpu]; |
7d9a8a9f SP |
2083 | |
2084 | update_turbo_state(); | |
80b120ca RW |
2085 | cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, |
2086 | intel_pstate_get_max_freq(cpu)); | |
93f0822d | 2087 | |
285cb990 | 2088 | if (policy->policy != CPUFREQ_POLICY_POWERSAVE && |
c410833a | 2089 | policy->policy != CPUFREQ_POLICY_PERFORMANCE) |
93f0822d DB |
2090 | return -EINVAL; |
2091 | ||
80b120ca RW |
2092 | intel_pstate_adjust_policy_max(policy, cpu); |
2093 | ||
93f0822d DB |
2094 | return 0; |
2095 | } | |
2096 | ||
001c76f0 RW |
2097 | static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy) |
2098 | { | |
2099 | intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]); | |
2100 | } | |
2101 | ||
bb18008f | 2102 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 2103 | { |
001c76f0 | 2104 | pr_debug("CPU %d exiting\n", policy->cpu); |
93f0822d | 2105 | |
001c76f0 | 2106 | intel_pstate_clear_update_util_hook(policy->cpu); |
984edbdc SP |
2107 | if (hwp_active) |
2108 | intel_pstate_hwp_save_state(policy); | |
2109 | else | |
001c76f0 RW |
2110 | intel_cpufreq_stop_cpu(policy); |
2111 | } | |
bb18008f | 2112 | |
001c76f0 RW |
2113 | static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) |
2114 | { | |
2115 | intel_pstate_exit_perf_limits(policy); | |
a4675fbc | 2116 | |
001c76f0 | 2117 | policy->fast_switch_possible = false; |
2f86dc4c | 2118 | |
001c76f0 | 2119 | return 0; |
93f0822d DB |
2120 | } |
2121 | ||
001c76f0 | 2122 | static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 2123 | { |
93f0822d | 2124 | struct cpudata *cpu; |
52e0a509 | 2125 | int rc; |
93f0822d DB |
2126 | |
2127 | rc = intel_pstate_init_cpu(policy->cpu); | |
2128 | if (rc) | |
2129 | return rc; | |
2130 | ||
2131 | cpu = all_cpu_data[policy->cpu]; | |
2132 | ||
e14cf885 RW |
2133 | cpu->max_perf = int_ext_tofp(1); |
2134 | cpu->min_perf = 0; | |
93f0822d | 2135 | |
b27580b0 DB |
2136 | policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; |
2137 | policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
2138 | |
2139 | /* cpuinfo and default policy values */ | |
b27580b0 | 2140 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; |
983e600e | 2141 | update_turbo_state(); |
7de32556 | 2142 | policy->cpuinfo.max_freq = global.turbo_disabled ? |
983e600e SP |
2143 | cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; |
2144 | policy->cpuinfo.max_freq *= cpu->pstate.scaling; | |
2145 | ||
9522a2ff | 2146 | intel_pstate_init_acpi_perf_limits(policy); |
93f0822d DB |
2147 | cpumask_set_cpu(policy->cpu, policy->cpus); |
2148 | ||
001c76f0 RW |
2149 | policy->fast_switch_possible = true; |
2150 | ||
93f0822d DB |
2151 | return 0; |
2152 | } | |
2153 | ||
001c76f0 | 2154 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
9522a2ff | 2155 | { |
001c76f0 RW |
2156 | int ret = __intel_pstate_cpu_init(policy); |
2157 | ||
2158 | if (ret) | |
2159 | return ret; | |
2160 | ||
2161 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; | |
7de32556 | 2162 | if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE)) |
001c76f0 RW |
2163 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; |
2164 | else | |
2165 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
9522a2ff SP |
2166 | |
2167 | return 0; | |
2168 | } | |
2169 | ||
001c76f0 | 2170 | static struct cpufreq_driver intel_pstate = { |
93f0822d DB |
2171 | .flags = CPUFREQ_CONST_LOOPS, |
2172 | .verify = intel_pstate_verify_policy, | |
2173 | .setpolicy = intel_pstate_set_policy, | |
984edbdc | 2174 | .suspend = intel_pstate_hwp_save_state, |
8442885f | 2175 | .resume = intel_pstate_resume, |
93f0822d DB |
2176 | .get = intel_pstate_get, |
2177 | .init = intel_pstate_cpu_init, | |
9522a2ff | 2178 | .exit = intel_pstate_cpu_exit, |
bb18008f | 2179 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 2180 | .name = "intel_pstate", |
93f0822d DB |
2181 | }; |
2182 | ||
001c76f0 RW |
2183 | static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy) |
2184 | { | |
2185 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
001c76f0 RW |
2186 | |
2187 | update_turbo_state(); | |
80b120ca RW |
2188 | cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, |
2189 | intel_pstate_get_max_freq(cpu)); | |
001c76f0 | 2190 | |
80b120ca | 2191 | intel_pstate_adjust_policy_max(policy, cpu); |
001c76f0 | 2192 | |
c5a2ee7d RW |
2193 | intel_pstate_update_perf_limits(policy, cpu); |
2194 | ||
001c76f0 RW |
2195 | return 0; |
2196 | } | |
2197 | ||
001c76f0 RW |
2198 | static int intel_cpufreq_target(struct cpufreq_policy *policy, |
2199 | unsigned int target_freq, | |
2200 | unsigned int relation) | |
2201 | { | |
2202 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
2203 | struct cpufreq_freqs freqs; | |
2204 | int target_pstate; | |
2205 | ||
64897b20 RW |
2206 | update_turbo_state(); |
2207 | ||
001c76f0 | 2208 | freqs.old = policy->cur; |
64897b20 | 2209 | freqs.new = target_freq; |
001c76f0 RW |
2210 | |
2211 | cpufreq_freq_transition_begin(policy, &freqs); | |
2212 | switch (relation) { | |
2213 | case CPUFREQ_RELATION_L: | |
2214 | target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); | |
2215 | break; | |
2216 | case CPUFREQ_RELATION_H: | |
2217 | target_pstate = freqs.new / cpu->pstate.scaling; | |
2218 | break; | |
2219 | default: | |
2220 | target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); | |
2221 | break; | |
2222 | } | |
2223 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); | |
2224 | if (target_pstate != cpu->pstate.current_pstate) { | |
2225 | cpu->pstate.current_pstate = target_pstate; | |
2226 | wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL, | |
2227 | pstate_funcs.get_val(cpu, target_pstate)); | |
2228 | } | |
64078299 | 2229 | freqs.new = target_pstate * cpu->pstate.scaling; |
001c76f0 RW |
2230 | cpufreq_freq_transition_end(policy, &freqs, false); |
2231 | ||
2232 | return 0; | |
2233 | } | |
2234 | ||
2235 | static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, | |
2236 | unsigned int target_freq) | |
2237 | { | |
2238 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
2239 | int target_pstate; | |
2240 | ||
64897b20 RW |
2241 | update_turbo_state(); |
2242 | ||
001c76f0 | 2243 | target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); |
64078299 | 2244 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); |
001c76f0 | 2245 | intel_pstate_update_pstate(cpu, target_pstate); |
64078299 | 2246 | return target_pstate * cpu->pstate.scaling; |
001c76f0 RW |
2247 | } |
2248 | ||
2249 | static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) | |
2250 | { | |
2251 | int ret = __intel_pstate_cpu_init(policy); | |
2252 | ||
2253 | if (ret) | |
2254 | return ret; | |
2255 | ||
2256 | policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; | |
2257 | /* This reflects the intel_pstate_get_cpu_pstates() setting. */ | |
2258 | policy->cur = policy->cpuinfo.min_freq; | |
2259 | ||
2260 | return 0; | |
2261 | } | |
2262 | ||
2263 | static struct cpufreq_driver intel_cpufreq = { | |
2264 | .flags = CPUFREQ_CONST_LOOPS, | |
2265 | .verify = intel_cpufreq_verify_policy, | |
2266 | .target = intel_cpufreq_target, | |
2267 | .fast_switch = intel_cpufreq_fast_switch, | |
2268 | .init = intel_cpufreq_cpu_init, | |
2269 | .exit = intel_pstate_cpu_exit, | |
2270 | .stop_cpu = intel_cpufreq_stop_cpu, | |
2271 | .name = "intel_cpufreq", | |
2272 | }; | |
2273 | ||
2274 | static struct cpufreq_driver *intel_pstate_driver = &intel_pstate; | |
2275 | ||
fb1fe104 RW |
2276 | static void intel_pstate_driver_cleanup(void) |
2277 | { | |
2278 | unsigned int cpu; | |
2279 | ||
2280 | get_online_cpus(); | |
2281 | for_each_online_cpu(cpu) { | |
2282 | if (all_cpu_data[cpu]) { | |
2283 | if (intel_pstate_driver == &intel_pstate) | |
2284 | intel_pstate_clear_update_util_hook(cpu); | |
2285 | ||
2286 | kfree(all_cpu_data[cpu]); | |
2287 | all_cpu_data[cpu] = NULL; | |
2288 | } | |
2289 | } | |
2290 | put_online_cpus(); | |
2291 | } | |
2292 | ||
2293 | static int intel_pstate_register_driver(void) | |
2294 | { | |
2295 | int ret; | |
2296 | ||
c5a2ee7d RW |
2297 | memset(&global, 0, sizeof(global)); |
2298 | global.max_perf_pct = 100; | |
c3a49c89 | 2299 | |
fb1fe104 RW |
2300 | ret = cpufreq_register_driver(intel_pstate_driver); |
2301 | if (ret) { | |
2302 | intel_pstate_driver_cleanup(); | |
2303 | return ret; | |
2304 | } | |
2305 | ||
c5a2ee7d RW |
2306 | global.min_perf_pct = min_perf_pct_min(); |
2307 | ||
fb1fe104 RW |
2308 | mutex_lock(&intel_pstate_limits_lock); |
2309 | driver_registered = true; | |
2310 | mutex_unlock(&intel_pstate_limits_lock); | |
2311 | ||
2312 | if (intel_pstate_driver == &intel_pstate && !hwp_active && | |
2313 | pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load) | |
2314 | intel_pstate_debug_expose_params(); | |
2315 | ||
2316 | return 0; | |
2317 | } | |
2318 | ||
2319 | static int intel_pstate_unregister_driver(void) | |
2320 | { | |
2321 | if (hwp_active) | |
2322 | return -EBUSY; | |
2323 | ||
2324 | if (intel_pstate_driver == &intel_pstate && !hwp_active && | |
2325 | pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load) | |
2326 | intel_pstate_debug_hide_params(); | |
2327 | ||
2328 | mutex_lock(&intel_pstate_limits_lock); | |
2329 | driver_registered = false; | |
2330 | mutex_unlock(&intel_pstate_limits_lock); | |
2331 | ||
2332 | cpufreq_unregister_driver(intel_pstate_driver); | |
2333 | intel_pstate_driver_cleanup(); | |
2334 | ||
2335 | return 0; | |
2336 | } | |
2337 | ||
2338 | static ssize_t intel_pstate_show_status(char *buf) | |
2339 | { | |
2340 | if (!driver_registered) | |
2341 | return sprintf(buf, "off\n"); | |
2342 | ||
2343 | return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? | |
2344 | "active" : "passive"); | |
2345 | } | |
2346 | ||
2347 | static int intel_pstate_update_status(const char *buf, size_t size) | |
2348 | { | |
2349 | int ret; | |
2350 | ||
2351 | if (size == 3 && !strncmp(buf, "off", size)) | |
2352 | return driver_registered ? | |
2353 | intel_pstate_unregister_driver() : -EINVAL; | |
2354 | ||
2355 | if (size == 6 && !strncmp(buf, "active", size)) { | |
2356 | if (driver_registered) { | |
2357 | if (intel_pstate_driver == &intel_pstate) | |
2358 | return 0; | |
2359 | ||
2360 | ret = intel_pstate_unregister_driver(); | |
2361 | if (ret) | |
2362 | return ret; | |
2363 | } | |
2364 | ||
2365 | intel_pstate_driver = &intel_pstate; | |
2366 | return intel_pstate_register_driver(); | |
2367 | } | |
2368 | ||
2369 | if (size == 7 && !strncmp(buf, "passive", size)) { | |
2370 | if (driver_registered) { | |
2371 | if (intel_pstate_driver != &intel_pstate) | |
2372 | return 0; | |
2373 | ||
2374 | ret = intel_pstate_unregister_driver(); | |
2375 | if (ret) | |
2376 | return ret; | |
2377 | } | |
2378 | ||
2379 | intel_pstate_driver = &intel_cpufreq; | |
2380 | return intel_pstate_register_driver(); | |
2381 | } | |
2382 | ||
2383 | return -EINVAL; | |
2384 | } | |
2385 | ||
eed43609 JZ |
2386 | static int no_load __initdata; |
2387 | static int no_hwp __initdata; | |
2388 | static int hwp_only __initdata; | |
29327c84 | 2389 | static unsigned int force_load __initdata; |
6be26498 | 2390 | |
29327c84 | 2391 | static int __init intel_pstate_msrs_not_valid(void) |
b563b4e3 | 2392 | { |
016c8150 | 2393 | if (!pstate_funcs.get_max() || |
c410833a SK |
2394 | !pstate_funcs.get_min() || |
2395 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
2396 | return -ENODEV; |
2397 | ||
b563b4e3 DB |
2398 | return 0; |
2399 | } | |
016c8150 | 2400 | |
7f7a516e SP |
2401 | #ifdef CONFIG_ACPI |
2402 | static void intel_pstate_use_acpi_profile(void) | |
2403 | { | |
55395345 RW |
2404 | switch (acpi_gbl_FADT.preferred_profile) { |
2405 | case PM_MOBILE: | |
2406 | case PM_TABLET: | |
2407 | case PM_APPLIANCE_PC: | |
2408 | case PM_DESKTOP: | |
2409 | case PM_WORKSTATION: | |
7f7a516e SP |
2410 | pstate_funcs.get_target_pstate = |
2411 | get_target_pstate_use_cpu_load; | |
55395345 | 2412 | } |
7f7a516e SP |
2413 | } |
2414 | #else | |
2415 | static void intel_pstate_use_acpi_profile(void) | |
2416 | { | |
2417 | } | |
2418 | #endif | |
2419 | ||
29327c84 | 2420 | static void __init copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
2421 | { |
2422 | pstate_funcs.get_max = funcs->get_max; | |
3bcc6fa9 | 2423 | pstate_funcs.get_max_physical = funcs->get_max_physical; |
016c8150 DB |
2424 | pstate_funcs.get_min = funcs->get_min; |
2425 | pstate_funcs.get_turbo = funcs->get_turbo; | |
b27580b0 | 2426 | pstate_funcs.get_scaling = funcs->get_scaling; |
fdfdb2b1 | 2427 | pstate_funcs.get_val = funcs->get_val; |
007bea09 | 2428 | pstate_funcs.get_vid = funcs->get_vid; |
157386b6 PL |
2429 | pstate_funcs.get_target_pstate = funcs->get_target_pstate; |
2430 | ||
7f7a516e | 2431 | intel_pstate_use_acpi_profile(); |
016c8150 DB |
2432 | } |
2433 | ||
9522a2ff | 2434 | #ifdef CONFIG_ACPI |
fbbcdc07 | 2435 | |
29327c84 | 2436 | static bool __init intel_pstate_no_acpi_pss(void) |
fbbcdc07 AH |
2437 | { |
2438 | int i; | |
2439 | ||
2440 | for_each_possible_cpu(i) { | |
2441 | acpi_status status; | |
2442 | union acpi_object *pss; | |
2443 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
2444 | struct acpi_processor *pr = per_cpu(processors, i); | |
2445 | ||
2446 | if (!pr) | |
2447 | continue; | |
2448 | ||
2449 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
2450 | if (ACPI_FAILURE(status)) | |
2451 | continue; | |
2452 | ||
2453 | pss = buffer.pointer; | |
2454 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
2455 | kfree(pss); | |
2456 | return false; | |
2457 | } | |
2458 | ||
2459 | kfree(pss); | |
2460 | } | |
2461 | ||
2462 | return true; | |
2463 | } | |
2464 | ||
29327c84 | 2465 | static bool __init intel_pstate_has_acpi_ppc(void) |
966916ea | 2466 | { |
2467 | int i; | |
2468 | ||
2469 | for_each_possible_cpu(i) { | |
2470 | struct acpi_processor *pr = per_cpu(processors, i); | |
2471 | ||
2472 | if (!pr) | |
2473 | continue; | |
2474 | if (acpi_has_method(pr->handle, "_PPC")) | |
2475 | return true; | |
2476 | } | |
2477 | return false; | |
2478 | } | |
2479 | ||
2480 | enum { | |
2481 | PSS, | |
2482 | PPC, | |
2483 | }; | |
2484 | ||
fbbcdc07 AH |
2485 | struct hw_vendor_info { |
2486 | u16 valid; | |
2487 | char oem_id[ACPI_OEM_ID_SIZE]; | |
2488 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
966916ea | 2489 | int oem_pwr_table; |
fbbcdc07 AH |
2490 | }; |
2491 | ||
2492 | /* Hardware vendor-specific info that has its own power management modes */ | |
29327c84 | 2493 | static struct hw_vendor_info vendor_info[] __initdata = { |
966916ea | 2494 | {1, "HP ", "ProLiant", PSS}, |
2495 | {1, "ORACLE", "X4-2 ", PPC}, | |
2496 | {1, "ORACLE", "X4-2L ", PPC}, | |
2497 | {1, "ORACLE", "X4-2B ", PPC}, | |
2498 | {1, "ORACLE", "X3-2 ", PPC}, | |
2499 | {1, "ORACLE", "X3-2L ", PPC}, | |
2500 | {1, "ORACLE", "X3-2B ", PPC}, | |
2501 | {1, "ORACLE", "X4470M2 ", PPC}, | |
2502 | {1, "ORACLE", "X4270M3 ", PPC}, | |
2503 | {1, "ORACLE", "X4270M2 ", PPC}, | |
2504 | {1, "ORACLE", "X4170M2 ", PPC}, | |
5aecc3c8 EZ |
2505 | {1, "ORACLE", "X4170 M3", PPC}, |
2506 | {1, "ORACLE", "X4275 M3", PPC}, | |
2507 | {1, "ORACLE", "X6-2 ", PPC}, | |
2508 | {1, "ORACLE", "Sudbury ", PPC}, | |
fbbcdc07 AH |
2509 | {0, "", ""}, |
2510 | }; | |
2511 | ||
29327c84 | 2512 | static bool __init intel_pstate_platform_pwr_mgmt_exists(void) |
fbbcdc07 AH |
2513 | { |
2514 | struct acpi_table_header hdr; | |
2515 | struct hw_vendor_info *v_info; | |
2f86dc4c DB |
2516 | const struct x86_cpu_id *id; |
2517 | u64 misc_pwr; | |
2518 | ||
2519 | id = x86_match_cpu(intel_pstate_cpu_oob_ids); | |
2520 | if (id) { | |
2521 | rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); | |
2522 | if ( misc_pwr & (1 << 8)) | |
2523 | return true; | |
2524 | } | |
fbbcdc07 | 2525 | |
c410833a SK |
2526 | if (acpi_disabled || |
2527 | ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) | |
fbbcdc07 AH |
2528 | return false; |
2529 | ||
2530 | for (v_info = vendor_info; v_info->valid; v_info++) { | |
c410833a | 2531 | if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && |
966916ea | 2532 | !strncmp(hdr.oem_table_id, v_info->oem_table_id, |
2533 | ACPI_OEM_TABLE_ID_SIZE)) | |
2534 | switch (v_info->oem_pwr_table) { | |
2535 | case PSS: | |
2536 | return intel_pstate_no_acpi_pss(); | |
2537 | case PPC: | |
aa4ea34d EZ |
2538 | return intel_pstate_has_acpi_ppc() && |
2539 | (!force_load); | |
966916ea | 2540 | } |
fbbcdc07 AH |
2541 | } |
2542 | ||
2543 | return false; | |
2544 | } | |
d0ea59e1 RW |
2545 | |
2546 | static void intel_pstate_request_control_from_smm(void) | |
2547 | { | |
2548 | /* | |
2549 | * It may be unsafe to request P-states control from SMM if _PPC support | |
2550 | * has not been enabled. | |
2551 | */ | |
2552 | if (acpi_ppc) | |
2553 | acpi_processor_pstate_control(); | |
2554 | } | |
fbbcdc07 AH |
2555 | #else /* CONFIG_ACPI not enabled */ |
2556 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
966916ea | 2557 | static inline bool intel_pstate_has_acpi_ppc(void) { return false; } |
d0ea59e1 | 2558 | static inline void intel_pstate_request_control_from_smm(void) {} |
fbbcdc07 AH |
2559 | #endif /* CONFIG_ACPI */ |
2560 | ||
7791e4aa SP |
2561 | static const struct x86_cpu_id hwp_support_ids[] __initconst = { |
2562 | { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP }, | |
2563 | {} | |
2564 | }; | |
2565 | ||
93f0822d DB |
2566 | static int __init intel_pstate_init(void) |
2567 | { | |
eb5139d1 | 2568 | int rc; |
93f0822d | 2569 | |
6be26498 DB |
2570 | if (no_load) |
2571 | return -ENODEV; | |
2572 | ||
eb5139d1 | 2573 | if (x86_match_cpu(hwp_support_ids)) { |
7791e4aa | 2574 | copy_cpu_funcs(&core_params.funcs); |
eb5139d1 RW |
2575 | if (no_hwp) { |
2576 | pstate_funcs.get_target_pstate = get_target_pstate_use_cpu_load; | |
2577 | } else { | |
2578 | hwp_active++; | |
2579 | intel_pstate.attr = hwp_cpufreq_attrs; | |
2580 | goto hwp_cpu_matched; | |
2581 | } | |
2582 | } else { | |
2583 | const struct x86_cpu_id *id; | |
2584 | struct cpu_defaults *cpu_def; | |
7791e4aa | 2585 | |
eb5139d1 RW |
2586 | id = x86_match_cpu(intel_pstate_cpu_ids); |
2587 | if (!id) | |
2588 | return -ENODEV; | |
93f0822d | 2589 | |
eb5139d1 | 2590 | cpu_def = (struct cpu_defaults *)id->driver_data; |
eb5139d1 RW |
2591 | copy_cpu_funcs(&cpu_def->funcs); |
2592 | } | |
016c8150 | 2593 | |
b563b4e3 DB |
2594 | if (intel_pstate_msrs_not_valid()) |
2595 | return -ENODEV; | |
2596 | ||
7791e4aa SP |
2597 | hwp_cpu_matched: |
2598 | /* | |
2599 | * The Intel pstate driver will be ignored if the platform | |
2600 | * firmware has its own power management modes. | |
2601 | */ | |
2602 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
2603 | return -ENODEV; | |
2604 | ||
fb1fe104 RW |
2605 | if (!hwp_active && hwp_only) |
2606 | return -ENOTSUPP; | |
2607 | ||
4836df17 | 2608 | pr_info("Intel P-state driver initializing\n"); |
93f0822d | 2609 | |
b57ffac5 | 2610 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
2611 | if (!all_cpu_data) |
2612 | return -ENOMEM; | |
93f0822d | 2613 | |
d0ea59e1 RW |
2614 | intel_pstate_request_control_from_smm(); |
2615 | ||
93f0822d | 2616 | intel_pstate_sysfs_expose_params(); |
b69880f9 | 2617 | |
0c30b65b | 2618 | mutex_lock(&intel_pstate_driver_lock); |
fb1fe104 | 2619 | rc = intel_pstate_register_driver(); |
0c30b65b | 2620 | mutex_unlock(&intel_pstate_driver_lock); |
fb1fe104 RW |
2621 | if (rc) |
2622 | return rc; | |
366430b5 | 2623 | |
7791e4aa | 2624 | if (hwp_active) |
4836df17 | 2625 | pr_info("HWP enabled\n"); |
7791e4aa | 2626 | |
fb1fe104 | 2627 | return 0; |
93f0822d DB |
2628 | } |
2629 | device_initcall(intel_pstate_init); | |
2630 | ||
6be26498 DB |
2631 | static int __init intel_pstate_setup(char *str) |
2632 | { | |
2633 | if (!str) | |
2634 | return -EINVAL; | |
2635 | ||
001c76f0 | 2636 | if (!strcmp(str, "disable")) { |
6be26498 | 2637 | no_load = 1; |
001c76f0 RW |
2638 | } else if (!strcmp(str, "passive")) { |
2639 | pr_info("Passive mode enabled\n"); | |
2640 | intel_pstate_driver = &intel_cpufreq; | |
2641 | no_hwp = 1; | |
2642 | } | |
539342f6 | 2643 | if (!strcmp(str, "no_hwp")) { |
4836df17 | 2644 | pr_info("HWP disabled\n"); |
2f86dc4c | 2645 | no_hwp = 1; |
539342f6 | 2646 | } |
aa4ea34d EZ |
2647 | if (!strcmp(str, "force")) |
2648 | force_load = 1; | |
d64c3b0b KCA |
2649 | if (!strcmp(str, "hwp_only")) |
2650 | hwp_only = 1; | |
eae48f04 SP |
2651 | if (!strcmp(str, "per_cpu_perf_limits")) |
2652 | per_cpu_limits = true; | |
9522a2ff SP |
2653 | |
2654 | #ifdef CONFIG_ACPI | |
2655 | if (!strcmp(str, "support_acpi_ppc")) | |
2656 | acpi_ppc = true; | |
2657 | #endif | |
2658 | ||
6be26498 DB |
2659 | return 0; |
2660 | } | |
2661 | early_param("intel_pstate", intel_pstate_setup); | |
2662 | ||
93f0822d DB |
2663 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
2664 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
2665 | MODULE_LICENSE("GPL"); |