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Commit | Line | Data |
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ec6bced6 | 1 | /* |
ffe4f0f1 | 2 | * CPU frequency scaling for OMAP using OPP information |
ec6bced6 TL |
3 | * |
4 | * Copyright (C) 2005 Nokia Corporation | |
5 | * Written by Tony Lindgren <tony@atomide.com> | |
6 | * | |
7 | * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King | |
8 | * | |
731e0cc6 SS |
9 | * Copyright (C) 2007-2011 Texas Instruments, Inc. |
10 | * - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar | |
11 | * | |
ec6bced6 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | #include <linux/types.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/cpufreq.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/err.h> | |
f8ce2547 | 23 | #include <linux/clk.h> |
fced80c7 | 24 | #include <linux/io.h> |
731e0cc6 | 25 | #include <linux/opp.h> |
46c12216 | 26 | #include <linux/cpu.h> |
c1b547bc | 27 | #include <linux/module.h> |
53dfe8a8 | 28 | #include <linux/regulator/consumer.h> |
ec6bced6 | 29 | |
731e0cc6 | 30 | #include <asm/smp_plat.h> |
46c12216 | 31 | #include <asm/cpu.h> |
ec6bced6 | 32 | |
42daffd2 AM |
33 | /* OPP tolerance in percentage */ |
34 | #define OPP_TOLERANCE 4 | |
35 | ||
731e0cc6 | 36 | static struct cpufreq_frequency_table *freq_table; |
1c78217f | 37 | static atomic_t freq_table_users = ATOMIC_INIT(0); |
b8488fbe | 38 | static struct clk *mpu_clk; |
a820ffa8 | 39 | static struct device *mpu_dev; |
53dfe8a8 | 40 | static struct regulator *mpu_reg; |
b8488fbe | 41 | |
b0a330dc | 42 | static int omap_verify_speed(struct cpufreq_policy *policy) |
ec6bced6 | 43 | { |
bf2a359d | 44 | if (!freq_table) |
ec6bced6 | 45 | return -EINVAL; |
bf2a359d | 46 | return cpufreq_frequency_table_verify(policy, freq_table); |
ec6bced6 TL |
47 | } |
48 | ||
b0a330dc | 49 | static unsigned int omap_getspeed(unsigned int cpu) |
ec6bced6 | 50 | { |
ec6bced6 TL |
51 | unsigned long rate; |
52 | ||
46c12216 | 53 | if (cpu >= NR_CPUS) |
ec6bced6 TL |
54 | return 0; |
55 | ||
ec6bced6 | 56 | rate = clk_get_rate(mpu_clk) / 1000; |
ec6bced6 TL |
57 | return rate; |
58 | } | |
59 | ||
60 | static int omap_target(struct cpufreq_policy *policy, | |
61 | unsigned int target_freq, | |
62 | unsigned int relation) | |
63 | { | |
bf2a359d | 64 | unsigned int i; |
53dfe8a8 | 65 | int r, ret = 0; |
731e0cc6 | 66 | struct cpufreq_freqs freqs; |
53dfe8a8 | 67 | struct opp *opp; |
42daffd2 | 68 | unsigned long freq, volt = 0, volt_old = 0, tol = 0; |
ec6bced6 | 69 | |
bf2a359d NM |
70 | if (!freq_table) { |
71 | dev_err(mpu_dev, "%s: cpu%d: no freq table!\n", __func__, | |
72 | policy->cpu); | |
73 | return -EINVAL; | |
74 | } | |
75 | ||
76 | ret = cpufreq_frequency_table_target(policy, freq_table, target_freq, | |
77 | relation, &i); | |
78 | if (ret) { | |
79 | dev_dbg(mpu_dev, "%s: cpu%d: no freq match for %d(ret=%d)\n", | |
80 | __func__, policy->cpu, target_freq, ret); | |
81 | return ret; | |
82 | } | |
83 | freqs.new = freq_table[i].frequency; | |
84 | if (!freqs.new) { | |
85 | dev_err(mpu_dev, "%s: cpu%d: no match for freq %d\n", __func__, | |
86 | policy->cpu, target_freq); | |
87 | return -EINVAL; | |
88 | } | |
aeec2990 | 89 | |
46c12216 | 90 | freqs.old = omap_getspeed(policy->cpu); |
ec6bced6 | 91 | |
022ac03b | 92 | if (freqs.old == freqs.new && policy->cur == freqs.new) |
aeec2990 KH |
93 | return ret; |
94 | ||
46c12216 | 95 | /* notifiers */ |
b43a7ffb | 96 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); |
731e0cc6 | 97 | |
53dfe8a8 | 98 | freq = freqs.new * 1000; |
8df0a663 KH |
99 | ret = clk_round_rate(mpu_clk, freq); |
100 | if (IS_ERR_VALUE(ret)) { | |
101 | dev_warn(mpu_dev, | |
102 | "CPUfreq: Cannot find matching frequency for %lu\n", | |
103 | freq); | |
104 | return ret; | |
105 | } | |
106 | freq = ret; | |
53dfe8a8 KH |
107 | |
108 | if (mpu_reg) { | |
f44d188a | 109 | rcu_read_lock(); |
53dfe8a8 KH |
110 | opp = opp_find_freq_ceil(mpu_dev, &freq); |
111 | if (IS_ERR(opp)) { | |
f44d188a | 112 | rcu_read_unlock(); |
53dfe8a8 KH |
113 | dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n", |
114 | __func__, freqs.new); | |
115 | return -EINVAL; | |
116 | } | |
117 | volt = opp_get_voltage(opp); | |
f44d188a | 118 | rcu_read_unlock(); |
42daffd2 | 119 | tol = volt * OPP_TOLERANCE / 100; |
53dfe8a8 KH |
120 | volt_old = regulator_get_voltage(mpu_reg); |
121 | } | |
122 | ||
123 | dev_dbg(mpu_dev, "cpufreq-omap: %u MHz, %ld mV --> %u MHz, %ld mV\n", | |
124 | freqs.old / 1000, volt_old ? volt_old / 1000 : -1, | |
125 | freqs.new / 1000, volt ? volt / 1000 : -1); | |
126 | ||
127 | /* scaling up? scale voltage before frequency */ | |
128 | if (mpu_reg && (freqs.new > freqs.old)) { | |
42daffd2 | 129 | r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol); |
53dfe8a8 KH |
130 | if (r < 0) { |
131 | dev_warn(mpu_dev, "%s: unable to scale voltage up.\n", | |
132 | __func__); | |
133 | freqs.new = freqs.old; | |
134 | goto done; | |
135 | } | |
136 | } | |
731e0cc6 | 137 | |
aeec2990 | 138 | ret = clk_set_rate(mpu_clk, freqs.new * 1000); |
46c12216 | 139 | |
53dfe8a8 KH |
140 | /* scaling down? scale voltage after frequency */ |
141 | if (mpu_reg && (freqs.new < freqs.old)) { | |
42daffd2 | 142 | r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol); |
53dfe8a8 KH |
143 | if (r < 0) { |
144 | dev_warn(mpu_dev, "%s: unable to scale voltage down.\n", | |
145 | __func__); | |
146 | ret = clk_set_rate(mpu_clk, freqs.old * 1000); | |
147 | freqs.new = freqs.old; | |
148 | goto done; | |
149 | } | |
150 | } | |
151 | ||
152 | freqs.new = omap_getspeed(policy->cpu); | |
46c12216 | 153 | |
53dfe8a8 | 154 | done: |
46c12216 | 155 | /* notifiers */ |
b43a7ffb | 156 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); |
ec6bced6 TL |
157 | |
158 | return ret; | |
159 | } | |
160 | ||
1c78217f NM |
161 | static inline void freq_table_free(void) |
162 | { | |
163 | if (atomic_dec_and_test(&freq_table_users)) | |
164 | opp_free_cpufreq_table(mpu_dev, &freq_table); | |
165 | } | |
166 | ||
790ab7e9 | 167 | static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy) |
ec6bced6 | 168 | { |
aeec2990 | 169 | int result = 0; |
731e0cc6 | 170 | |
e2ee1b4d | 171 | mpu_clk = clk_get(NULL, "cpufreq_ck"); |
ec6bced6 TL |
172 | if (IS_ERR(mpu_clk)) |
173 | return PTR_ERR(mpu_clk); | |
174 | ||
11e04fdd NM |
175 | if (policy->cpu >= NR_CPUS) { |
176 | result = -EINVAL; | |
177 | goto fail_ck; | |
178 | } | |
aeec2990 | 179 | |
46c12216 | 180 | policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu); |
1c78217f | 181 | |
1b865214 | 182 | if (!freq_table) |
1c78217f | 183 | result = opp_init_cpufreq_table(mpu_dev, &freq_table); |
bf2a359d NM |
184 | |
185 | if (result) { | |
186 | dev_err(mpu_dev, "%s: cpu%d: failed creating freq table[%d]\n", | |
187 | __func__, policy->cpu, result); | |
11e04fdd | 188 | goto fail_ck; |
aeec2990 KH |
189 | } |
190 | ||
1b865214 RN |
191 | atomic_inc_return(&freq_table_users); |
192 | ||
bf2a359d | 193 | result = cpufreq_frequency_table_cpuinfo(policy, freq_table); |
1c78217f NM |
194 | if (result) |
195 | goto fail_table; | |
196 | ||
197 | cpufreq_frequency_table_get_attr(freq_table, policy->cpu); | |
bf2a359d | 198 | |
731e0cc6 SS |
199 | policy->min = policy->cpuinfo.min_freq; |
200 | policy->max = policy->cpuinfo.max_freq; | |
46c12216 RK |
201 | policy->cur = omap_getspeed(policy->cpu); |
202 | ||
203 | /* | |
204 | * On OMAP SMP configuartion, both processors share the voltage | |
205 | * and clock. So both CPUs needs to be scaled together and hence | |
206 | * needs software co-ordination. Use cpufreq affected_cpus | |
207 | * interface to handle this scenario. Additional is_smp() check | |
208 | * is to keep SMP_ON_UP build working. | |
209 | */ | |
62b36cc1 | 210 | if (is_smp()) |
ed8ce00c | 211 | cpumask_setall(policy->cpus); |
731e0cc6 | 212 | |
aeec2990 | 213 | /* FIXME: what's the actual transition time? */ |
b029839c | 214 | policy->cpuinfo.transition_latency = 300 * 1000; |
ec6bced6 TL |
215 | |
216 | return 0; | |
11e04fdd | 217 | |
1c78217f NM |
218 | fail_table: |
219 | freq_table_free(); | |
11e04fdd NM |
220 | fail_ck: |
221 | clk_put(mpu_clk); | |
222 | return result; | |
ec6bced6 TL |
223 | } |
224 | ||
b8488fbe HD |
225 | static int omap_cpu_exit(struct cpufreq_policy *policy) |
226 | { | |
1c78217f | 227 | freq_table_free(); |
b8488fbe HD |
228 | clk_put(mpu_clk); |
229 | return 0; | |
230 | } | |
231 | ||
aeec2990 KH |
232 | static struct freq_attr *omap_cpufreq_attr[] = { |
233 | &cpufreq_freq_attr_scaling_available_freqs, | |
234 | NULL, | |
235 | }; | |
236 | ||
ec6bced6 TL |
237 | static struct cpufreq_driver omap_driver = { |
238 | .flags = CPUFREQ_STICKY, | |
239 | .verify = omap_verify_speed, | |
240 | .target = omap_target, | |
241 | .get = omap_getspeed, | |
242 | .init = omap_cpu_init, | |
b8488fbe | 243 | .exit = omap_cpu_exit, |
ec6bced6 | 244 | .name = "omap", |
aeec2990 | 245 | .attr = omap_cpufreq_attr, |
ec6bced6 TL |
246 | }; |
247 | ||
248 | static int __init omap_cpufreq_init(void) | |
249 | { | |
747a7f64 KH |
250 | mpu_dev = get_cpu_device(0); |
251 | if (!mpu_dev) { | |
a820ffa8 | 252 | pr_warning("%s: unable to get the mpu device\n", __func__); |
747a7f64 | 253 | return -EINVAL; |
a820ffa8 NM |
254 | } |
255 | ||
53dfe8a8 KH |
256 | mpu_reg = regulator_get(mpu_dev, "vcc"); |
257 | if (IS_ERR(mpu_reg)) { | |
258 | pr_warning("%s: unable to get MPU regulator\n", __func__); | |
259 | mpu_reg = NULL; | |
260 | } else { | |
261 | /* | |
262 | * Ensure physical regulator is present. | |
263 | * (e.g. could be dummy regulator.) | |
264 | */ | |
265 | if (regulator_get_voltage(mpu_reg) < 0) { | |
266 | pr_warn("%s: physical regulator not present for MPU\n", | |
267 | __func__); | |
268 | regulator_put(mpu_reg); | |
269 | mpu_reg = NULL; | |
270 | } | |
271 | } | |
272 | ||
ec6bced6 TL |
273 | return cpufreq_register_driver(&omap_driver); |
274 | } | |
275 | ||
731e0cc6 SS |
276 | static void __exit omap_cpufreq_exit(void) |
277 | { | |
278 | cpufreq_unregister_driver(&omap_driver); | |
279 | } | |
aeec2990 | 280 | |
731e0cc6 SS |
281 | MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs"); |
282 | MODULE_LICENSE("GPL"); | |
283 | module_init(omap_cpufreq_init); | |
284 | module_exit(omap_cpufreq_exit); |