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crypto: caam - fix uninitialized edesc->dst_dma field
[mirror_ubuntu-artful-kernel.git] / drivers / crypto / caam / caamhash.c
CommitLineData
045e3678
YK		 1/*
2 * caam - Freescale FSL CAAM support for ahash functions of crypto API
3 *
4 * Copyright 2011 Freescale Semiconductor, Inc.
5 *
6 * Based on caamalg.c crypto API driver.
7 *
8 * relationship of digest job descriptor or first job descriptor after init to
9 * shared descriptors:
10 *
11 * --------------- ---------------
12 * | JobDesc #1 |-------------------->| ShareDesc |
13 * | *(packet 1) | | (hashKey) |
14 * --------------- | (operation) |
15 * ---------------
16 *
17 * relationship of subsequent job descriptors to shared descriptors:
18 *
19 * --------------- ---------------
20 * | JobDesc #2 |-------------------->| ShareDesc |
21 * | *(packet 2) | |------------->| (hashKey) |
22 * --------------- | |-------->| (operation) |
23 * . | | | (load ctx2) |
24 * . | | ---------------
25 * --------------- | |
26 * | JobDesc #3 |------| |
27 * | *(packet 3) | |
28 * --------------- |
29 * . |
30 * . |
31 * --------------- |
32 * | JobDesc #4 |------------
33 * | *(packet 4) |
34 * ---------------
35 *
36 * The SharedDesc never changes for a connection unless rekeyed, but
37 * each packet will likely be in a different place. So all we need
38 * to know to process the packet is where the input is, where the
39 * output goes, and what context we want to process with. Context is
40 * in the SharedDesc, packet references in the JobDesc.
41 *
42 * So, a job desc looks like:
43 *
44 * ---------------------
45 * | Header |
46 * | ShareDesc Pointer |
47 * | SEQ_OUT_PTR |
48 * | (output buffer) |
49 * | (output length) |
50 * | SEQ_IN_PTR |
51 * | (input buffer) |
52 * | (input length) |
53 * ---------------------
54 */
55
56#include "compat.h"
57
58#include "regs.h"
59#include "intern.h"
60#include "desc_constr.h"
61#include "jr.h"
62#include "error.h"
63#include "sg_sw_sec4.h"
64#include "key_gen.h"
65
66#define CAAM_CRA_PRIORITY 3000
67
68/* max hash key is max split key size */
69#define CAAM_MAX_HASH_KEY_SIZE (SHA512_DIGEST_SIZE * 2)
70
71#define CAAM_MAX_HASH_BLOCK_SIZE SHA512_BLOCK_SIZE
72#define CAAM_MAX_HASH_DIGEST_SIZE SHA512_DIGEST_SIZE
73
74/* length of descriptors text */
045e3678
YK		 75#define DESC_AHASH_BASE (4 * CAAM_CMD_SZ)
76#define DESC_AHASH_UPDATE_LEN (6 * CAAM_CMD_SZ)
77#define DESC_AHASH_UPDATE_FIRST_LEN (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
78#define DESC_AHASH_FINAL_LEN (DESC_AHASH_BASE + 5 * CAAM_CMD_SZ)
79#define DESC_AHASH_FINUP_LEN (DESC_AHASH_BASE + 5 * CAAM_CMD_SZ)
80#define DESC_AHASH_DIGEST_LEN (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
81
82#define DESC_HASH_MAX_USED_BYTES (DESC_AHASH_FINAL_LEN + \
83 CAAM_MAX_HASH_KEY_SIZE)
84#define DESC_HASH_MAX_USED_LEN (DESC_HASH_MAX_USED_BYTES / CAAM_CMD_SZ)
85
86/* caam context sizes for hashes: running digest + 8 */
87#define HASH_MSG_LEN 8
88#define MAX_CTX_LEN (HASH_MSG_LEN + SHA512_DIGEST_SIZE)
89
90#ifdef DEBUG
91/* for print_hex_dumps with line references */
045e3678
YK		 92#define debug(format, arg...) printk(format, arg)
93#else
94#define debug(format, arg...)
95#endif
96
cfc6f11b
RG		 97
98static struct list_head hash_list;
99
045e3678
YK		 100/* ahash per-session context */
101struct caam_hash_ctx {
102 struct device *jrdev;
103 u32 sh_desc_update[DESC_HASH_MAX_USED_LEN];
104 u32 sh_desc_update_first[DESC_HASH_MAX_USED_LEN];
105 u32 sh_desc_fin[DESC_HASH_MAX_USED_LEN];
106 u32 sh_desc_digest[DESC_HASH_MAX_USED_LEN];
107 u32 sh_desc_finup[DESC_HASH_MAX_USED_LEN];
108 dma_addr_t sh_desc_update_dma;
109 dma_addr_t sh_desc_update_first_dma;
110 dma_addr_t sh_desc_fin_dma;
111 dma_addr_t sh_desc_digest_dma;
112 dma_addr_t sh_desc_finup_dma;
113 u32 alg_type;
114 u32 alg_op;
115 u8 key[CAAM_MAX_HASH_KEY_SIZE];
116 dma_addr_t key_dma;
117 int ctx_len;
118 unsigned int split_key_len;
119 unsigned int split_key_pad_len;
120};
121
122/* ahash state */
123struct caam_hash_state {
124 dma_addr_t buf_dma;
125 dma_addr_t ctx_dma;
126 u8 buf_0[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
127 int buflen_0;
128 u8 buf_1[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
129 int buflen_1;
130 u8 caam_ctx[MAX_CTX_LEN];
131 int (*update)(struct ahash_request *req);
132 int (*final)(struct ahash_request *req);
133 int (*finup)(struct ahash_request *req);
134 int current_buf;
135};
136
137/* Common job descriptor seq in/out ptr routines */
138
139/* Map state->caam_ctx, and append seq_out_ptr command that points to it */
ce572085
HG		 140static inline int map_seq_out_ptr_ctx(u32 *desc, struct device *jrdev,
141 struct caam_hash_state *state,
142 int ctx_len)
045e3678
YK		 143{
144 state->ctx_dma = dma_map_single(jrdev, state->caam_ctx,
145 ctx_len, DMA_FROM_DEVICE);
ce572085
HG		 146 if (dma_mapping_error(jrdev, state->ctx_dma)) {
147 dev_err(jrdev, "unable to map ctx\n");
148 return -ENOMEM;
149 }
150
045e3678 151 append_seq_out_ptr(desc, state->ctx_dma, ctx_len, 0);
ce572085
HG		 152
153 return 0;
045e3678
YK		 154}
155
156/* Map req->result, and append seq_out_ptr command that points to it */
157static inline dma_addr_t map_seq_out_ptr_result(u32 *desc, struct device *jrdev,
158 u8 *result, int digestsize)
159{
160 dma_addr_t dst_dma;
161
162 dst_dma = dma_map_single(jrdev, result, digestsize, DMA_FROM_DEVICE);
163 append_seq_out_ptr(desc, dst_dma, digestsize, 0);
164
165 return dst_dma;
166}
167
168/* Map current buffer in state and put it in link table */
169static inline dma_addr_t buf_map_to_sec4_sg(struct device *jrdev,
170 struct sec4_sg_entry *sec4_sg,
171 u8 *buf, int buflen)
172{
173 dma_addr_t buf_dma;
174
175 buf_dma = dma_map_single(jrdev, buf, buflen, DMA_TO_DEVICE);
176 dma_to_sec4_sg_one(sec4_sg, buf_dma, buflen, 0);
177
178 return buf_dma;
179}
180
181/* Map req->src and put it in link table */
182static inline void src_map_to_sec4_sg(struct device *jrdev,
183 struct scatterlist *src, int src_nents,
643b39b0
YK		 184 struct sec4_sg_entry *sec4_sg,
185 bool chained)
045e3678 186{
643b39b0 187 dma_map_sg_chained(jrdev, src, src_nents, DMA_TO_DEVICE, chained);
045e3678
YK		 188 sg_to_sec4_sg_last(src, src_nents, sec4_sg, 0);
189}
190
191/*
192 * Only put buffer in link table if it contains data, which is possible,
193 * since a buffer has previously been used, and needs to be unmapped,
194 */
195static inline dma_addr_t
196try_buf_map_to_sec4_sg(struct device *jrdev, struct sec4_sg_entry *sec4_sg,
197 u8 *buf, dma_addr_t buf_dma, int buflen,
198 int last_buflen)
199{
200 if (buf_dma && !dma_mapping_error(jrdev, buf_dma))
201 dma_unmap_single(jrdev, buf_dma, last_buflen, DMA_TO_DEVICE);
202 if (buflen)
203 buf_dma = buf_map_to_sec4_sg(jrdev, sec4_sg, buf, buflen);
204 else
205 buf_dma = 0;
206
207 return buf_dma;
208}
209
210/* Map state->caam_ctx, and add it to link table */
ce572085
HG		 211static inline int ctx_map_to_sec4_sg(u32 *desc, struct device *jrdev,
212 struct caam_hash_state *state, int ctx_len,
213 struct sec4_sg_entry *sec4_sg, u32 flag)
045e3678
YK		 214{
215 state->ctx_dma = dma_map_single(jrdev, state->caam_ctx, ctx_len, flag);
ce572085
HG		 216 if (dma_mapping_error(jrdev, state->ctx_dma)) {
217 dev_err(jrdev, "unable to map ctx\n");
218 return -ENOMEM;
219 }
220
045e3678 221 dma_to_sec4_sg_one(sec4_sg, state->ctx_dma, ctx_len, 0);
ce572085
HG		 222
223 return 0;
045e3678
YK		 224}
225
226/* Common shared descriptor commands */
227static inline void append_key_ahash(u32 *desc, struct caam_hash_ctx *ctx)
228{
229 append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len,
230 ctx->split_key_len, CLASS_2 |
231 KEY_DEST_MDHA_SPLIT | KEY_ENC);
232}
233
234/* Append key if it has been set */
235static inline void init_sh_desc_key_ahash(u32 *desc, struct caam_hash_ctx *ctx)
236{
237 u32 *key_jump_cmd;
238
61bb86bb 239 init_sh_desc(desc, HDR_SHARE_SERIAL);
045e3678
YK		 240
241 if (ctx->split_key_len) {
242 /* Skip if already shared */
243 key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
244 JUMP_COND_SHRD);
245
246 append_key_ahash(desc, ctx);
247
248 set_jump_tgt_here(desc, key_jump_cmd);
249 }
250
251 /* Propagate errors from shared to job descriptor */
252 append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
253}
254
255/*
256 * For ahash read data from seqin following state->caam_ctx,
257 * and write resulting class2 context to seqout, which may be state->caam_ctx
258 * or req->result
259 */
260static inline void ahash_append_load_str(u32 *desc, int digestsize)
261{
262 /* Calculate remaining bytes to read */
263 append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
264
265 /* Read remaining bytes */
266 append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_LAST2 |
267 FIFOLD_TYPE_MSG | KEY_VLF);
268
269 /* Store class2 context bytes */
270 append_seq_store(desc, digestsize, LDST_CLASS_2_CCB |
271 LDST_SRCDST_BYTE_CONTEXT);
272}
273
274/*
275 * For ahash update, final and finup, import context, read and write to seqout
276 */
277static inline void ahash_ctx_data_to_out(u32 *desc, u32 op, u32 state,
278 int digestsize,
279 struct caam_hash_ctx *ctx)
280{
281 init_sh_desc_key_ahash(desc, ctx);
282
283 /* Import context from software */
284 append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
285 LDST_CLASS_2_CCB | ctx->ctx_len);
286
287 /* Class 2 operation */
288 append_operation(desc, op | state | OP_ALG_ENCRYPT);
289
290 /*
291 * Load from buf and/or src and write to req->result or state->context
292 */
293 ahash_append_load_str(desc, digestsize);
294}
295
296/* For ahash firsts and digest, read and write to seqout */
297static inline void ahash_data_to_out(u32 *desc, u32 op, u32 state,
298 int digestsize, struct caam_hash_ctx *ctx)
299{
300 init_sh_desc_key_ahash(desc, ctx);
301
302 /* Class 2 operation */
303 append_operation(desc, op | state | OP_ALG_ENCRYPT);
304
305 /*
306 * Load from buf and/or src and write to req->result or state->context
307 */
308 ahash_append_load_str(desc, digestsize);
309}
310
311static int ahash_set_sh_desc(struct crypto_ahash *ahash)
312{
313 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
314 int digestsize = crypto_ahash_digestsize(ahash);
315 struct device *jrdev = ctx->jrdev;
316 u32 have_key = 0;
317 u32 *desc;
318
319 if (ctx->split_key_len)
320 have_key = OP_ALG_AAI_HMAC_PRECOMP;
321
322 /* ahash_update shared descriptor */
323 desc = ctx->sh_desc_update;
324
61bb86bb 325 init_sh_desc(desc, HDR_SHARE_SERIAL);
045e3678
YK		 326
327 /* Import context from software */
328 append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
329 LDST_CLASS_2_CCB | ctx->ctx_len);
330
331 /* Class 2 operation */
332 append_operation(desc, ctx->alg_type | OP_ALG_AS_UPDATE |
333 OP_ALG_ENCRYPT);
334
335 /* Load data and write to result or context */
336 ahash_append_load_str(desc, ctx->ctx_len);
337
338 ctx->sh_desc_update_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
339 DMA_TO_DEVICE);
340 if (dma_mapping_error(jrdev, ctx->sh_desc_update_dma)) {
341 dev_err(jrdev, "unable to map shared descriptor\n");
342 return -ENOMEM;
343 }
344#ifdef DEBUG
514df281
AP		 345 print_hex_dump(KERN_ERR,
346 "ahash update shdesc@"__stringify(__LINE__)": ",
045e3678
YK		 347 DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
348#endif
349
350 /* ahash_update_first shared descriptor */
351 desc = ctx->sh_desc_update_first;
352
353 ahash_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INIT,
354 ctx->ctx_len, ctx);
355
356 ctx->sh_desc_update_first_dma = dma_map_single(jrdev, desc,
357 desc_bytes(desc),
358 DMA_TO_DEVICE);
359 if (dma_mapping_error(jrdev, ctx->sh_desc_update_first_dma)) {
360 dev_err(jrdev, "unable to map shared descriptor\n");
361 return -ENOMEM;
362 }
363#ifdef DEBUG
514df281
AP		 364 print_hex_dump(KERN_ERR,
365 "ahash update first shdesc@"__stringify(__LINE__)": ",
045e3678
YK		 366 DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
367#endif
368
369 /* ahash_final shared descriptor */
370 desc = ctx->sh_desc_fin;
371
372 ahash_ctx_data_to_out(desc, have_key | ctx->alg_type,
373 OP_ALG_AS_FINALIZE, digestsize, ctx);
374
375 ctx->sh_desc_fin_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
376 DMA_TO_DEVICE);
377 if (dma_mapping_error(jrdev, ctx->sh_desc_fin_dma)) {
378 dev_err(jrdev, "unable to map shared descriptor\n");
379 return -ENOMEM;
380 }
381#ifdef DEBUG
514df281 382 print_hex_dump(KERN_ERR, "ahash final shdesc@"__stringify(__LINE__)": ",
045e3678
YK		 383 DUMP_PREFIX_ADDRESS, 16, 4, desc,
384 desc_bytes(desc), 1);
385#endif
386
387 /* ahash_finup shared descriptor */
388 desc = ctx->sh_desc_finup;
389
390 ahash_ctx_data_to_out(desc, have_key | ctx->alg_type,
391 OP_ALG_AS_FINALIZE, digestsize, ctx);
392
393 ctx->sh_desc_finup_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
394 DMA_TO_DEVICE);
395 if (dma_mapping_error(jrdev, ctx->sh_desc_finup_dma)) {
396 dev_err(jrdev, "unable to map shared descriptor\n");
397 return -ENOMEM;
398 }
399#ifdef DEBUG
514df281 400 print_hex_dump(KERN_ERR, "ahash finup shdesc@"__stringify(__LINE__)": ",
045e3678
YK		 401 DUMP_PREFIX_ADDRESS, 16, 4, desc,
402 desc_bytes(desc), 1);
403#endif
404
405 /* ahash_digest shared descriptor */
406 desc = ctx->sh_desc_digest;
407
408 ahash_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INITFINAL,
409 digestsize, ctx);
410
411 ctx->sh_desc_digest_dma = dma_map_single(jrdev, desc,
412 desc_bytes(desc),
413 DMA_TO_DEVICE);
414 if (dma_mapping_error(jrdev, ctx->sh_desc_digest_dma)) {
415 dev_err(jrdev, "unable to map shared descriptor\n");
416 return -ENOMEM;
417 }
418#ifdef DEBUG
514df281
AP		 419 print_hex_dump(KERN_ERR,
420 "ahash digest shdesc@"__stringify(__LINE__)": ",
045e3678
YK		 421 DUMP_PREFIX_ADDRESS, 16, 4, desc,
422 desc_bytes(desc), 1);
423#endif
424
425 return 0;
426}
427
66b3e887 428static int gen_split_hash_key(struct caam_hash_ctx *ctx, const u8 *key_in,
045e3678
YK		 429 u32 keylen)
430{
431 return gen_split_key(ctx->jrdev, ctx->key, ctx->split_key_len,
432 ctx->split_key_pad_len, key_in, keylen,
433 ctx->alg_op);
434}
435
436/* Digest hash size if it is too large */
66b3e887 437static int hash_digest_key(struct caam_hash_ctx *ctx, const u8 *key_in,
045e3678
YK		 438 u32 *keylen, u8 *key_out, u32 digestsize)
439{
440 struct device *jrdev = ctx->jrdev;
441 u32 *desc;
442 struct split_key_result result;
443 dma_addr_t src_dma, dst_dma;
444 int ret = 0;
445
9c23b7d3 446 desc = kmalloc(CAAM_CMD_SZ * 8 + CAAM_PTR_SZ * 2, GFP_KERNEL | GFP_DMA);
2af8f4a2
KP		 447 if (!desc) {
448 dev_err(jrdev, "unable to allocate key input memory\n");
449 return -ENOMEM;
450 }
045e3678
YK		 451
452 init_job_desc(desc, 0);
453
454 src_dma = dma_map_single(jrdev, (void *)key_in, *keylen,
455 DMA_TO_DEVICE);
456 if (dma_mapping_error(jrdev, src_dma)) {
457 dev_err(jrdev, "unable to map key input memory\n");
458 kfree(desc);
459 return -ENOMEM;
460 }
461 dst_dma = dma_map_single(jrdev, (void *)key_out, digestsize,
462 DMA_FROM_DEVICE);
463 if (dma_mapping_error(jrdev, dst_dma)) {
464 dev_err(jrdev, "unable to map key output memory\n");
465 dma_unmap_single(jrdev, src_dma, *keylen, DMA_TO_DEVICE);
466 kfree(desc);
467 return -ENOMEM;
468 }
469
470 /* Job descriptor to perform unkeyed hash on key_in */
471 append_operation(desc, ctx->alg_type | OP_ALG_ENCRYPT |
472 OP_ALG_AS_INITFINAL);
473 append_seq_in_ptr(desc, src_dma, *keylen, 0);
474 append_seq_fifo_load(desc, *keylen, FIFOLD_CLASS_CLASS2 |
475 FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_MSG);
476 append_seq_out_ptr(desc, dst_dma, digestsize, 0);
477 append_seq_store(desc, digestsize, LDST_CLASS_2_CCB |
478 LDST_SRCDST_BYTE_CONTEXT);
479
480#ifdef DEBUG
514df281 481 print_hex_dump(KERN_ERR, "key_in@"__stringify(__LINE__)": ",
045e3678 482 DUMP_PREFIX_ADDRESS, 16, 4, key_in, *keylen, 1);
514df281 483 print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
045e3678
YK		 484 DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
485#endif
486
487 result.err = 0;
488 init_completion(&result.completion);
489
490 ret = caam_jr_enqueue(jrdev, desc, split_key_done, &result);
491 if (!ret) {
492 /* in progress */
493 wait_for_completion_interruptible(&result.completion);
494 ret = result.err;
495#ifdef DEBUG
514df281
AP		 496 print_hex_dump(KERN_ERR,
497 "digested key@"__stringify(__LINE__)": ",
045e3678
YK		 498 DUMP_PREFIX_ADDRESS, 16, 4, key_in,
499 digestsize, 1);
500#endif
501 }
045e3678
YK		 502 dma_unmap_single(jrdev, src_dma, *keylen, DMA_TO_DEVICE);
503 dma_unmap_single(jrdev, dst_dma, digestsize, DMA_FROM_DEVICE);
504
e11aa9f1
HG		 505 *keylen = digestsize;
506
045e3678
YK		 507 kfree(desc);
508
509 return ret;
510}
511
512static int ahash_setkey(struct crypto_ahash *ahash,
513 const u8 *key, unsigned int keylen)
514{
515 /* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */
516 static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 };
517 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
518 struct device *jrdev = ctx->jrdev;
519 int blocksize = crypto_tfm_alg_blocksize(&ahash->base);
520 int digestsize = crypto_ahash_digestsize(ahash);
521 int ret = 0;
522 u8 *hashed_key = NULL;
523
524#ifdef DEBUG
525 printk(KERN_ERR "keylen %d\n", keylen);
526#endif
527
528 if (keylen > blocksize) {
529 hashed_key = kmalloc(sizeof(u8) * digestsize, GFP_KERNEL |
530 GFP_DMA);
531 if (!hashed_key)
532 return -ENOMEM;
533 ret = hash_digest_key(ctx, key, &keylen, hashed_key,
534 digestsize);
535 if (ret)
536 goto badkey;
537 key = hashed_key;
538 }
539
540 /* Pick class 2 key length from algorithm submask */
541 ctx->split_key_len = mdpadlen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >>
542 OP_ALG_ALGSEL_SHIFT] * 2;
543 ctx->split_key_pad_len = ALIGN(ctx->split_key_len, 16);
544
545#ifdef DEBUG
546 printk(KERN_ERR "split_key_len %d split_key_pad_len %d\n",
547 ctx->split_key_len, ctx->split_key_pad_len);
514df281 548 print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
045e3678
YK		 549 DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
550#endif
551
552 ret = gen_split_hash_key(ctx, key, keylen);
553 if (ret)
554 goto badkey;
555
556 ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len,
557 DMA_TO_DEVICE);
558 if (dma_mapping_error(jrdev, ctx->key_dma)) {
559 dev_err(jrdev, "unable to map key i/o memory\n");
3d67be27
HG		 560 ret = -ENOMEM;
561 goto map_err;
045e3678
YK		 562 }
563#ifdef DEBUG
514df281 564 print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
045e3678
YK		 565 DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
566 ctx->split_key_pad_len, 1);
567#endif
568
569 ret = ahash_set_sh_desc(ahash);
570 if (ret) {
571 dma_unmap_single(jrdev, ctx->key_dma, ctx->split_key_pad_len,
572 DMA_TO_DEVICE);
573 }
574
3d67be27 575map_err:
045e3678
YK		 576 kfree(hashed_key);
577 return ret;
578badkey:
579 kfree(hashed_key);
580 crypto_ahash_set_flags(ahash, CRYPTO_TFM_RES_BAD_KEY_LEN);
581 return -EINVAL;
582}
583
584/*
585 * ahash_edesc - s/w-extended ahash descriptor
586 * @dst_dma: physical mapped address of req->result
587 * @sec4_sg_dma: physical mapped address of h/w link table
643b39b0 588 * @chained: if source is chained
045e3678
YK		 589 * @src_nents: number of segments in input scatterlist
590 * @sec4_sg_bytes: length of dma mapped sec4_sg space
591 * @sec4_sg: pointer to h/w link table
592 * @hw_desc: the h/w job descriptor followed by any referenced link tables
593 */
594struct ahash_edesc {
595 dma_addr_t dst_dma;
596 dma_addr_t sec4_sg_dma;
643b39b0 597 bool chained;
045e3678
YK		 598 int src_nents;
599 int sec4_sg_bytes;
600 struct sec4_sg_entry *sec4_sg;
601 u32 hw_desc[0];
602};
603
604static inline void ahash_unmap(struct device *dev,
605 struct ahash_edesc *edesc,
606 struct ahash_request *req, int dst_len)
607{
608 if (edesc->src_nents)
643b39b0
YK		 609 dma_unmap_sg_chained(dev, req->src, edesc->src_nents,
610 DMA_TO_DEVICE, edesc->chained);
045e3678
YK		 611 if (edesc->dst_dma)
612 dma_unmap_single(dev, edesc->dst_dma, dst_len, DMA_FROM_DEVICE);
613
614 if (edesc->sec4_sg_bytes)
615 dma_unmap_single(dev, edesc->sec4_sg_dma,
616 edesc->sec4_sg_bytes, DMA_TO_DEVICE);
617}
618
619static inline void ahash_unmap_ctx(struct device *dev,
620 struct ahash_edesc *edesc,
621 struct ahash_request *req, int dst_len, u32 flag)
622{
623 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
624 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
625 struct caam_hash_state *state = ahash_request_ctx(req);
626
627 if (state->ctx_dma)
628 dma_unmap_single(dev, state->ctx_dma, ctx->ctx_len, flag);
629 ahash_unmap(dev, edesc, req, dst_len);
630}
631
632static void ahash_done(struct device *jrdev, u32 *desc, u32 err,
633 void *context)
634{
635 struct ahash_request *req = context;
636 struct ahash_edesc *edesc;
637 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
638 int digestsize = crypto_ahash_digestsize(ahash);
639#ifdef DEBUG
640 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
641 struct caam_hash_state *state = ahash_request_ctx(req);
642
643 dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
644#endif
645
646 edesc = (struct ahash_edesc *)((char *)desc -
647 offsetof(struct ahash_edesc, hw_desc));
fa9659cd
MV		 648 if (err)
649 caam_jr_strstatus(jrdev, err);
045e3678
YK		 650
651 ahash_unmap(jrdev, edesc, req, digestsize);
652 kfree(edesc);
653
654#ifdef DEBUG
514df281 655 print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
045e3678
YK		 656 DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
657 ctx->ctx_len, 1);
658 if (req->result)
514df281 659 print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
045e3678
YK		 660 DUMP_PREFIX_ADDRESS, 16, 4, req->result,
661 digestsize, 1);
662#endif
663
664 req->base.complete(&req->base, err);
665}
666
667static void ahash_done_bi(struct device *jrdev, u32 *desc, u32 err,
668 void *context)
669{
670 struct ahash_request *req = context;
671 struct ahash_edesc *edesc;
672 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
673 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
674#ifdef DEBUG
675 struct caam_hash_state *state = ahash_request_ctx(req);
676 int digestsize = crypto_ahash_digestsize(ahash);
677
678 dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
679#endif
680
681 edesc = (struct ahash_edesc *)((char *)desc -
682 offsetof(struct ahash_edesc, hw_desc));
fa9659cd
MV		 683 if (err)
684 caam_jr_strstatus(jrdev, err);
045e3678
YK		 685
686 ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL);
687 kfree(edesc);
688
689#ifdef DEBUG
514df281 690 print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
045e3678
YK		 691 DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
692 ctx->ctx_len, 1);
693 if (req->result)
514df281 694 print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
045e3678
YK		 695 DUMP_PREFIX_ADDRESS, 16, 4, req->result,
696 digestsize, 1);
697#endif
698
699 req->base.complete(&req->base, err);
700}
701
702static void ahash_done_ctx_src(struct device *jrdev, u32 *desc, u32 err,
703 void *context)
704{
705 struct ahash_request *req = context;
706 struct ahash_edesc *edesc;
707 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
708 int digestsize = crypto_ahash_digestsize(ahash);
709#ifdef DEBUG
710 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
711 struct caam_hash_state *state = ahash_request_ctx(req);
712
713 dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
714#endif
715
716 edesc = (struct ahash_edesc *)((char *)desc -
717 offsetof(struct ahash_edesc, hw_desc));
fa9659cd
MV		 718 if (err)
719 caam_jr_strstatus(jrdev, err);
045e3678 720
bc9e05f9 721 ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_TO_DEVICE);
045e3678
YK		 722 kfree(edesc);
723
724#ifdef DEBUG
514df281 725 print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
045e3678
YK		 726 DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
727 ctx->ctx_len, 1);
728 if (req->result)
514df281 729 print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
045e3678
YK		 730 DUMP_PREFIX_ADDRESS, 16, 4, req->result,
731 digestsize, 1);
732#endif
733
734 req->base.complete(&req->base, err);
735}
736
737static void ahash_done_ctx_dst(struct device *jrdev, u32 *desc, u32 err,
738 void *context)
739{
740 struct ahash_request *req = context;
741 struct ahash_edesc *edesc;
742 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
743 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
744#ifdef DEBUG
745 struct caam_hash_state *state = ahash_request_ctx(req);
746 int digestsize = crypto_ahash_digestsize(ahash);
747
748 dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
749#endif
750
751 edesc = (struct ahash_edesc *)((char *)desc -
752 offsetof(struct ahash_edesc, hw_desc));
fa9659cd
MV		 753 if (err)
754 caam_jr_strstatus(jrdev, err);
045e3678 755
ef62b231 756 ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_FROM_DEVICE);
045e3678
YK		 757 kfree(edesc);
758
759#ifdef DEBUG
514df281 760 print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
045e3678
YK		 761 DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
762 ctx->ctx_len, 1);
763 if (req->result)
514df281 764 print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
045e3678
YK		 765 DUMP_PREFIX_ADDRESS, 16, 4, req->result,
766 digestsize, 1);
767#endif
768
769 req->base.complete(&req->base, err);
770}
771
772/* submit update job descriptor */
773static int ahash_update_ctx(struct ahash_request *req)
774{
775 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
776 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
777 struct caam_hash_state *state = ahash_request_ctx(req);
778 struct device *jrdev = ctx->jrdev;
779 gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
780 CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
781 u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
782 int *buflen = state->current_buf ? &state->buflen_1 : &state->buflen_0;
783 u8 *next_buf = state->current_buf ? state->buf_0 : state->buf_1;
784 int *next_buflen = state->current_buf ? &state->buflen_0 :
785 &state->buflen_1, last_buflen;
786 int in_len = *buflen + req->nbytes, to_hash;
787 u32 *sh_desc = ctx->sh_desc_update, *desc;
788 dma_addr_t ptr = ctx->sh_desc_update_dma;
789 int src_nents, sec4_sg_bytes, sec4_sg_src_index;
790 struct ahash_edesc *edesc;
643b39b0 791 bool chained = false;
045e3678
YK		 792 int ret = 0;
793 int sh_len;
794
795 last_buflen = *next_buflen;
796 *next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1);
797 to_hash = in_len - *next_buflen;
798
799 if (to_hash) {
643b39b0
YK		 800 src_nents = __sg_count(req->src, req->nbytes - (*next_buflen),
801 &chained);
045e3678
YK		 802 sec4_sg_src_index = 1 + (*buflen ? 1 : 0);
803 sec4_sg_bytes = (sec4_sg_src_index + src_nents) *
804 sizeof(struct sec4_sg_entry);
805
806 /*
807 * allocate space for base edesc and hw desc commands,
808 * link tables
809 */
810 edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
811 sec4_sg_bytes, GFP_DMA | flags);
812 if (!edesc) {
813 dev_err(jrdev,
814 "could not allocate extended descriptor\n");
815 return -ENOMEM;
816 }
817
818 edesc->src_nents = src_nents;
643b39b0 819 edesc->chained = chained;
045e3678
YK		 820 edesc->sec4_sg_bytes = sec4_sg_bytes;
821 edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
822 DESC_JOB_IO_LEN;
045e3678 823
ce572085
HG		 824 ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
825 edesc->sec4_sg, DMA_BIDIRECTIONAL);
826 if (ret)
827 return ret;
045e3678
YK		 828
829 state->buf_dma = try_buf_map_to_sec4_sg(jrdev,
830 edesc->sec4_sg + 1,
831 buf, state->buf_dma,
832 *buflen, last_buflen);
833
834 if (src_nents) {
835 src_map_to_sec4_sg(jrdev, req->src, src_nents,
643b39b0
YK		 836 edesc->sec4_sg + sec4_sg_src_index,
837 chained);
045e3678
YK		 838 if (*next_buflen) {
839 sg_copy_part(next_buf, req->src, to_hash -
840 *buflen, req->nbytes);
841 state->current_buf = !state->current_buf;
842 }
843 } else {
844 (edesc->sec4_sg + sec4_sg_src_index - 1)->len |=
845 SEC4_SG_LEN_FIN;
846 }
847
848 sh_len = desc_len(sh_desc);
849 desc = edesc->hw_desc;
850 init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER |
851 HDR_REVERSE);
852
1da2be33
RG		 853 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
854 sec4_sg_bytes,
855 DMA_TO_DEVICE);
ce572085
HG		 856 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
857 dev_err(jrdev, "unable to map S/G table\n");
858 return -ENOMEM;
859 }
1da2be33 860
045e3678
YK		 861 append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len +
862 to_hash, LDST_SGF);
863
864 append_seq_out_ptr(desc, state->ctx_dma, ctx->ctx_len, 0);
865
866#ifdef DEBUG
514df281 867 print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
045e3678
YK		 868 DUMP_PREFIX_ADDRESS, 16, 4, desc,
869 desc_bytes(desc), 1);
870#endif
871
872 ret = caam_jr_enqueue(jrdev, desc, ahash_done_bi, req);
873 if (!ret) {
874 ret = -EINPROGRESS;
875 } else {
876 ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len,
877 DMA_BIDIRECTIONAL);
878 kfree(edesc);
879 }
880 } else if (*next_buflen) {
881 sg_copy(buf + *buflen, req->src, req->nbytes);
882 *buflen = *next_buflen;
883 *next_buflen = last_buflen;
884 }
885#ifdef DEBUG
514df281 886 print_hex_dump(KERN_ERR, "buf@"__stringify(__LINE__)": ",
045e3678 887 DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1);
514df281 888 print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ",
045e3678
YK		 889 DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
890 *next_buflen, 1);
891#endif
892
893 return ret;
894}
895
896static int ahash_final_ctx(struct ahash_request *req)
897{
898 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
899 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
900 struct caam_hash_state *state = ahash_request_ctx(req);
901 struct device *jrdev = ctx->jrdev;
902 gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
903 CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
904 u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
905 int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
906 int last_buflen = state->current_buf ? state->buflen_0 :
907 state->buflen_1;
908 u32 *sh_desc = ctx->sh_desc_fin, *desc;
909 dma_addr_t ptr = ctx->sh_desc_fin_dma;
910 int sec4_sg_bytes;
911 int digestsize = crypto_ahash_digestsize(ahash);
912 struct ahash_edesc *edesc;
913 int ret = 0;
914 int sh_len;
915
916 sec4_sg_bytes = (1 + (buflen ? 1 : 0)) * sizeof(struct sec4_sg_entry);
917
918 /* allocate space for base edesc and hw desc commands, link tables */
919 edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
920 sec4_sg_bytes, GFP_DMA | flags);
921 if (!edesc) {
922 dev_err(jrdev, "could not allocate extended descriptor\n");
923 return -ENOMEM;
924 }
925
926 sh_len = desc_len(sh_desc);
927 desc = edesc->hw_desc;
928 init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER | HDR_REVERSE);
929
930 edesc->sec4_sg_bytes = sec4_sg_bytes;
931 edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
932 DESC_JOB_IO_LEN;
045e3678
YK		 933 edesc->src_nents = 0;
934
ce572085
HG		 935 ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
936 edesc->sec4_sg, DMA_TO_DEVICE);
937 if (ret)
938 return ret;
045e3678
YK		 939
940 state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1,
941 buf, state->buf_dma, buflen,
942 last_buflen);
943 (edesc->sec4_sg + sec4_sg_bytes - 1)->len |= SEC4_SG_LEN_FIN;
944
1da2be33
RG		 945 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
946 sec4_sg_bytes, DMA_TO_DEVICE);
ce572085
HG		 947 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
948 dev_err(jrdev, "unable to map S/G table\n");
949 return -ENOMEM;
950 }
1da2be33 951
045e3678
YK		 952 append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len + buflen,
953 LDST_SGF);
954
955 edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
956 digestsize);
ce572085
HG		 957 if (dma_mapping_error(jrdev, edesc->dst_dma)) {
958 dev_err(jrdev, "unable to map dst\n");
959 return -ENOMEM;
960 }
045e3678
YK		 961
962#ifdef DEBUG
514df281 963 print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
045e3678
YK		 964 DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
965#endif
966
967 ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_src, req);
968 if (!ret) {
969 ret = -EINPROGRESS;
970 } else {
971 ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE);
972 kfree(edesc);
973 }
974
975 return ret;
976}
977
978static int ahash_finup_ctx(struct ahash_request *req)
979{
980 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
981 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
982 struct caam_hash_state *state = ahash_request_ctx(req);
983 struct device *jrdev = ctx->jrdev;
984 gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
985 CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
986 u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
987 int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
988 int last_buflen = state->current_buf ? state->buflen_0 :
989 state->buflen_1;
990 u32 *sh_desc = ctx->sh_desc_finup, *desc;
991 dma_addr_t ptr = ctx->sh_desc_finup_dma;
992 int sec4_sg_bytes, sec4_sg_src_index;
993 int src_nents;
994 int digestsize = crypto_ahash_digestsize(ahash);
995 struct ahash_edesc *edesc;
643b39b0 996 bool chained = false;
045e3678
YK		 997 int ret = 0;
998 int sh_len;
999
643b39b0 1000 src_nents = __sg_count(req->src, req->nbytes, &chained);
045e3678
YK		 1001 sec4_sg_src_index = 1 + (buflen ? 1 : 0);
1002 sec4_sg_bytes = (sec4_sg_src_index + src_nents) *
1003 sizeof(struct sec4_sg_entry);
1004
1005 /* allocate space for base edesc and hw desc commands, link tables */
1006 edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
1007 sec4_sg_bytes, GFP_DMA | flags);
1008 if (!edesc) {
1009 dev_err(jrdev, "could not allocate extended descriptor\n");
1010 return -ENOMEM;
1011 }
1012
1013 sh_len = desc_len(sh_desc);
1014 desc = edesc->hw_desc;
1015 init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER | HDR_REVERSE);
1016
1017 edesc->src_nents = src_nents;
643b39b0 1018 edesc->chained = chained;
045e3678
YK		 1019 edesc->sec4_sg_bytes = sec4_sg_bytes;
1020 edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
1021 DESC_JOB_IO_LEN;
045e3678 1022
ce572085
HG		 1023 ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
1024 edesc->sec4_sg, DMA_TO_DEVICE);
1025 if (ret)
1026 return ret;
045e3678
YK		 1027
1028 state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1,
1029 buf, state->buf_dma, buflen,
1030 last_buflen);
1031
1032 src_map_to_sec4_sg(jrdev, req->src, src_nents, edesc->sec4_sg +
643b39b0 1033 sec4_sg_src_index, chained);
045e3678 1034
1da2be33
RG		 1035 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1036 sec4_sg_bytes, DMA_TO_DEVICE);
ce572085
HG		 1037 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1038 dev_err(jrdev, "unable to map S/G table\n");
1039 return -ENOMEM;
1040 }
1da2be33 1041
045e3678
YK		 1042 append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len +
1043 buflen + req->nbytes, LDST_SGF);
1044
1045 edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
1046 digestsize);
ce572085
HG		 1047 if (dma_mapping_error(jrdev, edesc->dst_dma)) {
1048 dev_err(jrdev, "unable to map dst\n");
1049 return -ENOMEM;
1050 }
045e3678
YK		 1051
1052#ifdef DEBUG
514df281 1053 print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
045e3678
YK		 1054 DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
1055#endif
1056
1057 ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_src, req);
1058 if (!ret) {
1059 ret = -EINPROGRESS;
1060 } else {
1061 ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE);
1062 kfree(edesc);
1063 }
1064
1065 return ret;
1066}
1067
1068static int ahash_digest(struct ahash_request *req)
1069{
1070 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1071 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1072 struct device *jrdev = ctx->jrdev;
1073 gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1074 CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1075 u32 *sh_desc = ctx->sh_desc_digest, *desc;
1076 dma_addr_t ptr = ctx->sh_desc_digest_dma;
1077 int digestsize = crypto_ahash_digestsize(ahash);
1078 int src_nents, sec4_sg_bytes;
1079 dma_addr_t src_dma;
1080 struct ahash_edesc *edesc;
643b39b0 1081 bool chained = false;
045e3678
YK		 1082 int ret = 0;
1083 u32 options;
1084 int sh_len;
1085
643b39b0
YK		 1086 src_nents = sg_count(req->src, req->nbytes, &chained);
1087 dma_map_sg_chained(jrdev, req->src, src_nents ? : 1, DMA_TO_DEVICE,
1088 chained);
045e3678
YK		 1089 sec4_sg_bytes = src_nents * sizeof(struct sec4_sg_entry);
1090
1091 /* allocate space for base edesc and hw desc commands, link tables */
1092 edesc = kmalloc(sizeof(struct ahash_edesc) + sec4_sg_bytes +
1093 DESC_JOB_IO_LEN, GFP_DMA | flags);
1094 if (!edesc) {
1095 dev_err(jrdev, "could not allocate extended descriptor\n");
1096 return -ENOMEM;
1097 }
1098 edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
1099 DESC_JOB_IO_LEN;
45e9af78 1100 edesc->sec4_sg_bytes = sec4_sg_bytes;
045e3678 1101 edesc->src_nents = src_nents;
643b39b0 1102 edesc->chained = chained;
045e3678
YK		 1103
1104 sh_len = desc_len(sh_desc);
1105 desc = edesc->hw_desc;
1106 init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER | HDR_REVERSE);
1107
1108 if (src_nents) {
1109 sg_to_sec4_sg_last(req->src, src_nents, edesc->sec4_sg, 0);
1da2be33
RG		 1110 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1111 sec4_sg_bytes, DMA_TO_DEVICE);
ce572085
HG		 1112 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1113 dev_err(jrdev, "unable to map S/G table\n");
1114 return -ENOMEM;
1115 }
045e3678
YK		 1116 src_dma = edesc->sec4_sg_dma;
1117 options = LDST_SGF;
1118 } else {
1119 src_dma = sg_dma_address(req->src);
1120 options = 0;
1121 }
1122 append_seq_in_ptr(desc, src_dma, req->nbytes, options);
1123
1124 edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
1125 digestsize);
ce572085
HG		 1126 if (dma_mapping_error(jrdev, edesc->dst_dma)) {
1127 dev_err(jrdev, "unable to map dst\n");
1128 return -ENOMEM;
1129 }
045e3678
YK		 1130
1131#ifdef DEBUG
514df281 1132 print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
045e3678
YK		 1133 DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
1134#endif
1135
1136 ret = caam_jr_enqueue(jrdev, desc, ahash_done, req);
1137 if (!ret) {
1138 ret = -EINPROGRESS;
1139 } else {
1140 ahash_unmap(jrdev, edesc, req, digestsize);
1141 kfree(edesc);
1142 }
1143
1144 return ret;
1145}
1146
1147/* submit ahash final if it the first job descriptor */
1148static int ahash_final_no_ctx(struct ahash_request *req)
1149{
1150 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1151 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1152 struct caam_hash_state *state = ahash_request_ctx(req);
1153 struct device *jrdev = ctx->jrdev;
1154 gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1155 CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1156 u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
1157 int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
1158 u32 *sh_desc = ctx->sh_desc_digest, *desc;
1159 dma_addr_t ptr = ctx->sh_desc_digest_dma;
1160 int digestsize = crypto_ahash_digestsize(ahash);
1161 struct ahash_edesc *edesc;
1162 int ret = 0;
1163 int sh_len;
1164
1165 /* allocate space for base edesc and hw desc commands, link tables */
1166 edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN,
1167 GFP_DMA | flags);
1168 if (!edesc) {
1169 dev_err(jrdev, "could not allocate extended descriptor\n");
1170 return -ENOMEM;
1171 }
1172
1173 sh_len = desc_len(sh_desc);
1174 desc = edesc->hw_desc;
1175 init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER | HDR_REVERSE);
1176
1177 state->buf_dma = dma_map_single(jrdev, buf, buflen, DMA_TO_DEVICE);
ce572085
HG		 1178 if (dma_mapping_error(jrdev, state->buf_dma)) {
1179 dev_err(jrdev, "unable to map src\n");
1180 return -ENOMEM;
1181 }
045e3678
YK		 1182
1183 append_seq_in_ptr(desc, state->buf_dma, buflen, 0);
1184
1185 edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
1186 digestsize);
ce572085
HG		 1187 if (dma_mapping_error(jrdev, edesc->dst_dma)) {
1188 dev_err(jrdev, "unable to map dst\n");
1189 return -ENOMEM;
1190 }
045e3678
YK		 1191 edesc->src_nents = 0;
1192
1193#ifdef DEBUG
514df281 1194 print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
045e3678
YK		 1195 DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
1196#endif
1197
1198 ret = caam_jr_enqueue(jrdev, desc, ahash_done, req);
1199 if (!ret) {
1200 ret = -EINPROGRESS;
1201 } else {
1202 ahash_unmap(jrdev, edesc, req, digestsize);
1203 kfree(edesc);
1204 }
1205
1206 return ret;
1207}
1208
1209/* submit ahash update if it the first job descriptor after update */
1210static int ahash_update_no_ctx(struct ahash_request *req)
1211{
1212 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1213 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1214 struct caam_hash_state *state = ahash_request_ctx(req);
1215 struct device *jrdev = ctx->jrdev;
1216 gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1217 CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1218 u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
1219 int *buflen = state->current_buf ? &state->buflen_1 : &state->buflen_0;
1220 u8 *next_buf = state->current_buf ? state->buf_0 : state->buf_1;
1221 int *next_buflen = state->current_buf ? &state->buflen_0 :
1222 &state->buflen_1;
1223 int in_len = *buflen + req->nbytes, to_hash;
1224 int sec4_sg_bytes, src_nents;
1225 struct ahash_edesc *edesc;
1226 u32 *desc, *sh_desc = ctx->sh_desc_update_first;
1227 dma_addr_t ptr = ctx->sh_desc_update_first_dma;
643b39b0 1228 bool chained = false;
045e3678
YK		 1229 int ret = 0;
1230 int sh_len;
1231
1232 *next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1);
1233 to_hash = in_len - *next_buflen;
1234
1235 if (to_hash) {
643b39b0
YK		 1236 src_nents = __sg_count(req->src, req->nbytes - (*next_buflen),
1237 &chained);
045e3678
YK		 1238 sec4_sg_bytes = (1 + src_nents) *
1239 sizeof(struct sec4_sg_entry);
1240
1241 /*
1242 * allocate space for base edesc and hw desc commands,
1243 * link tables
1244 */
1245 edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
1246 sec4_sg_bytes, GFP_DMA | flags);
1247 if (!edesc) {
1248 dev_err(jrdev,
1249 "could not allocate extended descriptor\n");
1250 return -ENOMEM;
1251 }
1252
1253 edesc->src_nents = src_nents;
643b39b0 1254 edesc->chained = chained;
045e3678
YK		 1255 edesc->sec4_sg_bytes = sec4_sg_bytes;
1256 edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
1257 DESC_JOB_IO_LEN;
76b99080 1258 edesc->dst_dma = 0;
045e3678
YK		 1259
1260 state->buf_dma = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg,
1261 buf, *buflen);
1262 src_map_to_sec4_sg(jrdev, req->src, src_nents,
643b39b0 1263 edesc->sec4_sg + 1, chained);
045e3678
YK		 1264 if (*next_buflen) {
1265 sg_copy_part(next_buf, req->src, to_hash - *buflen,
1266 req->nbytes);
1267 state->current_buf = !state->current_buf;
1268 }
1269
1270 sh_len = desc_len(sh_desc);
1271 desc = edesc->hw_desc;
1272 init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER |
1273 HDR_REVERSE);
1274
1da2be33
RG		 1275 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1276 sec4_sg_bytes,
1277 DMA_TO_DEVICE);
ce572085
HG		 1278 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1279 dev_err(jrdev, "unable to map S/G table\n");
1280 return -ENOMEM;
1281 }
1da2be33 1282
045e3678
YK		 1283 append_seq_in_ptr(desc, edesc->sec4_sg_dma, to_hash, LDST_SGF);
1284
ce572085
HG		 1285 ret = map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len);
1286 if (ret)
1287 return ret;
045e3678
YK		 1288
1289#ifdef DEBUG
514df281 1290 print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
045e3678
YK		 1291 DUMP_PREFIX_ADDRESS, 16, 4, desc,
1292 desc_bytes(desc), 1);
1293#endif
1294
1295 ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_dst, req);
1296 if (!ret) {
1297 ret = -EINPROGRESS;
1298 state->update = ahash_update_ctx;
1299 state->finup = ahash_finup_ctx;
1300 state->final = ahash_final_ctx;
1301 } else {
1302 ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len,
1303 DMA_TO_DEVICE);
1304 kfree(edesc);
1305 }
1306 } else if (*next_buflen) {
1307 sg_copy(buf + *buflen, req->src, req->nbytes);
1308 *buflen = *next_buflen;
1309 *next_buflen = 0;
1310 }
1311#ifdef DEBUG
514df281 1312 print_hex_dump(KERN_ERR, "buf@"__stringify(__LINE__)": ",
045e3678 1313 DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1);
514df281 1314 print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ",
045e3678
YK		 1315 DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
1316 *next_buflen, 1);
1317#endif
1318
1319 return ret;
1320}
1321
1322/* submit ahash finup if it the first job descriptor after update */
1323static int ahash_finup_no_ctx(struct ahash_request *req)
1324{
1325 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1326 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1327 struct caam_hash_state *state = ahash_request_ctx(req);
1328 struct device *jrdev = ctx->jrdev;
1329 gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1330 CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1331 u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
1332 int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
1333 int last_buflen = state->current_buf ? state->buflen_0 :
1334 state->buflen_1;
1335 u32 *sh_desc = ctx->sh_desc_digest, *desc;
1336 dma_addr_t ptr = ctx->sh_desc_digest_dma;
1337 int sec4_sg_bytes, sec4_sg_src_index, src_nents;
1338 int digestsize = crypto_ahash_digestsize(ahash);
1339 struct ahash_edesc *edesc;
643b39b0 1340 bool chained = false;
045e3678
YK		 1341 int sh_len;
1342 int ret = 0;
1343
643b39b0 1344 src_nents = __sg_count(req->src, req->nbytes, &chained);
045e3678
YK		 1345 sec4_sg_src_index = 2;
1346 sec4_sg_bytes = (sec4_sg_src_index + src_nents) *
1347 sizeof(struct sec4_sg_entry);
1348
1349 /* allocate space for base edesc and hw desc commands, link tables */
1350 edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
1351 sec4_sg_bytes, GFP_DMA | flags);
1352 if (!edesc) {
1353 dev_err(jrdev, "could not allocate extended descriptor\n");
1354 return -ENOMEM;
1355 }
1356
1357 sh_len = desc_len(sh_desc);
1358 desc = edesc->hw_desc;
1359 init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER | HDR_REVERSE);
1360
1361 edesc->src_nents = src_nents;
643b39b0 1362 edesc->chained = chained;
045e3678
YK		 1363 edesc->sec4_sg_bytes = sec4_sg_bytes;
1364 edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
1365 DESC_JOB_IO_LEN;
045e3678
YK		 1366
1367 state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg, buf,
1368 state->buf_dma, buflen,
1369 last_buflen);
1370
643b39b0
YK		 1371 src_map_to_sec4_sg(jrdev, req->src, src_nents, edesc->sec4_sg + 1,
1372 chained);
045e3678 1373
1da2be33
RG		 1374 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1375 sec4_sg_bytes, DMA_TO_DEVICE);
ce572085
HG		 1376 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1377 dev_err(jrdev, "unable to map S/G table\n");
1378 return -ENOMEM;
1379 }
1da2be33 1380
045e3678
YK		 1381 append_seq_in_ptr(desc, edesc->sec4_sg_dma, buflen +
1382 req->nbytes, LDST_SGF);
1383
1384 edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
1385 digestsize);
ce572085
HG		 1386 if (dma_mapping_error(jrdev, edesc->dst_dma)) {
1387 dev_err(jrdev, "unable to map dst\n");
1388 return -ENOMEM;
1389 }
045e3678
YK		 1390
1391#ifdef DEBUG
514df281 1392 print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
045e3678
YK		 1393 DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
1394#endif
1395
1396 ret = caam_jr_enqueue(jrdev, desc, ahash_done, req);
1397 if (!ret) {
1398 ret = -EINPROGRESS;
1399 } else {
1400 ahash_unmap(jrdev, edesc, req, digestsize);
1401 kfree(edesc);
1402 }
1403
1404 return ret;
1405}
1406
1407/* submit first update job descriptor after init */
1408static int ahash_update_first(struct ahash_request *req)
1409{
1410 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1411 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1412 struct caam_hash_state *state = ahash_request_ctx(req);
1413 struct device *jrdev = ctx->jrdev;
1414 gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1415 CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1416 u8 *next_buf = state->buf_0 + state->current_buf *
1417 CAAM_MAX_HASH_BLOCK_SIZE;
1418 int *next_buflen = &state->buflen_0 + state->current_buf;
1419 int to_hash;
1420 u32 *sh_desc = ctx->sh_desc_update_first, *desc;
1421 dma_addr_t ptr = ctx->sh_desc_update_first_dma;
1422 int sec4_sg_bytes, src_nents;
1423 dma_addr_t src_dma;
1424 u32 options;
1425 struct ahash_edesc *edesc;
643b39b0 1426 bool chained = false;
045e3678
YK		 1427 int ret = 0;
1428 int sh_len;
1429
1430 *next_buflen = req->nbytes & (crypto_tfm_alg_blocksize(&ahash->base) -
1431 1);
1432 to_hash = req->nbytes - *next_buflen;
1433
1434 if (to_hash) {
643b39b0
YK		 1435 src_nents = sg_count(req->src, req->nbytes - (*next_buflen),
1436 &chained);
1437 dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
1438 DMA_TO_DEVICE, chained);
045e3678
YK		 1439 sec4_sg_bytes = src_nents * sizeof(struct sec4_sg_entry);
1440
1441 /*
1442 * allocate space for base edesc and hw desc commands,
1443 * link tables
1444 */
1445 edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
1446 sec4_sg_bytes, GFP_DMA | flags);
1447 if (!edesc) {
1448 dev_err(jrdev,
1449 "could not allocate extended descriptor\n");
1450 return -ENOMEM;
1451 }
1452
1453 edesc->src_nents = src_nents;
643b39b0 1454 edesc->chained = chained;
045e3678
YK		 1455 edesc->sec4_sg_bytes = sec4_sg_bytes;
1456 edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
1457 DESC_JOB_IO_LEN;
76b99080 1458 edesc->dst_dma = 0;
045e3678
YK		 1459
1460 if (src_nents) {
1461 sg_to_sec4_sg_last(req->src, src_nents,
1462 edesc->sec4_sg, 0);
1da2be33
RG		 1463 edesc->sec4_sg_dma = dma_map_single(jrdev,
1464 edesc->sec4_sg,
1465 sec4_sg_bytes,
1466 DMA_TO_DEVICE);
ce572085
HG		 1467 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1468 dev_err(jrdev, "unable to map S/G table\n");
1469 return -ENOMEM;
1470 }
045e3678
YK		 1471 src_dma = edesc->sec4_sg_dma;
1472 options = LDST_SGF;
1473 } else {
1474 src_dma = sg_dma_address(req->src);
1475 options = 0;
1476 }
1477
1478 if (*next_buflen)
1479 sg_copy_part(next_buf, req->src, to_hash, req->nbytes);
1480
1481 sh_len = desc_len(sh_desc);
1482 desc = edesc->hw_desc;
1483 init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER |
1484 HDR_REVERSE);
1485
1486 append_seq_in_ptr(desc, src_dma, to_hash, options);
1487
ce572085
HG		 1488 ret = map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len);
1489 if (ret)
1490 return ret;
045e3678
YK		 1491
1492#ifdef DEBUG
514df281 1493 print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
045e3678
YK		 1494 DUMP_PREFIX_ADDRESS, 16, 4, desc,
1495 desc_bytes(desc), 1);
1496#endif
1497
1498 ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_dst,
1499 req);
1500 if (!ret) {
1501 ret = -EINPROGRESS;
1502 state->update = ahash_update_ctx;
1503 state->finup = ahash_finup_ctx;
1504 state->final = ahash_final_ctx;
1505 } else {
1506 ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len,
1507 DMA_TO_DEVICE);
1508 kfree(edesc);
1509 }
1510 } else if (*next_buflen) {
1511 state->update = ahash_update_no_ctx;
1512 state->finup = ahash_finup_no_ctx;
1513 state->final = ahash_final_no_ctx;
1514 sg_copy(next_buf, req->src, req->nbytes);
1515 }
1516#ifdef DEBUG
514df281 1517 print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ",
045e3678
YK		 1518 DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
1519 *next_buflen, 1);
1520#endif
1521
1522 return ret;
1523}
1524
1525static int ahash_finup_first(struct ahash_request *req)
1526{
1527 return ahash_digest(req);
1528}
1529
1530static int ahash_init(struct ahash_request *req)
1531{
1532 struct caam_hash_state *state = ahash_request_ctx(req);
1533
1534 state->update = ahash_update_first;
1535 state->finup = ahash_finup_first;
1536 state->final = ahash_final_no_ctx;
1537
1538 state->current_buf = 0;
1539
1540 return 0;
1541}
1542
1543static int ahash_update(struct ahash_request *req)
1544{
1545 struct caam_hash_state *state = ahash_request_ctx(req);
1546
1547 return state->update(req);
1548}
1549
1550static int ahash_finup(struct ahash_request *req)
1551{
1552 struct caam_hash_state *state = ahash_request_ctx(req);
1553
1554 return state->finup(req);
1555}
1556
1557static int ahash_final(struct ahash_request *req)
1558{
1559 struct caam_hash_state *state = ahash_request_ctx(req);
1560
1561 return state->final(req);
1562}
1563
1564static int ahash_export(struct ahash_request *req, void *out)
1565{
1566 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1567 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1568 struct caam_hash_state *state = ahash_request_ctx(req);
1569
1570 memcpy(out, ctx, sizeof(struct caam_hash_ctx));
1571 memcpy(out + sizeof(struct caam_hash_ctx), state,
1572 sizeof(struct caam_hash_state));
1573 return 0;
1574}
1575
1576static int ahash_import(struct ahash_request *req, const void *in)
1577{
1578 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1579 struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1580 struct caam_hash_state *state = ahash_request_ctx(req);
1581
1582 memcpy(ctx, in, sizeof(struct caam_hash_ctx));
1583 memcpy(state, in + sizeof(struct caam_hash_ctx),
1584 sizeof(struct caam_hash_state));
1585 return 0;
1586}
1587
1588struct caam_hash_template {
1589 char name[CRYPTO_MAX_ALG_NAME];
1590 char driver_name[CRYPTO_MAX_ALG_NAME];
b0e09bae
YK		 1591 char hmac_name[CRYPTO_MAX_ALG_NAME];
1592 char hmac_driver_name[CRYPTO_MAX_ALG_NAME];
045e3678
YK		 1593 unsigned int blocksize;
1594 struct ahash_alg template_ahash;
1595 u32 alg_type;
1596 u32 alg_op;
1597};
1598
1599/* ahash descriptors */
1600static struct caam_hash_template driver_hash[] = {
1601 {
b0e09bae
YK		 1602 .name = "sha1",
1603 .driver_name = "sha1-caam",
1604 .hmac_name = "hmac(sha1)",
1605 .hmac_driver_name = "hmac-sha1-caam",
045e3678
YK		 1606 .blocksize = SHA1_BLOCK_SIZE,
1607 .template_ahash = {
1608 .init = ahash_init,
1609 .update = ahash_update,
1610 .final = ahash_final,
1611 .finup = ahash_finup,
1612 .digest = ahash_digest,
1613 .export = ahash_export,
1614 .import = ahash_import,
1615 .setkey = ahash_setkey,
1616 .halg = {
1617 .digestsize = SHA1_DIGEST_SIZE,
1618 },
1619 },
1620 .alg_type = OP_ALG_ALGSEL_SHA1,
1621 .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
1622 }, {
b0e09bae
YK		 1623 .name = "sha224",
1624 .driver_name = "sha224-caam",
1625 .hmac_name = "hmac(sha224)",
1626 .hmac_driver_name = "hmac-sha224-caam",
045e3678
YK		 1627 .blocksize = SHA224_BLOCK_SIZE,
1628 .template_ahash = {
1629 .init = ahash_init,
1630 .update = ahash_update,
1631 .final = ahash_final,
1632 .finup = ahash_finup,
1633 .digest = ahash_digest,
1634 .export = ahash_export,
1635 .import = ahash_import,
1636 .setkey = ahash_setkey,
1637 .halg = {
1638 .digestsize = SHA224_DIGEST_SIZE,
1639 },
1640 },
1641 .alg_type = OP_ALG_ALGSEL_SHA224,
1642 .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
1643 }, {
b0e09bae
YK		 1644 .name = "sha256",
1645 .driver_name = "sha256-caam",
1646 .hmac_name = "hmac(sha256)",
1647 .hmac_driver_name = "hmac-sha256-caam",
045e3678
YK		 1648 .blocksize = SHA256_BLOCK_SIZE,
1649 .template_ahash = {
1650 .init = ahash_init,
1651 .update = ahash_update,
1652 .final = ahash_final,
1653 .finup = ahash_finup,
1654 .digest = ahash_digest,
1655 .export = ahash_export,
1656 .import = ahash_import,
1657 .setkey = ahash_setkey,
1658 .halg = {
1659 .digestsize = SHA256_DIGEST_SIZE,
1660 },
1661 },
1662 .alg_type = OP_ALG_ALGSEL_SHA256,
1663 .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
1664 }, {
b0e09bae
YK		 1665 .name = "sha384",
1666 .driver_name = "sha384-caam",
1667 .hmac_name = "hmac(sha384)",
1668 .hmac_driver_name = "hmac-sha384-caam",
045e3678
YK		 1669 .blocksize = SHA384_BLOCK_SIZE,
1670 .template_ahash = {
1671 .init = ahash_init,
1672 .update = ahash_update,
1673 .final = ahash_final,
1674 .finup = ahash_finup,
1675 .digest = ahash_digest,
1676 .export = ahash_export,
1677 .import = ahash_import,
1678 .setkey = ahash_setkey,
1679 .halg = {
1680 .digestsize = SHA384_DIGEST_SIZE,
1681 },
1682 },
1683 .alg_type = OP_ALG_ALGSEL_SHA384,
1684 .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
1685 }, {
b0e09bae
YK		 1686 .name = "sha512",
1687 .driver_name = "sha512-caam",
1688 .hmac_name = "hmac(sha512)",
1689 .hmac_driver_name = "hmac-sha512-caam",
045e3678
YK		 1690 .blocksize = SHA512_BLOCK_SIZE,
1691 .template_ahash = {
1692 .init = ahash_init,
1693 .update = ahash_update,
1694 .final = ahash_final,
1695 .finup = ahash_finup,
1696 .digest = ahash_digest,
1697 .export = ahash_export,
1698 .import = ahash_import,
1699 .setkey = ahash_setkey,
1700 .halg = {
1701 .digestsize = SHA512_DIGEST_SIZE,
1702 },
1703 },
1704 .alg_type = OP_ALG_ALGSEL_SHA512,
1705 .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
1706 }, {
b0e09bae
YK		 1707 .name = "md5",
1708 .driver_name = "md5-caam",
1709 .hmac_name = "hmac(md5)",
1710 .hmac_driver_name = "hmac-md5-caam",
045e3678
YK		 1711 .blocksize = MD5_BLOCK_WORDS * 4,
1712 .template_ahash = {
1713 .init = ahash_init,
1714 .update = ahash_update,
1715 .final = ahash_final,
1716 .finup = ahash_finup,
1717 .digest = ahash_digest,
1718 .export = ahash_export,
1719 .import = ahash_import,
1720 .setkey = ahash_setkey,
1721 .halg = {
1722 .digestsize = MD5_DIGEST_SIZE,
1723 },
1724 },
1725 .alg_type = OP_ALG_ALGSEL_MD5,
1726 .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
1727 },
1728};
1729
1730struct caam_hash_alg {
1731 struct list_head entry;
045e3678
YK		 1732 int alg_type;
1733 int alg_op;
1734 struct ahash_alg ahash_alg;
1735};
1736
1737static int caam_hash_cra_init(struct crypto_tfm *tfm)
1738{
1739 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
1740 struct crypto_alg *base = tfm->__crt_alg;
1741 struct hash_alg_common *halg =
1742 container_of(base, struct hash_alg_common, base);
1743 struct ahash_alg *alg =
1744 container_of(halg, struct ahash_alg, halg);
1745 struct caam_hash_alg *caam_hash =
1746 container_of(alg, struct caam_hash_alg, ahash_alg);
1747 struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
045e3678
YK		 1748 /* Sizes for MDHA running digests: MD5, SHA1, 224, 256, 384, 512 */
1749 static const u8 runninglen[] = { HASH_MSG_LEN + MD5_DIGEST_SIZE,
1750 HASH_MSG_LEN + SHA1_DIGEST_SIZE,
1751 HASH_MSG_LEN + 32,
1752 HASH_MSG_LEN + SHA256_DIGEST_SIZE,
1753 HASH_MSG_LEN + 64,
1754 HASH_MSG_LEN + SHA512_DIGEST_SIZE };
045e3678
YK		 1755 int ret = 0;
1756
1757 /*
cfc6f11b 1758 * Get a Job ring from Job Ring driver to ensure in-order
045e3678
YK		 1759 * crypto request processing per tfm
1760 */
cfc6f11b
RG		 1761 ctx->jrdev = caam_jr_alloc();
1762 if (IS_ERR(ctx->jrdev)) {
1763 pr_err("Job Ring Device allocation for transform failed\n");
1764 return PTR_ERR(ctx->jrdev);
1765 }
045e3678
YK		 1766 /* copy descriptor header template value */
1767 ctx->alg_type = OP_TYPE_CLASS2_ALG | caam_hash->alg_type;
1768 ctx->alg_op = OP_TYPE_CLASS2_ALG | caam_hash->alg_op;
1769
1770 ctx->ctx_len = runninglen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >>
1771 OP_ALG_ALGSEL_SHIFT];
1772
1773 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1774 sizeof(struct caam_hash_state));
1775
1776 ret = ahash_set_sh_desc(ahash);
1777
1778 return ret;
1779}
1780
1781static void caam_hash_cra_exit(struct crypto_tfm *tfm)
1782{
1783 struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
1784
1785 if (ctx->sh_desc_update_dma &&
1786 !dma_mapping_error(ctx->jrdev, ctx->sh_desc_update_dma))
1787 dma_unmap_single(ctx->jrdev, ctx->sh_desc_update_dma,
1788 desc_bytes(ctx->sh_desc_update),
1789 DMA_TO_DEVICE);
1790 if (ctx->sh_desc_update_first_dma &&
1791 !dma_mapping_error(ctx->jrdev, ctx->sh_desc_update_first_dma))
1792 dma_unmap_single(ctx->jrdev, ctx->sh_desc_update_first_dma,
1793 desc_bytes(ctx->sh_desc_update_first),
1794 DMA_TO_DEVICE);
1795 if (ctx->sh_desc_fin_dma &&
1796 !dma_mapping_error(ctx->jrdev, ctx->sh_desc_fin_dma))
1797 dma_unmap_single(ctx->jrdev, ctx->sh_desc_fin_dma,
1798 desc_bytes(ctx->sh_desc_fin), DMA_TO_DEVICE);
1799 if (ctx->sh_desc_digest_dma &&
1800 !dma_mapping_error(ctx->jrdev, ctx->sh_desc_digest_dma))
1801 dma_unmap_single(ctx->jrdev, ctx->sh_desc_digest_dma,
1802 desc_bytes(ctx->sh_desc_digest),
1803 DMA_TO_DEVICE);
1804 if (ctx->sh_desc_finup_dma &&
1805 !dma_mapping_error(ctx->jrdev, ctx->sh_desc_finup_dma))
1806 dma_unmap_single(ctx->jrdev, ctx->sh_desc_finup_dma,
1807 desc_bytes(ctx->sh_desc_finup), DMA_TO_DEVICE);
cfc6f11b
RG		 1808
1809 caam_jr_free(ctx->jrdev);
045e3678
YK		 1810}
1811
1812static void __exit caam_algapi_hash_exit(void)
1813{
045e3678
YK		 1814 struct caam_hash_alg *t_alg, *n;
1815
cfc6f11b 1816 if (!hash_list.next)
045e3678
YK		 1817 return;
1818
cfc6f11b 1819 list_for_each_entry_safe(t_alg, n, &hash_list, entry) {
045e3678
YK		 1820 crypto_unregister_ahash(&t_alg->ahash_alg);
1821 list_del(&t_alg->entry);
1822 kfree(t_alg);
1823 }
1824}
1825
1826static struct caam_hash_alg *
cfc6f11b 1827caam_hash_alloc(struct caam_hash_template *template,
b0e09bae 1828 bool keyed)
045e3678
YK		 1829{
1830 struct caam_hash_alg *t_alg;
1831 struct ahash_alg *halg;
1832 struct crypto_alg *alg;
1833
1834 t_alg = kzalloc(sizeof(struct caam_hash_alg), GFP_KERNEL);
1835 if (!t_alg) {
cfc6f11b 1836 pr_err("failed to allocate t_alg\n");
045e3678
YK		 1837 return ERR_PTR(-ENOMEM);
1838 }
1839
1840 t_alg->ahash_alg = template->template_ahash;
1841 halg = &t_alg->ahash_alg;
1842 alg = &halg->halg.base;
1843
b0e09bae
YK		 1844 if (keyed) {
1845 snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s",
1846 template->hmac_name);
1847 snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
1848 template->hmac_driver_name);
1849 } else {
1850 snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s",
1851 template->name);
1852 snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
1853 template->driver_name);
1854 }
045e3678
YK		 1855 alg->cra_module = THIS_MODULE;
1856 alg->cra_init = caam_hash_cra_init;
1857 alg->cra_exit = caam_hash_cra_exit;
1858 alg->cra_ctxsize = sizeof(struct caam_hash_ctx);
1859 alg->cra_priority = CAAM_CRA_PRIORITY;
1860 alg->cra_blocksize = template->blocksize;
1861 alg->cra_alignmask = 0;
1862 alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_TYPE_AHASH;
1863 alg->cra_type = &crypto_ahash_type;
1864
1865 t_alg->alg_type = template->alg_type;
1866 t_alg->alg_op = template->alg_op;
045e3678
YK		 1867
1868 return t_alg;
1869}
1870
1871static int __init caam_algapi_hash_init(void)
1872{
35af6403
RG		 1873 struct device_node *dev_node;
1874 struct platform_device *pdev;
1875 struct device *ctrldev;
1876 void *priv;
045e3678
YK		 1877 int i = 0, err = 0;
1878
35af6403
RG		 1879 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
1880 if (!dev_node) {
1881 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
1882 if (!dev_node)
1883 return -ENODEV;
1884 }
1885
1886 pdev = of_find_device_by_node(dev_node);
1887 if (!pdev) {
1888 of_node_put(dev_node);
1889 return -ENODEV;
1890 }
1891
1892 ctrldev = &pdev->dev;
1893 priv = dev_get_drvdata(ctrldev);
1894 of_node_put(dev_node);
1895
1896 /*
1897 * If priv is NULL, it's probably because the caam driver wasn't
1898 * properly initialized (e.g. RNG4 init failed). Thus, bail out here.
1899 */
1900 if (!priv)
1901 return -ENODEV;
1902
cfc6f11b 1903 INIT_LIST_HEAD(&hash_list);
045e3678
YK		 1904
1905 /* register crypto algorithms the device supports */
1906 for (i = 0; i < ARRAY_SIZE(driver_hash); i++) {
1907 /* TODO: check if h/w supports alg */
1908 struct caam_hash_alg *t_alg;
1909
b0e09bae 1910 /* register hmac version */
cfc6f11b 1911 t_alg = caam_hash_alloc(&driver_hash[i], true);
b0e09bae
YK		 1912 if (IS_ERR(t_alg)) {
1913 err = PTR_ERR(t_alg);
cfc6f11b
RG		 1914 pr_warn("%s alg allocation failed\n",
1915 driver_hash[i].driver_name);
b0e09bae
YK		 1916 continue;
1917 }
1918
1919 err = crypto_register_ahash(&t_alg->ahash_alg);
1920 if (err) {
cfc6f11b 1921 pr_warn("%s alg registration failed\n",
b0e09bae
YK		 1922 t_alg->ahash_alg.halg.base.cra_driver_name);
1923 kfree(t_alg);
1924 } else
cfc6f11b 1925 list_add_tail(&t_alg->entry, &hash_list);
b0e09bae
YK		 1926
1927 /* register unkeyed version */
cfc6f11b 1928 t_alg = caam_hash_alloc(&driver_hash[i], false);
045e3678
YK		 1929 if (IS_ERR(t_alg)) {
1930 err = PTR_ERR(t_alg);
cfc6f11b
RG		 1931 pr_warn("%s alg allocation failed\n",
1932 driver_hash[i].driver_name);
045e3678
YK		 1933 continue;
1934 }
1935
1936 err = crypto_register_ahash(&t_alg->ahash_alg);
1937 if (err) {
cfc6f11b 1938 pr_warn("%s alg registration failed\n",
045e3678
YK		 1939 t_alg->ahash_alg.halg.base.cra_driver_name);
1940 kfree(t_alg);
1941 } else
cfc6f11b 1942 list_add_tail(&t_alg->entry, &hash_list);
045e3678
YK		 1943 }
1944
1945 return err;
1946}
1947
1948module_init(caam_algapi_hash_init);
1949module_exit(caam_algapi_hash_exit);
1950
1951MODULE_LICENSE("GPL");
1952MODULE_DESCRIPTION("FSL CAAM support for ahash functions of crypto API");
1953MODULE_AUTHOR("Freescale Semiconductor - NMG");
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