[mirror_ubuntu-artful-kernel.git] / drivers / crypto / ccp / ccp-dev.h

/*
 * AMD Cryptographic Coprocessor (CCP) driver
 *
 * Copyright (C) 2013,2016 Advanced Micro Devices, Inc.
 *
 * Author: Tom Lendacky <thomas.lendacky@amd.com>
 * Author: Gary R Hook <gary.hook@amd.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __CCP_DEV_H__
#define __CCP_DEV_H__

#include <linux/device.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/mutex.h>
#include <linux/list.h>
#include <linux/wait.h>
#include <linux/dmapool.h>
#include <linux/hw_random.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/irqreturn.h>
#include <linux/dmaengine.h>

#define MAX_CCP_NAME_LEN		16
#define MAX_DMAPOOL_NAME_LEN		32

#define MAX_HW_QUEUES			5
#define MAX_CMD_QLEN			100

#define TRNG_RETRIES			10

#define CACHE_NONE			0x00
#define CACHE_WB_NO_ALLOC		0xb7

/****** Register Mappings ******/
#define Q_MASK_REG			0x000
#define TRNG_OUT_REG			0x00c
#define IRQ_MASK_REG			0x040
#define IRQ_STATUS_REG			0x200

#define DEL_CMD_Q_JOB			0x124
#define DEL_Q_ACTIVE			0x00000200
#define DEL_Q_ID_SHIFT			6

#define CMD_REQ0			0x180
#define CMD_REQ_INCR			0x04

#define CMD_Q_STATUS_BASE		0x210
#define CMD_Q_INT_STATUS_BASE		0x214
#define CMD_Q_STATUS_INCR		0x20

#define CMD_Q_CACHE_BASE		0x228
#define CMD_Q_CACHE_INC			0x20

#define CMD_Q_ERROR(__qs)		((__qs) & 0x0000003f)
#define CMD_Q_DEPTH(__qs)		(((__qs) >> 12) & 0x0000000f)

/* ------------------------ CCP Version 5 Specifics ------------------------ */
#define CMD5_QUEUE_MASK_OFFSET		0x00
#define	CMD5_QUEUE_PRIO_OFFSET		0x04
#define CMD5_REQID_CONFIG_OFFSET	0x08
#define	CMD5_CMD_TIMEOUT_OFFSET		0x10
#define LSB_PUBLIC_MASK_LO_OFFSET	0x18
#define LSB_PUBLIC_MASK_HI_OFFSET	0x1C
#define LSB_PRIVATE_MASK_LO_OFFSET	0x20
#define LSB_PRIVATE_MASK_HI_OFFSET	0x24
#define CMD5_PSP_CCP_VERSION		0x100

#define CMD5_Q_CONTROL_BASE		0x0000
#define CMD5_Q_TAIL_LO_BASE		0x0004
#define CMD5_Q_HEAD_LO_BASE		0x0008
#define CMD5_Q_INT_ENABLE_BASE		0x000C
#define CMD5_Q_INTERRUPT_STATUS_BASE	0x0010

#define CMD5_Q_STATUS_BASE		0x0100
#define CMD5_Q_INT_STATUS_BASE		0x0104
#define CMD5_Q_DMA_STATUS_BASE		0x0108
#define CMD5_Q_DMA_READ_STATUS_BASE	0x010C
#define CMD5_Q_DMA_WRITE_STATUS_BASE	0x0110
#define CMD5_Q_ABORT_BASE		0x0114
#define CMD5_Q_AX_CACHE_BASE		0x0118

#define	CMD5_CONFIG_0_OFFSET		0x6000
#define	CMD5_TRNG_CTL_OFFSET		0x6008
#define	CMD5_AES_MASK_OFFSET		0x6010
#define	CMD5_CLK_GATE_CTL_OFFSET	0x603C

/* Address offset between two virtual queue registers */
#define CMD5_Q_STATUS_INCR		0x1000

/* Bit masks */
#define CMD5_Q_RUN			0x1
#define CMD5_Q_HALT			0x2
#define CMD5_Q_MEM_LOCATION		0x4
#define CMD5_Q_SIZE			0x1F
#define CMD5_Q_SHIFT			3
#define COMMANDS_PER_QUEUE		16
#define QUEUE_SIZE_VAL			((ffs(COMMANDS_PER_QUEUE) - 2) & \
					  CMD5_Q_SIZE)
#define Q_PTR_MASK			(2 << (QUEUE_SIZE_VAL + 5) - 1)
#define Q_DESC_SIZE			sizeof(struct ccp5_desc)
#define Q_SIZE(n)			(COMMANDS_PER_QUEUE*(n))

#define INT_COMPLETION			0x1
#define INT_ERROR			0x2
#define INT_QUEUE_STOPPED		0x4
#define	INT_EMPTY_QUEUE			0x8
#define SUPPORTED_INTERRUPTS		(INT_COMPLETION | INT_ERROR)

#define LSB_REGION_WIDTH		5
#define MAX_LSB_CNT			8

#define LSB_SIZE			16
#define LSB_ITEM_SIZE			32
#define PLSB_MAP_SIZE			(LSB_SIZE)
#define SLSB_MAP_SIZE			(MAX_LSB_CNT * LSB_SIZE)

#define LSB_ENTRY_NUMBER(LSB_ADDR)	(LSB_ADDR / LSB_ITEM_SIZE)

/* ------------------------ CCP Version 3 Specifics ------------------------ */
#define REQ0_WAIT_FOR_WRITE		0x00000004
#define REQ0_INT_ON_COMPLETE		0x00000002
#define REQ0_STOP_ON_COMPLETE		0x00000001

#define REQ0_CMD_Q_SHIFT		9
#define REQ0_JOBID_SHIFT		3

/****** REQ1 Related Values ******/
#define REQ1_PROTECT_SHIFT		27
#define REQ1_ENGINE_SHIFT		23
#define REQ1_KEY_KSB_SHIFT		2

#define REQ1_EOM			0x00000002
#define REQ1_INIT			0x00000001

/* AES Related Values */
#define REQ1_AES_TYPE_SHIFT		21
#define REQ1_AES_MODE_SHIFT		18
#define REQ1_AES_ACTION_SHIFT		17
#define REQ1_AES_CFB_SIZE_SHIFT		10

/* XTS-AES Related Values */
#define REQ1_XTS_AES_SIZE_SHIFT		10

/* SHA Related Values */
#define REQ1_SHA_TYPE_SHIFT		21

/* RSA Related Values */
#define REQ1_RSA_MOD_SIZE_SHIFT		10

/* Pass-Through Related Values */
#define REQ1_PT_BW_SHIFT		12
#define REQ1_PT_BS_SHIFT		10

/* ECC Related Values */
#define REQ1_ECC_AFFINE_CONVERT		0x00200000
#define REQ1_ECC_FUNCTION_SHIFT		18

/****** REQ4 Related Values ******/
#define REQ4_KSB_SHIFT			18
#define REQ4_MEMTYPE_SHIFT		16

/****** REQ6 Related Values ******/
#define REQ6_MEMTYPE_SHIFT		16

/****** Key Storage Block ******/
#define KSB_START			77
#define KSB_END				127
#define KSB_COUNT			(KSB_END - KSB_START + 1)
#define CCP_SB_BITS			256

#define CCP_JOBID_MASK			0x0000003f

/* ------------------------ General CCP Defines ------------------------ */

#define	CCP_DMA_DFLT			0x0
#define	CCP_DMA_PRIV			0x1
#define	CCP_DMA_PUB			0x2

#define CCP_DMAPOOL_MAX_SIZE		64
#define CCP_DMAPOOL_ALIGN		BIT(5)

#define CCP_REVERSE_BUF_SIZE		64

#define CCP_AES_KEY_SB_COUNT		1
#define CCP_AES_CTX_SB_COUNT		1

#define CCP_XTS_AES_KEY_SB_COUNT	1
#define CCP5_XTS_AES_KEY_SB_COUNT	2
#define CCP_XTS_AES_CTX_SB_COUNT	1

#define CCP_DES3_KEY_SB_COUNT		1
#define CCP_DES3_CTX_SB_COUNT		1

#define CCP_SHA_SB_COUNT		1

#define CCP_RSA_MAX_WIDTH		4096

#define CCP_PASSTHRU_BLOCKSIZE		256
#define CCP_PASSTHRU_MASKSIZE		32
#define CCP_PASSTHRU_SB_COUNT		1

#define CCP_ECC_MODULUS_BYTES		48      /* 384-bits */
#define CCP_ECC_MAX_OPERANDS		6
#define CCP_ECC_MAX_OUTPUTS		3
#define CCP_ECC_SRC_BUF_SIZE		448
#define CCP_ECC_DST_BUF_SIZE		192
#define CCP_ECC_OPERAND_SIZE		64
#define CCP_ECC_OUTPUT_SIZE		64
#define CCP_ECC_RESULT_OFFSET		60
#define CCP_ECC_RESULT_SUCCESS		0x0001

#define CCP_SB_BYTES			32

struct ccp_op;
struct ccp_device;
struct ccp_cmd;
struct ccp_fns;

struct ccp_dma_cmd {
	struct list_head entry;

	struct ccp_cmd ccp_cmd;
};

struct ccp_dma_desc {
	struct list_head entry;

	struct ccp_device *ccp;

	struct list_head pending;
	struct list_head active;

	enum dma_status status;
	struct dma_async_tx_descriptor tx_desc;
	size_t len;
};

struct ccp_dma_chan {
	struct ccp_device *ccp;

	spinlock_t lock;
	struct list_head created;
	struct list_head pending;
	struct list_head active;
	struct list_head complete;

	struct tasklet_struct cleanup_tasklet;

	enum dma_status status;
	struct dma_chan dma_chan;
};

struct ccp_cmd_queue {
	struct ccp_device *ccp;

	/* Queue identifier */
	u32 id;

	/* Queue dma pool */
	struct dma_pool *dma_pool;

	/* Queue base address (not neccessarily aligned)*/
	struct ccp5_desc *qbase;

	/* Aligned queue start address (per requirement) */
	struct mutex q_mutex ____cacheline_aligned;
	unsigned int qidx;

	/* Version 5 has different requirements for queue memory */
	unsigned int qsize;
	dma_addr_t qbase_dma;
	dma_addr_t qdma_tail;

	/* Per-queue reserved storage block(s) */
	u32 sb_key;
	u32 sb_ctx;

	/* Bitmap of LSBs that can be accessed by this queue */
	DECLARE_BITMAP(lsbmask, MAX_LSB_CNT);
	/* Private LSB that is assigned to this queue, or -1 if none.
	 * Bitmap for my private LSB, unused otherwise
	 */
	int lsb;
	DECLARE_BITMAP(lsbmap, PLSB_MAP_SIZE);

	/* Queue processing thread */
	struct task_struct *kthread;
	unsigned int active;
	unsigned int suspended;

	/* Number of free command slots available */
	unsigned int free_slots;

	/* Interrupt masks */
	u32 int_ok;
	u32 int_err;

	/* Register addresses for queue */
	void __iomem *reg_control;
	void __iomem *reg_tail_lo;
	void __iomem *reg_head_lo;
	void __iomem *reg_int_enable;
	void __iomem *reg_interrupt_status;
	void __iomem *reg_status;
	void __iomem *reg_int_status;
	void __iomem *reg_dma_status;
	void __iomem *reg_dma_read_status;
	void __iomem *reg_dma_write_status;
	u32 qcontrol; /* Cached control register */

	/* Status values from job */
	u32 int_status;
	u32 q_status;
	u32 q_int_status;
	u32 cmd_error;

	/* Interrupt wait queue */
	wait_queue_head_t int_queue;
	unsigned int int_rcvd;

	/* Per-queue Statistics */
	unsigned long total_ops;
	unsigned long total_aes_ops;
	unsigned long total_xts_aes_ops;
	unsigned long total_3des_ops;
	unsigned long total_sha_ops;
	unsigned long total_rsa_ops;
	unsigned long total_pt_ops;
	unsigned long total_ecc_ops;
} ____cacheline_aligned;

struct ccp_device {
	struct list_head entry;

	struct ccp_vdata *vdata;
	unsigned int ord;
	char name[MAX_CCP_NAME_LEN];
	char rngname[MAX_CCP_NAME_LEN];

	struct device *dev;

	/* Bus specific device information
	 */
	void *dev_specific;
	int (*get_irq)(struct ccp_device *ccp);
	void (*free_irq)(struct ccp_device *ccp);
	unsigned int qim;
	unsigned int irq;
	bool use_tasklet;
	struct tasklet_struct irq_tasklet;

	/* I/O area used for device communication. The register mapping
	 * starts at an offset into the mapped bar.
	 *   The CMD_REQx registers and the Delete_Cmd_Queue_Job register
	 *   need to be protected while a command queue thread is accessing
	 *   them.
	 */
	struct mutex req_mutex ____cacheline_aligned;
	void __iomem *io_map;
	void __iomem *io_regs;

	/* Master lists that all cmds are queued on. Because there can be
	 * more than one CCP command queue that can process a cmd a separate
	 * backlog list is neeeded so that the backlog completion call
	 * completes before the cmd is available for execution.
	 */
	spinlock_t cmd_lock ____cacheline_aligned;
	unsigned int cmd_count;
	struct list_head cmd;
	struct list_head backlog;

	/* The command queues. These represent the queues available on the
	 * CCP that are available for processing cmds
	 */
	struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES];
	unsigned int cmd_q_count;

	/* Support for the CCP True RNG
	 */
	struct hwrng hwrng;
	unsigned int hwrng_retries;

	/* Support for the CCP DMA capabilities
	 */
	struct dma_device dma_dev;
	struct ccp_dma_chan *ccp_dma_chan;
	struct kmem_cache *dma_cmd_cache;
	struct kmem_cache *dma_desc_cache;

	/* A counter used to generate job-ids for cmds submitted to the CCP
	 */
	atomic_t current_id ____cacheline_aligned;

	/* The v3 CCP uses key storage blocks (SB) to maintain context for
	 * certain operations. To prevent multiple cmds from using the same
	 * SB range a command queue reserves an SB range for the duration of
	 * the cmd. Each queue, will however, reserve 2 SB blocks for
	 * operations that only require single SB entries (eg. AES context/iv
	 * and key) in order to avoid allocation contention.  This will reserve
	 * at most 10 SB entries, leaving 40 SB entries available for dynamic
	 * allocation.
	 *
	 * The v5 CCP Local Storage Block (LSB) is broken up into 8
	 * memrory ranges, each of which can be enabled for access by one
	 * or more queues. Device initialization takes this into account,
	 * and attempts to assign one region for exclusive use by each
	 * available queue; the rest are then aggregated as "public" use.
	 * If there are fewer regions than queues, all regions are shared
	 * amongst all queues.
	 */
	struct mutex sb_mutex ____cacheline_aligned;
	DECLARE_BITMAP(sb, KSB_COUNT);
	wait_queue_head_t sb_queue;
	unsigned int sb_avail;
	unsigned int sb_count;
	u32 sb_start;

	/* Bitmap of shared LSBs, if any */
	DECLARE_BITMAP(lsbmap, SLSB_MAP_SIZE);

	/* Suspend support */
	unsigned int suspending;
	wait_queue_head_t suspend_queue;

	/* DMA caching attribute support */
	unsigned int axcache;

	/* Device Statistics */
	unsigned long total_interrupts;

	/* DebugFS info */
	struct dentry *debugfs_instance;
};

enum ccp_memtype {
	CCP_MEMTYPE_SYSTEM = 0,
	CCP_MEMTYPE_SB,
	CCP_MEMTYPE_LOCAL,
	CCP_MEMTYPE__LAST,
};
#define	CCP_MEMTYPE_LSB	CCP_MEMTYPE_KSB


struct ccp_dma_info {
	dma_addr_t address;
	unsigned int offset;
	unsigned int length;
	enum dma_data_direction dir;
} __packed __aligned(4);

struct ccp_dm_workarea {
	struct device *dev;
	struct dma_pool *dma_pool;

	u8 *address;
	struct ccp_dma_info dma;
	unsigned int length;
};

struct ccp_sg_workarea {
	struct scatterlist *sg;
	int nents;
	unsigned int sg_used;

	struct scatterlist *dma_sg;
	struct device *dma_dev;
	unsigned int dma_count;
	enum dma_data_direction dma_dir;

	u64 bytes_left;
};

struct ccp_data {
	struct ccp_sg_workarea sg_wa;
	struct ccp_dm_workarea dm_wa;
};

struct ccp_mem {
	enum ccp_memtype type;
	union {
		struct ccp_dma_info dma;
		u32 sb;
	} u;
};

struct ccp_aes_op {
	enum ccp_aes_type type;
	enum ccp_aes_mode mode;
	enum ccp_aes_action action;
	unsigned int size;
};

struct ccp_xts_aes_op {
	enum ccp_aes_type type;
	enum ccp_aes_action action;
	enum ccp_xts_aes_unit_size unit_size;
};

struct ccp_des3_op {
	enum ccp_des3_type type;
	enum ccp_des3_mode mode;
	enum ccp_des3_action action;
};

struct ccp_sha_op {
	enum ccp_sha_type type;
	u64 msg_bits;
};

struct ccp_rsa_op {
	u32 mod_size;
	u32 input_len;
};

struct ccp_passthru_op {
	enum ccp_passthru_bitwise bit_mod;
	enum ccp_passthru_byteswap byte_swap;
};

struct ccp_ecc_op {
	enum ccp_ecc_function function;
};

struct ccp_op {
	struct ccp_cmd_queue *cmd_q;

	u32 jobid;
	u32 ioc;
	u32 soc;
	u32 sb_key;
	u32 sb_ctx;
	u32 init;
	u32 eom;

	struct ccp_mem src;
	struct ccp_mem dst;
	struct ccp_mem exp;

	union {
		struct ccp_aes_op aes;
		struct ccp_xts_aes_op xts;
		struct ccp_des3_op des3;
		struct ccp_sha_op sha;
		struct ccp_rsa_op rsa;
		struct ccp_passthru_op passthru;
		struct ccp_ecc_op ecc;
	} u;
};

static inline u32 ccp_addr_lo(struct ccp_dma_info *info)
{
	return lower_32_bits(info->address + info->offset);
}

static inline u32 ccp_addr_hi(struct ccp_dma_info *info)
{
	return upper_32_bits(info->address + info->offset) & 0x0000ffff;
}

/**
 * descriptor for version 5 CPP commands
 * 8 32-bit words:
 * word 0: function; engine; control bits
 * word 1: length of source data
 * word 2: low 32 bits of source pointer
 * word 3: upper 16 bits of source pointer; source memory type
 * word 4: low 32 bits of destination pointer
 * word 5: upper 16 bits of destination pointer; destination memory type
 * word 6: low 32 bits of key pointer
 * word 7: upper 16 bits of key pointer; key memory type
 */
struct dword0 {
	unsigned int soc:1;
	unsigned int ioc:1;
	unsigned int rsvd1:1;
	unsigned int init:1;
	unsigned int eom:1;		/* AES/SHA only */
	unsigned int function:15;
	unsigned int engine:4;
	unsigned int prot:1;
	unsigned int rsvd2:7;
};

struct dword3 {
	unsigned int  src_hi:16;
	unsigned int  src_mem:2;
	unsigned int  lsb_cxt_id:8;
	unsigned int  rsvd1:5;
	unsigned int  fixed:1;
};

union dword4 {
	__le32 dst_lo;		/* NON-SHA	*/
	__le32 sha_len_lo;	/* SHA		*/
};

union dword5 {
	struct {
		unsigned int  dst_hi:16;
		unsigned int  dst_mem:2;
		unsigned int  rsvd1:13;
		unsigned int  fixed:1;
	} fields;
	__le32 sha_len_hi;
};

struct dword7 {
	unsigned int  key_hi:16;
	unsigned int  key_mem:2;
	unsigned int  rsvd1:14;
};

struct ccp5_desc {
	struct dword0 dw0;
	__le32 length;
	__le32 src_lo;
	struct dword3 dw3;
	union dword4 dw4;
	union dword5 dw5;
	__le32 key_lo;
	struct dword7 dw7;
};

int ccp_pci_init(void);
void ccp_pci_exit(void);

int ccp_platform_init(void);
void ccp_platform_exit(void);

void ccp_add_device(struct ccp_device *ccp);
void ccp_del_device(struct ccp_device *ccp);

extern void ccp_log_error(struct ccp_device *, int);

struct ccp_device *ccp_alloc_struct(struct device *dev);
bool ccp_queues_suspended(struct ccp_device *ccp);
int ccp_cmd_queue_thread(void *data);
int ccp_trng_read(struct hwrng *rng, void *data, size_t max, bool wait);

int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd);

int ccp_register_rng(struct ccp_device *ccp);
void ccp_unregister_rng(struct ccp_device *ccp);
int ccp_dmaengine_register(struct ccp_device *ccp);
void ccp_dmaengine_unregister(struct ccp_device *ccp);

void ccp5_debugfs_setup(struct ccp_device *ccp);
void ccp5_debugfs_destroy(void);

/* Structure for computation functions that are device-specific */
struct ccp_actions {
	int (*aes)(struct ccp_op *);
	int (*xts_aes)(struct ccp_op *);
	int (*des3)(struct ccp_op *);
	int (*sha)(struct ccp_op *);
	int (*rsa)(struct ccp_op *);
	int (*passthru)(struct ccp_op *);
	int (*ecc)(struct ccp_op *);
	u32 (*sballoc)(struct ccp_cmd_queue *, unsigned int);
	void (*sbfree)(struct ccp_cmd_queue *, unsigned int, unsigned int);
	unsigned int (*get_free_slots)(struct ccp_cmd_queue *);
	int (*init)(struct ccp_device *);
	void (*destroy)(struct ccp_device *);
	irqreturn_t (*irqhandler)(int, void *);
};

/* Structure to hold CCP version-specific values */
struct ccp_vdata {
	const unsigned int version;
	const unsigned int dma_chan_attr;
	void (*setup)(struct ccp_device *);
	const struct ccp_actions *perform;
	const unsigned int bar;
	const unsigned int offset;
};

extern const struct ccp_vdata ccpv3;
extern const struct ccp_vdata ccpv5a;
extern const struct ccp_vdata ccpv5b;

#endif
Commit	Line	Data
63b94509 TL	1	/*
	2	* AMD Cryptographic Coprocessor (CCP) driver
	3	*
553d2374	4	* Copyright (C) 2013,2016 Advanced Micro Devices, Inc.
63b94509 TL	5	*
63b94509 TL	6	* Author: Tom Lendacky <thomas.lendacky@amd.com>
fba8855c	7	* Author: Gary R Hook <gary.hook@amd.com>
63b94509 TL	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#ifndef __CCP_DEV_H__
	15	#define __CCP_DEV_H__
	16
	17	#include <linux/device.h>
	18	#include <linux/pci.h>
	19	#include <linux/spinlock.h>
	20	#include <linux/mutex.h>
	21	#include <linux/list.h>
	22	#include <linux/wait.h>
	23	#include <linux/dmapool.h>
	24	#include <linux/hw_random.h>
8db88467	25	#include <linux/bitops.h>
58ea8abf GH	26	#include <linux/interrupt.h>
	27	#include <linux/irqreturn.h>
	28	#include <linux/dmaengine.h>
63b94509	29
553d2374	30	#define MAX_CCP_NAME_LEN 16
63b94509 TL	31	#define MAX_DMAPOOL_NAME_LEN 32
	32
	33	#define MAX_HW_QUEUES 5
	34	#define MAX_CMD_QLEN 100
	35
	36	#define TRNG_RETRIES 10
	37
126ae9ad	38	#define CACHE_NONE 0x00
c4f4b325 TL	39	#define CACHE_WB_NO_ALLOC 0xb7
c4f4b325 TL	40
63b94509 TL	41	/**** Register Mappings ****/
	42	#define Q_MASK_REG 0x000
	43	#define TRNG_OUT_REG 0x00c
	44	#define IRQ_MASK_REG 0x040
	45	#define IRQ_STATUS_REG 0x200
	46
	47	#define DEL_CMD_Q_JOB 0x124
	48	#define DEL_Q_ACTIVE 0x00000200
	49	#define DEL_Q_ID_SHIFT 6
	50
	51	#define CMD_REQ0 0x180
	52	#define CMD_REQ_INCR 0x04
	53
	54	#define CMD_Q_STATUS_BASE 0x210
	55	#define CMD_Q_INT_STATUS_BASE 0x214
	56	#define CMD_Q_STATUS_INCR 0x20
	57
c4f4b325	58	#define CMD_Q_CACHE_BASE 0x228
63b94509 TL	59	#define CMD_Q_CACHE_INC 0x20
63b94509 TL	60
8db88467 TL	61	#define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f)
8db88467 TL	62	#define CMD_Q_DEPTH(__qs) (((__qs) >> 12) & 0x0000000f)
63b94509	63
4b394a23 GH	64	/* ------------------------ CCP Version 5 Specifics ------------------------ */
4b394a23 GH	65	#define CMD5_QUEUE_MASK_OFFSET 0x00
e14e7d12	66	#define CMD5_QUEUE_PRIO_OFFSET 0x04
4b394a23	67	#define CMD5_REQID_CONFIG_OFFSET 0x08
e14e7d12	68	#define CMD5_CMD_TIMEOUT_OFFSET 0x10
4b394a23 GH	69	#define LSB_PUBLIC_MASK_LO_OFFSET 0x18
	70	#define LSB_PUBLIC_MASK_HI_OFFSET 0x1C
	71	#define LSB_PRIVATE_MASK_LO_OFFSET 0x20
	72	#define LSB_PRIVATE_MASK_HI_OFFSET 0x24
3cdbe346	73	#define CMD5_PSP_CCP_VERSION 0x100
4b394a23 GH	74
	75	#define CMD5_Q_CONTROL_BASE 0x0000
	76	#define CMD5_Q_TAIL_LO_BASE 0x0004
	77	#define CMD5_Q_HEAD_LO_BASE 0x0008
	78	#define CMD5_Q_INT_ENABLE_BASE 0x000C
	79	#define CMD5_Q_INTERRUPT_STATUS_BASE 0x0010
	80
	81	#define CMD5_Q_STATUS_BASE 0x0100
	82	#define CMD5_Q_INT_STATUS_BASE 0x0104
	83	#define CMD5_Q_DMA_STATUS_BASE 0x0108
	84	#define CMD5_Q_DMA_READ_STATUS_BASE 0x010C
	85	#define CMD5_Q_DMA_WRITE_STATUS_BASE 0x0110
	86	#define CMD5_Q_ABORT_BASE 0x0114
	87	#define CMD5_Q_AX_CACHE_BASE 0x0118
	88
e14e7d12 GH	89	#define CMD5_CONFIG_0_OFFSET 0x6000
	90	#define CMD5_TRNG_CTL_OFFSET 0x6008
	91	#define CMD5_AES_MASK_OFFSET 0x6010
	92	#define CMD5_CLK_GATE_CTL_OFFSET 0x603C
	93
4b394a23 GH	94	/* Address offset between two virtual queue registers */
	95	#define CMD5_Q_STATUS_INCR 0x1000
	96
	97	/* Bit masks */
	98	#define CMD5_Q_RUN 0x1
	99	#define CMD5_Q_HALT 0x2
	100	#define CMD5_Q_MEM_LOCATION 0x4
	101	#define CMD5_Q_SIZE 0x1F
	102	#define CMD5_Q_SHIFT 3
	103	#define COMMANDS_PER_QUEUE 16
	104	#define QUEUE_SIZE_VAL ((ffs(COMMANDS_PER_QUEUE) - 2) & \
	105	CMD5_Q_SIZE)
	106	#define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
	107	#define Q_DESC_SIZE sizeof(struct ccp5_desc)
	108	#define Q_SIZE(n) (COMMANDS_PER_QUEUE*(n))
	109
	110	#define INT_COMPLETION 0x1
	111	#define INT_ERROR 0x2
	112	#define INT_QUEUE_STOPPED 0x4
56467cb1 GH	113	#define INT_EMPTY_QUEUE 0x8
56467cb1 GH	114	#define SUPPORTED_INTERRUPTS (INT_COMPLETION \| INT_ERROR)
4b394a23 GH	115
	116	#define LSB_REGION_WIDTH 5
	117	#define MAX_LSB_CNT 8
	118
	119	#define LSB_SIZE 16
	120	#define LSB_ITEM_SIZE 32
	121	#define PLSB_MAP_SIZE (LSB_SIZE)
	122	#define SLSB_MAP_SIZE (MAX_LSB_CNT * LSB_SIZE)
	123
	124	#define LSB_ENTRY_NUMBER(LSB_ADDR) (LSB_ADDR / LSB_ITEM_SIZE)
	125
	126	/* ------------------------ CCP Version 3 Specifics ------------------------ */
63b94509 TL	127	#define REQ0_WAIT_FOR_WRITE 0x00000004
	128	#define REQ0_INT_ON_COMPLETE 0x00000002
	129	#define REQ0_STOP_ON_COMPLETE 0x00000001
	130
	131	#define REQ0_CMD_Q_SHIFT 9
	132	#define REQ0_JOBID_SHIFT 3
	133
	134	/**** REQ1 Related Values ****/
	135	#define REQ1_PROTECT_SHIFT 27
	136	#define REQ1_ENGINE_SHIFT 23
	137	#define REQ1_KEY_KSB_SHIFT 2
	138
	139	#define REQ1_EOM 0x00000002
	140	#define REQ1_INIT 0x00000001
	141
	142	/* AES Related Values */
	143	#define REQ1_AES_TYPE_SHIFT 21
	144	#define REQ1_AES_MODE_SHIFT 18
	145	#define REQ1_AES_ACTION_SHIFT 17
	146	#define REQ1_AES_CFB_SIZE_SHIFT 10
	147
	148	/* XTS-AES Related Values */
	149	#define REQ1_XTS_AES_SIZE_SHIFT 10
	150
	151	/* SHA Related Values */
	152	#define REQ1_SHA_TYPE_SHIFT 21
	153
	154	/* RSA Related Values */
	155	#define REQ1_RSA_MOD_SIZE_SHIFT 10
	156
	157	/* Pass-Through Related Values */
	158	#define REQ1_PT_BW_SHIFT 12
	159	#define REQ1_PT_BS_SHIFT 10
	160
	161	/* ECC Related Values */
	162	#define REQ1_ECC_AFFINE_CONVERT 0x00200000
	163	#define REQ1_ECC_FUNCTION_SHIFT 18
	164
	165	/**** REQ4 Related Values ****/
	166	#define REQ4_KSB_SHIFT 18
	167	#define REQ4_MEMTYPE_SHIFT 16
	168
	169	/**** REQ6 Related Values ****/
	170	#define REQ6_MEMTYPE_SHIFT 16
	171
63b94509 TL	172	/**** Key Storage Block ****/
	173	#define KSB_START 77
	174	#define KSB_END 127
	175	#define KSB_COUNT (KSB_END - KSB_START + 1)
956ee21a	176	#define CCP_SB_BITS 256
63b94509 TL	177
	178	#define CCP_JOBID_MASK 0x0000003f
	179
4b394a23 GH	180	/* ------------------------ General CCP Defines ------------------------ */
4b394a23 GH	181
efc989fc GH	182	#define CCP_DMA_DFLT 0x0
	183	#define CCP_DMA_PRIV 0x1
	184	#define CCP_DMA_PUB 0x2
	185
63b94509	186	#define CCP_DMAPOOL_MAX_SIZE 64
8db88467	187	#define CCP_DMAPOOL_ALIGN BIT(5)
63b94509 TL	188
	189	#define CCP_REVERSE_BUF_SIZE 64
	190
956ee21a GH	191	#define CCP_AES_KEY_SB_COUNT 1
956ee21a GH	192	#define CCP_AES_CTX_SB_COUNT 1
63b94509	193
956ee21a	194	#define CCP_XTS_AES_KEY_SB_COUNT 1
d6bb8535	195	#define CCP5_XTS_AES_KEY_SB_COUNT 2
956ee21a	196	#define CCP_XTS_AES_CTX_SB_COUNT 1
63b94509	197
990672d4 GH	198	#define CCP_DES3_KEY_SB_COUNT 1
	199	#define CCP_DES3_CTX_SB_COUNT 1
	200
956ee21a	201	#define CCP_SHA_SB_COUNT 1
63b94509 TL	202
	203	#define CCP_RSA_MAX_WIDTH 4096
	204
	205	#define CCP_PASSTHRU_BLOCKSIZE 256
	206	#define CCP_PASSTHRU_MASKSIZE 32
956ee21a	207	#define CCP_PASSTHRU_SB_COUNT 1
63b94509 TL	208
	209	#define CCP_ECC_MODULUS_BYTES 48 /* 384-bits */
	210	#define CCP_ECC_MAX_OPERANDS 6
	211	#define CCP_ECC_MAX_OUTPUTS 3
	212	#define CCP_ECC_SRC_BUF_SIZE 448
	213	#define CCP_ECC_DST_BUF_SIZE 192
	214	#define CCP_ECC_OPERAND_SIZE 64
	215	#define CCP_ECC_OUTPUT_SIZE 64
	216	#define CCP_ECC_RESULT_OFFSET 60
	217	#define CCP_ECC_RESULT_SUCCESS 0x0001
	218
956ee21a GH	219	#define CCP_SB_BYTES 32
956ee21a GH	220
ea0375af	221	struct ccp_op;
63b94509 TL	222	struct ccp_device;
63b94509 TL	223	struct ccp_cmd;
4b394a23	224	struct ccp_fns;
63b94509	225
58ea8abf GH	226	struct ccp_dma_cmd {
	227	struct list_head entry;
	228
	229	struct ccp_cmd ccp_cmd;
	230	};
	231
	232	struct ccp_dma_desc {
	233	struct list_head entry;
	234
	235	struct ccp_device *ccp;
	236
	237	struct list_head pending;
	238	struct list_head active;
	239
	240	enum dma_status status;
	241	struct dma_async_tx_descriptor tx_desc;
	242	size_t len;
	243	};
	244
	245	struct ccp_dma_chan {
	246	struct ccp_device *ccp;
	247
	248	spinlock_t lock;
e5da5c56	249	struct list_head created;
58ea8abf GH	250	struct list_head pending;
	251	struct list_head active;
	252	struct list_head complete;
	253
	254	struct tasklet_struct cleanup_tasklet;
	255
	256	enum dma_status status;
	257	struct dma_chan dma_chan;
	258	};
	259
63b94509 TL	260	struct ccp_cmd_queue {
	261	struct ccp_device *ccp;
	262
	263	/* Queue identifier */
	264	u32 id;
	265
	266	/* Queue dma pool */
	267	struct dma_pool *dma_pool;
	268
4b394a23 GH	269	/* Queue base address (not neccessarily aligned)*/
	270	struct ccp5_desc *qbase;
	271
	272	/* Aligned queue start address (per requirement) */
	273	struct mutex q_mutex ____cacheline_aligned;
	274	unsigned int qidx;
	275
	276	/* Version 5 has different requirements for queue memory */
	277	unsigned int qsize;
	278	dma_addr_t qbase_dma;
	279	dma_addr_t qdma_tail;
	280
956ee21a GH	281	/* Per-queue reserved storage block(s) */
	282	u32 sb_key;
	283	u32 sb_ctx;
63b94509	284
4b394a23 GH	285	/* Bitmap of LSBs that can be accessed by this queue */
	286	DECLARE_BITMAP(lsbmask, MAX_LSB_CNT);
	287	/* Private LSB that is assigned to this queue, or -1 if none.
	288	* Bitmap for my private LSB, unused otherwise
	289	*/
3cf79968	290	int lsb;
4b394a23 GH	291	DECLARE_BITMAP(lsbmap, PLSB_MAP_SIZE);
4b394a23 GH	292
63b94509 TL	293	/* Queue processing thread */
	294	struct task_struct *kthread;
	295	unsigned int active;
	296	unsigned int suspended;
	297
	298	/* Number of free command slots available */
	299	unsigned int free_slots;
	300
	301	/* Interrupt masks */
	302	u32 int_ok;
	303	u32 int_err;
	304
	305	/* Register addresses for queue */
4b394a23 GH	306	void __iomem *reg_control;
	307	void __iomem *reg_tail_lo;
	308	void __iomem *reg_head_lo;
	309	void __iomem *reg_int_enable;
	310	void __iomem *reg_interrupt_status;
63b94509 TL	311	void __iomem *reg_status;
63b94509 TL	312	void __iomem *reg_int_status;
4b394a23 GH	313	void __iomem *reg_dma_status;
	314	void __iomem *reg_dma_read_status;
	315	void __iomem *reg_dma_write_status;
	316	u32 qcontrol; /* Cached control register */
63b94509 TL	317
	318	/* Status values from job */
	319	u32 int_status;
	320	u32 q_status;
	321	u32 q_int_status;
	322	u32 cmd_error;
	323
	324	/* Interrupt wait queue */
	325	wait_queue_head_t int_queue;
	326	unsigned int int_rcvd;
3cdbe346 GH	327
	328	/* Per-queue Statistics */
	329	unsigned long total_ops;
	330	unsigned long total_aes_ops;
	331	unsigned long total_xts_aes_ops;
	332	unsigned long total_3des_ops;
	333	unsigned long total_sha_ops;
	334	unsigned long total_rsa_ops;
	335	unsigned long total_pt_ops;
	336	unsigned long total_ecc_ops;
63b94509 TL	337	} ____cacheline_aligned;
	338
	339	struct ccp_device {
553d2374 GH	340	struct list_head entry;
553d2374 GH	341
c7019c4d	342	struct ccp_vdata *vdata;
553d2374 GH	343	unsigned int ord;
	344	char name[MAX_CCP_NAME_LEN];
	345	char rngname[MAX_CCP_NAME_LEN];
	346
63b94509 TL	347	struct device *dev;
63b94509 TL	348
fa242e80	349	/* Bus specific device information
63b94509 TL	350	*/
	351	void *dev_specific;
	352	int (get_irq)(struct ccp_device ccp);
	353	void (free_irq)(struct ccp_device ccp);
7b537b24	354	unsigned int qim;
3d77565b	355	unsigned int irq;
7b537b24 GH	356	bool use_tasklet;
7b537b24 GH	357	struct tasklet_struct irq_tasklet;
63b94509	358
fa242e80	359	/* I/O area used for device communication. The register mapping
63b94509 TL	360	* starts at an offset into the mapped bar.
	361	* The CMD_REQx registers and the Delete_Cmd_Queue_Job register
	362	* need to be protected while a command queue thread is accessing
	363	* them.
	364	*/
	365	struct mutex req_mutex ____cacheline_aligned;
	366	void __iomem *io_map;
	367	void __iomem *io_regs;
	368
fa242e80	369	/* Master lists that all cmds are queued on. Because there can be
63b94509 TL	370	* more than one CCP command queue that can process a cmd a separate
	371	* backlog list is neeeded so that the backlog completion call
	372	* completes before the cmd is available for execution.
	373	*/
	374	spinlock_t cmd_lock ____cacheline_aligned;
	375	unsigned int cmd_count;
	376	struct list_head cmd;
	377	struct list_head backlog;
	378
fa242e80	379	/* The command queues. These represent the queues available on the
63b94509 TL	380	* CCP that are available for processing cmds
	381	*/
	382	struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES];
	383	unsigned int cmd_q_count;
	384
fa242e80	385	/* Support for the CCP True RNG
63b94509 TL	386	*/
	387	struct hwrng hwrng;
	388	unsigned int hwrng_retries;
	389
fa242e80	390	/* Support for the CCP DMA capabilities
58ea8abf GH	391	*/
	392	struct dma_device dma_dev;
	393	struct ccp_dma_chan *ccp_dma_chan;
	394	struct kmem_cache *dma_cmd_cache;
	395	struct kmem_cache *dma_desc_cache;
	396
fa242e80	397	/* A counter used to generate job-ids for cmds submitted to the CCP
63b94509 TL	398	*/
	399	atomic_t current_id ____cacheline_aligned;
	400
58a690b7 GH	401	/* The v3 CCP uses key storage blocks (SB) to maintain context for
	402	* certain operations. To prevent multiple cmds from using the same
	403	* SB range a command queue reserves an SB range for the duration of
	404	* the cmd. Each queue, will however, reserve 2 SB blocks for
	405	* operations that only require single SB entries (eg. AES context/iv
	406	* and key) in order to avoid allocation contention. This will reserve
	407	* at most 10 SB entries, leaving 40 SB entries available for dynamic
	408	* allocation.
	409	*
	410	* The v5 CCP Local Storage Block (LSB) is broken up into 8
	411	* memrory ranges, each of which can be enabled for access by one
	412	* or more queues. Device initialization takes this into account,
	413	* and attempts to assign one region for exclusive use by each
	414	* available queue; the rest are then aggregated as "public" use.
	415	* If there are fewer regions than queues, all regions are shared
	416	* amongst all queues.
63b94509	417	*/
956ee21a GH	418	struct mutex sb_mutex ____cacheline_aligned;
	419	DECLARE_BITMAP(sb, KSB_COUNT);
	420	wait_queue_head_t sb_queue;
	421	unsigned int sb_avail;
	422	unsigned int sb_count;
	423	u32 sb_start;
63b94509	424
4b394a23 GH	425	/* Bitmap of shared LSBs, if any */
	426	DECLARE_BITMAP(lsbmap, SLSB_MAP_SIZE);
	427
63b94509 TL	428	/* Suspend support */
	429	unsigned int suspending;
	430	wait_queue_head_t suspend_queue;
126ae9ad TL	431
	432	/* DMA caching attribute support */
	433	unsigned int axcache;
3cdbe346 GH	434
	435	/* Device Statistics */
	436	unsigned long total_interrupts;
	437
	438	/* DebugFS info */
	439	struct dentry *debugfs_instance;
63b94509 TL	440	};
63b94509 TL	441
ea0375af GH	442	enum ccp_memtype {
ea0375af GH	443	CCP_MEMTYPE_SYSTEM = 0,
956ee21a	444	CCP_MEMTYPE_SB,
ea0375af GH	445	CCP_MEMTYPE_LOCAL,
	446	CCP_MEMTYPE__LAST,
	447	};
4b394a23	448	#define CCP_MEMTYPE_LSB CCP_MEMTYPE_KSB
ea0375af	449
2d158391	450
ea0375af GH	451	struct ccp_dma_info {
	452	dma_addr_t address;
	453	unsigned int offset;
	454	unsigned int length;
	455	enum dma_data_direction dir;
2d158391	456	} __packed __aligned(4);
ea0375af GH	457
	458	struct ccp_dm_workarea {
	459	struct device *dev;
	460	struct dma_pool *dma_pool;
ea0375af GH	461
	462	u8 *address;
	463	struct ccp_dma_info dma;
2d158391	464	unsigned int length;
ea0375af GH	465	};
	466
	467	struct ccp_sg_workarea {
	468	struct scatterlist *sg;
	469	int nents;
2d158391	470	unsigned int sg_used;
ea0375af GH	471
	472	struct scatterlist *dma_sg;
	473	struct device *dma_dev;
	474	unsigned int dma_count;
	475	enum dma_data_direction dma_dir;
	476
ea0375af GH	477	u64 bytes_left;
	478	};
	479
	480	struct ccp_data {
	481	struct ccp_sg_workarea sg_wa;
	482	struct ccp_dm_workarea dm_wa;
	483	};
	484
	485	struct ccp_mem {
	486	enum ccp_memtype type;
	487	union {
	488	struct ccp_dma_info dma;
956ee21a	489	u32 sb;
ea0375af GH	490	} u;
	491	};
	492
	493	struct ccp_aes_op {
	494	enum ccp_aes_type type;
	495	enum ccp_aes_mode mode;
	496	enum ccp_aes_action action;
f7cc02b3	497	unsigned int size;
ea0375af GH	498	};
	499
	500	struct ccp_xts_aes_op {
d6bb8535	501	enum ccp_aes_type type;
ea0375af GH	502	enum ccp_aes_action action;
	503	enum ccp_xts_aes_unit_size unit_size;
	504	};
	505
990672d4 GH	506	struct ccp_des3_op {
	507	enum ccp_des3_type type;
	508	enum ccp_des3_mode mode;
	509	enum ccp_des3_action action;
	510	};
	511
ea0375af GH	512	struct ccp_sha_op {
	513	enum ccp_sha_type type;
	514	u64 msg_bits;
	515	};
	516
	517	struct ccp_rsa_op {
	518	u32 mod_size;
	519	u32 input_len;
	520	};
	521
	522	struct ccp_passthru_op {
	523	enum ccp_passthru_bitwise bit_mod;
	524	enum ccp_passthru_byteswap byte_swap;
	525	};
	526
	527	struct ccp_ecc_op {
	528	enum ccp_ecc_function function;
	529	};
	530
	531	struct ccp_op {
	532	struct ccp_cmd_queue *cmd_q;
	533
	534	u32 jobid;
	535	u32 ioc;
	536	u32 soc;
956ee21a GH	537	u32 sb_key;
956ee21a GH	538	u32 sb_ctx;
ea0375af GH	539	u32 init;
	540	u32 eom;
	541
	542	struct ccp_mem src;
	543	struct ccp_mem dst;
4b394a23	544	struct ccp_mem exp;
ea0375af GH	545
	546	union {
	547	struct ccp_aes_op aes;
	548	struct ccp_xts_aes_op xts;
990672d4	549	struct ccp_des3_op des3;
ea0375af GH	550	struct ccp_sha_op sha;
	551	struct ccp_rsa_op rsa;
	552	struct ccp_passthru_op passthru;
	553	struct ccp_ecc_op ecc;
	554	} u;
	555	};
	556
	557	static inline u32 ccp_addr_lo(struct ccp_dma_info *info)
	558	{
	559	return lower_32_bits(info->address + info->offset);
	560	}
	561
	562	static inline u32 ccp_addr_hi(struct ccp_dma_info *info)
	563	{
	564	return upper_32_bits(info->address + info->offset) & 0x0000ffff;
	565	}
	566
4b394a23 GH	567	/**
	568	* descriptor for version 5 CPP commands
	569	* 8 32-bit words:
	570	* word 0: function; engine; control bits
	571	* word 1: length of source data
	572	* word 2: low 32 bits of source pointer
	573	* word 3: upper 16 bits of source pointer; source memory type
	574	* word 4: low 32 bits of destination pointer
	575	* word 5: upper 16 bits of destination pointer; destination memory type
	576	* word 6: low 32 bits of key pointer
	577	* word 7: upper 16 bits of key pointer; key memory type
	578	*/
	579	struct dword0 {
fdd2cf9d GH	580	unsigned int soc:1;
	581	unsigned int ioc:1;
	582	unsigned int rsvd1:1;
	583	unsigned int init:1;
	584	unsigned int eom:1; /* AES/SHA only */
	585	unsigned int function:15;
	586	unsigned int engine:4;
	587	unsigned int prot:1;
	588	unsigned int rsvd2:7;
4b394a23 GH	589	};
	590
	591	struct dword3 {
fdd2cf9d GH	592	unsigned int src_hi:16;
	593	unsigned int src_mem:2;
	594	unsigned int lsb_cxt_id:8;
	595	unsigned int rsvd1:5;
	596	unsigned int fixed:1;
4b394a23 GH	597	};
	598
	599	union dword4 {
	600	__le32 dst_lo; /* NON-SHA */
	601	__le32 sha_len_lo; /* SHA */
	602	};
	603
	604	union dword5 {
	605	struct {
fdd2cf9d GH	606	unsigned int dst_hi:16;
	607	unsigned int dst_mem:2;
	608	unsigned int rsvd1:13;
	609	unsigned int fixed:1;
4b394a23 GH	610	} fields;
	611	__le32 sha_len_hi;
	612	};
	613
	614	struct dword7 {
fdd2cf9d GH	615	unsigned int key_hi:16;
	616	unsigned int key_mem:2;
	617	unsigned int rsvd1:14;
4b394a23 GH	618	};
	619
	620	struct ccp5_desc {
	621	struct dword0 dw0;
	622	__le32 length;
	623	__le32 src_lo;
	624	struct dword3 dw3;
	625	union dword4 dw4;
	626	union dword5 dw5;
	627	__le32 key_lo;
	628	struct dword7 dw7;
	629	};
	630
63b94509 TL	631	int ccp_pci_init(void);
	632	void ccp_pci_exit(void);
	633
c4f4b325 TL	634	int ccp_platform_init(void);
	635	void ccp_platform_exit(void);
	636
ea0375af GH	637	void ccp_add_device(struct ccp_device *ccp);
	638	void ccp_del_device(struct ccp_device *ccp);
	639
81422bad GH	640	extern void ccp_log_error(struct ccp_device *, int);
81422bad GH	641
63b94509	642	struct ccp_device ccp_alloc_struct(struct device dev);
63b94509	643	bool ccp_queues_suspended(struct ccp_device *ccp);
ea0375af	644	int ccp_cmd_queue_thread(void *data);
8256e683	645	int ccp_trng_read(struct hwrng rng, void data, size_t max, bool wait);
63b94509 TL	646
	647	int ccp_run_cmd(struct ccp_cmd_queue cmd_q, struct ccp_cmd cmd);
	648
084935b2 GH	649	int ccp_register_rng(struct ccp_device *ccp);
084935b2 GH	650	void ccp_unregister_rng(struct ccp_device *ccp);
58ea8abf GH	651	int ccp_dmaengine_register(struct ccp_device *ccp);
	652	void ccp_dmaengine_unregister(struct ccp_device *ccp);
	653
3cdbe346 GH	654	void ccp5_debugfs_setup(struct ccp_device *ccp);
	655	void ccp5_debugfs_destroy(void);
	656
58a690b7 GH	657	/* Structure for computation functions that are device-specific */
	658	struct ccp_actions {
	659	int (aes)(struct ccp_op );
	660	int (xts_aes)(struct ccp_op );
990672d4	661	int (des3)(struct ccp_op );
58a690b7 GH	662	int (sha)(struct ccp_op );
	663	int (rsa)(struct ccp_op );
	664	int (passthru)(struct ccp_op );
	665	int (ecc)(struct ccp_op );
	666	u32 (sballoc)(struct ccp_cmd_queue , unsigned int);
990672d4	667	void (sbfree)(struct ccp_cmd_queue , unsigned int, unsigned int);
bb4e89b3	668	unsigned int (get_free_slots)(struct ccp_cmd_queue );
58a690b7 GH	669	int (init)(struct ccp_device );
	670	void (destroy)(struct ccp_device );
	671	irqreturn_t (irqhandler)(int, void );
	672	};
	673
	674	/* Structure to hold CCP version-specific values */
	675	struct ccp_vdata {
4b394a23	676	const unsigned int version;
efc989fc	677	const unsigned int dma_chan_attr;
4b394a23	678	void (setup)(struct ccp_device );
58a690b7 GH	679	const struct ccp_actions *perform;
	680	const unsigned int bar;
	681	const unsigned int offset;
	682	};
	683
9ddb9dc6 GH	684	extern const struct ccp_vdata ccpv3;
	685	extern const struct ccp_vdata ccpv5a;
	686	extern const struct ccp_vdata ccpv5b;
58a690b7	687
63b94509	688	#endif