[mirror_ubuntu-artful-kernel.git] / drivers / dma / dw / platform.c

/*
 * Platform driver for the Synopsys DesignWare DMA Controller
 *
 * Copyright (C) 2007-2008 Atmel Corporation
 * Copyright (C) 2010-2011 ST Microelectronics
 * Copyright (C) 2013 Intel Corporation
 *
 * Some parts of this driver are derived from the original dw_dmac.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/device.h>
#include <linux/clk.h>
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/of.h>
#include <linux/of_dma.h>
#include <linux/acpi.h>
#include <linux/acpi_dma.h>

#include "internal.h"

#define DRV_NAME	"dw_dmac"

static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec,
					struct of_dma *ofdma)
{
	struct dw_dma *dw = ofdma->of_dma_data;
	struct dw_dma_slave slave = {
		.dma_dev = dw->dma.dev,
	};
	dma_cap_mask_t cap;

	if (dma_spec->args_count != 3)
		return NULL;

	slave.src_id = dma_spec->args[0];
	slave.dst_id = dma_spec->args[0];
	slave.m_master = dma_spec->args[1];
	slave.p_master = dma_spec->args[2];

	if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS ||
		    slave.dst_id >= DW_DMA_MAX_NR_REQUESTS ||
		    slave.m_master >= dw->pdata->nr_masters ||
		    slave.p_master >= dw->pdata->nr_masters))
		return NULL;

	dma_cap_zero(cap);
	dma_cap_set(DMA_SLAVE, cap);

	/* TODO: there should be a simpler way to do this */
	return dma_request_channel(cap, dw_dma_filter, &slave);
}

#ifdef CONFIG_ACPI
static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param)
{
	struct acpi_dma_spec *dma_spec = param;
	struct dw_dma_slave slave = {
		.dma_dev = dma_spec->dev,
		.src_id = dma_spec->slave_id,
		.dst_id = dma_spec->slave_id,
		.m_master = 0,
		.p_master = 1,
	};

	return dw_dma_filter(chan, &slave);
}

static void dw_dma_acpi_controller_register(struct dw_dma *dw)
{
	struct device *dev = dw->dma.dev;
	struct acpi_dma_filter_info *info;
	int ret;

	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
	if (!info)
		return;

	dma_cap_zero(info->dma_cap);
	dma_cap_set(DMA_SLAVE, info->dma_cap);
	info->filter_fn = dw_dma_acpi_filter;

	ret = devm_acpi_dma_controller_register(dev, acpi_dma_simple_xlate,
						info);
	if (ret)
		dev_err(dev, "could not register acpi_dma_controller\n");
}
#else /* !CONFIG_ACPI */
static inline void dw_dma_acpi_controller_register(struct dw_dma *dw) {}
#endif /* !CONFIG_ACPI */

#ifdef CONFIG_OF
static struct dw_dma_platform_data *
dw_dma_parse_dt(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct dw_dma_platform_data *pdata;
	u32 tmp, arr[DW_DMA_MAX_NR_MASTERS], mb[DW_DMA_MAX_NR_CHANNELS];
	u32 nr_masters;
	u32 nr_channels;

	if (!np) {
		dev_err(&pdev->dev, "Missing DT data\n");
		return NULL;
	}

	if (of_property_read_u32(np, "dma-masters", &nr_masters))
		return NULL;
	if (nr_masters < 1 || nr_masters > DW_DMA_MAX_NR_MASTERS)
		return NULL;

	if (of_property_read_u32(np, "dma-channels", &nr_channels))
		return NULL;
	if (nr_channels > DW_DMA_MAX_NR_CHANNELS)
		return NULL;

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return NULL;

	pdata->nr_masters = nr_masters;
	pdata->nr_channels = nr_channels;

	if (of_property_read_bool(np, "is_private"))
		pdata->is_private = true;

	/*
	 * All known devices, which use DT for configuration, support
	 * memory-to-memory transfers. So enable it by default.
	 */
	pdata->is_memcpy = true;

	if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
		pdata->chan_allocation_order = (unsigned char)tmp;

	if (!of_property_read_u32(np, "chan_priority", &tmp))
		pdata->chan_priority = tmp;

	if (!of_property_read_u32(np, "block_size", &tmp))
		pdata->block_size = tmp;

	if (!of_property_read_u32_array(np, "data-width", arr, nr_masters)) {
		for (tmp = 0; tmp < nr_masters; tmp++)
			pdata->data_width[tmp] = arr[tmp];
	} else if (!of_property_read_u32_array(np, "data_width", arr, nr_masters)) {
		for (tmp = 0; tmp < nr_masters; tmp++)
			pdata->data_width[tmp] = BIT(arr[tmp] & 0x07);
	}

	if (!of_property_read_u32_array(np, "multi-block", mb, nr_channels)) {
		for (tmp = 0; tmp < nr_channels; tmp++)
			pdata->multi_block[tmp] = mb[tmp];
	} else {
		for (tmp = 0; tmp < nr_channels; tmp++)
			pdata->multi_block[tmp] = 1;
	}

	return pdata;
}
#else
static inline struct dw_dma_platform_data *
dw_dma_parse_dt(struct platform_device *pdev)
{
	return NULL;
}
#endif

static int dw_probe(struct platform_device *pdev)
{
	struct dw_dma_chip *chip;
	struct device *dev = &pdev->dev;
	struct resource *mem;
	const struct dw_dma_platform_data *pdata;
	int err;

	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	chip->irq = platform_get_irq(pdev, 0);
	if (chip->irq < 0)
		return chip->irq;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	chip->regs = devm_ioremap_resource(dev, mem);
	if (IS_ERR(chip->regs))
		return PTR_ERR(chip->regs);

	err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
	if (err)
		return err;

	pdata = dev_get_platdata(dev);
	if (!pdata)
		pdata = dw_dma_parse_dt(pdev);

	chip->dev = dev;
	chip->pdata = pdata;

	chip->clk = devm_clk_get(chip->dev, "hclk");
	if (IS_ERR(chip->clk))
		return PTR_ERR(chip->clk);
	err = clk_prepare_enable(chip->clk);
	if (err)
		return err;

	pm_runtime_enable(&pdev->dev);

	err = dw_dma_probe(chip);
	if (err)
		goto err_dw_dma_probe;

	platform_set_drvdata(pdev, chip);

	if (pdev->dev.of_node) {
		err = of_dma_controller_register(pdev->dev.of_node,
						 dw_dma_of_xlate, chip->dw);
		if (err)
			dev_err(&pdev->dev,
				"could not register of_dma_controller\n");
	}

	if (ACPI_HANDLE(&pdev->dev))
		dw_dma_acpi_controller_register(chip->dw);

	return 0;

err_dw_dma_probe:
	pm_runtime_disable(&pdev->dev);
	clk_disable_unprepare(chip->clk);
	return err;
}

static int dw_remove(struct platform_device *pdev)
{
	struct dw_dma_chip *chip = platform_get_drvdata(pdev);

	if (pdev->dev.of_node)
		of_dma_controller_free(pdev->dev.of_node);

	dw_dma_remove(chip);
	pm_runtime_disable(&pdev->dev);
	clk_disable_unprepare(chip->clk);

	return 0;
}

static void dw_shutdown(struct platform_device *pdev)
{
	struct dw_dma_chip *chip = platform_get_drvdata(pdev);

	/*
	 * We have to call dw_dma_disable() to stop any ongoing transfer. On
	 * some platforms we can't do that since DMA device is powered off.
	 * Moreover we have no possibility to check if the platform is affected
	 * or not. That's why we call pm_runtime_get_sync() / pm_runtime_put()
	 * unconditionally. On the other hand we can't use
	 * pm_runtime_suspended() because runtime PM framework is not fully
	 * used by the driver.
	 */
	pm_runtime_get_sync(chip->dev);
	dw_dma_disable(chip);
	pm_runtime_put_sync_suspend(chip->dev);

	clk_disable_unprepare(chip->clk);
}

#ifdef CONFIG_OF
static const struct of_device_id dw_dma_of_id_table[] = {
	{ .compatible = "snps,dma-spear1340" },
	{}
};
MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
#endif

#ifdef CONFIG_ACPI
static const struct acpi_device_id dw_dma_acpi_id_table[] = {
	{ "INTL9C60", 0 },
	{ }
};
MODULE_DEVICE_TABLE(acpi, dw_dma_acpi_id_table);
#endif

#ifdef CONFIG_PM_SLEEP

static int dw_suspend_late(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct dw_dma_chip *chip = platform_get_drvdata(pdev);

	dw_dma_disable(chip);
	clk_disable_unprepare(chip->clk);

	return 0;
}

static int dw_resume_early(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct dw_dma_chip *chip = platform_get_drvdata(pdev);

	clk_prepare_enable(chip->clk);
	return dw_dma_enable(chip);
}

#endif /* CONFIG_PM_SLEEP */

static const struct dev_pm_ops dw_dev_pm_ops = {
	SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_suspend_late, dw_resume_early)
};

static struct platform_driver dw_driver = {
	.probe		= dw_probe,
	.remove		= dw_remove,
	.shutdown       = dw_shutdown,
	.driver = {
		.name	= DRV_NAME,
		.pm	= &dw_dev_pm_ops,
		.of_match_table = of_match_ptr(dw_dma_of_id_table),
		.acpi_match_table = ACPI_PTR(dw_dma_acpi_id_table),
	},
};

static int __init dw_init(void)
{
	return platform_driver_register(&dw_driver);
}
subsys_initcall(dw_init);

static void __exit dw_exit(void)
{
	platform_driver_unregister(&dw_driver);
}
module_exit(dw_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller platform driver");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
9cade1a4 AS	1	/*
	2	* Platform driver for the Synopsys DesignWare DMA Controller
	3	*
	4	* Copyright (C) 2007-2008 Atmel Corporation
	5	* Copyright (C) 2010-2011 ST Microelectronics
	6	* Copyright (C) 2013 Intel Corporation
	7	*
	8	* Some parts of this driver are derived from the original dw_dmac.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/module.h>
	16	#include <linux/device.h>
	17	#include <linux/clk.h>
6acf3998	18	#include <linux/pm_runtime.h>
9cade1a4 AS	19	#include <linux/platform_device.h>
	20	#include <linux/dmaengine.h>
	21	#include <linux/dma-mapping.h>
	22	#include <linux/of.h>
	23	#include <linux/of_dma.h>
	24	#include <linux/acpi.h>
	25	#include <linux/acpi_dma.h>
	26
	27	#include "internal.h"
	28
a104a45b AS	29	#define DRV_NAME "dw_dmac"
a104a45b AS	30
9cade1a4 AS	31	static struct dma_chan dw_dma_of_xlate(struct of_phandle_args dma_spec,
	32	struct of_dma *ofdma)
	33	{
	34	struct dw_dma *dw = ofdma->of_dma_data;
4d130de2 AS	35	struct dw_dma_slave slave = {
4d130de2 AS	36	.dma_dev = dw->dma.dev,
9cade1a4 AS	37	};
	38	dma_cap_mask_t cap;
	39
	40	if (dma_spec->args_count != 3)
	41	return NULL;
	42
4d130de2 AS	43	slave.src_id = dma_spec->args[0];
4d130de2 AS	44	slave.dst_id = dma_spec->args[0];
c422025c AS	45	slave.m_master = dma_spec->args[1];
c422025c AS	46	slave.p_master = dma_spec->args[2];
9cade1a4	47
4d130de2 AS	48	if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS \|\|
4d130de2 AS	49	slave.dst_id >= DW_DMA_MAX_NR_REQUESTS \|\|
161c3d04 AS	50	slave.m_master >= dw->pdata->nr_masters \|\|
161c3d04 AS	51	slave.p_master >= dw->pdata->nr_masters))
9cade1a4 AS	52	return NULL;
	53
	54	dma_cap_zero(cap);
	55	dma_cap_set(DMA_SLAVE, cap);
	56
	57	/* TODO: there should be a simpler way to do this */
4d130de2	58	return dma_request_channel(cap, dw_dma_filter, &slave);
9cade1a4 AS	59	}
	60
	61	#ifdef CONFIG_ACPI
	62	static bool dw_dma_acpi_filter(struct dma_chan chan, void param)
	63	{
9cade1a4	64	struct acpi_dma_spec *dma_spec = param;
4d130de2 AS	65	struct dw_dma_slave slave = {
	66	.dma_dev = dma_spec->dev,
	67	.src_id = dma_spec->slave_id,
	68	.dst_id = dma_spec->slave_id,
c422025c AS	69	.m_master = 0,
c422025c AS	70	.p_master = 1,
4d130de2	71	};
9cade1a4	72
4d130de2	73	return dw_dma_filter(chan, &slave);
9cade1a4 AS	74	}
	75
	76	static void dw_dma_acpi_controller_register(struct dw_dma *dw)
	77	{
	78	struct device *dev = dw->dma.dev;
	79	struct acpi_dma_filter_info *info;
	80	int ret;
	81
	82	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
	83	if (!info)
	84	return;
	85
	86	dma_cap_zero(info->dma_cap);
	87	dma_cap_set(DMA_SLAVE, info->dma_cap);
	88	info->filter_fn = dw_dma_acpi_filter;
	89
	90	ret = devm_acpi_dma_controller_register(dev, acpi_dma_simple_xlate,
	91	info);
	92	if (ret)
	93	dev_err(dev, "could not register acpi_dma_controller\n");
	94	}
	95	#else /* !CONFIG_ACPI */
	96	static inline void dw_dma_acpi_controller_register(struct dw_dma *dw) {}
	97	#endif /* !CONFIG_ACPI */
	98
	99	#ifdef CONFIG_OF
	100	static struct dw_dma_platform_data *
	101	dw_dma_parse_dt(struct platform_device *pdev)
	102	{
	103	struct device_node *np = pdev->dev.of_node;
	104	struct dw_dma_platform_data *pdata;
bd2c6636	105	u32 tmp, arr[DW_DMA_MAX_NR_MASTERS], mb[DW_DMA_MAX_NR_CHANNELS];
969f750f	106	u32 nr_masters;
2b574ba9	107	u32 nr_channels;
9cade1a4 AS	108
	109	if (!np) {
	110	dev_err(&pdev->dev, "Missing DT data\n");
	111	return NULL;
	112	}
	113
969f750f AS	114	if (of_property_read_u32(np, "dma-masters", &nr_masters))
	115	return NULL;
	116	if (nr_masters < 1 \|\| nr_masters > DW_DMA_MAX_NR_MASTERS)
	117	return NULL;
	118
2b574ba9 MR	119	if (of_property_read_u32(np, "dma-channels", &nr_channels))
2b574ba9 MR	120	return NULL;
bd2c6636 EP	121	if (nr_channels > DW_DMA_MAX_NR_CHANNELS)
bd2c6636 EP	122	return NULL;
2b574ba9	123
9cade1a4 AS	124	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	125	if (!pdata)
	126	return NULL;
	127
969f750f	128	pdata->nr_masters = nr_masters;
2b574ba9	129	pdata->nr_channels = nr_channels;
9cade1a4 AS	130
	131	if (of_property_read_bool(np, "is_private"))
	132	pdata->is_private = true;
	133
258f2277 EP	134	/*
	135	* All known devices, which use DT for configuration, support
	136	* memory-to-memory transfers. So enable it by default.
	137	*/
	138	pdata->is_memcpy = true;
	139
9cade1a4 AS	140	if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
	141	pdata->chan_allocation_order = (unsigned char)tmp;
	142
	143	if (!of_property_read_u32(np, "chan_priority", &tmp))
	144	pdata->chan_priority = tmp;
	145
	146	if (!of_property_read_u32(np, "block_size", &tmp))
	147	pdata->block_size = tmp;
	148
2e65060e	149	if (!of_property_read_u32_array(np, "data-width", arr, nr_masters)) {
969f750f	150	for (tmp = 0; tmp < nr_masters; tmp++)
9cade1a4	151	pdata->data_width[tmp] = arr[tmp];
2e65060e AS	152	} else if (!of_property_read_u32_array(np, "data_width", arr, nr_masters)) {
	153	for (tmp = 0; tmp < nr_masters; tmp++)
	154	pdata->data_width[tmp] = BIT(arr[tmp] & 0x07);
969f750f	155	}
9cade1a4	156
bd2c6636 EP	157	if (!of_property_read_u32_array(np, "multi-block", mb, nr_channels)) {
	158	for (tmp = 0; tmp < nr_channels; tmp++)
	159	pdata->multi_block[tmp] = mb[tmp];
	160	} else {
	161	for (tmp = 0; tmp < nr_channels; tmp++)
	162	pdata->multi_block[tmp] = 1;
	163	}
	164
9cade1a4 AS	165	return pdata;
	166	}
	167	#else
	168	static inline struct dw_dma_platform_data *
	169	dw_dma_parse_dt(struct platform_device *pdev)
	170	{
	171	return NULL;
	172	}
	173	#endif
	174
	175	static int dw_probe(struct platform_device *pdev)
	176	{
	177	struct dw_dma_chip *chip;
	178	struct device *dev = &pdev->dev;
	179	struct resource *mem;
3a14c66d	180	const struct dw_dma_platform_data *pdata;
9cade1a4 AS	181	int err;
	182
	183	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	184	if (!chip)
	185	return -ENOMEM;
	186
	187	chip->irq = platform_get_irq(pdev, 0);
	188	if (chip->irq < 0)
	189	return chip->irq;
	190
	191	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	192	chip->regs = devm_ioremap_resource(dev, mem);
	193	if (IS_ERR(chip->regs))
	194	return PTR_ERR(chip->regs);
	195
24353b8b RK	196	err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
	197	if (err)
	198	return err;
9cade1a4 AS	199
	200	pdata = dev_get_platdata(dev);
	201	if (!pdata)
	202	pdata = dw_dma_parse_dt(pdev);
	203
	204	chip->dev = dev;
3a14c66d	205	chip->pdata = pdata;
9cade1a4	206
a15636e8 AS	207	chip->clk = devm_clk_get(chip->dev, "hclk");
	208	if (IS_ERR(chip->clk))
	209	return PTR_ERR(chip->clk);
	210	err = clk_prepare_enable(chip->clk);
9cade1a4 AS	211	if (err)
	212	return err;
	213
6acf3998 AS	214	pm_runtime_enable(&pdev->dev);
6acf3998 AS	215
3a14c66d	216	err = dw_dma_probe(chip);
a15636e8 AS	217	if (err)
	218	goto err_dw_dma_probe;
	219
9cade1a4 AS	220	platform_set_drvdata(pdev, chip);
	221
	222	if (pdev->dev.of_node) {
	223	err = of_dma_controller_register(pdev->dev.of_node,
	224	dw_dma_of_xlate, chip->dw);
	225	if (err)
	226	dev_err(&pdev->dev,
	227	"could not register of_dma_controller\n");
	228	}
	229
	230	if (ACPI_HANDLE(&pdev->dev))
	231	dw_dma_acpi_controller_register(chip->dw);
	232
	233	return 0;
a15636e8 AS	234
a15636e8 AS	235	err_dw_dma_probe:
6acf3998	236	pm_runtime_disable(&pdev->dev);
a15636e8 AS	237	clk_disable_unprepare(chip->clk);
a15636e8 AS	238	return err;
9cade1a4 AS	239	}
	240
	241	static int dw_remove(struct platform_device *pdev)
	242	{
	243	struct dw_dma_chip *chip = platform_get_drvdata(pdev);
	244
	245	if (pdev->dev.of_node)
	246	of_dma_controller_free(pdev->dev.of_node);
	247
a15636e8	248	dw_dma_remove(chip);
6acf3998	249	pm_runtime_disable(&pdev->dev);
a15636e8 AS	250	clk_disable_unprepare(chip->clk);
	251
	252	return 0;
9cade1a4 AS	253	}
	254
	255	static void dw_shutdown(struct platform_device *pdev)
	256	{
	257	struct dw_dma_chip *chip = platform_get_drvdata(pdev);
	258
32146588 AS	259	/*
	260	* We have to call dw_dma_disable() to stop any ongoing transfer. On
	261	* some platforms we can't do that since DMA device is powered off.
	262	* Moreover we have no possibility to check if the platform is affected
	263	* or not. That's why we call pm_runtime_get_sync() / pm_runtime_put()
	264	* unconditionally. On the other hand we can't use
	265	* pm_runtime_suspended() because runtime PM framework is not fully
	266	* used by the driver.
	267	*/
	268	pm_runtime_get_sync(chip->dev);
2540f74b	269	dw_dma_disable(chip);
32146588 AS	270	pm_runtime_put_sync_suspend(chip->dev);
32146588 AS	271
a15636e8	272	clk_disable_unprepare(chip->clk);
9cade1a4 AS	273	}
	274
	275	#ifdef CONFIG_OF
	276	static const struct of_device_id dw_dma_of_id_table[] = {
	277	{ .compatible = "snps,dma-spear1340" },
	278	{}
	279	};
	280	MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
	281	#endif
	282
	283	#ifdef CONFIG_ACPI
	284	static const struct acpi_device_id dw_dma_acpi_id_table[] = {
bc0bb1fd	285	{ "INTL9C60", 0 },
9cade1a4 AS	286	{ }
9cade1a4 AS	287	};
be480dcb	288	MODULE_DEVICE_TABLE(acpi, dw_dma_acpi_id_table);
9cade1a4 AS	289	#endif
	290
	291	#ifdef CONFIG_PM_SLEEP
	292
067bd4fd	293	static int dw_suspend_late(struct device *dev)
9cade1a4 AS	294	{
	295	struct platform_device *pdev = to_platform_device(dev);
	296	struct dw_dma_chip *chip = platform_get_drvdata(pdev);
	297
2540f74b	298	dw_dma_disable(chip);
a15636e8 AS	299	clk_disable_unprepare(chip->clk);
	300
	301	return 0;
9cade1a4 AS	302	}
9cade1a4 AS	303
067bd4fd	304	static int dw_resume_early(struct device *dev)
9cade1a4 AS	305	{
	306	struct platform_device *pdev = to_platform_device(dev);
	307	struct dw_dma_chip *chip = platform_get_drvdata(pdev);
	308
a15636e8	309	clk_prepare_enable(chip->clk);
2540f74b	310	return dw_dma_enable(chip);
9cade1a4 AS	311	}
9cade1a4 AS	312
067bd4fd	313	#endif /* CONFIG_PM_SLEEP */
9cade1a4 AS	314
9cade1a4 AS	315	static const struct dev_pm_ops dw_dev_pm_ops = {
067bd4fd	316	SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_suspend_late, dw_resume_early)
9cade1a4 AS	317	};
	318
	319	static struct platform_driver dw_driver = {
	320	.probe = dw_probe,
	321	.remove = dw_remove,
2540f74b	322	.shutdown = dw_shutdown,
9cade1a4	323	.driver = {
a104a45b	324	.name = DRV_NAME,
9cade1a4 AS	325	.pm = &dw_dev_pm_ops,
	326	.of_match_table = of_match_ptr(dw_dma_of_id_table),
	327	.acpi_match_table = ACPI_PTR(dw_dma_acpi_id_table),
	328	},
	329	};
	330
	331	static int __init dw_init(void)
	332	{
	333	return platform_driver_register(&dw_driver);
	334	}
	335	subsys_initcall(dw_init);
	336
	337	static void __exit dw_exit(void)
	338	{
	339	platform_driver_unregister(&dw_driver);
	340	}
	341	module_exit(dw_exit);
	342
	343	MODULE_LICENSE("GPL v2");
	344	MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller platform driver");
a104a45b	345	MODULE_ALIAS("platform:" DRV_NAME);